Hi Ard,
Please see my replies inline.
From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Tuesday, October 18, 2016 2:51 PM
On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:
From: Sakar Arora sakar.arora@nxp.com
NXP/FSL's LS1043A RDB board houses 2 GB DDR4 SDRAM.
There is a DDR controller IP which controls access to this SDRAM.
This patch adds a library which allows required initialization of
this
controller. This library executes out of the XIP NOR flash mememory.
Signed-off-by: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com
Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h | 190
+++++++++++++++++++++
Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c | 188
++++++++++++++++++++
Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf | 41 +++++ 3 files changed, 419 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c create mode 100644
Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf
diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h
Please declare this library class in the [LibraryClasses] section of the package .dec file
new file mode 100644 index 0000000..0d715fb --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h @@ -0,0 +1,190 @@ +/** @Ddr.h
- Header defining the Ddr controller constants (Base addresses,
+sizes, flags),
- function prototype, structures etc
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
- This program and the accompanying materials are licensed and made
- available under the terms and conditions of the BSD License which
- accompanies this distribution. The full text of the license may be
- found at http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
- BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
+**/
+#ifndef __DDR_H__ +#define __DDR_H__
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PlatformLib.h>
+/* DDR4 fixed timing */ +#define LS1043A_CS0_BNDS 0x0000007f /* 0x000 */ +#define LS1043A_CS0_CONFIG 0x80010322 /* 0x080 */ +#define LS1043A_TIMING_CFG_3 0x020C1000 /* 0x100 */ +#define LS1043A_TIMING_CFG_0 0xD0550018 /* 0x104 */ +#define LS1043A_TIMING_CFG_1 0xC2C68C42 /* 0x108 */ +#define LS1043A_TIMING_CFG_2 0x0048C114 /* 0x10c */ +#define LS1043A_DDR_SDRAM_CFG 0x450C000C /* 0x110 */ +#define LS1043A_DDR_SDRAM_CFG_2 0x00401010 /* 0x114 */ +#define LS1043A_DDR_SDRAM_MODE 0x01010214 /* 0x118 */ +#define LS1043A_DDR_SDRAM_INTERVAL 0x18600618 /* 0x124 */ +#define LS1043A_DDR_SDRAM_CLK_CNTL 0x02000000 /* 0x130 */ +#define LS1043A_TIMING_CFG_4 0x00000002 /* 0x160 */ +#define LS1043A_TIMING_CFG_5 0x04401400 /* 0x164 */ +#define LS1043A_TIMING_CFG_7 0x13300000 /* 0x16c */ +#define LS1043A_DDR_ZQ_CNTL 0x8A090705 /* 0x170 */ +#define LS1043A_DDR_WRLVL_CNTL 0x8655F606 /* 0x174 */ +#define LS1043A_DDR_WRLVL_CNTL_2 0x05070600 /* 0x190 */ +#define LS1043A_DDR_SDRAM_MODE_9 0x00000400 /* 0x220 */ +#define LS1043A_DDR_SDRAM_MODE_10 0x04000000 /* 0x224 */ +#define LS1043A_TIMING_CFG_8 0x03115600 /* 0x250 */ +#define LS1043A_DDRCDR_1 0x80040000 /* 0xb28 */ +#define LS1043A_DDRCDR_2 0x0000A181 /* 0xb2c */
+#define LS1043A_DDR_SDRAM_CFG_MEM_EN 0x80000000
+/**
- DDR memory controller registers
+**/ +struct CcsrDdr {
- UINT32 Cs0Bnds; /** Chip Select 0 Memory
Bounds */
- CHAR8 Res04[4];
- UINT32 Cs1Bnds; /** Chip Select 1 Memory
Bounds */
- CHAR8 Res0c[4];
- UINT32 Cs2Bnds; /** Chip Select 2 Memory
Bounds */
- CHAR8 Res14[4];
- UINT32 Cs3Bnds; /** Chip Select 3 Memory
Bounds */
- CHAR8 Res1c[100];
- UINT32 Cs0Config; /** Chip Select Configuration
*/
- UINT32 Cs1Config; /** Chip Select Configuration
*/
- UINT32 Cs2Config; /** Chip Select Configuration
*/
- UINT32 Cs3Config; /** Chip Select Configuration
*/
- CHAR8 Res90[48];
- UINT32 Cs0Config2; /** Chip Select Configuration
2 */
- UINT32 Cs1Config2; /** Chip Select Configuration
2 */
- UINT32 Cs2Config2; /** Chip Select Configuration
2 */
- UINT32 Cs3Config2; /** Chip Select Configuration
2 */
- CHAR8 Resd0[48];
- UINT32 TimingCfg3; /** SDRAM Timing
Configuration 3 */
- UINT32 TimingCfg0; /** SDRAM Timing
Configuration 0 */
- UINT32 TimingCfg1; /** SDRAM Timing
Configuration 1 */
- UINT32 TimingCfg2; /** SDRAM Timing
Configuration 2 */
- UINT32 SdramCfg; /** SDRAM Control
Configuration */
- UINT32 SdramCfg2; /** SDRAM Control
Configuration 2 */
- UINT32 SdramMode; /** SDRAM Mode Configuration
*/
- UINT32 SdramMode2; /** SDRAM Mode Configuration
2 */
- UINT32 SdramMdCntl; /** SDRAM Mode Control */
- UINT32 SdramInterval; /** SDRAM Interval Configuration */
- UINT32 SdramDataInit; /** SDRAM Data initialization */
- CHAR8 Res12c[4];
- UINT32 SdramClkCntl; /** SDRAM Clock Control */
- CHAR8 Res134[20];
- UINT32 InitAddr; /** training init addr */
- UINT32 InitExtAddr; /** training init extended
addr */
- CHAR8 Res150[16];
- UINT32 TimingCfg4; /** SDRAM Timing
Configuration 4 */
- UINT32 TimingCfg5; /** SDRAM Timing
Configuration 5 */
- UINT32 TimingCfg6; /** SDRAM Timing
Configuration 6 */
- UINT32 TimingCfg7; /** SDRAM Timing
Configuration 7 */
- UINT32 DdrZqCntl; /** ZQ calibration control*/
- UINT32 DdrWrlvlCntl; /** write leveling control*/
- CHAR8 Reg178[4];
- UINT32 DdrSrCntr; /** self refresh counter */
- UINT32 DdrSdramRcw1; /** Control Words 1 */
- UINT32 DdrSdramRcw2; /** Control Words 2 */
- CHAR8 Reg188[8];
- UINT32 DdrWrlvlCntl2; /** write leveling control 2 */
- UINT32 DdrWrlvlCntl3; /** write leveling control 3 */
- CHAR8 Res198[8];
- UINT32 DdrSdramRcw3;
- UINT32 DdrSdramRcw4;
- UINT32 DdrSdramRcw5;
- UINT32 DdrSdramRcw6;
- CHAR8 Res1b0[80];
- UINT32 SdramMode3; /** SDRAM Mode Configuration
3 */
- UINT32 SdramMode4; /** SDRAM Mode Configuration
4 */
- UINT32 SdramMode5; /** SDRAM Mode Configuration
5 */
- UINT32 SdramMode6; /** SDRAM Mode Configuration
6 */
- UINT32 SdramMode7; /** SDRAM Mode Configuration
7 */
- UINT32 SdramMode8; /** SDRAM Mode Configuration
8 */
- CHAR8 Res218[8];
- UINT32 SdramMode9; /** SDRAM Mode Configuration
9 */
- UINT32 SdramMode10; /** SDRAM Mode Configuration
10 */
- UINT32 SdramMode11; /** SDRAM Mode Configuration
11 */
- UINT32 SdramMode12; /** SDRAM Mode Configuration
12 */
- UINT32 SdramMode13; /** SDRAM Mode Configuration
13 */
- UINT32 SdramMode14; /** SDRAM Mode Configuration
14 */
- UINT32 SdramMode15; /** SDRAM Mode Configuration
15 */
- UINT32 SdramMode16; /** SDRAM Mode Configuration
16 */
- CHAR8 Res240[16];
- UINT32 TimingCfg8; /* SDRAM Timing Configuration 8 */
- CHAR8 Res254[12];
- UINT32 SdramCfg3;
- CHAR8 Res264[412];
- UINT32 DqMap0;
- UINT32 DqMap1;
- UINT32 DqMap2;
- UINT32 DqMap3;
- CHAR8 Res410[1808];
- UINT32 DdrDsr1; /** Debug Status 1 */
- UINT32 DdrDsr2; /** Debug Status 2 */
- UINT32 DdrCdr1; /** Control Driver 1 */
- UINT32 DdrCdr2; /** Control Driver 2 */
- CHAR8 ResB30[200];
- UINT32 IpRev1; /** IP Block Revision 1 */
- UINT32 IpRev2; /** IP Block Revision 2 */
- UINT32 Eor; /** Enhanced Optimization
Register */
- CHAR8 ResC04[252];
- UINT32 Mtcr; /** Memory Test Control
Register */
- CHAR8 ResD04[28];
- UINT32 Mtp1; /** Memory Test Pattern 1 */
- UINT32 Mtp2; /** Memory Test Pattern 2 */
- UINT32 Mtp3; /** Memory Test Pattern 3 */
- UINT32 Mtp4; /** Memory Test Pattern 4 */
- UINT32 Mtp5; /** Memory Test Pattern 5 */
- UINT32 Mtp6; /** Memory Test Pattern 6 */
- UINT32 Mtp7; /** Memory Test Pattern 7 */
- UINT32 Mtp8; /** Memory Test Pattern 8 */
- UINT32 Mtp9; /** Memory Test Pattern 9 */
- UINT32 Mtp10; /** Memory Test Pattern 10 */
- CHAR8 ResD48[184];
- UINT32 DataErrInjectHi; /** Data Path Err Injection
Mask High */
- UINT32 DataErrInjectLo; /** Data Path Err Injection
Mask Low */
- UINT32 EccErrInject; /** Data Path Err Injection
Mask ECC */
- CHAR8 ResE0c[20];
- UINT32 CaptureDataHi; /** Data Path Read Capture High */
- UINT32 CaptureDataLo; /** Data Path Read Capture Low */
- UINT32 CaptureEcc; /** Data Path Read Capture
ECC */
- CHAR8 ResE2c[20];
- UINT32 ErrDetect; /** Error Detect */
- UINT32 ErrDisable; /** Error Disable */
- UINT32 ErrIntEn;
- UINT32 CaptureAttributes; /** Error Attrs Capture */
- UINT32 CaptureAddress; /** Error Addr Capture */
- UINT32 CaptureExtAddress; /** Error Extended Addr
Capture */
- UINT32 ErrSbe; /** Single-Bit ECC Error Management
*/
- CHAR8 ResE5c[164];
- UINT32 Debug[32]; /** Debug_1 to Debug_32 */
- CHAR8 ResF80[128];
+};
+/**
- Main function to initialize DDR
- **/
+VOID +DramInit(
- );
+/**
- Function to dump DDRC registers
+**/ +VOID +DdrRegDump (
- VOID
- );
+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c new file mode 100644 index 0000000..1c33de4 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c @@ -0,0 +1,188 @@ +/** @DdrLib.c
- Ddr Library containing functions to initialize ddr controller
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
- This program and the accompanying materials are licensed and made
- available under the terms and conditions of the BSD License which
- accompanies this distribution. The full text of the license may be
- found at http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
- BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
+**/
+#include <Library/Ddr.h> +#include <Library/BaseLib.h>
+#define Uswap32(X) \
((((X) & 0xff000000) >> 24) | \(((X) & 0x00ff0000) >> 8) | \(((X) & 0x0000ff00) << 8) | \(((X) & 0x000000ff) << 24))+#define DDRMC_DELAY 10000
+/**
- Function to dump DDRC registers
+**/
+VOID +DdrRegDump (
- VOID
- )
+{
- struct CcsrDdr *Ddr = (VOID *)LS1043A_DDR_ADDR;
- DEBUG((EFI_D_INFO, "Cs0Bnds =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Bnds)));
- DEBUG((EFI_D_INFO, "Cs1Bnds =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Bnds)));
- DEBUG((EFI_D_INFO, "Cs2Bnds =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Bnds)));
- DEBUG((EFI_D_INFO, "Cs3Bnds =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Bnds)));
- DEBUG((EFI_D_INFO, "Cs0Config =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config)));
- DEBUG((EFI_D_INFO, "Cs1Config =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config)));
- DEBUG((EFI_D_INFO, "Cs2Config =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config)));
- DEBUG((EFI_D_INFO, "Cs3Config =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config)));
- DEBUG((EFI_D_INFO, "Cs0Config2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config2)));
- DEBUG((EFI_D_INFO, "Cs1Config2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config2)));
- DEBUG((EFI_D_INFO, "Cs2Config2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config2)));
- DEBUG((EFI_D_INFO, "Cs3Config2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config2)));
- DEBUG((EFI_D_INFO, "TimingCfg3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg3)));
- DEBUG((EFI_D_INFO, "TimingCfg0 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg0)));
- DEBUG((EFI_D_INFO, "TimingCfg1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg1)));
- DEBUG((EFI_D_INFO, "TimingCfg2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg2)));
- DEBUG((EFI_D_INFO, "SdramCfg =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg)));
- DEBUG((EFI_D_INFO, "SdramCfg2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg2)));
- DEBUG((EFI_D_INFO, "SdramMode =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode)));
- DEBUG((EFI_D_INFO, "SdramMode2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode2)));
- DEBUG((EFI_D_INFO, "SdramMdCntl =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMdCntl)));
- DEBUG((EFI_D_INFO, "SdramInterval =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramInterval)));
- DEBUG((EFI_D_INFO, "SdramDataInit =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramDataInit)));
- DEBUG((EFI_D_INFO, "SdramClkCntl =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramClkCntl)));
- DEBUG((EFI_D_INFO, "InitAddr =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->InitAddr)));
- DEBUG((EFI_D_INFO, "InitExtAddr =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->InitExtAddr)));
- DEBUG((EFI_D_INFO, "TimingCfg4 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg4)));
- DEBUG((EFI_D_INFO, "TimingCfg5 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg5)));
- DEBUG((EFI_D_INFO, "TimingCfg6 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg6)));
- DEBUG((EFI_D_INFO, "TimingCfg7 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg7)));
- DEBUG((EFI_D_INFO, "DdrZqCntl =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrZqCntl)));
- DEBUG((EFI_D_INFO, "DdrWrlvlCntl =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl)));
- DEBUG((EFI_D_INFO, "DdrSrCntr =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSrCntr)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw1)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw2)));
- DEBUG((EFI_D_INFO, "DdrWrlvlCntl2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl2)));
- DEBUG((EFI_D_INFO, "DdrWrlvlCntl3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl3)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw3)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw4 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw4)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw5 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw5)));
- DEBUG((EFI_D_INFO, "DdrSdramRcw6 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw6)));
- DEBUG((EFI_D_INFO, "SdramMode3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode3)));
- DEBUG((EFI_D_INFO, "SdramMode4 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode4)));
- DEBUG((EFI_D_INFO, "SdramMode5 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode5)));
- DEBUG((EFI_D_INFO, "SdramMode6 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode6)));
- DEBUG((EFI_D_INFO, "SdramMode7 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode7)));
- DEBUG((EFI_D_INFO, "SdramMode8 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode8)));
- DEBUG((EFI_D_INFO, "SdramMode9 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode9)));
- DEBUG((EFI_D_INFO, "SdramMode10 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode10)));
- DEBUG((EFI_D_INFO, "SdramMode11 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode11)));
- DEBUG((EFI_D_INFO, "SdramMode12 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode12)));
- DEBUG((EFI_D_INFO, "SdramMode13 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode13)));
- DEBUG((EFI_D_INFO, "SdramMode14 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode14)));
- DEBUG((EFI_D_INFO, "SdramMode15 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode15)));
- DEBUG((EFI_D_INFO, "SdramMode16 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode16)));
- DEBUG((EFI_D_INFO, "TimingCfg8 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg8)));
- DEBUG((EFI_D_INFO, "SdramCfg3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg3)));
- DEBUG((EFI_D_INFO, "DqMap0 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap0)));
- DEBUG((EFI_D_INFO, "DqMap1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap1)));
- DEBUG((EFI_D_INFO, "DqMap2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap2)));
- DEBUG((EFI_D_INFO, "DqMap3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap3)));
- DEBUG((EFI_D_INFO, "DdrDsr1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr1)));
- DEBUG((EFI_D_INFO, "DdrDsr2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr2)));
- DEBUG((EFI_D_INFO, "DdrCdr1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr1)));
- DEBUG((EFI_D_INFO, "DdrCdr2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr2)));
- DEBUG((EFI_D_INFO, "IpRev1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev1)));
- DEBUG((EFI_D_INFO, "IpRev2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev2)));
- DEBUG((EFI_D_INFO, "Eor = 0x%x\n",MmioReadBe32((UINTN)&Ddr-
Eor)));
- DEBUG((EFI_D_INFO, "Mtcr =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtcr)));
- DEBUG((EFI_D_INFO, "Mtp1 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp1)));
- DEBUG((EFI_D_INFO, "Mtp2 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp2)));
- DEBUG((EFI_D_INFO, "Mtp3 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp3)));
- DEBUG((EFI_D_INFO, "Mtp4 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp4)));
- DEBUG((EFI_D_INFO, "Mtp5 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp5)));
- DEBUG((EFI_D_INFO, "Mtp6 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp6)));
- DEBUG((EFI_D_INFO, "Mtp7 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp7)));
- DEBUG((EFI_D_INFO, "Mtp8 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp8)));
- DEBUG((EFI_D_INFO, "Mtp9 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp9)));
- DEBUG((EFI_D_INFO, "Mtp10 =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp10)));
- DEBUG((EFI_D_INFO, "DataErrInjectHi =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectHi)));
- DEBUG((EFI_D_INFO, "DataErrInjectLo =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectLo)));
- DEBUG((EFI_D_INFO, "EccErrInject =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->EccErrInject)));
- DEBUG((EFI_D_INFO, "CaptureDataHi =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataHi)));
- DEBUG((EFI_D_INFO, "CaptureDataLo =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataLo)));
- DEBUG((EFI_D_INFO, "CaptureEcc =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureEcc)));
- DEBUG((EFI_D_INFO, "ErrDetect =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDetect)));
- DEBUG((EFI_D_INFO, "ErrDisable =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDisable)));
- DEBUG((EFI_D_INFO, "ErrIntEn =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrIntEn)));
- DEBUG((EFI_D_INFO, "CaptureAttributes =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAttributes)));
- DEBUG((EFI_D_INFO, "CaptureAddress =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAddress)));
- DEBUG((EFI_D_INFO, "CaptureExtAddress =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureExtAddress)));
- DEBUG((EFI_D_INFO, "ErrSbe =
+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrSbe)));
- DEBUG((EFI_D_ERROR,"\n"));
+}
+/**
- Function to initialize DDR
- **/
+VOID +DramInit (
- )
+{
- struct CcsrDdr *Ddr;
UINT32 Count, Delay = DDRMC_DELAY;- Ddr = (VOID *)LS1043A_DDR_ADDR;
- MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG);
Where is MmioWriteBe32() defined?
I sent a separate patch for ARM IoLib on EDK2 mailing list where we added the support for MmioWriteBe32: https://lists.01.org/pipermail/edk2-devel/2016-October/002791.html
Now that the discussion seems concluded, I will change the patch accordingly.
- MmioWriteBe32((UINTN)&Ddr->Cs0Bnds, LS1043A_CS0_BNDS);
- MmioWriteBe32((UINTN)&Ddr->Cs0Config, LS1043A_CS0_CONFIG);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg0, LS1043A_TIMING_CFG_0);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg1, LS1043A_TIMING_CFG_1);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg2, LS1043A_TIMING_CFG_2);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg3, LS1043A_TIMING_CFG_3);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg4, LS1043A_TIMING_CFG_4);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg5, LS1043A_TIMING_CFG_5);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg7, LS1043A_TIMING_CFG_7);
- MmioWriteBe32((UINTN)&Ddr->TimingCfg8, LS1043A_TIMING_CFG_8);
- MmioWriteBe32((UINTN)&Ddr->SdramCfg2, LS1043A_DDR_SDRAM_CFG_2);
- MmioWriteBe32((UINTN)&Ddr->SdramMode, LS1043A_DDR_SDRAM_MODE);
- MmioWriteBe32((UINTN)&Ddr->SdramMode2, 0);
- MmioWriteBe32((UINTN)&Ddr->SdramInterval,
- LS1043A_DDR_SDRAM_INTERVAL);
- MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl, LS1043A_DDR_WRLVL_CNTL);
- MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl2,
LS1043A_DDR_WRLVL_CNTL_2);
- MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl3, 0);
- MmioWriteBe32((UINTN)&Ddr->DdrCdr1, LS1043A_DDRCDR_1);
- MmioWriteBe32((UINTN)&Ddr->DdrCdr2, LS1043A_DDRCDR_2);
- MmioWriteBe32((UINTN)&Ddr->SdramClkCntl,
- LS1043A_DDR_SDRAM_CLK_CNTL);
- MmioWriteBe32((UINTN)&Ddr->DdrZqCntl, LS1043A_DDR_ZQ_CNTL);
- MmioWriteBe32((UINTN)&Ddr->SdramMode9, LS1043A_DDR_SDRAM_MODE_9);
- MmioWriteBe32((UINTN)&Ddr->SdramMode10, LS1043A_DDR_SDRAM_MODE_10);
- MmioWriteBe32((UINTN)&Ddr->Cs0Config2, 0);
- for(Count = 0; Count < Delay; Count++)
;- MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG
| LS1043A_DDR_SDRAM_CFG_MEM_EN);- return;
No 'return's add the end of void functions please
Ok.
+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf new file mode 100644 index 0000000..e8e3aed --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf @@ -0,0 +1,41 @@ +#/** DdrLib.inf +# +# Component description file for DdrLib module # # Copyright (c) +2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials # are licensed and +made available under the terms and conditions of the BSD License # +which accompanies this distribution. The full text of the license +may be found at # http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
+# +#**/
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DdrLib
- FILE_GUID = 8ecefc8f-a2c4-4091-b31f-
20f7aeb0567f
Please use a fresh GUID
Ok.
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = DdrLib
+[Sources.common]
- DdrLib.c
+[LibraryClasses]
- ArmLib
- IoLib
- BaseMemoryLib
- BaseLib
- SocLib
+[Packages]
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec
- OpenPlatformPkg/Chips/Nxp/QoriqLs/NxpQoriqLs.dec
-- 1.9.1
Regards, Bhupesh