On 07/14/2016 09:16 AM, Ard Biesheuvel wrote:
On 14 July 2016 at 15:58, Jeremy Linton jeremy.linton@arm.com wrote:
The AXI<->PCIe translation comments are out of date with respect to the code. In the first case the AXI master port is incorrectly called a slave. In the second case the the translation direction indicated for the slave port is the wrong direction.
Correct both of these comments to reflect what the code is doing.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton jeremy.linton@arm.com
ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 0c7881d..d134cc4 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -84,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID));
//
- // PCIE Window 0 -> AXI4 Slave 0 Address Translations
- // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0;
@@ -101,7 +101,7 @@ HWPciRbInit ( ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY);
//
- // PCIE Window 0 -> AXI4 Slave 0 Address Translations
- // AXI4 Slave 0 -> PCIE Window 0 Address Translations // TranslationTable = VEXPRESS_ATR_AXI4_SLV1;
Slave 0 or slave 1?
Slave 1, I actually was just talking to Leif about tweaking it before committing it.