Re: [Linaro-uefi] [edk2] [PATCH] OpenPlatformPkg/MarvellYukonDxe : Marvell Yukon driver

5 May 2016

Hi Ryan,
Thanks for your comments. This PCD variable has been declared outside of 
OpenPlatformPkg. I'll move it to the correct location in the next 
version of patch.
Thanks,
Daniil
On 05/04/2016 10:41 AM, Ryan Harkin wrote:
...
Hi Daniil,
On 4 May 2016 at 02:48, Daniil Egranov daniil.egranov@arm.com wrote:
...
The UEFI driver for Marvell Yukon chipset
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov daniil.egranov@arm.com

On the Juno platform, this driver requires another platform-specific patch
initializing the Marvell network adapter with correct MAC address.
Without the patch, the PcdYukonMacAddressvariable has to be set.
I guess there is also another patch needed to the generic code to add
your new PCD?
I get this compilation failure:
/working/platforms/uefi/edk2/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf(67):
error 3000: PCD [gEmbeddedTokenSpaceGuid.PcdYukonMacAddress] in
[/working/platforms/uefi/edk2/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf]
is not found in dependent packages:
         /working/platforms/uefi/edk2/EmbeddedPkg/EmbeddedPkg.dec
     /working/platforms/uefi/edk2/NetworkPkg/NetworkPkg.dec
     /working/platforms/uefi/edk2/MdeModulePkg/MdeModulePkg.dec
     /working/platforms/uefi/edk2/MdePkg/MdePkg.dec
...
Drivers/Net/MarvellYukonDxe/ComponentName.c     |  313 +++
  Drivers/Net/MarvellYukonDxe/DriverBinding.c     |  431 ++++
  Drivers/Net/MarvellYukonDxe/MarvellYukon.h      |  735 ++++++
  Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf |   81 +
  Drivers/Net/MarvellYukonDxe/Snp.c               | 1474 +++++++++++
  Drivers/Net/MarvellYukonDxe/e1000phy.c          |  659 +++++
  Drivers/Net/MarvellYukonDxe/e1000phyreg.h       |  398 +++
  Drivers/Net/MarvellYukonDxe/if_media.h          |  273 +++
  Drivers/Net/MarvellYukonDxe/if_msk.c            | 2982 +++++++++++++++++++++++
  Drivers/Net/MarvellYukonDxe/if_msk.h            |   52 +
  Drivers/Net/MarvellYukonDxe/if_mskreg.h         | 2491 +++++++++++++++++++
  Drivers/Net/MarvellYukonDxe/miivar.h            |  198 ++
  Platforms/ARM/Juno/ArmJuno.dsc                  |    9 +
  Platforms/ARM/Juno/ArmJuno.fdf                  |    1 +
Maybe you could keep the driver and the Juno patches separate and add
the Juno mods along with the patch to read the MAC address?
Cheers,
Ryan.
...
14 files changed, 10097 insertions(+)
  create mode 100644 Drivers/Net/MarvellYukonDxe/ComponentName.c
  create mode 100644 Drivers/Net/MarvellYukonDxe/DriverBinding.c
  create mode 100644 Drivers/Net/MarvellYukonDxe/MarvellYukon.h
  create mode 100644 Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
  create mode 100644 Drivers/Net/MarvellYukonDxe/Snp.c
  create mode 100644 Drivers/Net/MarvellYukonDxe/e1000phy.c
  create mode 100644 Drivers/Net/MarvellYukonDxe/e1000phyreg.h
  create mode 100644 Drivers/Net/MarvellYukonDxe/if_media.h
  create mode 100644 Drivers/Net/MarvellYukonDxe/if_msk.c
  create mode 100644 Drivers/Net/MarvellYukonDxe/if_msk.h
  create mode 100644 Drivers/Net/MarvellYukonDxe/if_mskreg.h
  create mode 100644 Drivers/Net/MarvellYukonDxe/miivar.h

diff --git a/Drivers/Net/MarvellYukonDxe/ComponentName.c b/Drivers/Net/MarvellYukonDxe/ComponentName.c
new file mode 100644
index 0000000..2c5251f
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/ComponentName.c
@@ -0,0 +1,313 @@
+/**
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+#include "MarvellYukon.h"



+//
+// EFI Component Name Functions
+//
+/**

Retrieves a Unicode string that is the user readable name of the driver.

This function retrieves the user readable name of a driver in the form of a
Unicode string. If the driver specified by This has a user readable name in
the language specified by Language, then a pointer to the driver name is
returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
by This does not support the language specified by Language,
then EFI_UNSUPPORTED is returned.

<at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
                                 EFI_COMPONENT_NAME_PROTOCOL instance.



<at> param  Language[in]           A pointer to a Null-terminated ASCII string
                                 array indicating the language. This is the


                                 language of the driver name that the caller is


                                 requesting, and it must match one of the


                                 languages specified in SupportedLanguages. The


                                 number of languages supported by a driver is up


                                 to the driver writer. Language is specified


                                 in RFC 4646 or ISO 639-2 language code format.



<at> param  DriverName[out]        A pointer to the Unicode string to return.
                                 This Unicode string is the name of the


                                 driver specified by This in the language


                                 specified by Language.



<at> retval EFI_SUCCESS            The Unicode string for the Driver specified by
                                 This and the language specified by Language was


                                 returned in DriverName.



<at> retval EFI_INVALID_PARAMETER  Language is NULL.

<at> retval EFI_INVALID_PARAMETER  DriverName is NULL.

<at> retval EFI_UNSUPPORTED        The driver specified by This does not support
                                 the language specified by Language.




+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetDriverName (

IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
IN  CHAR8                        *Language,
OUT CHAR16                       **DriverName
);



+/**

Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.

This function retrieves the user readable name of the controller specified by
ControllerHandle and ChildHandle in the form of a Unicode string. If the
driver specified by This has a user readable name in the language specified by
Language, then a pointer to the controller name is returned in ControllerName,
and EFI_SUCCESS is returned.  If the driver specified by This is not currently
managing the controller specified by ControllerHandle and ChildHandle,
then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
support the language specified by Language, then EFI_UNSUPPORTED is returned.

<at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
                                 EFI_COMPONENT_NAME_PROTOCOL instance.



<at> param  ControllerHandle[in]   The handle of a controller that the driver
                                 specified by This is managing.  This handle


                                 specifies the controller whose name is to be


                                 returned.



<at> param  ChildHandle[in]        The handle of the child controller to retrieve
                                 the name of.  This is an optional parameter that


                                 may be NULL.  It will be NULL for device


                                 drivers.  It will also be NULL for a bus drivers


                                 that wish to retrieve the name of the bus


                                 controller.  It will not be NULL for a bus


                                 driver that wishes to retrieve the name of a


                                 child controller.



<at> param  Language[in]           A pointer to a Null-terminated ASCII string
                                 array indicating the language.  This is the


                                 language of the driver name that the caller is


                                 requesting, and it must match one of the


                                 languages specified in SupportedLanguages. The


                                 number of languages supported by a driver is up


                                 to the driver writer. Language is specified in


                                 RFC 4646 or ISO 639-2 language code format.



<at> param  ControllerName[out]    A pointer to the Unicode string to return.
                                 This Unicode string is the name of the


                                 controller specified by ControllerHandle and


                                 ChildHandle in the language specified by


                                 Language from the point of view of the driver


                                 specified by This.



<at> retval EFI_SUCCESS            The Unicode string for the user readable name in
                                 the language specified by Language for the


                                 driver specified by This was returned in


                                 DriverName.



<at> retval EFI_INVALID_PARAMETER  ControllerHandle is not a valid EFI_HANDLE.

<at> retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid
                                 EFI_HANDLE.



<at> retval EFI_INVALID_PARAMETER  Language is NULL.

<at> retval EFI_INVALID_PARAMETER  ControllerName is NULL.

<at> retval EFI_UNSUPPORTED        The driver specified by This is not currently
                                 managing the controller specified by


                                 ControllerHandle and ChildHandle.



<at> retval EFI_UNSUPPORTED        The driver specified by This does not support
                                 the language specified by Language.




+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetControllerName (

IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
IN  EFI_HANDLE                                      ControllerHandle,
IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
IN  CHAR8                                           *Language,
OUT CHAR16                                          **ControllerName
);



+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gSimpleNetworkComponentName = {

SimpleNetworkComponentNameGetDriverName,
SimpleNetworkComponentNameGetControllerName,
"eng"

+};



+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSimpleNetworkComponentName2 = {

(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SimpleNetworkComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SimpleNetworkComponentNameGetControllerName,
"en"

+};




+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSimpleNetworkDriverNameTable[] = {

{
"eng;en",
L"Marvell Yukon Simple Network Protocol Driver"
},
{
NULL,
NULL
}

+};



+/**

Retrieves a Unicode string that is the user readable name of the driver.

This function retrieves the user readable name of a driver in the form of a
Unicode string. If the driver specified by This has a user readable name in
the language specified by Language, then a pointer to the driver name is
returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
by This does not support the language specified by Language,
then EFI_UNSUPPORTED is returned.

<at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
                                 EFI_COMPONENT_NAME_PROTOCOL instance.



<at> param  Language[in]           A pointer to a Null-terminated ASCII string
                                 array indicating the language. This is the


                                 language of the driver name that the caller is


                                 requesting, and it must match one of the


                                 languages specified in SupportedLanguages. The


                                 number of languages supported by a driver is up


                                 to the driver writer. Language is specified


                                 in RFC 4646 or ISO 639-2 language code format.



<at> param  DriverName[out]        A pointer to the Unicode string to return.
                                 This Unicode string is the name of the


                                 driver specified by This in the language


                                 specified by Language.



<at> retval EFI_SUCCESS            The Unicode string for the Driver specified by
                                 This and the language specified by Language was


                                 returned in DriverName.



<at> retval EFI_INVALID_PARAMETER  Language is NULL.

<at> retval EFI_INVALID_PARAMETER  DriverName is NULL.

<at> retval EFI_UNSUPPORTED        The driver specified by This does not support
                                 the language specified by Language.




+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetDriverName (

IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
IN  CHAR8                        *Language,
OUT CHAR16                       **DriverName
)

+{

return LookupUnicodeString2 (
   Language,


   This->SupportedLanguages,


   mSimpleNetworkDriverNameTable,


   DriverName,


   (BOOLEAN)(This == &gSimpleNetworkComponentName)


   );



+}



+/**

Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.

This function retrieves the user readable name of the controller specified by
ControllerHandle and ChildHandle in the form of a Unicode string. If the
driver specified by This has a user readable name in the language specified by
Language, then a pointer to the controller name is returned in ControllerName,
and EFI_SUCCESS is returned.  If the driver specified by This is not currently
managing the controller specified by ControllerHandle and ChildHandle,
then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
support the language specified by Language, then EFI_UNSUPPORTED is returned.
Currently not implemented.

<at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL
                                 or EFI_COMPONENT_NAME_PROTOCOL instance.



<at> param  ControllerHandle[in]   The handle of a controller that the driver
                                 specified by This is managing.  This handle


                                 specifies the controller whose name is to be


                                 returned.



<at> param  ChildHandle[in]        The handle of the child controller to retrieve
                                 the name of.  This is an optional parameter that


                                 may be NULL.  It will be NULL for device


                                 drivers.  It will also be NULL for a bus drivers


                                 that wish to retrieve the name of the bus


                                 controller.  It will not be NULL for a bus


                                 driver that wishes to retrieve the name of a


                                 child controller.



<at> param  Language[in]           A pointer to a Null-terminated ASCII string
                                 array indicating the language.  This is the


                                 language of the driver name that the caller is


                                 requesting, and it must match one of the


                                 languages specified in SupportedLanguages. The


                                 number of languages supported by a driver is up


                                 to the driver writer. Language is specified in


                                 RFC 4646 or ISO 639-2 language code format.



<at> param  ControllerName[out]    A pointer to the Unicode string to return.
                                 This Unicode string is the name of the


                                 controller specified by ControllerHandle and


                                 ChildHandle in the language specified by


                                 Language from the point of view of the driver


                                 specified by This.



<at> retval EFI_SUCCESS            The Unicode string for the user readable name in
                                 the language specified by Language for the


                                 driver specified by This was returned in


                                 DriverName.



<at> retval EFI_INVALID_PARAMETER  ControllerHandle is not a valid EFI_HANDLE.

<at> retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid
                                 EFI_HANDLE.



<at> retval EFI_INVALID_PARAMETER  Language is NULL.

<at> retval EFI_INVALID_PARAMETER  ControllerName is NULL.

<at> retval EFI_UNSUPPORTED        The driver specified by This is not currently
                                 managing the controller specified by


                                 ControllerHandle and ChildHandle.



<at> retval EFI_UNSUPPORTED        The driver specified by This does not support
                                 the language specified by Language.




+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetControllerName (

IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
IN  EFI_HANDLE                                      ControllerHandle,
IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
IN  CHAR8                                           *Language,
OUT CHAR16                                          **ControllerName
)

+{

return EFI_UNSUPPORTED;

+}
diff --git a/Drivers/Net/MarvellYukonDxe/DriverBinding.c b/Drivers/Net/MarvellYukonDxe/DriverBinding.c
new file mode 100644
index 0000000..6410817
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/DriverBinding.c
@@ -0,0 +1,431 @@
+/**  <at> file

Implementation of driver entry point and driver binding protocol.


+Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.



+This program and the accompanying materials are licensed
+and made available under the terms and conditions of the BSD License which
+accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php



+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.



+**/



+#include "MarvellYukon.h"
+#include "if_msk.h"
+#include <Library/NetLib.h>
+#include <Library/DevicePathLib.h>



+/**

Test to see if this driver supports ControllerHandle. This service
is called by the EFI boot service ConnectController(). In
order to make drivers as small as possible, there are a few calling
restrictions for this service. ConnectController() must
follow these calling restrictions. If any other agent wishes to call
Supported() it must also follow these calling restrictions.

<at> param  This                   Protocol instance pointer.
<at> param  ControllerHandle       Handle of device to test.
<at> param  RemainingDevicePath    Optional parameter use to pick a specific child
                                                        device to start.



<at> retval EFI_SUCCESS            This driver supports this device.
<at> retval EFI_ALREADY_STARTED    This driver is already running on this device.
<at> retval other                  This driver does not support this device.


+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverSupported (

IN EFI_DRIVER_BINDING_PROTOCOL    *This,
IN EFI_HANDLE                     Controller,
IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
)

+{

EFI_STATUS              Status;
EFI_PCI_IO_PROTOCOL     *PciIo;

//
// Test that the PCI IO Protocol is attached to the controller handle and no other driver is consuming it
//
Status = gBS->OpenProtocol (
   Controller,


   &gEfiPciIoProtocolGuid,


   (VOID **) &PciIo,


   This->DriverBindingHandle,


   Controller,


   EFI_OPEN_PROTOCOL_BY_DRIVER


   );



if (!EFI_ERROR (Status)) {
//
// Test whether the controller is on a supported NIC
//
Status = mskc_probe (PciIo);
if (EFI_ERROR (Status)) {
 Status = EFI_UNSUPPORTED;


}

gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     This->DriverBindingHandle,


     Controller


     );



DEBUG ((EFI_D_INFO, "Marvell Yukon: MarvellYukonDriverSupported: Status = %d, Controller = %p\n", Status, Controller));
}

return Status;

+}



+/**

Start this driver on Controller by opening PciIo and DevicePath protocols.
Initialize PXE structures, create a copy of the Controller Device Path with the
NIC's MAC address appended to it, install the NetworkInterfaceIdentifier protocol
on the newly created Device Path.

@param [in] pThis                   Protocol instance pointer.
@param [in] Controller              Handle of device to work with.
@param [in] pRemainingDevicePath    Not used, always produce all possible children.

@retval EFI_SUCCESS                 This driver is added to Controller.
@retval other                       This driver does not support this device.


+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverStart (

IN EFI_DRIVER_BINDING_PROTOCOL * pThis,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL * pRemainingDevicePath
)

+{


EFI_STATUS                       Status;
UINTN                            LengthInBytes;
EFI_DEVICE_PATH_PROTOCOL         *ParentDevicePath = NULL;
MAC_ADDR_DEVICE_PATH             MacDeviceNode;

YUKON_DRIVER    *YukonDriver;

LengthInBytes = sizeof ( *YukonDriver );
YukonDriver = (YUKON_DRIVER *)AllocateZeroPool (sizeof (YUKON_DRIVER));
if (YukonDriver == NULL) {
return EFI_OUT_OF_RESOURCES;
}

EfiInitializeLock (&YukonDriver->Lock, TPL_NOTIFY);

//
//  Set the structure signature
//
ZeroMem ( YukonDriver, LengthInBytes );
YukonDriver->Signature = YUKON_DRIVER_SIGNATURE;

Status = gBS->OpenProtocol (
   Controller,


   &gEfiPciIoProtocolGuid,


   (VOID **) &YukonDriver->PciIo,


   pThis->DriverBindingHandle,


   Controller,


   EFI_OPEN_PROTOCOL_BY_DRIVER


   );



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Marvell Yukon: OpenProtocol: EFI_PCI_IO_PROTOCOL ERROR Status = %r\n", Status));
gBS->FreePool ( YukonDriver );
return Status;
}

//
//  Initialize the simple network protocol
//
Status = InitializeSNPProtocol ( YukonDriver );

if (EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR, "Marvell Yukon: InitializeSNPProtocol: ERROR Status = %r\n", Status));
gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );


}

//
// Set Device Path
//
Status = gBS->OpenProtocol (
   Controller,


   &gEfiDevicePathProtocolGuid,


   (VOID **) &ParentDevicePath,


   pThis->DriverBindingHandle,


   Controller,


   EFI_OPEN_PROTOCOL_BY_DRIVER


   );



if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "Marvell Yukon: OpenProtocol:EFI_DEVICE_PATH_PROTOCOL error. Status = %r\n", Status));

gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );



gBS->FreePool ( YukonDriver );
return Status;
}

ZeroMem (&MacDeviceNode, sizeof (MAC_ADDR_DEVICE_PATH));
MacDeviceNode.Header.Type = MESSAGING_DEVICE_PATH;
MacDeviceNode.Header.SubType = MSG_MAC_ADDR_DP;

SetDevicePathNodeLength (&MacDeviceNode.Header, sizeof (MAC_ADDR_DEVICE_PATH));

// Initialize Yukon card so we can get the MAC address
Status = mskc_attach (YukonDriver->PciIo, &YukonDriver->SnpMode.PermanentAddress);

if (EFI_ERROR (Status)) {
gBS->FreePool (YukonDriver);
return Status;
}

mskc_detach();

// Assign fields for device path
CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS));
CopyMem (&MacDeviceNode.MacAddress, &YukonDriver->SnpMode.CurrentAddress, PXE_HWADDR_LEN_ETHER);

MacDeviceNode.IfType = YukonDriver->SnpMode.IfType;
YukonDriver->DevicePath = AppendDevicePathNode ( ParentDevicePath,  (EFI_DEVICE_PATH_PROTOCOL *) &MacDeviceNode);
YukonDriver->Controller = NULL;

//
//  Install both the simple network and device path protocols.
//
Status = gBS->InstallMultipleProtocolInterfaces (
   &YukonDriver->Controller,


   &gEfiCallerIdGuid,


   YukonDriver,


   &gEfiSimpleNetworkProtocolGuid,


   &YukonDriver->Snp,


   &gEfiDevicePathProtocolGuid,


   YukonDriver->DevicePath,


   NULL


   );



if (EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR, "Marvell Yukon: InstallMultipleProtocolInterfaces error. Status = %r\n", Status));

gBS->CloseProtocol (
     Controller,


     &gEfiDevicePathProtocolGuid,


     pThis->DriverBindingHandle,


     Controller);



gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );



gBS->FreePool ( YukonDriver );
return Status;
}

//
// Open For Child Device
//
Status = gBS->OpenProtocol (
   Controller,


   &gEfiPciIoProtocolGuid,


   (VOID **) &YukonDriver->PciIo,


   pThis->DriverBindingHandle,


   YukonDriver->Controller,


   EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER


   );



if (EFI_ERROR(Status)){
gBS->UninstallMultipleProtocolInterfaces (
     &YukonDriver->Controller,


     &gEfiCallerIdGuid,


     YukonDriver,


     &gEfiSimpleNetworkProtocolGuid,


     &YukonDriver->Snp,


     &gEfiDevicePathProtocolGuid,


     YukonDriver->DevicePath,


     NULL


     );


gBS->CloseProtocol (
     Controller,


     &gEfiDevicePathProtocolGuid,


     pThis->DriverBindingHandle,


     Controller);


gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );


gBS->FreePool ( YukonDriver );
}

return Status;

+}



+/**

Stop this driver on Controller by removing NetworkInterfaceIdentifier protocol and
closing the DevicePath and PciIo protocols on Controller.

@param [in] pThis                   Protocol instance pointer.
@param [in] Controller              Handle of device to stop driver on.
@param [in] NumberOfChildren        How many children need to be stopped.
@param [in] pChildHandleBuffer      Not used.

@retval EFI_SUCCESS                 This driver is removed Controller.
@retval EFI_DEVICE_ERROR            The device could not be stopped due to a device error.
@retval other                       This driver was not removed from this device.


+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverStop (

IN  EFI_DRIVER_BINDING_PROTOCOL * pThis,
IN  EFI_HANDLE Controller,
IN  UINTN NumberOfChildren,
IN  EFI_HANDLE * ChildHandleBuffer
)

+{

EFI_SIMPLE_NETWORK_PROTOCOL  *SimpleNetwork;
EFI_STATUS                   Status = EFI_SUCCESS;
YUKON_DRIVER                 *YukonDriver;

//
// Complete all outstanding transactions to Controller.
// Don't allow any new transaction to Controller to be started.
//
Status = gBS->OpenProtocol (
   Controller,


   &gEfiSimpleNetworkProtocolGuid,


   (VOID **) &SimpleNetwork,


   pThis->DriverBindingHandle,


   Controller,


   EFI_OPEN_PROTOCOL_GET_PROTOCOL


   );



if (EFI_ERROR(Status)) {
//
// This is a 2nd type handle(multi-lun root), it needs to close devicepath
// and pciio protocol.
//
gBS->CloseProtocol (
     Controller,


     &gEfiDevicePathProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );


gBS->CloseProtocol (
     Controller,


     &gEfiPciIoProtocolGuid,


     pThis->DriverBindingHandle,


     Controller


     );


return EFI_SUCCESS;
}

YukonDriver = YUKON_DEV_FROM_THIS ( SimpleNetwork );

Status = gBS->UninstallMultipleProtocolInterfaces (
   Controller,


   &gEfiCallerIdGuid,


   YukonDriver,


   &gEfiSimpleNetworkProtocolGuid,


   &YukonDriver->Snp,


   &gEfiDevicePathProtocolGuid,


   YukonDriver->DevicePath,


   NULL


   );



if (EFI_ERROR (Status)) {
return Status;
}

//
// Close the bus driver
//
Status = gBS->CloseProtocol (
   Controller,


   &gEfiDevicePathProtocolGuid,


   pThis->DriverBindingHandle,


   Controller


   );



if (EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR, "Marvell Yukon: MarvellYukonDriverStop: Close EfiDevicePathProtocol error. Status %r\n", Status));
}

Status = gBS->CloseProtocol (
   Controller,


   &gEfiPciIoProtocolGuid,


   pThis->DriverBindingHandle,


   Controller


   );



if (EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR, "Marvell Yukon: MarvellYukonDriverStop:Close EfiPciIoProtocol error. Status %r\n", Status));
}

gBS->FreePool (YukonDriver);
return EFI_SUCCESS;

+}



+//
+// Simple Network Protocol Driver Global Variables
+//
+EFI_DRIVER_BINDING_PROTOCOL gMarvellYukonDriverBinding = {

MarvellYukonDriverSupported,
MarvellYukonDriverStart,
MarvellYukonDriverStop,
0xa,
NULL,
NULL

+};



+/**

The Marvel Yukon driver entry point.

<at> param ImageHandle             The driver image handle.
<at> param SystemTable             The system table.

<at> retval EFI_SUCCESS            Initialization routine has found and initialized
                                 hardware successfully.


<at> retval Other                  Return value from HandleProtocol for
                                 DeviceIoProtocol or LoadedImageProtocol




+**/
+EFI_STATUS
+EFIAPI
+InitializeMarvellYukonDriver (

IN EFI_HANDLE       ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)

+{

DEBUG ((EFI_D_NET, "Marvell Yukon: InitializeMarvellYukonDriver()\n"));
EFI_STATUS Status = EfiLibInstallDriverBindingComponentName2 (
   ImageHandle,


   SystemTable,


   &gMarvellYukonDriverBinding,


   NULL,


   &gSimpleNetworkComponentName,


   &gSimpleNetworkComponentName2


   );



return Status;

+}
diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukon.h b/Drivers/Net/MarvellYukonDxe/MarvellYukon.h
new file mode 100644
index 0000000..a21c1bb
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/MarvellYukon.h
@@ -0,0 +1,735 @@
+/**
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+#ifndef _SNP_H_
+#define _SNP_H_




+#include <Uefi.h>



+#include <Protocol/SimpleNetwork.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/DevicePath.h>



+#include <Guid/EventGroup.h>



+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/NetLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>



+#include <IndustryStandard/Pci.h>



+//#define FOUR_GIGABYTES  (UINT64) 0x100000000ULL




+#define YUKON_DRIVER_SIGNATURE  SIGNATURE_32 ('m', 'y', 'u', 'k')
+/*#define MAX_MAP_LENGTH        100



+#define PCI_BAR_IO_MASK       0x00000003
+#define PCI_BAR_IO_MODE       0x00000001



+#define PCI_BAR_MEM_MASK      0x0000000F
+#define PCI_BAR_MEM_MODE      0x00000000
+#define PCI_BAR_MEM_64BIT     0x00000004
+*/



+#define NIC_YUKONII_DEVICE_ID  0x4362
+#define NIC_MARVELL_VENDOR_ID  0x11AB



+typedef struct {

UINT32                      Signature;
EFI_LOCK                    Lock;

EFI_HANDLE Controller;

EFI_SIMPLE_NETWORK_PROTOCOL Snp;
EFI_SIMPLE_NETWORK_MODE     SnpMode;

// Transmit Buffer recycle queue

+#define TX_QUEUE_DEPTH 16

VOID              *TxQueue[TX_QUEUE_DEPTH];
UINTN             TxQueHead;
UINTN             TxQueTail;

EFI_HANDLE                  DeviceHandle;
EFI_DEVICE_PATH_PROTOCOL*   DevicePath;
EFI_PCI_IO_PROTOCOL*        PciIo;

//
//  Local instance data needed by SNP driver
//
//  EFI_EVENT              ExitBootServicesEvent;


+} YUKON_DRIVER;



+#define YUKON_DEV_FROM_THIS(a) CR (a, YUKON_DRIVER, Snp, YUKON_DRIVER_SIGNATURE)



+#define SNP_MEM_PAGES(x)  (((x) - 1) / 4096 + 1)



+//
+// Global Variables
+//
+extern EFI_COMPONENT_NAME_PROTOCOL    gSimpleNetworkComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL   gSimpleNetworkComponentName2;



+//
+// The SNP driver control functions
+//



+EFI_STATUS
+InitializeSNPProtocol (

IN OUT  YUKON_DRIVER *YukonDriver
);


+/**

Changes the state of a network interface from "stopped" to "started".

This function starts a network interface. If the network interface successfully
starts, then EFI_SUCCESS will be returned.

<at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> retval EFI_SUCCESS            The network interface was started.
<at> retval EFI_ALREADY_STARTED    The network interface is already in the started state.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpStart (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
);


+/**

Changes the state of a network interface from "started" to "stopped".

This function stops a network interface. This call is only valid if the network
interface is in the started state. If the network interface was successfully
stopped, then EFI_SUCCESS will be returned.

<at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.


<at> retval EFI_SUCCESS            The network interface was stopped.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpStop (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
);


+//
+// The SNP protocol functions
+//




+/**

Resets a network adapter and allocates the transmit and receive buffers
required by the network interface; optionally, also requests allocation of
additional transmit and receive buffers.

This function allocates the transmit and receive buffers required by the network
interface. If this allocation fails, then EFI_OUT_OF_RESOURCES is returned.
If the allocation succeeds and the network interface is successfully initialized,
then EFI_SUCCESS will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> param ExtraRxBufferSize       The size, in bytes, of the extra receive buffer space
                                 that the driver should allocate for the network interface.


                                 Some network interfaces will not be able to use the


                                 extra buffer, and the caller will not know if it is


                                 actually being used.


<at> param ExtraTxBufferSize       The size, in bytes, of the extra transmit buffer space
                                 that the driver should allocate for the network interface.


                                 Some network interfaces will not be able to use the


                                 extra buffer, and the caller will not know if it is


                                 actually being used.



<at> retval EFI_SUCCESS            The network interface was initialized.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_OUT_OF_RESOURCES   There was not enough memory for the transmit and
                                 receive buffers.


<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        The increased buffer size feature is not supported.


+**/
+EFI_STATUS
+EFIAPI
+SnpInitialize (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINTN                       ExtraRxBufferSize OPTIONAL,
IN UINTN                       ExtraTxBufferSize OPTIONAL
);


+/**

Resets a network adapter and reinitializes it with the parameters that were
provided in the previous call to Initialize().

This function resets a network adapter and reinitializes it with the parameters
that were provided in the previous call to Initialize(). The transmit and
receive queues are emptied and all pending interrupts are cleared.
Receive filters, the station address, the statistics, and the multicast-IP-to-HW
MAC addresses are not reset by this call. If the network interface was
successfully reset, then EFI_SUCCESS will be returned. If the driver has not
been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param ExtendedVerification    Indicates that the driver may perform a more
                                 exhaustive verification operation of the device


                                 during reset.



<at> retval EFI_SUCCESS            The network interface was reset.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported value.
<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpReset (

IN EFI_SIMPLE_NETWORK_PROTOCOL  *This,
IN BOOLEAN                      ExtendedVerification
);


+/**

Resets a network adapter and leaves it in a state that is safe for another
driver to initialize.

This function releases the memory buffers assigned in the Initialize() call.
Pending transmits and receives are lost, and interrupts are cleared and disabled.
After this call, only the Initialize() and Stop() calls may be used. If the
network interface was successfully shutdown, then EFI_SUCCESS will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param                         This  A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> retval EFI_SUCCESS            The network interface was shutdown.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpShutdown (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
);


+/**

Manages the multicast receive filters of a network interface.

This function is used enable and disable the hardware and software receive
filters for the underlying network device.
The receive filter change is broken down into three steps:

The filter mask bits that are set (ON) in the Enable parameter are added to


the current receive filter settings.

The filter mask bits that are set (ON) in the Disable parameter are subtracted


from the updated receive filter settings.

If the resulting receive filter setting is not supported by the hardware a


more liberal setting is selected.
If the same bits are set in the Enable and Disable parameters, then the bits
in the Disable parameter takes precedence.
If the ResetMCastFilter parameter is TRUE, then the multicast address list
filter is disabled (irregardless of what other multicast bits are set in the
Enable and Disable parameters). The SNP->SnpMode->MCastFilterCount field is set
to zero. The Snp->SnpMode->MCastFilter contents are undefined.
After enabling or disabling receive filter settings, software should verify
the new settings by checking the Snp->SnpMode->ReceiveFilterSettings,
Snp->SnpMode->MCastFilterCount and Snp->SnpMode->MCastFilter fields.
Note: Some network drivers and/or devices will automatically promote receive
filter settings if the requested setting can not be honored. For example, if
a request for four multicast addresses is made and the underlying hardware
only supports two multicast addresses the driver might set the promiscuous
or promiscuous multicast receive filters instead. The receiving software is
responsible for discarding any extra packets that get through the hardware
receive filters.
Note: Note: To disable all receive filter hardware, the network driver must
 be Shutdown() and Stopped(). Calling ReceiveFilters() with Disable set to


 Snp->SnpMode->ReceiveFilterSettings will make it so no more packets are


 returned by the Receive() function, but the receive hardware may still be


 moving packets into system memory before inspecting and discarding them.


 Unexpected system errors, reboots and hangs can occur if an OS is loaded


 and the network devices are not Shutdown() and Stopped().


If ResetMCastFilter is TRUE, then the multicast receive filter list on the
network interface will be reset to the default multicast receive filter list.
If ResetMCastFilter is FALSE, and this network interface allows the multicast
receive filter list to be modified, then the MCastFilterCnt and MCastFilter
are used to update the current multicast receive filter list. The modified
receive filter list settings can be found in the MCastFilter field of
EFI_SIMPLE_NETWORK_MODE. If the network interface does not allow the multicast
receive filter list to be modified, then EFI_INVALID_PARAMETER will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
If the receive filter mask and multicast receive filter list have been
successfully updated on the network interface, EFI_SUCCESS will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Enable                  A bit mask of receive filters to enable on the network
                                 interface.


<at> param Disable                 A bit mask of receive filters to disable on the network
                                 interface. For backward compatibility with EFI 1.1


                                 platforms, the EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit


                                 must be set when the ResetMCastFilter parameter is TRUE.


<at> param ResetMCastFilter        Set to TRUE to reset the contents of the multicast
                                 receive filters on the network interface to their


                                 default values.


<at> param MCastFilterCnt          Number of multicast HW MAC addresses in the new MCastFilter
                                 list. This value must be less than or equal to the


                                 MCastFilterCnt field of EFI_SIMPLE_NETWORK_MODE.


                                 This field is optional if ResetMCastFilter is TRUE.


<at> param MCastFilter             A pointer to a list of new multicast receive filter HW
                                 MAC addresses. This list will replace any existing


                                 multicast HW MAC address list. This field is optional


                                 if ResetMCastFilter is TRUE.



<at> retval EFI_SUCCESS            The multicast receive filter list was updated.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * This is NULL


                                 * There are bits set in Enable that are not set


                                   in Snp->SnpMode->ReceiveFilterMask


                                 * There are bits set in Disable that are not set


                                   in Snp->SnpMode->ReceiveFilterMask


                                 * Multicast is being enabled (the


                                   EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is


                                   set in Enable, it is not set in Disable, and


                                   ResetMCastFilter is FALSE) and MCastFilterCount


                                   is zero


                                 * Multicast is being enabled and MCastFilterCount


                                   is greater than Snp->SnpMode->MaxMCastFilterCount


                                 * Multicast is being enabled and MCastFilter is NULL


                                 * Multicast is being enabled and one or more of


                                   the addresses in the MCastFilter list are not


                                   valid multicast MAC addresses


<at> retval EFI_DEVICE_ERROR       One or more of the following conditions is TRUE:
                                 * The network interface has been started but has


                                   not been initialized


                                 * An unexpected error was returned by the


                                   underlying network driver or device


<at> retval EFI_UNSUPPORTED        This function is not supported by the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINT32                      Enable,
IN UINT32                      Disable,
IN BOOLEAN                     ResetMCastFilter,
IN UINTN                       MCastFilterCnt,  OPTIONAL
IN EFI_MAC_ADDRESS             *MCastFilter     OPTIONAL
);


+/**

Modifies or resets the current station address, if supported.

This function modifies or resets the current station address of a network
interface, if supported. If Reset is TRUE, then the current station address is
set to the network interface's permanent address. If Reset is FALSE, and the
network interface allows its station address to be modified, then the current
station address is changed to the address specified by New. If the network
interface does not allow its station address to be modified, then
EFI_INVALID_PARAMETER will be returned. If the station address is successfully
updated on the network interface, EFI_SUCCESS will be returned. If the driver
has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This  A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Reset Flag used to reset the station address to the network interface's
          permanent address.


<at> param New   New station address to be used for the network interface.


<at> retval EFI_SUCCESS            The network interface's station address was updated.
<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
                                 started by calling Start().


<at> retval EFI_INVALID_PARAMETER  The New station address was not accepted by the NIC.
<at> retval EFI_INVALID_PARAMETER  Reset is FALSE and New is NULL.
<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_DEVICE_ERROR       An error occurred attempting to set the new
                                 station address.


<at> retval EFI_UNSUPPORTED        The NIC does not support changing the network
                                 interface's station address.




+**/
+EFI_STATUS
+EFIAPI
+SnpStationAddress (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     Reset,
IN EFI_MAC_ADDRESS             *New  OPTIONAL
);


+/**

Resets or collects the statistics on a network interface.

This function resets or collects the statistics on a network interface. If the
size of the statistics table specified by StatisticsSize is not big enough for
all the statistics that are collected by the network interface, then a partial
buffer of statistics is returned in StatisticsTable, StatisticsSize is set to
the size required to collect all the available statistics, and
EFI_BUFFER_TOO_SMALL is returned.
If StatisticsSize is big enough for all the statistics, then StatisticsTable
will be filled, StatisticsSize will be set to the size of the returned
StatisticsTable structure, and EFI_SUCCESS is returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
If Reset is FALSE, and both StatisticsSize and StatisticsTable are NULL, then
no operations will be performed, and EFI_SUCCESS will be returned.
If Reset is TRUE, then all of the supported statistics counters on this network
interface will be reset to zero.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Reset                   Set to TRUE to reset the statistics for the network interface.
<at> param StatisticsSize          On input the size, in bytes, of StatisticsTable. On output
                                 the size, in bytes, of the resulting table of statistics.


<at> param StatisticsTable         A pointer to the EFI_NETWORK_STATISTICS structure that
                                 contains the statistics. Type EFI_NETWORK_STATISTICS is


                                 defined in "Related Definitions" below.



<at> retval EFI_SUCCESS            The requested operation succeeded.
<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
                                 started by calling Start().


<at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
                                 NULL. The current buffer size that is needed to


                                 hold all the statistics is returned in StatisticsSize.


<at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
                                 not NULL. The current buffer size that is needed


                                 to hold all the statistics is returned in


                                 StatisticsSize. A partial set of statistics is


                                 returned in StatisticsTable.


<at> retval EFI_INVALID_PARAMETER  StatisticsSize is NULL and StatisticsTable is not
                                 NULL.


<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_DEVICE_ERROR       An error was encountered collecting statistics
                                 from the NIC.


<at> retval EFI_UNSUPPORTED        The NIC does not support collecting statistics
                                 from the network interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpStatistics (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     Reset,
IN OUT UINTN                   *StatisticsSize,  OPTIONAL
IN OUT EFI_NETWORK_STATISTICS  *StatisticsTable  OPTIONAL
);


+/**

Converts a multicast IP address to a multicast HW MAC address.

This function converts a multicast IP address to a multicast HW MAC address
for all packet transactions. If the mapping is accepted, then EFI_SUCCESS will
be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param IPv6                    Set to TRUE if the multicast IP address is IPv6 [RFC 2460].
                                 Set to FALSE if the multicast IP address is IPv4 [RFC 791].


<at> param IP                      The multicast IP address that is to be converted to a multicast
                                 HW MAC address.


<at> param MAC                     The multicast HW MAC address that is to be generated from IP.

<at> retval EFI_SUCCESS            The multicast IP address was mapped to the
                                 multicast HW MAC address.


<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not
                                 been started by calling Start().


<at> retval EFI_INVALID_PARAMETER  IP is NULL.
<at> retval EFI_INVALID_PARAMETER  MAC is NULL.
<at> retval EFI_INVALID_PARAMETER  IP does not point to a valid IPv4 or IPv6
                                 multicast address.


<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_UNSUPPORTED        IPv6 is TRUE and the implementation does not
                                 support IPv6 multicast to MAC address conversion.




+**/
+EFI_STATUS
+EFIAPI
+SnpMcastIpToMac (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     IPv6,
IN EFI_IP_ADDRESS              *IP,
OUT EFI_MAC_ADDRESS            *MAC
);


+/**

Performs read and write operations on the NVRAM device attached to a network
interface.

This function performs read and write operations on the NVRAM device attached
to a network interface. If ReadWrite is TRUE, a read operation is performed.
If ReadWrite is FALSE, a write operation is performed. Offset specifies the
byte offset at which to start either operation. Offset must be a multiple of
NvRamAccessSize , and it must have a value between zero and NvRamSize.
BufferSize specifies the length of the read or write operation. BufferSize must
also be a multiple of NvRamAccessSize, and Offset + BufferSize must not exceed
NvRamSize.
If any of the above conditions is not met, then EFI_INVALID_PARAMETER will be
returned.
If all the conditions are met and the operation is "read," the NVRAM device
attached to the network interface will be read into Buffer and EFI_SUCCESS
will be returned. If this is a write operation, the contents of Buffer will be
used to update the contents of the NVRAM device attached to the network
interface and EFI_SUCCESS will be returned.

It does the basic checking on the input parameters and retrieves snp structure
and then calls the read_nvdata() call which does the actual reading

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param ReadWrite               TRUE for read operations, FALSE for write operations.
<at> param Offset                  Byte offset in the NVRAM device at which to start the read or
                                 write operation. This must be a multiple of NvRamAccessSize


                                 and less than NvRamSize. (See EFI_SIMPLE_NETWORK_MODE)


<at> param BufferSize              The number of bytes to read or write from the NVRAM device.
                                 This must also be a multiple of NvramAccessSize.


<at> param Buffer                  A pointer to the data buffer.

<at> retval EFI_SUCCESS            The NVRAM access was performed.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * The This parameter is NULL


                                 * The This parameter does not point to a valid


                                   EFI_SIMPLE_NETWORK_PROTOCOL  structure


                                 * The Offset parameter is not a multiple of


                                   EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize


                                 * The Offset parameter is not less than


                                   EFI_SIMPLE_NETWORK_MODE.NvRamSize


                                 * The BufferSize parameter is not a multiple of


                                   EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize


                                 * The Buffer parameter is NULL


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
                                 interface.


<at> retval EFI_UNSUPPORTED        This function is not supported by the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpNvData (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     ReadWrite,
IN UINTN                       Offset,
IN UINTN                       BufferSize,
IN OUT VOID                    *Buffer
);


+/**

Reads the current interrupt status and recycled transmit buffer status from a
network interface.

This function gets the current interrupt and recycled transmit buffer status
from the network interface. The interrupt status is returned as a bit mask in
InterruptStatus. If InterruptStatus is NULL, the interrupt status will not be
read. If TxBuf is not NULL, a recycled transmit buffer address will be retrieved.
If a recycled transmit buffer address is returned in TxBuf, then the buffer has
been successfully transmitted, and the status for that buffer is cleared. If
the status of the network interface is successfully collected, EFI_SUCCESS
will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will
be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param InterruptStatus         A pointer to the bit mask of the currently active
                                 interrupts (see "Related Definitions"). If this is NULL,


                                 the interrupt status will not be read from the device.


                                 If this is not NULL, the interrupt status will be read


                                 from the device. When the interrupt status is read, it


                                 will also be cleared. Clearing the transmit interrupt does


                                 not empty the recycled transmit buffer array.


<at> param TxBuf                   Recycled transmit buffer address. The network interface
                                 will not transmit if its internal recycled transmit


                                 buffer array is full. Reading the transmit buffer does


                                 not clear the transmit interrupt. If this is NULL, then


                                 the transmit buffer status will not be read. If there


                                 are no transmit buffers to recycle and TxBuf is not NULL,


                                 TxBuf will be set to NULL.



<at> retval EFI_SUCCESS            The status of the network interface was retrieved.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpGetStatus (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
OUT UINT32                     *InterruptStatus, OPTIONAL
OUT VOID                       **TxBuf           OPTIONAL
);


+/**

Places a packet in the transmit queue of a network interface.

This function places the packet specified by Header and Buffer on the transmit
queue. If HeaderSize is nonzero and HeaderSize is not equal to
This->SnpMode->MediaHeaderSize, then EFI_INVALID_PARAMETER will be returned. If
BufferSize is less than This->SnpMode->MediaHeaderSize, then EFI_BUFFER_TOO_SMALL
will be returned. If Buffer is NULL, then EFI_INVALID_PARAMETER will be
returned. If HeaderSize is nonzero and DestAddr or Protocol is NULL, then
EFI_INVALID_PARAMETER will be returned. If the transmit engine of the network
interface is busy, then EFI_NOT_READY will be returned. If this packet can be
accepted by the transmit engine of the network interface, the packet contents
specified by Buffer will be placed on the transmit queue of the network
interface, and EFI_SUCCESS will be returned. GetStatus() can be used to
determine when the packet has actually been transmitted. The contents of the
Buffer must not be modified until the packet has actually been transmitted.
The Transmit() function performs nonblocking I/O. A caller who wants to perform
blocking I/O, should call Transmit(), and then GetStatus() until the
transmitted buffer shows up in the recycled transmit buffer.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param HeaderSize              The size, in bytes, of the media header to be filled in by the
                                 Transmit() function. If HeaderSize is nonzero, then it must


                                 be equal to This->SnpMode->MediaHeaderSize and the DestAddr and


                                 Protocol parameters must not be NULL.


<at> param BufferSize              The size, in bytes, of the entire packet (media header and
                                 data) to be transmitted through the network interface.


<at> param Buffer                  A pointer to the packet (media header followed by data) to be
                                 transmitted. This parameter cannot be NULL. If HeaderSize is


                                 zero, then the media header in Buffer must already be filled


                                 in by the caller. If HeaderSize is nonzero, then the media


                                 header will be filled in by the Transmit() function.


<at> param SrcAddr                 The source HW MAC address. If HeaderSize is zero, then this
                                 parameter is ignored. If HeaderSize is nonzero and SrcAddr


                                 is NULL, then This->SnpMode->CurrentAddress is used for the


                                 source HW MAC address.


<at> param DestAddr                The destination HW MAC address. If HeaderSize is zero, then
                                 this parameter is ignored.


<at> param Protocol                The type of header to build. If HeaderSize is zero, then this
                                 parameter is ignored. See RFC 1700, section "Ether Types,"


                                 for examples.



<at> retval EFI_SUCCESS            The packet was placed on the transmit queue.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_NOT_READY          The network interface is too busy to accept this
                                 transmit request.


<at> retval EFI_BUFFER_TOO_SMALL   The BufferSize parameter is too small.
<at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported
                                 value.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpTransmit (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINTN                       HeaderSize,
IN UINTN                       BufferSize,
IN VOID                        *Buffer,
IN EFI_MAC_ADDRESS             *SrcAddr,  OPTIONAL
IN EFI_MAC_ADDRESS             *DestAddr, OPTIONAL
IN UINT16                      *Protocol  OPTIONAL
);


+/**

Receives a packet from a network interface.

This function retrieves one packet from the receive queue of a network interface.
If there are no packets on the receive queue, then EFI_NOT_READY will be
returned. If there is a packet on the receive queue, and the size of the packet
is smaller than BufferSize, then the contents of the packet will be placed in
Buffer, and BufferSize will be updated with the actual size of the packet.
In addition, if SrcAddr, DestAddr, and Protocol are not NULL, then these values
will be extracted from the media header and returned. EFI_SUCCESS will be
returned if a packet was successfully received.
If BufferSize is smaller than the received packet, then the size of the receive
packet will be placed in BufferSize and EFI_BUFFER_TOO_SMALL will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param HeaderSize              The size, in bytes, of the media header received on the network
                                 interface. If this parameter is NULL, then the media header size


                                 will not be returned.


<at> param BufferSize              On entry, the size, in bytes, of Buffer. On exit, the size, in
                                 bytes, of the packet that was received on the network interface.


<at> param Buffer                  A pointer to the data buffer to receive both the media
                                 header and the data.


<at> param SrcAddr                 The source HW MAC address. If this parameter is NULL, the HW
                                 MAC source address will not be extracted from the media header.


<at> param DestAddr                The destination HW MAC address. If this parameter is NULL,
                                 the HW MAC destination address will not be extracted from


                                 the media header.


<at> param Protocol                The media header type. If this parameter is NULL, then the
                                 protocol will not be extracted from the media header. See


                                 RFC 1700 section "Ether Types" for examples.



<at> retval EFI_SUCCESS            The received data was stored in Buffer, and
                                 BufferSize has been updated to the number of


                                 bytes received.


<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_NOT_READY          No packets have been received on the network interface.
<at> retval EFI_BUFFER_TOO_SMALL   BufferSize is too small for the received packets.
                                 BufferSize has been updated to the required size.


<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * The This parameter is NULL


                                 * The This parameter does not point to a valid


                                   EFI_SIMPLE_NETWORK_PROTOCOL structure.


                                 * The BufferSize parameter is NULL


                                 * The Buffer parameter is NULL


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpReceive (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
OUT UINTN                      *HeaderSize OPTIONAL,
IN OUT UINTN                   *BufferSize,
OUT VOID                       *Buffer,
OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
OUT EFI_MAC_ADDRESS            *DestAddr OPTIONAL,
OUT UINT16                     *Protocol OPTIONAL
);


+/**

Nofication call back function for WaitForPacket event.

<at> param  Event       EFI Event.
<at> param  SnpPtr      Pointer to YUKON_DRIVER structure.


+**/
+VOID
+EFIAPI
+SnpWaitForPacketNotify (

EFI_EVENT Event,
VOID      *SnpPtr
);



+#endif /*  _SNP_H_  */
diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
new file mode 100644
index 0000000..4047cd6
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
@@ -0,0 +1,81 @@
+##  <at> file
+# Component description file for Marvell Yukon II SNP module.
+#
+# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed
+# and made available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##



+[Defines]

INF_VERSION                    = 0x00010005
BASE_NAME                      = MarvellYukonDxe
FILE_GUID                      = d7de5d0c-99f8-4970-b85c-c19df8997d7d
MODULE_TYPE                    = UEFI_DRIVER
VERSION_STRING                 = 1.0
ENTRY_POINT                    = InitializeMarvellYukonDriver


+#
+# The following information is for reference only and not required by the build tools.
+#
+#  DRIVER_BINDING                =  gMarvellYukonDriverBinding
+#  COMPONENT_NAME                =  gSimpleNetworkComponentName
+#  COMPONENT_NAME2               =  gSimpleNetworkComponentName2
+#



+[Sources]

MarvellYukon.h
miivar.h
if_media.h
if_mskreg.h
if_msk.h
e1000phyreg.h
Snp.c
DriverBinding.c
ComponentName.c
e1000phy.c
if_msk.c



+[Packages]

EmbeddedPkg/EmbeddedPkg.dec
NetworkPkg/NetworkPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec


+[LibraryClasses]

UefiLib
BaseLib
UefiBootServicesTableLib
UefiDriverEntryPoint
BaseMemoryLib
MemoryAllocationLib
IoLib
DebugLib
TimerLib
NetLib
ArmLib
DevicePathLib


+[Pcd]

gEmbeddedTokenSpaceGuid.PcdYukonMacAddress


+#[Guids]
+#  gEfiEventExitBootServicesGuid                 ## CONSUMES



+[Protocols]

gEfiPciIoProtocolGuid
gEfiSimpleNetworkProtocolGuid
gEfiMetronomeArchProtocolGuid
gEfiPxeBaseCodeProtocolGuid
gEfiDevicePathProtocolGuid


+[Depex]

TRUE


diff --git a/Drivers/Net/MarvellYukonDxe/Snp.c b/Drivers/Net/MarvellYukonDxe/Snp.c
new file mode 100644
index 0000000..ba0dc9d
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/Snp.c
@@ -0,0 +1,1474 @@
+/**  <at> file
+Provides the Simple Network functions.



+Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.



+This program and the accompanying materials are licensed
+and made available under the terms and conditions of the BSD License which
+accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php



+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.



+**/



+#include "MarvellYukon.h"
+#include "if_msk.h"



+EFI_STATUS
+InitializeSNPProtocol (

IN OUT  YUKON_DRIVER *YukonDriver
)

+{

EFI_STATUS    Status;

Status = RETURN_SUCCESS;

EfiInitializeLock (&YukonDriver->Lock, TPL_NOTIFY);

YukonDriver->Snp.Revision       = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
YukonDriver->Snp.Start          = SnpStart;
YukonDriver->Snp.Stop           = SnpStop;
YukonDriver->Snp.Initialize     = SnpInitialize;
YukonDriver->Snp.Reset          = SnpReset;
YukonDriver->Snp.Shutdown       = SnpShutdown;
YukonDriver->Snp.ReceiveFilters = SnpReceiveFilters;
YukonDriver->Snp.StationAddress = SnpStationAddress;
YukonDriver->Snp.Statistics     = SnpStatistics;
YukonDriver->Snp.MCastIpToMac   = SnpMcastIpToMac;
YukonDriver->Snp.NvData         = SnpNvData;
YukonDriver->Snp.GetStatus      = SnpGetStatus;
YukonDriver->Snp.Transmit       = SnpTransmit;
YukonDriver->Snp.Receive        = SnpReceive;
YukonDriver->Snp.WaitForPacket  = NULL;

YukonDriver->Snp.Mode           = &YukonDriver->SnpMode;

//
//  Initialize simple network protocol mode structure
//
YukonDriver->SnpMode.State               = EfiSimpleNetworkStopped;
YukonDriver->SnpMode.HwAddressSize       = NET_ETHER_ADDR_LEN;
YukonDriver->SnpMode.MediaHeaderSize     = sizeof (ETHER_HEAD);
YukonDriver->SnpMode.MaxPacketSize       = MAX_SUPPORTED_PACKET_SIZE;
YukonDriver->SnpMode.NvRamAccessSize     = 0;
YukonDriver->SnpMode.NvRamSize           = 0;
YukonDriver->SnpMode.IfType              = NET_IFTYPE_ETHERNET;
YukonDriver->SnpMode.MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
YukonDriver->SnpMode.MCastFilterCount    = 0;
ZeroMem (&YukonDriver->SnpMode.MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));

//
//  Set broadcast address
//
SetMem (&YukonDriver->SnpMode.BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);

YukonDriver->SnpMode.MediaPresentSupported = FALSE;
YukonDriver->SnpMode.MacAddressChangeable = FALSE;
YukonDriver->SnpMode.MultipleTxSupported = FALSE;
YukonDriver->SnpMode.ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST;
YukonDriver->SnpMode.ReceiveFilterSetting = 0;

YukonDriver->SnpMode.MediaPresent = TRUE;

return Status;

+}



+/**

Reads the current interrupt status and recycled transmit buffer status from a
network interface.

This function gets the current interrupt and recycled transmit buffer status
from the network interface. The interrupt status is returned as a bit mask in
InterruptStatus. If InterruptStatus is NULL, the interrupt status will not be
read. If TxBuf is not NULL, a recycled transmit buffer address will be retrieved.
If a recycled transmit buffer address is returned in TxBuf, then the buffer has
been successfully transmitted, and the status for that buffer is cleared. If
the status of the network interface is successfully collected, EFI_SUCCESS
will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will
be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param InterruptStatus         A pointer to the bit mask of the currently active
                                 interrupts (see "Related Definitions"). If this is NULL,


                                 the interrupt status will not be read from the device.


                                 If this is not NULL, the interrupt status will be read


                                 from the device. When the interrupt status is read, it


                                 will also be cleared. Clearing the transmit interrupt does


                                 not empty the recycled transmit buffer array.


<at> param TxBuf                   Recycled transmit buffer address. The network interface
                                 will not transmit if its internal recycled transmit


                                 buffer array is full. Reading the transmit buffer does


                                 not clear the transmit interrupt. If this is NULL, then


                                 the transmit buffer status will not be read. If there


                                 are no transmit buffers to recycle and TxBuf is not NULL,


                                 TxBuf will be set to NULL.



<at> retval EFI_SUCCESS            The status of the network interface was retrieved.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpGetStatus (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
OUT UINT32                     *InterruptStatus, OPTIONAL
OUT VOID                       **TxBuf           OPTIONAL
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *Snp;
EFI_TPL       OldTpl;

if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

Snp = YUKON_DEV_FROM_THIS (This);
if (Snp == NULL) {
return EFI_INVALID_PARAMETER;
}

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (Snp->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

mskc_getstatus (InterruptStatus, TxBuf);
Status = EFI_SUCCESS;


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Resets a network adapter and allocates the transmit and receive buffers
required by the network interface; optionally, also requests allocation of
additional transmit and receive buffers.

This function allocates the transmit and receive buffers required by the network
interface. If this allocation fails, then EFI_OUT_OF_RESOURCES is returned.
If the allocation succeeds and the network interface is successfully initialized,
then EFI_SUCCESS will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> param ExtraRxBufferSize       The size, in bytes, of the extra receive buffer space
                                 that the driver should allocate for the network interface.


                                 Some network interfaces will not be able to use the


                                 extra buffer, and the caller will not know if it is


                                 actually being used.


<at> param ExtraTxBufferSize       The size, in bytes, of the extra transmit buffer space
                                 that the driver should allocate for the network interface.


                                 Some network interfaces will not be able to use the


                                 extra buffer, and the caller will not know if it is


                                 actually being used.



<at> retval EFI_SUCCESS            The network interface was initialized.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_OUT_OF_RESOURCES   There was not enough memory for the transmit and
                                 receive buffers.


<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                                              EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        The increased buffer size feature is not supported.


+**/
+EFI_STATUS
+EFIAPI
+SnpInitialize (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINTN                       ExtraRxBufferSize OPTIONAL,
IN UINTN                       ExtraTxBufferSize OPTIONAL
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpInitialize()\n"));
if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpInitialize() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkStarted:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_ERROR_RESTORE_TPL;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}

Status = gBS->CreateEvent (
   EVT_NOTIFY_WAIT,


   TPL_NOTIFY,


   &SnpWaitForPacketNotify,


   YukonDriver,


   &YukonDriver->Snp.WaitForPacket


   );



if (EFI_ERROR (Status)) {
YukonDriver->Snp.WaitForPacket = NULL;
Status = EFI_DEVICE_ERROR;
goto ON_ERROR_RESTORE_TPL;
}
//
//
//
YukonDriver->SnpMode.MCastFilterCount      = 0;
YukonDriver->SnpMode.ReceiveFilterSetting  = 0;
ZeroMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter);
CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS));

Status = mskc_init ();

if (EFI_ERROR (Status)) {
gBS->CloseEvent (YukonDriver->Snp.WaitForPacket);
goto ON_ERROR_RESTORE_TPL;
}

YukonDriver->SnpMode.State = EfiSimpleNetworkInitialized;
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpInitialize() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Converts a multicast IP address to a multicast HW MAC address.

This function converts a multicast IP address to a multicast HW MAC address
for all packet transactions. If the mapping is accepted, then EFI_SUCCESS will
be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param IPv6                    Set to TRUE if the multicast IP address is IPv6 [RFC 2460].
                                 Set to FALSE if the multicast IP address is IPv4 [RFC 791].


<at> param IP                      The multicast IP address that is to be converted to a multicast
                                 HW MAC address.


<at> param MAC                     The multicast HW MAC address that is to be generated from IP.

<at> retval EFI_SUCCESS            The multicast IP address was mapped to the
                                 multicast HW MAC address.


<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not
                                 been started by calling Start().


<at> retval EFI_INVALID_PARAMETER  IP is NULL.
<at> retval EFI_INVALID_PARAMETER  MAC is NULL.
<at> retval EFI_INVALID_PARAMETER  IP does not point to a valid IPv4 or IPv6
                                 multicast address.


<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_UNSUPPORTED        IPv6 is TRUE and the implementation does not
                                 support IPv6 multicast to MAC address conversion.




+**/
+EFI_STATUS
+EFIAPI
+SnpMcastIpToMac (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     IPv6,
IN EFI_IP_ADDRESS              *IP,
OUT EFI_MAC_ADDRESS            *MAC
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpMcastIpToMac()\n"));

//
// Get pointer to SNP driver instance for *this.
//
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

if (IP == NULL || MAC == NULL) {
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

Status = EFI_UNSUPPORTED;


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Performs read and write operations on the NVRAM device attached to a network
interface.

This function performs read and write operations on the NVRAM device attached
to a network interface. If ReadWrite is TRUE, a read operation is performed.
If ReadWrite is FALSE, a write operation is performed. Offset specifies the
byte offset at which to start either operation. Offset must be a multiple of
NvRamAccessSize , and it must have a value between zero and NvRamSize.
BufferSize specifies the length of the read or write operation. BufferSize must
also be a multiple of NvRamAccessSize, and Offset + BufferSize must not exceed
NvRamSize.
If any of the above conditions is not met, then EFI_INVALID_PARAMETER will be
returned.
If all the conditions are met and the operation is "read," the NVRAM device
attached to the network interface will be read into Buffer and EFI_SUCCESS
will be returned. If this is a write operation, the contents of Buffer will be
used to update the contents of the NVRAM device attached to the network
interface and EFI_SUCCESS will be returned.

It does the basic checking on the input parameters and retrieves snp structure
and then calls the read_nvdata() call which does the actual reading

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param ReadWrite               TRUE for read operations, FALSE for write operations.
<at> param Offset                  Byte offset in the NVRAM device at which to start the read or
                                 write operation. This must be a multiple of NvRamAccessSize


                                 and less than NvRamSize. (See EFI_SIMPLE_NETWORK_MODE)


<at> param BufferSize              The number of bytes to read or write from the NVRAM device.
                                 This must also be a multiple of NvramAccessSize.


<at> param Buffer                  A pointer to the data buffer.

<at> retval EFI_SUCCESS            The NVRAM access was performed.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * The This parameter is NULL


                                 * The This parameter does not point to a valid


                                   EFI_SIMPLE_NETWORK_PROTOCOL  structure


                                 * The Offset parameter is not a multiple of


                                   EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize


                                 * The Offset parameter is not less than


                                   EFI_SIMPLE_NETWORK_MODE.NvRamSize


                                 * The BufferSize parameter is not a multiple of


                                   EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize


                                 * The Buffer parameter is NULL


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
                                 interface.


<at> retval EFI_UNSUPPORTED        This function is not supported by the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpNvData (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     ReadWrite,
IN UINTN                       Offset,
IN UINTN                       BufferSize,
IN OUT VOID                    *Buffer
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpNvData()\n"));
//
// Get pointer to SNP driver instance for *this.
//
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

//
// Return error if the SNP is not initialized.
//
switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



case EfiSimpleNetworkStarted:
default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}
//
// Return error if non-volatile memory variables are not valid.
//
if (YukonDriver->SnpMode.NvRamSize == 0 || YukonDriver->SnpMode.NvRamAccessSize == 0) {
Status = EFI_UNSUPPORTED;
goto ON_EXIT;
}
//
// Check for invalid parameter combinations.
//
if ((BufferSize == 0) ||
 (Buffer == NULL) ||


 (Offset >= YukonDriver->SnpMode.NvRamSize) ||


 (Offset + BufferSize > YukonDriver->SnpMode.NvRamSize) ||


 (BufferSize % YukonDriver->SnpMode.NvRamAccessSize != 0) ||


 (Offset % YukonDriver->SnpMode.NvRamAccessSize != 0)


 ) {


Status = EFI_INVALID_PARAMETER;
goto ON_EXIT;
}

Status = EFI_UNSUPPORTED;


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Receives a packet from a network interface.

This function retrieves one packet from the receive queue of a network interface.
If there are no packets on the receive queue, then EFI_NOT_READY will be
returned. If there is a packet on the receive queue, and the size of the packet
is smaller than BufferSize, then the contents of the packet will be placed in
Buffer, and BufferSize will be updated with the actual size of the packet.
In addition, if SrcAddr, DestAddr, and Protocol are not NULL, then these values
will be extracted from the media header and returned. EFI_SUCCESS will be
returned if a packet was successfully received.
If BufferSize is smaller than the received packet, then the size of the receive
packet will be placed in BufferSize and EFI_BUFFER_TOO_SMALL will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param HeaderSize              The size, in bytes, of the media header received on the network
                                 interface. If this parameter is NULL, then the media header size


                                 will not be returned.


<at> param BufferSize              On entry, the size, in bytes, of Buffer. On exit, the size, in
                                 bytes, of the packet that was received on the network interface.


<at> param Buffer                  A pointer to the data buffer to receive both the media
                                 header and the data.


<at> param SrcAddr                 The source HW MAC address. If this parameter is NULL, the HW
                                 MAC source address will not be extracted from the media header.


<at> param DestAddr                The destination HW MAC address. If this parameter is NULL,
                                 the HW MAC destination address will not be extracted from


                                 the media header.


<at> param Protocol                The media header type. If this parameter is NULL, then the
                                 protocol will not be extracted from the media header. See


                                 RFC 1700 section "Ether Types" for examples.



<at> retval EFI_SUCCESS            The received data was stored in Buffer, and
                                 BufferSize has been updated to the number of


                                 bytes received.


<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_NOT_READY          No packets have been received on the network interface.
<at> retval EFI_BUFFER_TOO_SMALL   BufferSize is too small for the received packets.
                                 BufferSize has been updated to the required size.


<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * The This parameter is NULL


                                 * The This parameter does not point to a valid


                                   EFI_SIMPLE_NETWORK_PROTOCOL structure.


                                 * The BufferSize parameter is NULL


                                 * The Buffer parameter is NULL


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpReceive (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
OUT UINTN                      *HeaderSize OPTIONAL,
IN OUT UINTN                   *BufferSize,
OUT VOID                       *Buffer,
OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
OUT EFI_MAC_ADDRESS            *DestAddr OPTIONAL,
OUT UINT16                     *Protocol OPTIONAL
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *Snp;
EFI_TPL       OldTpl;

if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

Snp = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (Snp->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

if ((BufferSize == NULL) || (Buffer == NULL)) {
Status = EFI_INVALID_PARAMETER;
goto ON_EXIT;
}

Status = mskc_receive (BufferSize, Buffer);
if (EFI_ERROR (Status)) {
if (Status == EFI_NOT_READY) {
 goto ON_EXIT_NO_DEBUG;


}
} else {
// Extract header info
if (HeaderSize != NULL) {
 *HeaderSize = sizeof (ETHER_HEAD);


}

if (SrcAddr != NULL) {
 ZeroMem (SrcAddr, NET_ETHER_ADDR_LEN);


 CopyMem (SrcAddr, ((UINT8 *) Buffer) + NET_ETHER_ADDR_LEN, NET_ETHER_ADDR_LEN);


}

if (DestAddr != NULL) {
 ZeroMem (DestAddr, NET_ETHER_ADDR_LEN);


 CopyMem (DestAddr, ((UINT8 *) Buffer), NET_ETHER_ADDR_LEN);


}

if (Protocol != NULL) {
 *Protocol = NTOHS (*((UINT16 *) (((UINT8 *) Buffer) + (2 * NET_ETHER_ADDR_LEN))));


}
}


+ON_EXIT:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceive() Status = %r\n", Status));


+ON_EXIT_NO_DEBUG:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Manages the multicast receive filters of a network interface.

This function is used enable and disable the hardware and software receive
filters for the underlying network device.
The receive filter change is broken down into three steps:

The filter mask bits that are set (ON) in the Enable parameter are added to


the current receive filter settings.

The filter mask bits that are set (ON) in the Disable parameter are subtracted


from the updated receive filter settings.

If the resulting receive filter setting is not supported by the hardware a


more liberal setting is selected.
If the same bits are set in the Enable and Disable parameters, then the bits
in the Disable parameter takes precedence.
If the ResetMCastFilter parameter is TRUE, then the multicast address list
filter is disabled (irregardless of what other multicast bits are set in the
Enable and Disable parameters). The SNP->Mode->MCastFilterCount field is set
to zero. The Snp->Mode->MCastFilter contents are undefined.
After enabling or disabling receive filter settings, software should verify
the new settings by checking the Snp->Mode->ReceiveFilterSettings,
Snp->Mode->MCastFilterCount and Snp->Mode->MCastFilter fields.
Note: Some network drivers and/or devices will automatically promote receive
filter settings if the requested setting can not be honored. For example, if
a request for four multicast addresses is made and the underlying hardware
only supports two multicast addresses the driver might set the promiscuous
or promiscuous multicast receive filters instead. The receiving software is
responsible for discarding any extra packets that get through the hardware
receive filters.
Note: Note: To disable all receive filter hardware, the network driver must
 be Shutdown() and Stopped(). Calling ReceiveFilters() with Disable set to


 Snp->Mode->ReceiveFilterSettings will make it so no more packets are


 returned by the Receive() function, but the receive hardware may still be


 moving packets into system memory before inspecting and discarding them.


 Unexpected system errors, reboots and hangs can occur if an OS is loaded


 and the network devices are not Shutdown() and Stopped().


If ResetMCastFilter is TRUE, then the multicast receive filter list on the
network interface will be reset to the default multicast receive filter list.
If ResetMCastFilter is FALSE, and this network interface allows the multicast
receive filter list to be modified, then the MCastFilterCnt and MCastFilter
are used to update the current multicast receive filter list. The modified
receive filter list settings can be found in the MCastFilter field of
EFI_SIMPLE_NETWORK_MODE. If the network interface does not allow the multicast
receive filter list to be modified, then EFI_INVALID_PARAMETER will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
If the receive filter mask and multicast receive filter list have been
successfully updated on the network interface, EFI_SUCCESS will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Enable                  A bit mask of receive filters to enable on the network
                                 interface.


<at> param Disable                 A bit mask of receive filters to disable on the network
                                 interface. For backward compatibility with EFI 1.1


                                 platforms, the EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit


                                 must be set when the ResetMCastFilter parameter is TRUE.


<at> param ResetMCastFilter        Set to TRUE to reset the contents of the multicast
                                 receive filters on the network interface to their


                                 default values.


<at> param MCastFilterCnt          Number of multicast HW MAC addresses in the new MCastFilter
                                 list. This value must be less than or equal to the


                                 MCastFilterCnt field of EFI_SIMPLE_NETWORK_MODE.


                                 This field is optional if ResetMCastFilter is TRUE.


<at> param MCastFilter             A pointer to a list of new multicast receive filter HW
                                 MAC addresses. This list will replace any existing


                                 multicast HW MAC address list. This field is optional


                                 if ResetMCastFilter is TRUE.



<at> retval EFI_SUCCESS            The multicast receive filter list was updated.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
                                 * This is NULL


                                 * There are bits set in Enable that are not set


                                   in Snp->Mode->ReceiveFilterMask


                                 * There are bits set in Disable that are not set


                                   in Snp->Mode->ReceiveFilterMask


                                 * Multicast is being enabled (the


                                   EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is


                                   set in Enable, it is not set in Disable, and


                                   ResetMCastFilter is FALSE) and MCastFilterCount


                                   is zero


                                 * Multicast is being enabled and MCastFilterCount


                                   is greater than Snp->Mode->MaxMCastFilterCount


                                 * Multicast is being enabled and MCastFilter is NULL


                                 * Multicast is being enabled and one or more of


                                   the addresses in the MCastFilter list are not


                                   valid multicast MAC addresses


<at> retval EFI_DEVICE_ERROR       One or more of the following conditions is TRUE:
                                 * The network interface has been started but has


                                   not been initialized


                                 * An unexpected error was returned by the


                                   underlying network driver or device


<at> retval EFI_UNSUPPORTED        This function is not supported by the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINT32                      Enable,
IN UINT32                      Disable,
IN BOOLEAN                     ResetMCastFilter,
IN UINTN                       MCastFilterCnt,  OPTIONAL
IN EFI_MAC_ADDRESS             *MCastFilter     OPTIONAL
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;
UINT32        newReceiveFilter;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters()\n"));
if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_ERROR_RESTORE_TPL;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}
//
// check if we are asked to enable or disable something that the NIC
// does not even support!
//
newReceiveFilter = (YukonDriver->SnpMode.ReceiveFilterSetting | Enable) & ~Disable;
if ((newReceiveFilter & ~YukonDriver->SnpMode.ReceiveFilterMask) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters() NIC does not support Enable = 0x%x, Disable = 0x%x\n", Enable, Disable));
Status = EFI_INVALID_PARAMETER;
goto ON_ERROR_RESTORE_TPL;
}

if (ResetMCastFilter) {
newReceiveFilter &= ~(EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST & YukonDriver->SnpMode.ReceiveFilterMask);
MCastFilterCnt = 0;
MCastFilter    = NULL;
} else {
if (MCastFilterCnt != 0) {
 if ((MCastFilterCnt > YukonDriver->SnpMode.MaxMCastFilterCount) ||


     (MCastFilter == NULL)) {



   DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters() NIC does not support MCastFilterCnt = %d (Max = %d)\n", MCastFilterCnt,


           YukonDriver->SnpMode.MaxMCastFilterCount));


   Status = EFI_INVALID_PARAMETER;


   goto ON_ERROR_RESTORE_TPL;


 }


}
}

if (newReceiveFilter == YukonDriver->SnpMode.ReceiveFilterSetting && !ResetMCastFilter && MCastFilterCnt == 0) {
Status = EFI_SUCCESS;
goto ON_EXIT;
}

if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) != 0 && MCastFilterCnt == 0) {
Status = EFI_INVALID_PARAMETER;
goto ON_ERROR_RESTORE_TPL;
}

YukonDriver->SnpMode.ReceiveFilterSetting = newReceiveFilter;
mskc_rxfilter (YukonDriver->SnpMode.ReceiveFilterSetting, MCastFilterCnt, MCastFilter);

Status = EFI_SUCCESS;
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Resets a network adapter and reinitializes it with the parameters that were
provided in the previous call to Initialize().

This function resets a network adapter and reinitializes it with the parameters
that were provided in the previous call to Initialize(). The transmit and
receive queues are emptied and all pending interrupts are cleared.
Receive filters, the station address, the statistics, and the multicast-IP-to-HW
MAC addresses are not reset by this call. If the network interface was
successfully reset, then EFI_SUCCESS will be returned. If the driver has not
been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param ExtendedVerification    Indicates that the driver may perform a more
                                 exhaustive verification operation of the device


                                 during reset.



<at> retval EFI_SUCCESS            The network interface was reset.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported value.
<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpReset (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     ExtendedVerification
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReset()\n"));
//
// Resolve Warning 4 unreferenced parameter problem
//
ExtendedVerification = 0;
DEBUG ((EFI_D_WARN, "ExtendedVerification = %d is not implemented!\n", ExtendedVerification));

if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReset() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_ERROR_RESTORE_TPL;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}

// Always succeeds
Status = EFI_SUCCESS;
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReset() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Resets a network adapter and leaves it in a state that is safe for another
driver to initialize.

This function releases the memory buffers assigned in the Initialize() call.
Pending transmits and receives are lost, and interrupts are cleared and disabled.
After this call, only the Initialize() and Stop() calls may be used. If the
network interface was successfully shutdown, then EFI_SUCCESS will be returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> retval EFI_SUCCESS            The network interface was shutdown.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpShutdown (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpShutdown()\n"));
//
// Get pointer to SNP driver instance for *This.
//
if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpShutdown() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

//
// Return error if the SNP is not initialized.
//
switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_ERROR_RESTORE_TPL;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}

mskc_shutdown ();
YukonDriver->SnpMode.State = EfiSimpleNetworkStarted;
Status = EFI_SUCCESS;

YukonDriver->SnpMode.State                 = EfiSimpleNetworkStarted;
YukonDriver->SnpMode.ReceiveFilterSetting  = 0;

YukonDriver->SnpMode.MCastFilterCount      = 0;
YukonDriver->SnpMode.ReceiveFilterSetting  = 0;
ZeroMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter);
CopyMem (
   &YukonDriver->SnpMode.CurrentAddress,


   &YukonDriver->SnpMode.PermanentAddress,


   sizeof (EFI_MAC_ADDRESS)


   );



gBS->CloseEvent (YukonDriver->Snp.WaitForPacket);
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpShutdown() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Change the state of a network interface from "stopped" to "started."

This function starts a network interface. If the network interface successfully
starts, then EFI_SUCCESS will be returned.

<at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.

<at> retval EFI_SUCCESS            The network interface was started.
<at> retval EFI_ALREADY_STARTED    The network interface is already in the started state.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
                                 EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpStart (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
)

+{

YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;
EFI_STATUS    Status;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStart()\n"));
if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStart() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkStopped:
 break;



case EfiSimpleNetworkStarted:
case EfiSimpleNetworkInitialized:
 Status = EFI_ALREADY_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}

Status = mskc_attach (YukonDriver->PciIo, &YukonDriver->SnpMode.PermanentAddress);

if (EFI_ERROR (Status)) {
goto ON_ERROR_RESTORE_TPL;
}

YukonDriver->SnpMode.State = EfiSimpleNetworkStarted;
CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS));
YukonDriver->SnpMode.MCastFilterCount = 0;
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStart() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Modifies or resets the current station address, if supported.

This function modifies or resets the current station address of a network
interface, if supported. If Reset is TRUE, then the current station address is
set to the network interface's permanent address. If Reset is FALSE, and the
network interface allows its station address to be modified, then the current
station address is changed to the address specified by New. If the network
interface does not allow its station address to be modified, then
EFI_INVALID_PARAMETER will be returned. If the station address is successfully
updated on the network interface, EFI_SUCCESS will be returned. If the driver
has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Reset                   Flag used to reset the station address to the network interface's
                                 permanent address.


<at> param New                     New station address to be used for the network interface.


<at> retval EFI_SUCCESS            The network interface's station address was updated.
<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
                                                            started by calling Start().


<at> retval EFI_INVALID_PARAMETER  The New station address was not accepted by the NIC.
<at> retval EFI_INVALID_PARAMETER  Reset is FALSE and New is NULL.
<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_DEVICE_ERROR       An error occurred attempting to set the new
                                 station address.


<at> retval EFI_UNSUPPORTED        The NIC does not support changing the network
                                 interface's station address.




+**/
+EFI_STATUS
+EFIAPI
+SnpStationAddress (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     Reset,
IN EFI_MAC_ADDRESS             *New OPTIONAL
)

+{

YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;
EFI_STATUS    Status;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStationAddress()\n"));
//
// Check for invalid parameter combinations.
//
if ((This == NULL) || (!Reset && (New == NULL))) {
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

//
// Return error if the SNP is not initialized.
//
switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

Status = EFI_UNSUPPORTED;


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Resets or collects the statistics on a network interface.

This function resets or collects the statistics on a network interface. If the
size of the statistics table specified by StatisticsSize is not big enough for
all the statistics that are collected by the network interface, then a partial
buffer of statistics is returned in StatisticsTable, StatisticsSize is set to
the size required to collect all the available statistics, and
EFI_BUFFER_TOO_SMALL is returned.
If StatisticsSize is big enough for all the statistics, then StatisticsTable
will be filled, StatisticsSize will be set to the size of the returned
StatisticsTable structure, and EFI_SUCCESS is returned.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
If Reset is FALSE, and both StatisticsSize and StatisticsTable are NULL, then
no operations will be performed, and EFI_SUCCESS will be returned.
If Reset is TRUE, then all of the supported statistics counters on this network
interface will be reset to zero.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param Reset                   Set to TRUE to reset the statistics for the network interface.
<at> param StatisticsSize          On input the size, in bytes, of StatisticsTable. On output
                                 the size, in bytes, of the resulting table of statistics.


<at> param StatisticsTable         A pointer to the EFI_NETWORK_STATISTICS structure that
                                 contains the statistics. Type EFI_NETWORK_STATISTICS is


                                 defined in "Related Definitions" below.



<at> retval EFI_SUCCESS            The requested operation succeeded.
<at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
                                 started by calling Start().


<at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
                                 NULL. The current buffer size that is needed to


                                 hold all the statistics is returned in StatisticsSize.


<at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
                                 not NULL. The current buffer size that is needed


                                 to hold all the statistics is returned in


                                 StatisticsSize. A partial set of statistics is


                                 returned in StatisticsTable.


<at> retval EFI_INVALID_PARAMETER  StatisticsSize is NULL and StatisticsTable is not
                                 NULL.


<at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
                                 been initialized by calling Initialize().


<at> retval EFI_DEVICE_ERROR       An error was encountered collecting statistics
                                 from the NIC.


<at> retval EFI_UNSUPPORTED        The NIC does not support collecting statistics
                                 from the network interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpStatistics (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN BOOLEAN                     Reset,
IN OUT UINTN                   *StatisticsSize, OPTIONAL
IN OUT EFI_NETWORK_STATISTICS  *StatisticsTable OPTIONAL
)

+{

EFI_STATUS        Status;
YUKON_DRIVER        *YukonDriver;
EFI_TPL           OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStatistics()\n"));
//
// Get pointer to SNP driver instance for *This.
//
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

Status = EFI_SUCCESS;
YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

//
// Return error if the SNP is not initialized.
//
switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



case EfiSimpleNetworkStarted:
default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

//
// Error Checking
//

if (!Reset && (StatisticsSize == NULL) && (StatisticsTable == NULL)) {
Status = EFI_SUCCESS;
goto ON_EXIT;
}

if ((StatisticsSize == NULL) && (StatisticsTable != NULL)) {
Status = EFI_INVALID_PARAMETER;
goto ON_EXIT;
}

if ((StatisticsSize != NULL) && (StatisticsTable == NULL)) {
*StatisticsSize = sizeof (EFI_NETWORK_STATISTICS);
Status = EFI_BUFFER_TOO_SMALL;
goto ON_EXIT;
}

if ((StatisticsSize != NULL) && (StatisticsTable != NULL)) {
if (*StatisticsSize < sizeof (EFI_NETWORK_STATISTICS)) {
 if (*StatisticsSize == 0) {


   Status = EFI_BUFFER_TOO_SMALL;


   // Note: From here on, the Status value must be preserved.


 } else {


   // FixMe: Return partial statistics for the available size and also set


   //        Status = EFI_BUFFER_TOO_SMALL;


   //        but for now it is unsupported.


   Status = EFI_UNSUPPORTED;


   // Note: From here on, the Status value must be preserved.


 }


 *StatisticsSize = sizeof (EFI_NETWORK_STATISTICS);


} else {
 // FixMe: Return full statistics and also set


 //        Status = EFI_SUCCESS;


 //        but for now it is unsupported.


 Status = EFI_UNSUPPORTED;


}
}

if (Reset == TRUE) {
// FixMe: Reset all statistics;

// Preserve any previous errors else return success.
if (!EFI_ERROR (Status)) {
 // FixMe: Should return success


 //        Status = EFI_SUCCESS;


 //        but for now it is unsupported.


 Status = EFI_UNSUPPORTED;


}
}


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Changes the state of a network interface from "started" to "stopped."

This function stops a network interface. This call is only valid if the network
interface is in the started state. If the network interface was successfully
stopped, then EFI_SUCCESS will be returned.

<at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL
                                                             instance.




<at> retval EFI_SUCCESS            The network interface was stopped.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a
                                 valid EFI_SIMPLE_NETWORK_PROTOCOL structure.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
                                 interface.


<at> retval EFI_UNSUPPORTED        This function is not supported by the network
                                 interface.




+**/
+EFI_STATUS
+EFIAPI
+SnpStop (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStop()\n"));
if (This == NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStop() failed with Status = %r\n", EFI_INVALID_PARAMETER));
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkStarted:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_ERROR_RESTORE_TPL;



case EfiSimpleNetworkInitialized:
default:
 Status = EFI_DEVICE_ERROR;


 goto ON_ERROR_RESTORE_TPL;


}

mskc_detach ();
YukonDriver->SnpMode.State = EfiSimpleNetworkStopped;
ZeroMem (&YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS));
Status = EFI_SUCCESS;
goto ON_EXIT;


+ON_ERROR_RESTORE_TPL:

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStop() failed with Status = %r\n", Status));


+ON_EXIT:

gBS->RestoreTPL (OldTpl);
return Status;

+}



+/**

Places a packet in the transmit queue of a network interface.

This function places the packet specified by Header and Buffer on the transmit
queue. If HeaderSize is nonzero and HeaderSize is not equal to
This->SnpMode->MediaHeaderSize, then EFI_INVALID_PARAMETER will be returned. If
BufferSize is less than This->SnpMode->MediaHeaderSize, then EFI_BUFFER_TOO_SMALL
will be returned. If Buffer is NULL, then EFI_INVALID_PARAMETER will be
returned. If HeaderSize is nonzero and DestAddr or Protocol is NULL, then
EFI_INVALID_PARAMETER will be returned. If the transmit engine of the network
interface is busy, then EFI_NOT_READY will be returned. If this packet can be
accepted by the transmit engine of the network interface, the packet contents
specified by Buffer will be placed on the transmit queue of the network
interface, and EFI_SUCCESS will be returned. GetStatus() can be used to
determine when the packet has actually been transmitted. The contents of the
Buffer must not be modified until the packet has actually been transmitted.
The Transmit() function performs nonblocking I/O. A caller who wants to perform
blocking I/O, should call Transmit(), and then GetStatus() until the
transmitted buffer shows up in the recycled transmit buffer.
If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.

<at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
<at> param HeaderSize              The size, in bytes, of the media header to be filled in by the
                                 Transmit() function. If HeaderSize is nonzero, then it must


                                 be equal to This->SnpMode->MediaHeaderSize and the DestAddr and


                                 Protocol parameters must not be NULL.


<at> param BufferSize              The size, in bytes, of the entire packet (media header and
                                 data) to be transmitted through the network interface.


<at> param Buffer                  A pointer to the packet (media header followed by data) to be
                                 transmitted. This parameter cannot be NULL. If HeaderSize is


                                 zero, then the media header in Buffer must already be filled


                                 in by the caller. If HeaderSize is nonzero, then the media


                                 header will be filled in by the Transmit() function.


<at> param SrcAddr                 The source HW MAC address. If HeaderSize is zero, then this
                                 parameter is ignored. If HeaderSize is nonzero and SrcAddr


                                 is NULL, then This->SnpMode->CurrentAddress is used for the


                                 source HW MAC address.


<at> param DestAddr                The destination HW MAC address. If HeaderSize is zero, then
                                 this parameter is ignored.


<at> param Protocol                The type of header to build. If HeaderSize is zero, then this
                                 parameter is ignored. See RFC 1700, section "Ether Types,"


                                 for examples.



<at> retval EFI_SUCCESS            The packet was placed on the transmit queue.
<at> retval EFI_NOT_STARTED        The network interface has not been started.
<at> retval EFI_NOT_READY          The network interface is too busy to accept this
                                 transmit request.


<at> retval EFI_BUFFER_TOO_SMALL   The BufferSize parameter is too small.
<at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported
                                 value.


<at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
<at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.


+**/
+EFI_STATUS
+EFIAPI
+SnpTransmit (

IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
IN UINTN                       HeaderSize,
IN UINTN                       BufferSize,
IN VOID                        *Buffer,
IN EFI_MAC_ADDRESS             *SrcAddr,  OPTIONAL
IN EFI_MAC_ADDRESS             *DestAddr, OPTIONAL
IN UINT16                      *Protocol  OPTIONAL
)

+{

EFI_STATUS    Status;
YUKON_DRIVER    *YukonDriver;
EFI_TPL       OldTpl;
ETHER_HEAD    *Frame;
UINT16        ProtocolNet;

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpTransmit()\n"));
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}

YukonDriver = YUKON_DEV_FROM_THIS (This);

if (YukonDriver == NULL) {
return EFI_DEVICE_ERROR;
}

OldTpl = gBS->RaiseTPL (TPL_CALLBACK);

switch (YukonDriver->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
 Status = EFI_NOT_STARTED;


 goto ON_EXIT;



default:
 Status = EFI_DEVICE_ERROR;


 goto ON_EXIT;


}

if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto ON_EXIT;
}

if (BufferSize < YukonDriver->SnpMode.MediaHeaderSize) {
Status = EFI_BUFFER_TOO_SMALL;
goto ON_EXIT;
}

//
// Construct the frame header if not already presented
//
if (HeaderSize != 0) {
if (HeaderSize != YukonDriver->SnpMode.MediaHeaderSize || DestAddr == 0 || Protocol == 0) {
 Status = EFI_INVALID_PARAMETER;


 goto ON_EXIT;


}
Frame       = (ETHER_HEAD*)Buffer;
ProtocolNet = NTOHS (*Protocol);

CopyMem (Frame->SrcMac,     SrcAddr,      NET_ETHER_ADDR_LEN);
CopyMem (Frame->DstMac,     DestAddr,     NET_ETHER_ADDR_LEN);
CopyMem (&Frame->EtherType, &ProtocolNet, sizeof (UINT16));
}

Status = mskc_transmit (BufferSize, Buffer);


+ON_EXIT:

gBS->RestoreTPL (OldTpl);

return Status;

+}



+/**

Notification call back function for WaitForPacket event.

<at> param  Event       EFI Event.
<at> param  SnpPtr      Pointer to YUKON_DRIVER structure.


+**/
+VOID
+EFIAPI
+SnpWaitForPacketNotify (

EFI_EVENT     Event,
VOID          *SnpPtr
)

+{

DEBUG ((EFI_D_NET, "Marvell Yukon: SnpWaitForPacketNotify()\n"));
//
// Do nothing if either parameter is a NULL pointer.
//
if (Event == NULL || SnpPtr == NULL) {
return ;
}
//
// Do nothing if the SNP interface is not initialized.
//
switch (((YUKON_DRIVER *) SnpPtr)->SnpMode.State) {
case EfiSimpleNetworkInitialized:
 break;



case EfiSimpleNetworkStopped:
case EfiSimpleNetworkStarted:
default:
 return ;


}
//  if (PxeDbGetStatus.RxFrameLen != 0) {
//    gBS->SignalEvent (Event);
//  }

+}
diff --git a/Drivers/Net/MarvellYukonDxe/e1000phy.c b/Drivers/Net/MarvellYukonDxe/e1000phy.c
new file mode 100644
index 0000000..d544e88
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/e1000phy.c
@@ -0,0 +1,659 @@
+/**  <at> file
+*  Support for Marvell 88E1000 Series PHYs
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*-


Principal Author: Parag Patel



Copyright (c) 2001



All rights reserved.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice unmodified, this list of conditions, and the following



disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.







THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND



ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE



IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE



ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE



FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL



DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS



OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)



HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT



LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY



OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF



SUCH DAMAGE.







Additonal Copyright (c) 2001 by Traakan Software under same licence.



Secondary Author: Matthew Jacob


*/


+/*


driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.


*/


+/*


Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and



1000baseSX PHY.



Nathan Binkert <nate <at> openbsd.org>



Jung-uk Kim <jkim <at> niksun.com>


*/


+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>



+#include "if_media.h"



+#include "miivar.h"



+#include "e1000phyreg.h"



+static EFI_STATUS e1000phy_probe (const struct mii_attach_args *ma);
+static void  e1000phy_attach (const struct mii_attach_args *ma);
+static const struct mii_phydesc * mii_phy_match (const struct mii_attach_args *ma,

                                            const struct mii_phydesc *mpd);



+static const struct mii_phydesc * mii_phy_match_gen (const struct mii_attach_args *ma,

                                                const struct mii_phydesc *mpd, UINTN endlen);



+static EFI_STATUS mii_phy_dev_probe (const struct mii_attach_args *ma, const struct mii_phydesc *mpd);



+struct e1000phy_softc {

struct mii_softc mii_sc;
INTN mii_model;
const struct msk_mii_data *mmd;

+};



+struct e1000phy_softc *mPhySoftc;



+static void mii_phy_update (INTN);
+static void  e1000phy_service (INTN);
+static void  e1000phy_status (struct mii_softc *);
+static void  e1000phy_reset (struct mii_softc *);
+static void  e1000phy_mii_phy_auto (void);



+static const struct mii_phydesc e1000phys[] = {

MII_PHY_DESC (MARVELL, E1000),
MII_PHY_DESC (MARVELL, E1011),
MII_PHY_DESC (MARVELL, E1000_3),
MII_PHY_DESC (MARVELL, E1000S),
MII_PHY_DESC (MARVELL, E1000_5),
MII_PHY_DESC (MARVELL, E1000_6),
MII_PHY_DESC (MARVELL, E3082),
MII_PHY_DESC (MARVELL, E1112),
MII_PHY_DESC (MARVELL, E1149),
MII_PHY_DESC (MARVELL, E1111),
MII_PHY_DESC (MARVELL, E1116),
MII_PHY_DESC (MARVELL, E1116R),
MII_PHY_DESC (MARVELL, E1118),
MII_PHY_DESC (MARVELL, E3016),
MII_PHY_DESC (MARVELL, PHYG65G),
MII_PHY_DESC (xxMARVELL, E1000),
MII_PHY_DESC (xxMARVELL, E1011),
MII_PHY_DESC (xxMARVELL, E1000_3),
MII_PHY_DESC (xxMARVELL, E1000_5),
MII_PHY_DESC (xxMARVELL, E1111),
MII_PHY_END

+};



+EFI_STATUS
+e1000_probe_and_attach (

struct mii_data             *mii,
const struct msk_mii_data   *mmd
)

+{

struct mii_attach_args    ma;
INTN                      bmsr;
EFI_STATUS                Status;

mPhySoftc = AllocateZeroPool (sizeof (struct e1000phy_softc));
if (mPhySoftc == NULL) {
return EFI_OUT_OF_RESOURCES;
}
mPhySoftc->mmd = mmd;


/*

Check to see if there is a PHY at this address.  Note,



many braindead PHYs report 0/0 in their ID registers,



so we test for media in the BMSR.


*/
bmsr = PHY_READ (mPhySoftc, E1000_SR);
if (bmsr == 0 || bmsr == 0xffff || (bmsr & (E1000_SR_EXTENDED_STATUS|E1000_SR_MEDIAMASK)) == 0) {
/* Assume no PHY at this address. */
FreePool (mPhySoftc);
return EFI_DEVICE_ERROR;
}

/*

Extract the IDs.


*/
ma.mii_id1 = PHY_READ (mPhySoftc, E1000_ID1);
ma.mii_id2 = PHY_READ (mPhySoftc, E1000_ID2);

ma.mii_data = mii;

Status = e1000phy_probe (&ma);
if (EFI_ERROR (Status)) {
FreePool (mPhySoftc);
return Status;
}

e1000phy_attach (&ma);
return EFI_SUCCESS;

+}



+EFI_STATUS
+e1000phy_probe (

const struct mii_attach_args    *ma
)

+{

return (mii_phy_dev_probe (ma, e1000phys));

+}



+static void
+e1000phy_attach (

const struct mii_attach_args    *ma
)

+{

struct mii_softc    *sc;

sc = &mPhySoftc->mii_sc;
sc->mii_pdata = ma->mii_data;
sc->mii_anegticks = MII_ANEGTICKS_GIGE;

mPhySoftc->mii_model = MII_MODEL (ma->mii_id2);

if (mPhySoftc->mmd != NULL && (mPhySoftc->mmd->mii_flags & MIIF_HAVEFIBER) != 0) {
sc->mii_flags |= MIIF_HAVEFIBER;
}

switch (mPhySoftc->mii_model) {
case MII_MODEL_MARVELL_E1011:
case MII_MODEL_MARVELL_E1112:
 if (PHY_READ (mPhySoftc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) {


   sc->mii_flags |= MIIF_HAVEFIBER;


 }


 break;


case MII_MODEL_MARVELL_E1149:
 /*


* Some 88E1149 PHY's page select is initialized to


* point to other bank instead of copper/fiber bank


* which in turn resulted in wrong registers were


* accessed during PHY operation. It is believed that


* page 0 should be used for copper PHY so reinitialize


* E1000_EADR to select default copper PHY. If parent


* device know the type of PHY(either copper or fiber),


* that information should be used to select default


* type of PHY.


*/


 PHY_WRITE (mPhySoftc, E1000_EADR, 0);


 break;


}

e1000phy_reset (sc);

sc->mii_capabilities = PHY_READ (mPhySoftc, E1000_SR) & 0xFFFFFFFF;
if (sc->mii_capabilities & E1000_SR_EXTENDED_STATUS) {
sc->mii_extcapabilities = PHY_READ (mPhySoftc, E1000_ESR);
}

+}



+static void
+e1000phy_reset (

struct mii_softc    *sc
)

+{

UINT16  reg;
UINT16  page;

reg = PHY_READ (mPhySoftc, E1000_SCR);
if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
reg &= ~E1000_SCR_AUTO_X_MODE;
PHY_WRITE (mPhySoftc, E1000_SCR, reg);
if (mPhySoftc->mii_model == MII_MODEL_MARVELL_E1112) {
 // Select 1000BASE-X only mode.


 page = PHY_READ (mPhySoftc, E1000_EADR);


 PHY_WRITE (mPhySoftc, E1000_EADR, 2);


 reg = PHY_READ (mPhySoftc, E1000_SCR);


 reg &= ~E1000_SCR_MODE_MASK;


 reg |= E1000_SCR_MODE_1000BX;


 PHY_WRITE (mPhySoftc, E1000_SCR, reg);


 if (mPhySoftc->mmd != NULL && mPhySoftc->mmd->pmd == 'P') {


   // Set SIGDET polarity low for SFP module


   PHY_WRITE (mPhySoftc, E1000_EADR, 1);


   reg = PHY_READ (mPhySoftc, E1000_SCR);


   reg |= E1000_SCR_FIB_SIGDET_POLARITY;


   PHY_WRITE (mPhySoftc, E1000_SCR, reg);


 }


 PHY_WRITE (mPhySoftc, E1000_EADR, page);


}
} else {
switch (mPhySoftc->mii_model) {
 case MII_MODEL_MARVELL_E1111:


 case MII_MODEL_MARVELL_E1112:


 case MII_MODEL_MARVELL_E1116:


 case MII_MODEL_MARVELL_E1118:


 case MII_MODEL_MARVELL_E1149:


 case MII_MODEL_MARVELL_PHYG65G:


   // Disable energy detect mode


   reg &= ~E1000_SCR_EN_DETECT_MASK;


   reg |= E1000_SCR_AUTO_X_MODE;


   if (mPhySoftc->mii_model == MII_MODEL_MARVELL_E1116)


     reg &= ~E1000_SCR_POWER_DOWN;


   reg |= E1000_SCR_ASSERT_CRS_ON_TX;


   break;


 case MII_MODEL_MARVELL_E3082:


   reg |= (E1000_SCR_AUTO_X_MODE >> 1);


   reg |= E1000_SCR_ASSERT_CRS_ON_TX;


   break;


 case MII_MODEL_MARVELL_E3016:


   reg |= E1000_SCR_AUTO_MDIX;


   reg &= ~(E1000_SCR_EN_DETECT |


            E1000_SCR_SCRAMBLER_DISABLE);


   reg |= E1000_SCR_LPNP;


   // XXX Enable class A driver for Yukon FE+ A0


   PHY_WRITE (mPhySoftc, 0x1C, PHY_READ (mPhySoftc, 0x1C) | 0x0001);


   break;


 default:


   reg &= ~E1000_SCR_AUTO_X_MODE;


   reg |= E1000_SCR_ASSERT_CRS_ON_TX;


   break;


}
if (mPhySoftc->mii_model != MII_MODEL_MARVELL_E3016) {
 /* Auto correction for reversed cable polarity. */


 reg &= ~E1000_SCR_POLARITY_REVERSAL;


}
PHY_WRITE (mPhySoftc, E1000_SCR, reg);

if (mPhySoftc->mii_model == MII_MODEL_MARVELL_E1116 ||
   mPhySoftc->mii_model == MII_MODEL_MARVELL_E1149) {


 PHY_WRITE (mPhySoftc, E1000_EADR, 2);


 reg = PHY_READ (mPhySoftc, E1000_SCR);


 reg |= E1000_SCR_RGMII_POWER_UP;


 PHY_WRITE (mPhySoftc, E1000_SCR, reg);


 PHY_WRITE (mPhySoftc, E1000_EADR, 0);


}
}

switch (mPhySoftc->mii_model) {
case MII_MODEL_MARVELL_E3082:
case MII_MODEL_MARVELL_E1112:
case MII_MODEL_MARVELL_E1118:
 break;


case MII_MODEL_MARVELL_E1116:
 page = PHY_READ (mPhySoftc, E1000_EADR);


 /* Select page 3, LED control register. */


 PHY_WRITE (mPhySoftc, E1000_EADR, 3);


 PHY_WRITE (mPhySoftc, E1000_SCR,


            E1000_SCR_LED_LOS (1) |  /* Link/Act */


            E1000_SCR_LED_INIT (8) |  /* 10Mbps */


            E1000_SCR_LED_STAT1 (7) |  /* 100Mbps */


            E1000_SCR_LED_STAT0 (7));  /* 1000Mbps */


 /* Set blink rate. */


 PHY_WRITE (mPhySoftc, E1000_IER, E1000_PULSE_DUR (E1000_PULSE_170MS) | E1000_BLINK_RATE (E1000_BLINK_84MS));


 PHY_WRITE (mPhySoftc, E1000_EADR, page);


 break;


case MII_MODEL_MARVELL_E3016:
 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */


 PHY_WRITE (mPhySoftc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);


 /* Integrated register calibration workaround. */


 PHY_WRITE (mPhySoftc, 0x1D, 17);


 PHY_WRITE (mPhySoftc, 0x1E, 0x3F60);


 break;


default:
 /* Force TX_CLK to 25MHz clock. */


 reg = PHY_READ (mPhySoftc, E1000_ESCR);


 reg |= E1000_ESCR_TX_CLK_25;


 PHY_WRITE (mPhySoftc, E1000_ESCR, reg);


 break;


}

/* Reset the PHY so all changes take effect. */
reg = PHY_READ (mPhySoftc, E1000_CR);
reg |= E1000_CR_RESET;
PHY_WRITE (mPhySoftc, E1000_CR, reg);

+}



+static void
+mii_phy_update (

INTN    cmd
)

+{

struct mii_softc      *sc = &mPhySoftc->mii_sc;
struct mii_data       *mii = sc->mii_pdata;

if (sc->mii_media_active != mii->mii_media_active ||
 sc->mii_media_status != mii->mii_media_status ||


 cmd == MII_MEDIACHG)


{
msk_miibus_statchg (mPhySoftc->mmd->port);
sc->mii_media_active = mii->mii_media_active;
sc->mii_media_status = mii->mii_media_status;
}

+}



+void
+e1000phy_tick (

VOID
)

+{

e1000phy_service (MII_TICK);

+}



+void
+e1000phy_mediachg (

VOID
)

+{

struct mii_data *mii = mPhySoftc->mii_sc.mii_pdata;
mii->mii_media_status = 0;
mii->mii_media_active = IFM_NONE;
e1000phy_service (MII_MEDIACHG);

+}



+static void
+e1000phy_service (

INTN cmd
)

+{

struct mii_softc    *sc = &mPhySoftc->mii_sc;
INTN                reg;

switch (cmd) {
case MII_POLLSTAT:
 break;



case MII_MEDIACHG:
 //


 // Always try to auto-negotiate


 //


 e1000phy_mii_phy_auto ();


 break;



 /*    speed = 0;


switch (IFM_SUBTYPE (ife->ifm_media)) {
case IFM_1000_T:
 if ((sc->mii_extcapabilities &


     (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)


   return (EINVAL);


 speed = E1000_CR_SPEED_1000;


 break;


case IFM_1000_SX:
 if ((sc->mii_extcapabilities &


     (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)


   return (EINVAL);


 speed = E1000_CR_SPEED_1000;


 break;


case IFM_100_TX:
 speed = E1000_CR_SPEED_100;


 break;


case IFM_10_T:
 speed = E1000_CR_SPEED_10;


 break;


case IFM_NONE:
 reg = PHY_READ (sc, E1000_CR);


 PHY_WRITE (sc, E1000_CR,


     reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);


 goto done;


default:
 return (EINVAL);


}

if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
 speed |= E1000_CR_FULL_DUPLEX;


 gig = E1000_1GCR_1000T_FD;


} else
 gig = E1000_1GCR_1000T;



reg = PHY_READ (sc, E1000_CR);
reg &= ~E1000_CR_AUTO_NEG_ENABLE;
PHY_WRITE (sc, E1000_CR, reg | E1000_CR_RESET);

+*/

 /*


* When setting the link manually, one side must


* be the master and the other the slave. However


* ifmedia doesn't give us a good way to specify


* this, so we fake it by using one of the LINK


* flags. If LINK0 is set, we program the PHY to


* be a master, otherwise it's a slave.


*/


 /*    if (IFM_SUBTYPE (ife->ifm_media) == IFM_1000_T ||


   (IFM_SUBTYPE (ife->ifm_media) == IFM_1000_SX)) {


 if ((mii->mii_ifp->if_flags & IFF_LINK0))


   PHY_WRITE (sc, E1000_1GCR, gig |


       E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE);


 else


   PHY_WRITE (sc, E1000_1GCR, gig |


       E1000_1GCR_MS_ENABLE);


} else {
 if ((sc->mii_extcapabilities &


     (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)


   PHY_WRITE (sc, E1000_1GCR, 0);


}
PHY_WRITE (sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
PHY_WRITE (sc, E1000_CR, speed | E1000_CR_RESET);

+done:

break;*/
case MII_TICK:
 /*


* Only used for autonegotiation.


*/


 /*    if (IFM_SUBTYPE (ife->ifm_media) != IFM_AUTO) {


 sc->mii_ticks = 0;


 break;


}*/

 /*


* check for link.


* Read the status register twice; Link Status is latch-low.


*/


 reg = PHY_READ (mPhySoftc, E1000_SR) | PHY_READ (mPhySoftc, E1000_SR);


 if (reg & E1000_SR_LINK_STATUS) {


   sc->mii_ticks = 0;


   break;


 }



 /* Announce link loss right after it happens. */


 if (sc->mii_ticks++ == 0) {


   break;


 }


 if (sc->mii_ticks <= sc->mii_anegticks) {


   break;


 }



 //


 // Restart the auto-negotiation


 //


 sc->mii_ticks = 0;


 e1000phy_reset (sc);


 e1000phy_mii_phy_auto ();


 break;


}

/* Update the media status. */
e1000phy_status (sc);

/* Callback if something changed. */
mii_phy_update (cmd);

+}



+static void
+e1000phy_status (

struct mii_softc  *sc
)

+{

struct mii_data     *mii = sc->mii_pdata;
INTN                bmcr;
INTN                bmsr;
INTN                gsr;
INTN                ssr;
INTN                ar;
INTN                lpar;

mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;

bmsr = PHY_READ (mPhySoftc, E1000_SR) | PHY_READ (mPhySoftc, E1000_SR);
bmcr = PHY_READ (mPhySoftc, E1000_CR);
ssr = PHY_READ (mPhySoftc, E1000_SSR);

if (bmsr & E1000_SR_LINK_STATUS) {
DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_status, link up\n"));
mii->mii_media_status |= IFM_ACTIVE;
}

if (bmcr & E1000_CR_LOOPBACK) {
mii->mii_media_active |= IFM_LOOP;
}

if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
/* Erg, still trying, I guess... */
DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_status, auto negotiation not complete\n"));
mii->mii_media_active |= IFM_NONE;
return;
}

if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
switch (ssr & E1000_SSR_SPEED) {
 case E1000_SSR_1000MBS:


   mii->mii_media_active |= IFM_1000_T;


   break;


 case E1000_SSR_100MBS:


   mii->mii_media_active |= IFM_100_TX;


   break;


 case E1000_SSR_10MBS:


   mii->mii_media_active |= IFM_10_T;


   break;


 default:


   mii->mii_media_active |= IFM_NONE;


   return;


}
} else {
/*
* Some fiber PHY(88E1112) does not seem to set resolved


* speed so always assume we've got IFM_1000_SX.


*/


mii->mii_media_active |= IFM_1000_SX;
}

if (ssr & E1000_SSR_DUPLEX) {
mii->mii_media_active |= IFM_FDX;
} else {
mii->mii_media_active |= IFM_HDX;
}

if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
ar = PHY_READ (mPhySoftc, E1000_AR);
lpar = PHY_READ (mPhySoftc, E1000_LPAR);
/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;


} else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
          (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {


 mii->mii_media_active |= IFM_FLAG1;


} else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
          !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {


 mii->mii_media_active |= IFM_FLAG0;


}
}

/* FLAG2 : local PHY resolved to MASTER */
if ((IFM_SUBTYPE (mii->mii_media_active) == IFM_1000_T) ||
 (IFM_SUBTYPE (mii->mii_media_active) == IFM_1000_SX)) {


PHY_READ (mPhySoftc, E1000_1GSR);
gsr = PHY_READ (mPhySoftc, E1000_1GSR);
if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0) {
 mii->mii_media_active |= IFM_FLAG2;


}
}

+}



+static void
+e1000phy_mii_phy_auto (

VOID
)

+{

struct mii_softc    *sc;
UINT16              reg;

DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_mii_phy_auto negotiation started\n"));
sc = &mPhySoftc->mii_sc;
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
reg = PHY_READ (mPhySoftc, E1000_AR);
reg |= E1000_AR_10T | E1000_AR_10T_FD |
   E1000_AR_100TX | E1000_AR_100TX_FD |


   E1000_AR_PAUSE | E1000_AR_ASM_DIR;


PHY_WRITE (mPhySoftc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
} else {
PHY_WRITE (mPhySoftc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
}

if ((sc->mii_extcapabilities & (E1000_ESR_1000T_FD | E1000_ESR_1000T)) != 0) {
PHY_WRITE (mPhySoftc, E1000_1GCR, E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
}

PHY_WRITE (mPhySoftc, E1000_CR, E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);

+}



+//
+// Generic helper functions
+//



+const struct mii_phydesc *

mii_phy_match_gen (
const struct mii_attach_args    *ma,
const struct mii_phydesc        *mpd,
UINTN                           len
)

+{


for (; mpd->mpd_name != NULL;
  mpd = (const struct mii_phydesc *) ((const CHAR8 *) mpd + len)) {


if (MII_OUI (ma->mii_id1, ma->mii_id2) == mpd->mpd_oui &&
   MII_MODEL (ma->mii_id2) == mpd->mpd_model) {


 return (mpd);


}
}
return (NULL);

+}



+const struct mii_phydesc *

mii_phy_match (
const struct mii_attach_args    *ma,
const struct mii_phydesc        *mpd
)

+{


return (mii_phy_match_gen (ma, mpd, sizeof (struct mii_phydesc)));

+}



+EFI_STATUS
+mii_phy_dev_probe (

const struct mii_attach_args    *ma,
const struct mii_phydesc        *mpd
)

+{


mpd = mii_phy_match (ma, mpd);
if (mpd != NULL) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Found PHY (%a)\n", mpd->mpd_name));
return EFI_SUCCESS;
}

DEBUG ((EFI_D_NET, "Marvell Yukon: PHY not found (OUI=0x%x, MODEL=0x%x)\n", MII_OUI (ma->mii_id1, ma->mii_id2), MII_MODEL (ma->mii_id2)));
return EFI_NOT_FOUND;

+}
diff --git a/Drivers/Net/MarvellYukonDxe/e1000phyreg.h b/Drivers/Net/MarvellYukonDxe/e1000phyreg.h
new file mode 100644
index 0000000..f90ab51
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/e1000phyreg.h
@@ -0,0 +1,398 @@
+/**  <at> file
+*  Registers and Macros for Marvell 88E1000 Series PHYs. Ported from FreeBSD.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.7.2.2.2.1 2010/06/14 02:09:06 kensmith Exp $ */
+/*-


Principal Author: Parag Patel



Copyright (c) 2001



All rights reserved.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice unmodified, this list of conditions, and the following



disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.







THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND



ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE



IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE



ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE



FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL



DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS



OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)



HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT



LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY



OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF



SUCH DAMAGE.







Additonal Copyright (c) 2001 by Traakan Software under same licence.



Secondary Author: Matthew Jacob


*/


+/*-


Derived by information released by Intel under the following license:







Copyright (c) 1999 - 2001, Intel Corporation







All rights reserved.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions are met:








Redistributions of source code must retain the above copyright notice,





this list of conditions and the following disclaimer.










Redistributions in binary form must reproduce the above copyright notice,





this list of conditions and the following disclaimer in the





documentation and/or other materials provided with the distribution.










Neither the name of Intel Corporation nor the names of its contributors





may be used to endorse or promote products derived from this software





without specific prior written permission.









THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''



AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE



IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE



ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,



INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES



(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;



LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND



ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT



(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.






*/


+/*


Marvell E1000 PHY registers


*/


+#define E1000_MAX_REG_ADDRESS        0x1F



+#define E1000_CR            0x00    /* control register */
+#define E1000_CR_SPEED_SELECT_MSB   0x0040
+#define E1000_CR_COLL_TEST_ENABLE   0x0080
+#define E1000_CR_FULL_DUPLEX        0x0100
+#define E1000_CR_RESTART_AUTO_NEG   0x0200
+#define E1000_CR_ISOLATE            0x0400
+#define E1000_CR_POWER_DOWN         0x0800
+#define E1000_CR_AUTO_NEG_ENABLE    0x1000
+#define E1000_CR_SPEED_SELECT_LSB   0x2000
+#define E1000_CR_LOOPBACK           0x4000
+#define E1000_CR_RESET              0x8000



+#define E1000_CR_SPEED_1000         0x0040
+#define E1000_CR_SPEED_100          0x2000
+#define E1000_CR_SPEED_10           0x0000



+#define E1000_SR                    0x01    /* status register */
+#define E1000_SR_EXTENDED           0x0001
+#define E1000_SR_JABBER_DETECT      0x0002
+#define E1000_SR_LINK_STATUS        0x0004
+#define E1000_SR_AUTO_NEG           0x0008
+#define E1000_SR_REMOTE_FAULT       0x0010
+#define E1000_SR_AUTO_NEG_COMPLETE  0x0020
+#define E1000_SR_PREAMBLE_SUPPRESS  0x0040
+#define E1000_SR_EXTENDED_STATUS    0x0100
+#define E1000_SR_100T2              0x0200
+#define E1000_SR_100T2_FD           0x0400
+#define E1000_SR_10T                0x0800
+#define E1000_SR_10T_FD             0x1000
+#define E1000_SR_100TX              0x2000
+#define E1000_SR_100TX_FD           0x4000
+#define E1000_SR_100T4              0x8000
+#define E1000_SR_MEDIAMASK  (E1000_SR_100T4|E1000_SR_100TX_FD|E1000_SR_100TX| \

E1000_SR_10T_FD|E1000_SR_10T|E1000_SR_100T2_FD|E1000_SR_100T2)


+#define E1000_ID1            0x02    /* ID register 1 */
+#define E1000_ID2            0x03    /* ID register 2 */
+#define E1000_ID_88E1000     0x01410C50
+#define E1000_ID_88E1000S    0x01410C40
+#define E1000_ID_88E1011     0x01410C20
+#define E1000_ID_MASK        0xFFFFFFF0



+#define IDR2_OUILSB 0xfc00  /* OUI LSB */
+#define IDR2_MODEL  0x03f0  /* vendor model */
+#define IDR2_REV  0x000f    /* vendor revision */
+#define MII_OUI(id1, id2)   (((id1) << 6) | ((id2) >> 10))
+#define MII_MODEL(id2)      (((id2) & IDR2_MODEL) >> 4)
+#define MII_REV(id2)        ((id2) & IDR2_REV)




+#define E1000_AR                0x04    /* autonegotiation advertise reg */
+#define E1000_AR_SELECTOR_FIELD 0x0001
+#define E1000_AR_10T            0x0020
+#define E1000_AR_10T_FD         0x0040
+#define E1000_AR_100TX          0x0080
+#define E1000_AR_100TX_FD       0x0100
+#define E1000_AR_100T4          0x0200
+#define E1000_AR_PAUSE          0x0400
+#define E1000_AR_ASM_DIR        0x0800
+#define E1000_AR_REMOTE_FAULT   0x2000
+#define E1000_AR_NEXT_PAGE      0x8000
+#define E1000_AR_SPEED_MASK     0x01E0



+/* Autonegotiation register bits for fiber cards (Alaska Only!) */
+#define E1000_FA_1000X_FD       0x0020
+#define E1000_FA_1000X          0x0040
+#define E1000_FA_SYM_PAUSE      0x0080
+#define E1000_FA_ASYM_PAUSE     0x0100
+#define E1000_FA_FAULT1         0x1000
+#define E1000_FA_FAULT2         0x2000
+#define E1000_FA_NEXT_PAGE      0x8000



+#define E1000_LPAR                0x05    /* autoneg link partner abilities reg */
+#define E1000_LPAR_SELECTOR_FIELD 0x0001
+#define E1000_LPAR_10T            0x0020
+#define E1000_LPAR_10T_FD         0x0040
+#define E1000_LPAR_100TX          0x0080
+#define E1000_LPAR_100TX_FD       0x0100
+#define E1000_LPAR_100T4          0x0200
+#define E1000_LPAR_PAUSE          0x0400
+#define E1000_LPAR_ASM_DIR        0x0800
+#define E1000_LPAR_REMOTE_FAULT   0x2000
+#define E1000_LPAR_ACKNOWLEDGE    0x4000
+#define E1000_LPAR_NEXT_PAGE      0x8000



+/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
+#define E1000_FPAR_1000X_FD       0x0020
+#define E1000_FPAR_1000X          0x0040
+#define E1000_FPAR_SYM_PAUSE      0x0080
+#define E1000_FPAR_ASYM_PAUSE     0x0100
+#define E1000_FPAR_FAULT1         0x1000
+#define E1000_FPAR_FAULT2         0x2000
+#define E1000_FPAR_ACK            0x4000
+#define E1000_FPAR_NEXT_PAGE      0x8000



+#define E1000_ER                     0x06    /* autoneg expansion reg */
+#define E1000_ER_LP_NWAY             0x0001
+#define E1000_ER_PAGE_RXD            0x0002
+#define E1000_ER_NEXT_PAGE           0x0004
+#define E1000_ER_LP_NEXT_PAGE        0x0008
+#define E1000_ER_PAR_DETECT_FAULT    0x0100



+#define E1000_NPTX                0x07    /* autoneg next page TX */
+#define E1000_NPTX_MSG_CODE_FIELD 0x0001
+#define E1000_NPTX_TOGGLE         0x0800
+#define E1000_NPTX_ACKNOWLDGE2    0x1000
+#define E1000_NPTX_MSG_PAGE       0x2000
+#define E1000_NPTX_NEXT_PAGE      0x8000



+#define E1000_RNPR                0x08    /* autoneg link-partner (?) next page */
+#define E1000_RNPR_MSG_CODE_FIELD 0x0001
+#define E1000_RNPR_TOGGLE         0x0800
+#define E1000_RNPR_ACKNOWLDGE2    0x1000
+#define E1000_RNPR_MSG_PAGE       0x2000
+#define E1000_RNPR_ACKNOWLDGE     0x4000
+#define E1000_RNPR_NEXT_PAGE      0x8000



+#define E1000_1GCR                  0x09    /* 1000T (1G) control reg */
+#define E1000_1GCR_ASYM_PAUSE       0x0080
+#define E1000_1GCR_1000T            0x0100
+#define E1000_1GCR_1000T_FD         0x0200
+#define E1000_1GCR_REPEATER_DTE     0x0400
+#define E1000_1GCR_MS_VALUE         0x0800
+#define E1000_1GCR_MS_ENABLE        0x1000
+#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
+#define E1000_1GCR_TEST_MODE_1      0x2000
+#define E1000_1GCR_TEST_MODE_2      0x4000
+#define E1000_1GCR_TEST_MODE_3      0x6000
+#define E1000_1GCR_TEST_MODE_4      0x8000
+#define E1000_1GCR_SPEED_MASK       0x0300



+#define E1000_1GSR                  0x0A    /* 1000T (1G) status reg */
+#define E1000_1GSR_IDLE_ERROR_CNT   0x0000
+#define E1000_1GSR_ASYM_PAUSE_DIR   0x0100
+#define E1000_1GSR_LP               0x0400
+#define E1000_1GSR_LP_FD            0x0800
+#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
+#define E1000_1GSR_LOCAL_RX_STATUS  0x2000
+#define E1000_1GSR_MS_CONFIG_RES    0x4000
+#define E1000_1GSR_MS_CONFIG_FAULT  0x8000



+#define E1000_ESR                   0x0F    /* IEEE extended status reg */
+#define E1000_ESR_1000T             0x1000
+#define E1000_ESR_1000T_FD          0x2000
+#define E1000_ESR_1000X             0x4000
+#define E1000_ESR_1000X_FD          0x8000



+#define E1000_TX_POLARITY_MASK      0x0100
+#define E1000_TX_NORMAL_POLARITY    0



+#define E1000_AUTO_POLARITY_DISABLE 0x0010



+#define E1000_SCR                   0x10    /* special control register */
+#define E1000_SCR_JABBER_DISABLE    0x0001
+#define E1000_SCR_POLARITY_REVERSAL 0x0002
+#define E1000_SCR_SQE_TEST          0x0004
+#define E1000_SCR_INT_FIFO_DISABLE  0x0008
+#define E1000_SCR_CLK125_DISABLE    0x0010
+#define E1000_SCR_MDI_MANUAL_MODE   0x0000
+#define E1000_SCR_MDIX_MANUAL_MODE  0x0020
+#define E1000_SCR_AUTO_X_1000T      0x0040
+#define E1000_SCR_AUTO_X_MODE       0x0060
+#define E1000_SCR_10BT_EXT_ENABLE   0x0080
+#define E1000_SCR_MII_5BIT_ENABLE   0x0100
+#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
+#define E1000_SCR_FORCE_LINK_GOOD   0x0400
+#define E1000_SCR_ASSERT_CRS_ON_TX  0x0800
+#define E1000_SCR_RX_FIFO_DEPTH_6   0x0000
+#define E1000_SCR_RX_FIFO_DEPTH_8   0x1000
+#define E1000_SCR_RX_FIFO_DEPTH_10  0x2000
+#define E1000_SCR_RX_FIFO_DEPTH_12  0x3000
+#define E1000_SCR_TX_FIFO_DEPTH_6   0x0000
+#define E1000_SCR_TX_FIFO_DEPTH_8   0x4000
+#define E1000_SCR_TX_FIFO_DEPTH_10  0x8000
+#define E1000_SCR_TX_FIFO_DEPTH_12  0xC000



+/* 88E3016 only */
+#define    E1000_SCR_AUTO_MDIX        0x0030
+#define    E1000_SCR_SIGDET_POLARITY  0x0040
+#define    E1000_SCR_EXT_DISTANCE     0x0080
+#define    E1000_SCR_FEFI_DISABLE     0x0100
+#define    E1000_SCR_NLP_GEN_DISABLE  0x0800
+#define    E1000_SCR_LPNP             0x1000
+#define    E1000_SCR_NLP_CHK_DISABLE  0x2000
+#define    E1000_SCR_EN_DETECT        0x4000



+#define E1000_SCR_EN_DETECT_MASK      0x0300



+/* 88E1112 page 1 fiber specific control */
+#define E1000_SCR_FIB_TX_DIS          0x0008
+#define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
+#define E1000_SCR_FIB_FORCE_LINK      0x0400



+/* 88E1112 page 2 */
+#define E1000_SCR_MODE_MASK           0x0380
+#define E1000_SCR_MODE_AUTO           0x0180
+#define E1000_SCR_MODE_COPPER         0x0280
+#define E1000_SCR_MODE_1000BX         0x0380



+/* 88E1116 page 0 */
+#define    E1000_SCR_POWER_DOWN       0x0004
+/* 88E1116, 88E1149 page 2 */
+#define    E1000_SCR_RGMII_POWER_UP   0x0008



+/* 88E1116, 88E1149 page 3 */
+#define E1000_SCR_LED_STAT0_MASK      0x000F
+#define E1000_SCR_LED_STAT1_MASK      0x00F0
+#define E1000_SCR_LED_INIT_MASK       0x0F00
+#define E1000_SCR_LED_LOS_MASK        0xF000
+#define E1000_SCR_LED_STAT0(x)        ((x) & E1000_SCR_LED_STAT0_MASK)
+#define E1000_SCR_LED_STAT1(x)        ((x) & E1000_SCR_LED_STAT1_MASK)
+#define E1000_SCR_LED_INIT(x)         ((x) & E1000_SCR_LED_INIT_MASK)
+#define E1000_SCR_LED_LOS(x)          ((x) & E1000_SCR_LED_LOS_MASK)



+#define E1000_SSR                   0x11    /* special status register */
+#define E1000_SSR_JABBER            0x0001
+#define E1000_SSR_REV_POLARITY      0x0002
+#define E1000_SSR_MDIX              0x0020
+#define E1000_SSR_LINK              0x0400
+#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
+#define E1000_SSR_PAGE_RCVD         0x1000
+#define E1000_SSR_DUPLEX            0x2000
+#define E1000_SSR_SPEED             0xC000
+#define E1000_SSR_10MBS             0x0000
+#define E1000_SSR_100MBS            0x4000
+#define E1000_SSR_1000MBS           0x8000



+#define E1000_IER                   0x12    /* interrupt enable reg */
+#define E1000_IER_JABBER            0x0001
+#define E1000_IER_POLARITY_CHANGE   0x0002
+#define E1000_IER_MDIX_CHANGE       0x0040
+#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
+#define E1000_IER_FALSE_CARRIER     0x0100
+#define E1000_IER_SYMBOL_ERROR      0x0200
+#define E1000_IER_LINK_STAT_CHANGE  0x0400
+#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
+#define E1000_IER_PAGE_RECEIVED     0x1000
+#define E1000_IER_DUPLEX_CHANGED    0x2000
+#define E1000_IER_SPEED_CHANGED     0x4000
+#define E1000_IER_AUTO_NEG_ERR      0x8000



+/* 88E1116, 88E1149 page 3, LED timer control. */
+#define    E1000_PULSE_MASK       0x7000
+#define    E1000_PULSE_NO_STR     0    /* no pulse stretching */
+#define    E1000_PULSE_21MS       1    /* 21 ms to 42 ms */
+#define    E1000_PULSE_42MS       2    /* 42 ms to 84 ms */
+#define    E1000_PULSE_84MS       3    /* 84 ms to 170 ms */
+#define    E1000_PULSE_170MS      4    /* 170 ms to 340 ms */
+#define    E1000_PULSE_340MS      5    /* 340 ms to 670 ms */
+#define    E1000_PULSE_670MS      6    /* 670 ms to 1300 ms */
+#define    E1000_PULSE_1300MS     7    /* 1300 ms to 2700 ms */
+#define    E1000_PULSE_DUR(x)     ((x) &    E1000_PULSE_MASK)



+#define    E1000_BLINK_MASK       0x0700
+#define    E1000_BLINK_42MS       0    /* 42 ms */
+#define    E1000_BLINK_84MS       1    /* 84 ms */
+#define    E1000_BLINK_170MS      2    /* 170 ms */
+#define    E1000_BLINK_340MS      3    /* 340 ms */
+#define    E1000_BLINK_670MS      4    /* 670 ms */
+#define    E1000_BLINK_RATE(x)    ((x) &    E1000_BLINK_MASK)



+#define E1000_ISR                   0x13    /* interrupt status reg */
+#define E1000_ISR_JABBER            0x0001
+#define E1000_ISR_POLARITY_CHANGE   0x0002
+#define E1000_ISR_MDIX_CHANGE       0x0040
+#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
+#define E1000_ISR_FALSE_CARRIER     0x0100
+#define E1000_ISR_SYMBOL_ERROR      0x0200
+#define E1000_ISR_LINK_STAT_CHANGE  0x0400
+#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
+#define E1000_ISR_PAGE_RECEIVED     0x1000
+#define E1000_ISR_DUPLEX_CHANGED    0x2000
+#define E1000_ISR_SPEED_CHANGED     0x4000
+#define E1000_ISR_AUTO_NEG_ERR      0x8000



+#define E1000_ESCR                  0x14    /* extended special control reg */
+#define E1000_ESCR_FIBER_LOOPBACK   0x4000
+#define E1000_ESCR_DOWN_NO_IDLE     0x8000
+#define E1000_ESCR_TX_CLK_2_5       0x0060
+#define E1000_ESCR_TX_CLK_25        0x0070
+#define E1000_ESCR_TX_CLK_0         0x0000



+#define E1000_RECR                  0x15    /* RX error counter reg */



+#define E1000_EADR                  0x16    /* extended address reg */



+#define E1000_LCR                   0x18    /* LED control reg */
+#define E1000_LCR_LED_TX            0x0001
+#define E1000_LCR_LED_RX            0x0002
+#define E1000_LCR_LED_DUPLEX        0x0004
+#define E1000_LCR_LINK              0x0008
+#define E1000_LCR_BLINK_42MS        0x0000
+#define E1000_LCR_BLINK_84MS        0x0100
+#define E1000_LCR_BLINK_170MS       0x0200
+#define E1000_LCR_BLINK_340MS       0x0300
+#define E1000_LCR_BLINK_670MS       0x0400
+#define E1000_LCR_PULSE_OFF         0x0000
+#define E1000_LCR_PULSE_21_42MS     0x1000
+#define E1000_LCR_PULSE_42_84MS     0x2000
+#define E1000_LCR_PULSE_84_170MS    0x3000
+#define E1000_LCR_PULSE_170_340MS   0x4000
+#define E1000_LCR_PULSE_340_670MS   0x5000
+#define E1000_LCR_PULSE_670_13S     0x6000
+#define E1000_LCR_PULSE_13_26S      0x7000



+/* The following register is found only on the 88E1011 Alaska PHY */
+#define E1000_ESSR                  0x1B    /* Extended PHY specific sts */
+#define E1000_ESSR_FIBER_LINK       0x2000
+#define E1000_ESSR_GMII_COPPER      0x000f
+#define E1000_ESSR_GMII_FIBER       0x0007
+#define E1000_ESSR_TBI_COPPER       0x000d
+#define E1000_ESSR_TBI_FIBER        0x0005
diff --git a/Drivers/Net/MarvellYukonDxe/if_media.h b/Drivers/Net/MarvellYukonDxe/if_media.h
new file mode 100644
index 0000000..00f5f7f
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_media.h
@@ -0,0 +1,273 @@
+/**  <at> file
+*  Prototypes and definitions for BSD/OS-compatible network interface media selection.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*  $NetBSD: if_media.h,v 1.3 1997/03/26 01:19:27 thorpej Exp $  */
+/* $FreeBSD: src/sys/net/if_media.h,v 1.47.2.1.4.1 2010/06/14 02:09:06 kensmith Exp $ */



+/*-


Copyright (c) 1997



Jonathan Stone and Jason R. Thorpe.  All rights reserved.







This software is derived from information provided by Matt Thomas.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




All advertising materials mentioning features or use of this software





must display the following acknowledgement:



This product includes software developed by Jonathan Stone



and Jason R. Thorpe for the NetBSD Project.




The names of the authors may not be used to endorse or promote products





derived from this software without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR



IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES



OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.



IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,



INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,



BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;



LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED



AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,



OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY



OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF



SUCH DAMAGE.


*/


+#ifndef _NET_IF_MEDIA_H_
+#define _NET_IF_MEDIA_H_



+/*


Prototypes and definitions for BSD/OS-compatible network interface



media selection.







Where it is safe to do so, this code strays slightly from the BSD/OS



design.  Software which uses the API (device drivers, basically)



shouldn't notice any difference.







Many thanks to Matt Thomas for providing the information necessary



to implement this interface.


*/


+/*


if_media Options word:



Bits  Use








0-4  Media variant



5-7  Media type



8-15  Type specific options



16-18  Mode (for multi-mode devices)



19  RFU



20-27  Shared (global) options



28-31  Instance


*/


+/*


Ethernet


*/

+#define  IFM_ETHER          0x00000020
+#define  IFM_10_T           3   /* 10BaseT - RJ45 */
+#define  IFM_10_2           4   /* 10Base2 - Thinnet */
+#define  IFM_10_5           5   /* 10Base5 - AUI */
+#define  IFM_100_TX         6   /* 100BaseTX - RJ45 */
+#define  IFM_100_FX         7   /* 100BaseFX - Fiber */
+#define  IFM_100_T4         8   /* 100BaseT4 - 4 pair cat 3 */
+#define  IFM_100_VG         9   /* 100VG-AnyLAN */
+#define  IFM_100_T2         10  /* 100BaseT2 */
+#define  IFM_1000_SX        11  /* 1000BaseSX - multi-mode fiber */
+#define  IFM_10_STP         12  /* 10BaseT over shielded TP */
+#define  IFM_10_FL          13  /* 10BaseFL - Fiber */
+#define  IFM_1000_LX        14  /* 1000baseLX - single-mode fiber */
+#define  IFM_1000_CX        15  /* 1000baseCX - 150ohm STP */
+#define  IFM_1000_T         16  /* 1000baseT - 4 pair cat 5 */
+#define  IFM_HPNA_1         17  /* HomePNA 1.0 (1Mb/s) */
+#define  IFM_10G_LR         18  /* 10GBase-LR 1310nm Single-mode */
+#define  IFM_10G_SR         19  /* 10GBase-SR 850nm Multi-mode */
+#define  IFM_10G_CX4        20  /* 10GBase CX4 copper */
+#define IFM_2500_SX         21  /* 2500BaseSX - multi-mode fiber */
+#define IFM_10G_TWINAX      22  /* 10GBase Twinax copper */
+#define IFM_10G_TWINAX_LONG 23  /* 10GBase Twinax Long copper */
+#define IFM_10G_LRM         24  /* 10GBase-LRM 850nm Multi-mode */
+#define IFM_UNKNOWN         25  /* media types not defined yet */
+#define IFM_10G_T           26  /* 10GBase-T - RJ45 */




+/* note 31 is the max! */



+#define  IFM_ETH_MASTER  0x00000100  /* master mode (1000baseT) */



+/*


Token ring


*/

+#define  IFM_TOKEN        0x00000040
+#define  IFM_TOK_STP4     3    /* Shielded twisted pair 4m - DB9 */
+#define  IFM_TOK_STP16    4    /* Shielded twisted pair 16m - DB9 */
+#define  IFM_TOK_UTP4     5    /* Unshielded twisted pair 4m - RJ45 */
+#define  IFM_TOK_UTP16    6    /* Unshielded twisted pair 16m - RJ45 */
+#define  IFM_TOK_STP100   7    /* Shielded twisted pair 100m - DB9 */
+#define  IFM_TOK_UTP100   8    /* Unshielded twisted pair 100m - RJ45 */
+#define  IFM_TOK_ETR      0x00000200  /* Early token release */
+#define  IFM_TOK_SRCRT    0x00000400  /* Enable source routing features */
+#define  IFM_TOK_ALLR     0x00000800  /* All routes / Single route bcast */
+#define  IFM_TOK_DTR      0x00002000  /* Dedicated token ring */
+#define  IFM_TOK_CLASSIC  0x00004000  /* Classic token ring */
+#define  IFM_TOK_AUTO     0x00008000  /* Automatic Dedicate/Classic token ring */



+/*


FDDI


*/

+#define  IFM_FDDI       0x00000060
+#define  IFM_FDDI_SMF   3    /* Single-mode fiber */
+#define  IFM_FDDI_MMF   4    /* Multi-mode fiber */
+#define  IFM_FDDI_UTP   5    /* CDDI / UTP */
+#define  IFM_FDDI_DA    0x00000100  /* Dual attach / single attach */



+/*


IEEE 802.11 Wireless


*/

+#define  IFM_IEEE80211          0x00000080
+/* NB: 0,1,2 are auto, manual, none defined below */
+#define  IFM_IEEE80211_FH1      3  /* Frequency Hopping 1Mbps */
+#define  IFM_IEEE80211_FH2      4  /* Frequency Hopping 2Mbps */
+#define  IFM_IEEE80211_DS1      5  /* Direct Sequence 1Mbps */
+#define  IFM_IEEE80211_DS2      6  /* Direct Sequence 2Mbps */
+#define  IFM_IEEE80211_DS5      7  /* Direct Sequence 5.5Mbps */
+#define  IFM_IEEE80211_DS11     8  /* Direct Sequence 11Mbps */
+#define  IFM_IEEE80211_DS22     9  /* Direct Sequence 22Mbps */
+#define  IFM_IEEE80211_OFDM6    10  /* OFDM 6Mbps */
+#define  IFM_IEEE80211_OFDM9    11  /* OFDM 9Mbps */
+#define  IFM_IEEE80211_OFDM12   12  /* OFDM 12Mbps */
+#define  IFM_IEEE80211_OFDM18   13  /* OFDM 18Mbps */
+#define  IFM_IEEE80211_OFDM24   14  /* OFDM 24Mbps */
+#define  IFM_IEEE80211_OFDM36   15  /* OFDM 36Mbps */
+#define  IFM_IEEE80211_OFDM48   16  /* OFDM 48Mbps */
+#define  IFM_IEEE80211_OFDM54   17  /* OFDM 54Mbps */
+#define  IFM_IEEE80211_OFDM72   18  /* OFDM 72Mbps */
+#define  IFM_IEEE80211_DS354k   19  /* Direct Sequence 354Kbps */
+#define  IFM_IEEE80211_DS512k   20  /* Direct Sequence 512Kbps */
+#define  IFM_IEEE80211_OFDM3    21  /* OFDM 3Mbps */
+#define  IFM_IEEE80211_OFDM4    22  /* OFDM 4.5Mbps */
+#define  IFM_IEEE80211_OFDM27   23  /* OFDM 27Mbps */
+/* NB: not enough bits to express MCS fully */
+#define  IFM_IEEE80211_MCS      24  /* HT MCS rate */



+#define  IFM_IEEE80211_ADHOC    0x00000100  /* Operate in Adhoc mode */
+#define  IFM_IEEE80211_HOSTAP   0x00000200  /* Operate in Host AP mode */
+#define  IFM_IEEE80211_IBSS     0x00000400  /* Operate in IBSS mode */
+#define  IFM_IEEE80211_WDS      0x00000800  /* Operate in WDS mode */
+#define  IFM_IEEE80211_TURBO    0x00001000  /* Operate in turbo mode */
+#define  IFM_IEEE80211_MONITOR  0x00002000  /* Operate in monitor mode */
+#define  IFM_IEEE80211_MBSS     0x00004000  /* Operate in MBSS mode */



+/* operating mode for multi-mode devices */
+#define  IFM_IEEE80211_11A      0x00010000  /* 5Ghz, OFDM mode */
+#define  IFM_IEEE80211_11B      0x00020000  /* Direct Sequence mode */
+#define  IFM_IEEE80211_11G      0x00030000  /* 2Ghz, CCK mode */
+#define  IFM_IEEE80211_FH       0x00040000  /* 2Ghz, GFSK mode */
+#define  IFM_IEEE80211_11NA     0x00050000  /* 5Ghz, HT mode */
+#define  IFM_IEEE80211_11NG     0x00060000  /* 2Ghz, HT mode */



+/*


ATM


*/

+#define IFM_ATM             0x000000a0
+#define IFM_ATM_UNKNOWN     3
+#define IFM_ATM_UTP_25      4
+#define IFM_ATM_TAXI_100    5
+#define IFM_ATM_TAXI_140    6
+#define IFM_ATM_MM_155      7
+#define IFM_ATM_SM_155      8
+#define IFM_ATM_UTP_155     9
+#define IFM_ATM_MM_622      10
+#define IFM_ATM_SM_622      11
+#define  IFM_ATM_VIRTUAL    12
+#define IFM_ATM_SDH         0x00000100  /* SDH instead of SONET */
+#define IFM_ATM_NOSCRAMB    0x00000200  /* no scrambling */
+#define IFM_ATM_UNASSIGNED  0x00000400  /* unassigned cells */



+/*


CARP Common Address Redundancy Protocol


*/

+#define  IFM_CARP  0x000000c0



+/*


Shared media sub-types


*/

+#define  IFM_AUTO   0    /* Autoselect best media */
+#define  IFM_MANUAL 1    /* Jumper/dipswitch selects media */
+#define  IFM_NONE   2    /* Deselect all media */



+/*


Shared options


*/

+#define  IFM_FDX   0x00100000  /* Force full duplex */
+#define  IFM_HDX   0x00200000  /* Force half duplex */
+#define  IFM_FLAG0 0x01000000  /* Driver defined flag */
+#define  IFM_FLAG1 0x02000000  /* Driver defined flag */
+#define  IFM_FLAG2 0x04000000  /* Driver defined flag */
+#define  IFM_LOOP  0x08000000  /* Put hardware in loopback */



+/*


Masks


*/

+#define  IFM_NMASK  0x000000e0  /* Network type */
+#define  IFM_TMASK  0x0000001f  /* Media sub-type */
+#define  IFM_IMASK  0xf0000000  /* Instance */
+#define  IFM_ISHIFT 28    /* Instance shift */
+#define  IFM_OMASK  0x0000ff00  /* Type specific options */
+#define  IFM_MMASK  0x00070000  /* Mode */
+#define  IFM_MSHIFT 16    /* Mode shift */
+#define  IFM_GMASK  0x0ff00000  /* Global options */



+/*


Status bits


*/

+#define  IFM_AVALID  0x00000001  /* Active bit valid */
+#define  IFM_ACTIVE  0x00000002  /* Interface attached to working net */



+/* Mask of "status valid" bits, for ifconfig(8). */
+#define  IFM_STATUS_VALID  IFM_AVALID



+/* List of "status valid" bits, for ifconfig(8). */
+#define IFM_STATUS_VALID_LIST {            \

IFM_AVALID,              \
0                \
}


+/*


Macros to extract various bits of information from the media word.


*/

+#define  IFM_TYPE(x)         ((x) & IFM_NMASK)
+#define  IFM_SUBTYPE(x)      ((x) & IFM_TMASK)
+#define  IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK)
+#define  IFM_INST(x)         (((x) & IFM_IMASK) >> IFM_ISHIFT)
+#define  IFM_OPTIONS(x)      ((x) & (IFM_OMASK|IFM_GMASK))
+#define  IFM_MODE(x)         ((x) & IFM_MMASK)



+#define  IFM_INST_MAX  IFM_INST(IFM_IMASK)



+/*


Macro to create a media word.


*/

+#define  IFM_MAKEWORD(type, subtype, options, instance)      \

((type) | (subtype) | (options) | ((instance) << IFM_ISHIFT))

+#define  IFM_MAKEMODE(mode) \

(((mode) << IFM_MSHIFT) & IFM_MMASK)



+#endif  /* _NET_IF_MEDIA_H_ */
diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c
new file mode 100644
index 0000000..c298601
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_msk.c
@@ -0,0 +1,2982 @@
+/**  <at> file
+*  Support for PCIe Marvell Yukon gigabit ethernet adapter product family
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+/******************************************************************************






LICENSE:



Copyright (C) Marvell International Ltd. and/or its affiliates







The computer program files contained in this folder ("Files")



are provided to you under the BSD-type license terms provided



below, and any use of such Files and any derivative works



thereof created by you shall be governed by the following terms



and conditions:








Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above





copyright notice, this list of conditions and the following



disclaimer in the documentation and/or other materials provided



with the distribution.




Neither the name of Marvell nor the names of its contributors





may be used to endorse or promote products derived from this



software without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS



"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT



LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS



FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE



COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,



INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,



BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;



LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)



HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,



STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)



ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED



OF THE POSSIBILITY OF SUCH DAMAGE.



/LICENSE






*****************************************************************************/


+/*-


Copyright (c) 1997, 1998, 1999, 2000



Bill Paul <wpaul <at> ctr.columbia.edu>.  All rights reserved.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




All advertising materials mentioning features or use of this software





must display the following acknowledgement:



This product includes software developed by Bill Paul.




Neither the name of the author nor the names of any co-contributors





may be used to endorse or promote products derived from this software



without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND



ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE



IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE



ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD



BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR



CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF



SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS



INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN



CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)



ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF



THE POSSIBILITY OF SUCH DAMAGE.


*/

+/*-


Copyright (c) 2003 Nathan L. Binkert <binkertn <at> umich.edu>







Permission to use, copy, modify, and distribute this software for any



purpose with or without fee is hereby granted, provided that the above



copyright notice and this permission notice appear in all copies.







THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES



WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF



MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR



ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES



WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN



ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF



OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.


*/


+/*


Device driver for the Marvell Yukon II Ethernet controller.



Due to lack of documentation, this driver is based on the code from



sk (4) and Marvell's myk (4) driver for FreeBSD 5.x.


*/


+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/NetLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/PciIo.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Acpi.h>
+#include "miivar.h"
+#include "if_media.h"
+#include "if_mskreg.h"
+#include "if_msk.h"



+//
+// Global Variables
+//
+static EFI_PCI_IO_PROTOCOL         *mPciIo;
+static struct msk_softc            *mSoftc;



+#define MSK_CSUM_FEATURES  (CSUM_TCP | CSUM_UDP)



+/*


Devices supported by this driver.


*/

+static struct msk_product {

UINT16  msk_vendorid;
UINT16  msk_deviceid;
const CHAR8  *msk_name;

+} msk_products[] = { +{ VENDORID_SK,      DEVICEID_SK_YUKON2, +{ VENDORID_SK,      DEVICEID_SK_YUKON2_EXPR, +{ VENDORID_MARVELL, DEVICEID_MRVL_8021CU, +{ VENDORID_MARVELL, DEVICEID_MRVL_8021X, +{ VENDORID_MARVELL, DEVICEID_MRVL_8022CU, +{ VENDORID_MARVELL, DEVICEID_MRVL_8022X, +{ VENDORID_MARVELL, DEVICEID_MRVL_8061CU, +{ VENDORID_MARVELL, DEVICEID_MRVL_8061X, +{ VENDORID_MARVELL, DEVICEID_MRVL_8062CU, +{ VENDORID_MARVELL, DEVICEID_MRVL_8062X, +{ VENDORID_MARVELL, DEVICEID_MRVL_8035, +{ VENDORID_MARVELL, DEVICEID_MRVL_8036, +{ VENDORID_MARVELL, DEVICEID_MRVL_8038, +{ VENDORID_MARVELL, DEVICEID_MRVL_8039, +{ VENDORID_MARVELL, DEVICEID_MRVL_8040, +{ VENDORID_MARVELL, DEVICEID_MRVL_8040T, +{ VENDORID_MARVELL, DEVICEID_MRVL_8042, +{ VENDORID_MARVELL, DEVICEID_MRVL_8048, +{ VENDORID_MARVELL, DEVICEID_MRVL_4361, +{ VENDORID_MARVELL, DEVICEID_MRVL_4360, +{ VENDORID_MARVELL, DEVICEID_MRVL_4362, +{ VENDORID_MARVELL, DEVICEID_MRVL_4363, +{ VENDORID_MARVELL, DEVICEID_MRVL_4364, +{ VENDORID_MARVELL, DEVICEID_MRVL_4365, +{ VENDORID_MARVELL, DEVICEID_MRVL_436A, +{ VENDORID_MARVELL, DEVICEID_MRVL_436B, +{ VENDORID_MARVELL, DEVICEID_MRVL_436C, +{ VENDORID_MARVELL, DEVICEID_MRVL_4380, +{ VENDORID_MARVELL, DEVICEID_MRVL_4381, +{ VENDORID_DLINK,   DEVICEID_DLINK_DGE550SX, +{ VENDORID_DLINK,   DEVICEID_DLINK_DGE560SX, +{ VENDORID_DLINK,   DEVICEID_DLINK_DGE560T, +};

"SK-9Sxx Gigabit Ethernet" }, "SK-9Exx Gigabit Ethernet"}, "Marvell Yukon 88E8021CU Gigabit Ethernet" }, "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, "Marvell Yukon 88E8022CU Gigabit Ethernet" }, "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, "Marvell Yukon 88E8061CU Gigabit Ethernet" }, "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, "Marvell Yukon 88E8062CU Gigabit Ethernet" }, "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, "Marvell Yukon 88E8035 Fast Ethernet" }, "Marvell Yukon 88E8036 Fast Ethernet" }, "Marvell Yukon 88E8038 Fast Ethernet" }, "Marvell Yukon 88E8039 Fast Ethernet" }, "Marvell Yukon 88E8040 Fast Ethernet" }, "Marvell Yukon 88E8040T Fast Ethernet" }, "Marvell Yukon 88E8042 Fast Ethernet" }, "Marvell Yukon 88E8048 Fast Ethernet" }, "Marvell Yukon 88E8050 Gigabit Ethernet" }, "Marvell Yukon 88E8052 Gigabit Ethernet" }, "Marvell Yukon 88E8053 Gigabit Ethernet" }, "Marvell Yukon 88E8055 Gigabit Ethernet" }, "Marvell Yukon 88E8056 Gigabit Ethernet" }, "Marvell Yukon 88E8070 Gigabit Ethernet" }, "Marvell Yukon 88E8058 Gigabit Ethernet" }, "Marvell Yukon 88E8071 Gigabit Ethernet" }, "Marvell Yukon 88E8072 Gigabit Ethernet" }, "Marvell Yukon 88E8057 Gigabit Ethernet" }, "Marvell Yukon 88E8059 Gigabit Ethernet" }, "D-Link 550SX Gigabit Ethernet" }, "D-Link 560SX Gigabit Ethernet" }, "D-Link 560T Gigabit Ethernet" }



+static const CHAR8 *model_name[] = {

"Yukon XL",
"Yukon EC Ultra",
"Yukon EX",
"Yukon EC",
"Yukon FE",
"Yukon FE+",
"Yukon Supreme",
"Yukon Ultra 2",
"Yukon Unknown",
"Yukon Optima",

+};



+//
+// Forward declarations
+//
+static VOID mskc_setup_rambuffer (VOID);
+static VOID mskc_reset (VOID);



+static EFI_STATUS msk_attach (INT32);
+static VOID msk_detach (INT32);



+static VOID mskc_tick (IN EFI_EVENT, IN VOID*);
+static VOID msk_intr (VOID);
+static VOID msk_intr_phy (struct msk_if_softc *);
+static VOID msk_intr_gmac (struct msk_if_softc *);
+static __inline VOID msk_rxput (struct msk_if_softc *);
+static INTN msk_handle_events (VOID);
+static VOID msk_handle_hwerr (struct msk_if_softc *, UINT32);
+static VOID msk_intr_hwerr (VOID);
+static VOID msk_rxeof (struct msk_if_softc *, UINT32, UINT32, INTN);
+static VOID msk_txeof (struct msk_if_softc *, INTN);
+static EFI_STATUS msk_encap (struct msk_if_softc *, MSK_SYSTEM_BUF *);
+static VOID msk_start (INT32);
+static VOID msk_set_prefetch (INTN, EFI_PHYSICAL_ADDRESS, UINT32);
+static VOID msk_set_rambuffer (struct msk_if_softc *);
+static VOID msk_set_tx_stfwd (struct msk_if_softc *);
+static EFI_STATUS msk_init (struct msk_if_softc *);
+static VOID msk_stop (struct msk_if_softc *);
+static VOID msk_phy_power (struct msk_softc *, INTN);
+static EFI_STATUS msk_status_dma_alloc (VOID);
+static VOID msk_status_dma_free (VOID);
+static EFI_STATUS msk_txrx_dma_alloc (struct msk_if_softc *);
+static VOID msk_txrx_dma_free (struct msk_if_softc *);
+static EFI_STATUS msk_init_rx_ring (struct msk_if_softc *);
+static VOID msk_init_tx_ring (struct msk_if_softc *);
+static __inline VOID msk_discard_rxbuf (struct msk_if_softc *, INTN);
+static EFI_STATUS msk_newbuf (struct msk_if_softc *, INTN);



+static VOID msk_rxfilter (

struct msk_if_softc         *sc_if,
UINT32                      FilterFlags,
UINTN                       MCastFilterCnt,
EFI_MAC_ADDRESS             *MCastFilter
);

+static VOID msk_setvlan (struct msk_if_softc *);



+static VOID msk_stats_clear (struct msk_if_softc *);
+static VOID msk_stats_update (struct msk_if_softc *);



+//
+// Functions
+//



+INTN
+msk_phy_readreg (

INTN  port,
INTN  reg
)

+{

INTN  i;
INTN  val;

GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

for (i = 0; i < MSK_TIMEOUT; i++) {
MicroSecondDelay (1);
val = GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL);
if ((val & GM_SMI_CT_RD_VAL) != 0) {
 val = GMAC_READ_2 (mSoftc, port, GM_SMI_DATA);


 break;


}
}

if (i == MSK_TIMEOUT) {
DEBUG ((EFI_D_NET, "Marvell Yukon: phy failed to come ready\n"));
val = 0;
}

return (val);

+}



+INTN
+msk_phy_writereg (

INTN  port,
INTN  reg,
INTN  val
)

+{

INTN i;

GMAC_WRITE_2 (mSoftc, port, GM_SMI_DATA, val);
GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
for (i = 0; i < MSK_TIMEOUT; i++) {
MicroSecondDelay (1);
if ((GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) {
 break;


}
}
if (i == MSK_TIMEOUT) {
DEBUG ((EFI_D_NET, "Marvell Yukon: phy write timeout\n"));
}

return (0);

+}



+VOID
+msk_miibus_statchg (

INTN  port
)

+{

struct msk_if_softc   *sc_if = mSoftc->msk_if[port];
struct mii_data       *mii = &sc_if->mii_d;
UINT32                gmac;

sc_if->msk_flags &= ~MSK_FLAG_LINK;

if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE)) {

DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, phy is active\n"));
switch (IFM_SUBTYPE (mii->mii_media_active)) {
 case IFM_10_T:


 case IFM_100_TX:


   sc_if->msk_flags |= MSK_FLAG_LINK;


   break;


 case IFM_1000_T:


 case IFM_1000_SX:


 case IFM_1000_LX:


 case IFM_1000_CX:


   if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) {


     sc_if->msk_flags |= MSK_FLAG_LINK;


   }


   break;


 default:


   break;


}
}

if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
// Enable Tx FIFO Underrun
DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, link up\n"));

CSR_WRITE_1 (mSoftc, MR_ADDR (port, GMAC_IRQ_MSK), GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
//
// Because mii(4) notify msk (4) that it detected link status
// change, there is no need to enable automatic
// speed/flow-control/duplex updates.
//
gmac = GM_GPCR_AU_ALL_DIS;
switch (IFM_SUBTYPE (mii->mii_media_active)) {
 case IFM_1000_SX:


 case IFM_1000_T:


   gmac |= GM_GPCR_SPEED_1000;


   break;


 case IFM_100_TX:


   gmac |= GM_GPCR_SPEED_100;


   break;


 case IFM_10_T:


   break;


}

// Disable Rx flow control
if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG0) == 0) {
 gmac |= GM_GPCR_FC_RX_DIS;


}
// Disable Tx flow control
if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG1) == 0) {
 gmac |= GM_GPCR_FC_TX_DIS;


}
if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
 gmac |= GM_GPCR_DUP_FULL;


} else {
 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;


}
gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
GMAC_WRITE_2 (mSoftc, port, GM_GP_CTRL, gmac);
// Read again to ensure writing
GMAC_READ_2 (mSoftc, port, GM_GP_CTRL);
gmac = GMC_PAUSE_OFF;
if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
 if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG0) != 0) {


   gmac = GMC_PAUSE_ON;


 }


}
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), gmac);

// Enable PHY interrupt for FIFO underrun/overflow
msk_phy_writereg (port, PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
} else {
//
// Link state changed to down.
// Disable PHY interrupts.
//
DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, link down\n"));
msk_phy_writereg (port, PHY_MARV_INT_MASK, 0);
// Disable Rx/Tx MAC
gmac = GMAC_READ_2 (mSoftc, port, GM_GP_CTRL);
if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);


 GMAC_WRITE_2 (mSoftc, port, GM_GP_CTRL, gmac);


 // Read again to ensure writing


 GMAC_READ_2 (mSoftc, port, GM_GP_CTRL);


}
}

+}



+UINT32
+ether_crc32_be (

const UINT8   *buf,
UINTN         len
)

+{

UINTN     i;
UINT32    crc;
UINT32    carry;
INTN      bit;
UINT8     data;

crc = 0xffffffff; // initial value

for (i = 0; i < len; i++) {
for (data = *buf++, bit = 0; bit < 8; bit++, data >>= 1) {
 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);


 crc <<= 1;


 if (carry) {


   crc = (crc ^ ETHER_CRC_POLY_BE) | carry;


 }


}
}

return crc;

+}



+VOID
+mskc_rxfilter (

UINT32                      FilterFlags,
UINTN                       MCastFilterCnt,
EFI_MAC_ADDRESS             *MCastFilter
)

+{

msk_rxfilter (mSoftc->msk_if[MSK_PORT_A], FilterFlags, MCastFilterCnt, MCastFilter);

+}



+static VOID
+msk_rxfilter (

struct msk_if_softc         *sc_if,
UINT32                      FilterFlags,
UINTN                       MCastFilterCnt,
EFI_MAC_ADDRESS             *MCastFilter
)

+{

UINT32  mchash[2];
UINT32  crc;
UINT16  mode;
INTN    port = sc_if->msk_md.port;

ZeroMem (mchash, sizeof (mchash));
mode = GMAC_READ_2 (mSoftc, port, GM_RX_CTRL);
//  if ((ifp->if_flags & IFF_PROMISC) != 0)
if ((FilterFlags & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
}
//  else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
else if ((FilterFlags & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
mchash[0] = 0xffff;
mchash[1] = 0xffff;
} else {
mode |= GM_RXCR_UCF_ENA;
while (MCastFilterCnt-- > 0) {
 //      if (ifma->ifma_addr->sa_family != AF_LINK)


 //        continue;


 //      crc = ether_crc32_be (LLADDR ((struct sockaddr_dl *)


 //          ifma->ifma_addr), ETHER_ADDR_LEN);


 crc = ether_crc32_be (MCastFilter[MCastFilterCnt].Addr, NET_ETHER_ADDR_LEN);


 /* Just want the 6 least significant bits. */


 crc &= 0x3f;


 /* Set the corresponding bit in the hash table. */


 mchash[crc >> 5] |= 1 << (crc & 0x1f);


}
if (mchash[0] != 0 || mchash[1] != 0) {
 mode |= GM_RXCR_MCF_ENA;


}
}

GMAC_WRITE_2 (mSoftc, port, GM_MC_ADDR_H1,  mchash[0]        & 0xffff  );
GMAC_WRITE_2 (mSoftc, port, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff  );
GMAC_WRITE_2 (mSoftc, port, GM_MC_ADDR_H3,  mchash[1]        & 0xffff  );
GMAC_WRITE_2 (mSoftc, port, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff  );
GMAC_WRITE_2 (mSoftc, port, GM_RX_CTRL,    mode                        );

+}



+static
+VOID
+msk_setvlan (

struct msk_if_softc   *sc_if
)

+{

//
// Disable automatic VLAN tagging/stripping
//
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);

+}



+static
+EFI_STATUS
+msk_init_rx_ring (

struct msk_if_softc   *sc_if
)

+{

struct msk_ring_data  *rd;
struct msk_rxdesc     *rxd;
INTN                  i;
INTN                  prod;
EFI_STATUS            Status;

sc_if->msk_cdata.msk_rx_cons = 0;
sc_if->msk_cdata.msk_rx_prod = 0;
sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;

rd = &sc_if->msk_rdata;
ZeroMem (rd->msk_rx_ring, MSK_RX_RING_SZ);
prod = sc_if->msk_cdata.msk_rx_prod;
for (i = 0; i < MSK_RX_RING_CNT; i++) {
rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
ZeroMem (&rxd->rx_m, sizeof (MSK_DMA_BUF));
rxd->rx_le = &rd->msk_rx_ring[prod];
Status = msk_newbuf (sc_if, prod);
if (EFI_ERROR (Status)) {
 return Status;


}
MSK_INC (prod, MSK_RX_RING_CNT);
}

// Update prefetch unit.
sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
CSR_WRITE_2 (mSoftc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);

return EFI_SUCCESS;

+}



+STATIC
+VOID
+msk_init_tx_ring (

struct msk_if_softc   *sc_if
)

+{

struct msk_ring_data  *rd;
struct msk_txdesc     *txd;
INTN                  i;

sc_if->msk_cdata.msk_tx_prod = 0;
sc_if->msk_cdata.msk_tx_cons = 0;
sc_if->msk_cdata.msk_tx_cnt = 0;

rd = &sc_if->msk_rdata;
ZeroMem (rd->msk_tx_ring, sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT);
for (i = 0; i < MSK_TX_RING_CNT; i++) {
txd = &sc_if->msk_cdata.msk_txdesc[i];
ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF));
txd->tx_le = &rd->msk_tx_ring[i];
}

+}



+static
+__inline
+VOID
+msk_discard_rxbuf (

struct msk_if_softc   *sc_if,
INTN                  idx
)

+{

struct msk_rx_desc  *rx_le;
struct msk_rxdesc   *rxd;
MSK_DMA_BUF         *DmaBuffer;

DEBUG ((EFI_D_NET, "Marvell Yukon: discard rxbuf\n"));

rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
DmaBuffer = &rxd->rx_m;
rx_le = rxd->rx_le;
rx_le->msk_control = htole32 (DmaBuffer->Length | OP_PACKET | HW_OWNER);

+}



+static
+EFI_STATUS
+msk_newbuf (

IN struct msk_if_softc    *sc_if,
IN INTN                   idx
)

+{

struct msk_rx_desc    *rx_le;
struct msk_rxdesc     *rxd;
UINTN                 Length;
VOID                  *Buffer;
VOID                  *Mapping;
EFI_PHYSICAL_ADDRESS  PhysAddr;
EFI_STATUS            Status;

Length = MAX_SUPPORTED_PACKET_SIZE;

rxd = &sc_if->msk_cdata.msk_rxdesc[idx];

if ((rxd->rx_m.Buf != NULL) && (rxd->rx_m.Length >= Length)) {
return EFI_ALREADY_STARTED;
} else if (rxd->rx_m.Buf != NULL) {
mPciIo->Unmap (mPciIo, rxd->rx_m.DmaMapping);
mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf);
}

Status = mPciIo->AllocateBuffer (mPciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES (Length), &Buffer, 0);
if (EFI_ERROR (Status)) {
return Status;
}

Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterWrite, Buffer, &Length, &PhysAddr, &Mapping);
if (EFI_ERROR (Status)) {
Length = MAX_SUPPORTED_PACKET_SIZE;
mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (Length), Buffer);
return Status;
}

ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF));
rxd->rx_m.DmaMapping = Mapping;
rxd->rx_m.Buf = Buffer;
rxd->rx_m.Length = Length;
rx_le = rxd->rx_le;
rx_le->msk_addr = htole32 (MSK_ADDR_LO (PhysAddr));
rx_le->msk_control = htole32 (Length | OP_PACKET | HW_OWNER);

return EFI_SUCCESS;

+}



+EFI_STATUS
+mskc_probe (

EFI_PCI_IO_PROTOCOL *PciIo
)

+{

struct msk_product  *mp;
UINT16              vendor;
UINT16              devid;
UINT32              PciID;
INTN                i;
EFI_STATUS          Status;

Status = PciIo->Pci.Read (
   PciIo,


   EfiPciIoWidthUint32,


   PCI_VENDOR_ID_OFFSET,


   1,


   &PciID


   );


if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}

vendor = PciID & 0xFFFF;
devid = PciID >> 16;
mp = msk_products;
for (i = 0; i < sizeof (msk_products)/sizeof (msk_products[0]); i++, mp++) {
if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
 DEBUG ((EFI_D_NET, "Marvell Yukon: Probe found device %a\n", mp->msk_name));


 return EFI_SUCCESS;


}
}
return EFI_UNSUPPORTED;

+}



+static
+VOID
+mskc_setup_rambuffer (

VOID
)

+{

INTN next;
INTN i;

/* Get adapter SRAM size. */
mSoftc->msk_ramsize = CSR_READ_1 (mSoftc, B2_E_0) * 4;
DEBUG ((EFI_D_NET, "Marvell Yukon: RAM buffer size : %dKB\n", mSoftc->msk_ramsize));
if (mSoftc->msk_ramsize == 0) {
return;
}

mSoftc->msk_pflags |= MSK_FLAG_RAMBUF;
/*

Give receiver 2/3 of memory and round down to the multiple



of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple



of 1024.


*/
mSoftc->msk_rxqsize = (((mSoftc->msk_ramsize * 1024 * 2) / 3) / 1024) * 1024;
mSoftc->msk_txqsize = (mSoftc->msk_ramsize * 1024) - mSoftc->msk_rxqsize;
for (i = 0, next = 0; i < mSoftc->msk_num_port; i++) {
mSoftc->msk_rxqstart[i] = next;
mSoftc->msk_rxqend[i] = next + mSoftc->msk_rxqsize - 1;
next = mSoftc->msk_rxqend[i] + 1;
mSoftc->msk_txqstart[i] = next;
mSoftc->msk_txqend[i] = next + mSoftc->msk_txqsize - 1;
next = mSoftc->msk_txqend[i] + 1;
DEBUG ((EFI_D_NET, "Marvell Yukon: Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
       mSoftc->msk_rxqsize / 1024, mSoftc->msk_rxqstart[i], mSoftc->msk_rxqend[i]));


DEBUG ((EFI_D_NET, "Marvell Yukon: Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
       mSoftc->msk_txqsize / 1024, mSoftc->msk_txqstart[i], mSoftc->msk_txqend[i]));


}

+}



+static
+VOID
+msk_phy_power (

struct msk_softc  *sc,
INTN              mode
)

+{

UINT32  our;
UINT32  val;
INTN    i;

switch (mode) {
case MSK_PHY_POWERUP:
 // Switch power to VCC (WA for VAUX problem)


 CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);



 // Disable Core Clock Division, set Clock Select to 0


 CSR_WRITE_4 (sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);



 val = 0;


 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {


   // Enable bits are inverted


   val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |


       Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |


       Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;


 }


 //


 // Enable PCI & Core Clock, enable clock gating for both Links.


 //


 CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);



 val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);


 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);


 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {


   if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {


     // Deassert Low Power for 1st PHY


     val |= PCI_Y2_PHY1_COMA;


     if (sc->msk_num_port > 1) {


       val |= PCI_Y2_PHY2_COMA;


     }


   }


 }


 // Release PHY from PowerDown/COMA mode


 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);



 switch (sc->msk_hw_id) {


   case CHIP_ID_YUKON_EC_U:


   case CHIP_ID_YUKON_EX:


   case CHIP_ID_YUKON_FE_P:


   case CHIP_ID_YUKON_UL_2:


   case CHIP_ID_YUKON_OPT:


     CSR_WRITE_2 (sc, B0_CTST, Y2_HW_WOL_OFF);



     // Enable all clocks


     CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_3, 0);


     our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_4);


     our &= (PCI_FORCE_ASPM_REQUEST | PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | PCI_ASPM_CLKRUN_REQUEST);


     // Set all bits to 0 except bits 15..12


     CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_4, our);


     our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_5);


     our &= PCI_CTL_TIM_VMAIN_AV_MSK;


     CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_5, our);


     CSR_PCI_WRITE_4 (sc, PCI_CFG_REG_1, 0);


     //


     // Disable status race, workaround for


     // Yukon EC Ultra & Yukon EX.


     //


     val = CSR_READ_4 (sc, B2_GP_IO);


     val |= GLB_GPIO_STAT_RACE_DIS;


     CSR_WRITE_4 (sc, B2_GP_IO, val);


     CSR_READ_4 (sc, B2_GP_IO);


     break;


   default:


     break;


 }


 for (i = 0; i < sc->msk_num_port; i++) {


   CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_SET);


   CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_CLR);


 }


 break;


case MSK_PHY_POWERDOWN:
 val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);


 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;


 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {


   val &= ~PCI_Y2_PHY1_COMA;


   if (sc->msk_num_port > 1) {


     val &= ~PCI_Y2_PHY2_COMA;


   }


 }


 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);



 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |


     Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |


     Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;


 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {


   // Enable bits are inverted


   val = 0;


 }


 //


 // Disable PCI & Core Clock, disable clock gating for


 // both Links.


 //


 CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);


 CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);


 break;


default:
 break;


}

+}



+static
+VOID
+clear_pci_errors (

VOID
)

+{

EFI_STATUS  Status;
UINT16      val;

// Clear all error bits in the PCI status register.
Status = mPciIo->Pci.Read (
   mPciIo,


   EfiPciIoWidthUint16,


   PCI_PRIMARY_STATUS_OFFSET,


   1,


   &val


   );


if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Reading PCI Status failed: %r", Status));
}
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
val |= PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT;


Status = mPciIo->Pci.Write (
   mPciIo,


   EfiPciIoWidthUint16,


   PCI_PRIMARY_STATUS_OFFSET,


   1,


   &val


   );


if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Writing PCI Status failed: %r", Status));
}
CSR_WRITE_2 (mSoftc, B0_CTST, CS_MRST_CLR);

+}



+static
+VOID
+mskc_reset (

VOID
)

+{

EFI_STATUS            Status;
EFI_PHYSICAL_ADDRESS  PhysAddr;
UINT16                status;
UINT32                val;
INTN                  i;

CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_CLR);

// Disable ASF
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_EX) {
status = CSR_READ_2 (mSoftc, B28_Y2_ASF_HCU_CCSR);
// Clear AHB bridge & microcontroller reset
status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | Y2_ASF_HCU_CCSR_CPU_RST_MODE);
// Clear ASF microcontroller state
status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
CSR_WRITE_2 (mSoftc, B28_Y2_ASF_HCU_CCSR, status);
} else {
CSR_WRITE_1 (mSoftc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
}
CSR_WRITE_2 (mSoftc, B0_CTST, Y2_ASF_DISABLE);

//
// Since we disabled ASF, S/W reset is required for Power Management.
//
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_SET);
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_CLR);

clear_pci_errors ();
switch (mSoftc->msk_bustype) {
case MSK_PEX_BUS:
 // Clear all PEX errors


 CSR_PCI_WRITE_4 (mSoftc, PEX_UNC_ERR_STAT, 0xffffffff);


 val = CSR_PCI_READ_4 (mSoftc, PEX_UNC_ERR_STAT);


 if ((val & PEX_RX_OV) != 0) {


   mSoftc->msk_intrmask &= ~Y2_IS_HW_ERR;


   mSoftc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;


 }


 break;


case MSK_PCI_BUS:
case MSK_PCIX_BUS:
 // Set Cache Line Size to 2 (8bytes) if configured to 0


 Status = mPciIo->Pci.Read (


       mPciIo,


       EfiPciIoWidthUint8,


       PCI_CACHELINE_SIZE_OFFSET,


       1,


       &val


       );


 if (EFI_ERROR (Status)) {


   DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Reading PCI cache line size failed: %r", Status));


 }


 if (val == 0) {


   val = 2;


   Status = mPciIo->Pci.Write (


         mPciIo,


         EfiPciIoWidthUint8,


         PCI_CACHELINE_SIZE_OFFSET,


         1,


         &val


         );


   if (EFI_ERROR (Status)) {


     DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Writing PCI cache line size failed: %r", Status));


   }


 }


 if (mSoftc->msk_bustype == MSK_PCIX_BUS) {


   Status = mPciIo->Pci.Read (


         mPciIo,


         EfiPciIoWidthUint32,


         PCI_OUR_REG_1,


         1,


         &val


         );


   if (EFI_ERROR (Status)) {


     DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Reading Our Reg 1 failed: %r", Status));


   }


   val |= PCI_CLS_OPT;


   Status = mPciIo->Pci.Write (


         mPciIo,


         EfiPciIoWidthUint32,


         PCI_OUR_REG_1,


         1,


         &val


         );


   if (EFI_ERROR (Status)) {


     DEBUG ((EFI_D_NET, "Marvell Yukon: Warning - Writing Our Reg 1 failed: %r", Status));


   }


 }


 break;


}

// Set PHY power state
msk_phy_power (mSoftc, MSK_PHY_POWERUP);

// Reset GPHY/GMAC Control
for (i = 0; i < mSoftc->msk_num_port; i++) {
// GPHY Control reset
CSR_WRITE_4 (mSoftc, MR_ADDR (i, GPHY_CTRL), GPC_RST_SET);
CSR_WRITE_4 (mSoftc, MR_ADDR (i, GPHY_CTRL), GPC_RST_CLR);
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_UL_2) {
 // Magic value observed under Linux.


 CSR_WRITE_4 (mSoftc, MR_ADDR (i, GPHY_CTRL), 0x00105226);


}
// GMAC Control reset
CSR_WRITE_4 (mSoftc, MR_ADDR (i, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4 (mSoftc, MR_ADDR (i, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4 (mSoftc, MR_ADDR (i, GMAC_CTRL), GMC_F_LOOPB_OFF);
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_EX) {
 CSR_WRITE_4 (mSoftc, MR_ADDR (i, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);


}
}
if ((mSoftc->msk_hw_id == CHIP_ID_YUKON_OPT) && (mSoftc->msk_hw_rev == 0)) {
// Disable PCIe PHY powerdown (reg 0x80, bit7)
CSR_WRITE_4 (mSoftc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
}
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

// LED On
CSR_WRITE_2 (mSoftc, B0_CTST, Y2_LED_STAT_ON);

// Enable plug in go
CSR_WRITE_2 (mSoftc, B0_CTST, Y_ULTRA_2_PLUG_IN_GO_EN);

// Clear TWSI IRQ
CSR_WRITE_4 (mSoftc, B2_I2C_IRQ, I2C_CLR_IRQ);

// Turn off hardware timer
CSR_WRITE_1 (mSoftc, B2_TI_CTRL, TIM_STOP);
CSR_WRITE_1 (mSoftc, B2_TI_CTRL, TIM_CLR_IRQ);

// Turn off descriptor polling
CSR_WRITE_1 (mSoftc, B28_DPT_CTRL, DPT_STOP);

// Turn off time stamps
CSR_WRITE_1 (mSoftc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
CSR_WRITE_1 (mSoftc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

// Configure timeout values
for (i = 0; i < mSoftc->msk_num_port; i++) {
CSR_WRITE_2 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_CTRL),    RI_RST_SET);
CSR_WRITE_2 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_CTRL),    RI_RST_CLR);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R1),  MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA1), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS1), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R1),  MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA1), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS1), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R2),  MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA2), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS2), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R2),  MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA2), MSK_RI_TO_53);
CSR_WRITE_1 (mSoftc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS2), MSK_RI_TO_53);
}

// Disable all interrupts
CSR_WRITE_4 (mSoftc, B0_HWE_IMSK, 0);
CSR_READ_4 (mSoftc, B0_HWE_IMSK);
CSR_WRITE_4 (mSoftc, B0_IMSK, 0);
CSR_READ_4 (mSoftc, B0_IMSK);

/*

On dual port PCI-X card, there is an problem where status



can be received out of order due to split transactions.


*/
/*  if (mSoftc->msk_pcixcap != 0 && mSoftc->msk_num_port > 1) {

+//    uint16_t pcix_cmd;

UINT16 pcix_cmd;

pcix_cmd = pci_read_config (mSoftc->msk_dev,
   mSoftc->msk_pcixcap + PCIXR_COMMAND, 2);*/


/* Clear Max Outstanding Split Transactions. */
/*    pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
pci_write_config (mSoftc->msk_dev,
   mSoftc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);


CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
   }*/


/*  if (mSoftc->msk_expcap != 0) {*/
/* Change Max. Read Request Size to 2048 bytes. */
/*    if (pci_get_max_read_req(mSoftc->msk_dev) == 512)
 pci_set_max_read_req(mSoftc->msk_dev, 2048);


}

+*/

// Clear status list
ZeroMem (mSoftc->msk_stat_ring, sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT);
mSoftc->msk_stat_cons = 0;
CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_RST_SET);
CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_RST_CLR);

// Set the status list base address
PhysAddr = mSoftc->msk_stat_ring_paddr;
CSR_WRITE_4 (mSoftc, STAT_LIST_ADDR_LO, MSK_ADDR_LO (PhysAddr));
CSR_WRITE_4 (mSoftc, STAT_LIST_ADDR_HI, MSK_ADDR_HI (PhysAddr));

// Set the status list last index
CSR_WRITE_2 (mSoftc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
if ((mSoftc->msk_hw_id == CHIP_ID_YUKON_EC) && (mSoftc->msk_hw_rev == CHIP_REV_YU_EC_A1)) {
// WA for dev. #4.3
CSR_WRITE_2 (mSoftc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
// WA for dev. #4.18
CSR_WRITE_1 (mSoftc, STAT_FIFO_WM, 0x21);
CSR_WRITE_1 (mSoftc, STAT_FIFO_ISR_WM, 0x07);
} else {
CSR_WRITE_2 (mSoftc, STAT_TX_IDX_TH, 0x0a);
CSR_WRITE_1 (mSoftc, STAT_FIFO_WM, 0x10);
if ((mSoftc->msk_hw_id == CHIP_ID_YUKON_XL) && (mSoftc->msk_hw_rev == CHIP_REV_YU_XL_A0)) {
 CSR_WRITE_1 (mSoftc, STAT_FIFO_ISR_WM, 0x04);


} else {
 CSR_WRITE_1 (mSoftc, STAT_FIFO_ISR_WM, 0x10);


}
CSR_WRITE_4 (mSoftc, STAT_ISR_TIMER_INI, 0x0190);
}
//
// Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
//
CSR_WRITE_4 (mSoftc, STAT_TX_TIMER_INI, MSK_USECS (mSoftc, 1000));

// Enable status unit
CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_OP_ON);

CSR_WRITE_1 (mSoftc, STAT_TX_TIMER_CTRL, TIM_START);
CSR_WRITE_1 (mSoftc, STAT_LEV_TIMER_CTRL, TIM_START);
CSR_WRITE_1 (mSoftc, STAT_ISR_TIMER_CTRL, TIM_START);

+}



+static
+EFI_STATUS
+msk_attach (

INT32 Port
)

+{

struct msk_if_softc   *sc_if;
INTN                  i;
EFI_STATUS            Status;

sc_if = mSoftc->msk_if[Port];
sc_if->msk_md.port = Port;
sc_if->msk_flags = mSoftc->msk_pflags;

// Setup Tx/Rx queue register offsets
if (Port == MSK_PORT_A) {
sc_if->msk_txq = Q_XA1;
sc_if->msk_txsq = Q_XS1;
sc_if->msk_rxq = Q_R1;
} else {
sc_if->msk_txq = Q_XA2;
sc_if->msk_txsq = Q_XS2;
sc_if->msk_rxq = Q_R2;
}

Status = msk_txrx_dma_alloc (sc_if);
if (EFI_ERROR (Status)) {
return Status;
}

/*

Get station address for this interface. Note that



dual port cards actually come with three station



addresses: one for each port, plus an extra. The



extra one is used by the SysKonnect driver software



as a 'virtual' station address for when both ports



are operating in failover mode. Currently we don't



use this extra address.


*/
for (i = 0; i < NET_ETHER_ADDR_LEN; i++) {
sc_if->MacAddress.Addr[i] = CSR_READ_1 (mSoftc, B2_MAC_1 + (Port * 8) + i);
}

DEBUG ((EFI_D_NET,"Mac Address: %x.%x.%x.%x.%x.%x\n",
     sc_if->MacAddress.Addr[0], sc_if->MacAddress.Addr[1], sc_if->MacAddress.Addr[2],


 sc_if->MacAddress.Addr[3], sc_if->MacAddress.Addr[4], sc_if->MacAddress.Addr[5]));



Status = e1000_probe_and_attach (&sc_if->mii_d, &sc_if->msk_md);
if (EFI_ERROR (Status)) {
mSoftc->msk_if[Port] = NULL;
msk_detach (Port);
}

return (Status);

+}



+/*


Attach the interface. Allocate softc structures, do ifmedia



setup and ethernet/BPF attach.


*/

+EFI_STATUS
+mskc_attach (

IN  EFI_PCI_IO_PROTOCOL   *PciIo,
OUT EFI_MAC_ADDRESS       *Mac
)

+{

struct msk_mii_data   *mmd;
UINT64                Supports;
UINT8                 *PciBarResources;
UINT32                MacAddrL;
UINT32                MacAddrH;
EFI_STATUS            Status;
struct msk_if_softc   *ScIf;

mPciIo = PciIo;
mSoftc = AllocateZeroPool (sizeof (struct msk_softc));
if (mSoftc == NULL) {
return EFI_OUT_OF_RESOURCES;
}

//
// Save original PCI attributes
//
Status = mPciIo->Attributes (
   mPciIo,


   EfiPciIoAttributeOperationGet,


   0,


   &mSoftc->OriginalPciAttributes


   );


if (EFI_ERROR (Status)) {
FreePool (mSoftc);
return Status;
}

Status = mPciIo->Attributes (
   mPciIo,


   EfiPciIoAttributeOperationSupported,


   0,


   &Supports


   );


if (!EFI_ERROR (Status)) {
Supports &= EFI_PCI_DEVICE_ENABLE;
Status = mPciIo->Attributes (
     mPciIo,


     EfiPciIoAttributeOperationEnable,


     Supports,


     NULL


     );


}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Marvell Yukon: Failed to enable NIC controller\n"));
goto RESTORE_PCI_ATTRIBS;
}

Status = mPciIo->GetBarAttributes (mPciIo, 0, &Supports, (VOID**)&PciBarResources);
if (!EFI_ERROR (Status) && (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR)) {
if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
 if (!(((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) {


   mSoftc->RegBase = ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->AddrRangeMin;


   // Should assert that Bar is 32 bits wide


   DEBUG ((EFI_D_NET, "Marvell Yukon: GlobalRegistersBase = 0x%x\n", mSoftc->RegBase));


 } else {


   Status = EFI_NOT_FOUND;


 }


} else {
 Status = EFI_NOT_FOUND;


}
}
if (EFI_ERROR (Status)) {
goto RESTORE_PCI_ATTRIBS;
}

// Clear Software Reset
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_CLR);

// Get Hardware ID & Revision
mSoftc->msk_hw_id = CSR_READ_1 (mSoftc, B2_CHIP_ID);
mSoftc->msk_hw_rev = (CSR_READ_1 (mSoftc, B2_MAC_CFG) >> 4) & 0x0f;

// Bail out if chip is not recognized
if (mSoftc->msk_hw_id < CHIP_ID_YUKON_XL ||
 mSoftc->msk_hw_id > CHIP_ID_YUKON_OPT ||


 mSoftc->msk_hw_id == CHIP_ID_YUKON_SUPR ||


 mSoftc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {


DEBUG ((EFI_D_NET, "Marvell Yukon: unknown device: id=0x%02x, rev=0x%02x\n", mSoftc->msk_hw_id, mSoftc->msk_hw_rev));
Status = EFI_DEVICE_ERROR;
goto RESTORE_PCI_ATTRIBS;
}
DEBUG ((EFI_D_NET, "Marvell Yukon: Marvell Technology Group Ltd. %a Id:0x%02x Rev:0x%02x\n",
     model_name[mSoftc->msk_hw_id - CHIP_ID_YUKON_XL], mSoftc->msk_hw_id, mSoftc->msk_hw_rev));



mSoftc->msk_process_limit = MSK_PROC_DEFAULT;
mSoftc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;

// Set the MAC Address if needed
if (PcdGet64 (PcdYukonMacAddress) != 0)
{
MacAddrH = (UINT32) (((UINT64) PcdGet64 (PcdYukonMacAddress)));
MacAddrL = (UINT32) (((UINT64) PcdGet64 (PcdYukonMacAddress) >> 32) & 0xFFFF);

CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_4 (mSoftc, B2_MAC_1, MacAddrH);
CSR_WRITE_4 (mSoftc, B2_MAC_1+4, MacAddrL);
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
} else {
DEBUG ((EFI_D_NET, "Marvell Yukon: MAC address is invalid (0.0.0.0.0.0)\n"));
}

// Soft reset
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_SET);
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_CLR);
mSoftc->msk_pmd = CSR_READ_1 (mSoftc, B2_PMD_TYP);

// Check number of MACs
mSoftc->msk_num_port = 1;
if ((CSR_READ_1 (mSoftc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
if (!(CSR_READ_1 (mSoftc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) {
 mSoftc->msk_num_port++;


}
}

/* Check bus type. */
/*  if (pci_find_extcap (sc->msk_dev, PCIY_EXPRESS, &reg) == 0) {
sc->msk_bustype = MSK_PEX_BUS;
sc->msk_expcap = reg;
} else if (pci_find_extcap (sc->msk_dev, PCIY_PCIX, &reg) == 0) {
sc->msk_bustype = MSK_PCIX_BUS;
sc->msk_pcixcap = reg;
} else
sc->msk_bustype = MSK_PCI_BUS;

+*/

mSoftc->msk_bustype = MSK_PEX_BUS; /* Only support PCI Express */
mSoftc->msk_expcap = 1;

switch (mSoftc->msk_hw_id) {
case CHIP_ID_YUKON_EC:
 mSoftc->msk_clock = 125;  /* 125 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO;


 break;


case CHIP_ID_YUKON_EC_U:
 mSoftc->msk_clock = 125;  /* 125 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;


 break;


case CHIP_ID_YUKON_EX:
 mSoftc->msk_clock = 125;  /* 125 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;


 /*


* Yukon Extreme seems to have silicon bug for


* automatic Tx checksum calculation capability.


*/


 if (mSoftc->msk_hw_rev == CHIP_REV_YU_EX_B0) {


   mSoftc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;


 }


 /*


* Yukon Extreme A0 could not use store-and-forward


* for jumbo frames, so disable Tx checksum


* offloading for jumbo frames.


*/


 if (mSoftc->msk_hw_rev == CHIP_REV_YU_EX_A0) {


   mSoftc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;


 }


 break;


case CHIP_ID_YUKON_FE:
 mSoftc->msk_clock = 100;  /* 100 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_FASTETHER;


 break;


case CHIP_ID_YUKON_FE_P:
 mSoftc->msk_clock = 50;  /* 50 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;


 if (mSoftc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {


   /*


  * XXX


  * FE+ A0 has status LE writeback bug so msk (4)


  * does not rely on status word of received frame


  * in msk_rxeof () which in turn disables all


  * hardware assistance bits reported by the status


  * word as well as validity of the recevied frame.


  * Just pass received frames to upper stack with


  * minimal test and let upper stack handle them.


  */


   mSoftc->msk_pflags |= MSK_FLAG_NOHWVLAN | MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;


 }


 break;


case CHIP_ID_YUKON_XL:
 mSoftc->msk_clock = 156;  /* 156 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO;


 break;


case CHIP_ID_YUKON_UL_2:
 mSoftc->msk_clock = 125;  /* 125 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO;


 break;


case CHIP_ID_YUKON_OPT:
 mSoftc->msk_clock = 125;  /* 125 MHz */


 mSoftc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;


 break;


default:
 mSoftc->msk_clock = 156;  /* 156 MHz */


 break;


}

Status = msk_status_dma_alloc ();
if (EFI_ERROR (Status)) {
goto fail;
}

// Set base interrupt mask
mSoftc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
mSoftc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;

// Reset the adapter
mskc_reset ();

mskc_setup_rambuffer ();

ScIf = AllocateZeroPool (sizeof (struct msk_if_softc));
if (ScIf == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto fail;
}
mSoftc->msk_if[MSK_PORT_A] = ScIf;
Status = msk_attach (MSK_PORT_A);
if (EFI_ERROR (Status)) {
goto fail;
}

if (Mac != NULL) {
CopyMem (Mac, &ScIf->MacAddress, sizeof (EFI_MAC_ADDRESS));
}

mmd = &ScIf->msk_md;
mmd->port = MSK_PORT_A;
mmd->pmd = mSoftc->msk_pmd;
if (mSoftc->msk_pmd == 'L' || mSoftc->msk_pmd == 'S' || mSoftc->msk_pmd == 'P') {
mmd->mii_flags |= MIIF_HAVEFIBER;
}

if (mSoftc->msk_num_port > 1) {
ScIf = AllocateZeroPool (sizeof (struct msk_if_softc));
if (ScIf == NULL) {
 Status = EFI_OUT_OF_RESOURCES;


 goto fail;


}
mSoftc->msk_if[MSK_PORT_B] = ScIf;
Status = msk_attach (MSK_PORT_B);
if (EFI_ERROR (Status)) {
 goto fail;


}

mmd = &ScIf->msk_md;
mmd->port = MSK_PORT_B;
mmd->pmd = mSoftc->msk_pmd;
if (mSoftc->msk_pmd == 'L' || mSoftc->msk_pmd == 'S' || mSoftc->msk_pmd == 'P') {
 mmd->mii_flags |= MIIF_HAVEFIBER;


}
}

// Create timer for tick
Status = gBS->CreateEvent (
   EVT_NOTIFY_SIGNAL | EVT_TIMER,


   TPL_CALLBACK,


   mskc_tick,


   mSoftc,


   &mSoftc->Timer


   );


if (EFI_ERROR (Status)) {
goto fail;
}

InitializeListHead (&mSoftc->TransmitQueueHead);
InitializeListHead (&mSoftc->TransmitFreeQueueHead);
InitializeListHead (&mSoftc->ReceiveQueueHead);


+fail:

if (EFI_ERROR (Status)) {
mskc_detach ();
}

return (Status);


+RESTORE_PCI_ATTRIBS:

//
// Restore original PCI attributes
//
mPciIo->Attributes (
   mPciIo,


   EfiPciIoAttributeOperationSet,


   mSoftc->OriginalPciAttributes,


   NULL


   );


FreePool (mSoftc);
return Status;

+}



+/*


Shutdown hardware and free up resources. This can be called any



time after the mutex has been initialized. It is called in both



the error case in attach and the normal detach case so it needs



to be careful about only freeing resources that have actually been



allocated.


*/

+static
+VOID
+msk_detach (

INT32   Port
)

+{

struct msk_if_softc   *sc_if;

sc_if = mSoftc->msk_if[Port];

msk_stop (sc_if);

msk_txrx_dma_free (sc_if);

+}



+VOID
+mskc_detach (

VOID
)

+{

if (mSoftc->msk_if[MSK_PORT_A] != NULL) {
msk_detach (MSK_PORT_A);
FreePool (mSoftc->msk_if[MSK_PORT_A]);
mSoftc->msk_if[MSK_PORT_A] = NULL;
}
if (mSoftc->msk_if[MSK_PORT_B] != NULL) {
msk_detach (MSK_PORT_B);
FreePool (mSoftc->msk_if[MSK_PORT_B]);
mSoftc->msk_if[MSK_PORT_B] = NULL;
}

/* Disable all interrupts. */
CSR_WRITE_4 (mSoftc, B0_IMSK, 0);
CSR_READ_4 (mSoftc, B0_IMSK);
CSR_WRITE_4 (mSoftc, B0_HWE_IMSK, 0);
CSR_READ_4 (mSoftc, B0_HWE_IMSK);

// LED Off.
CSR_WRITE_2 (mSoftc, B0_CTST, Y2_LED_STAT_OFF);

// Put hardware reset.
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_SET);

msk_status_dma_free ();

if (mSoftc->Timer != NULL) {
gBS->SetTimer (mSoftc->Timer, TimerCancel, 0);
gBS->CloseEvent (mSoftc->Timer);

mSoftc->Timer = NULL;
}
//
// Restore original PCI attributes
//
mPciIo->Attributes (
   mPciIo,


   EfiPciIoAttributeOperationSet,


   mSoftc->OriginalPciAttributes,


   NULL


   );


FreePool (mSoftc);
mSoftc = NULL;
mPciIo = NULL;

+}



+/* Create status DMA region. */
+static
+EFI_STATUS
+msk_status_dma_alloc (

VOID
)

+{

EFI_STATUS  Status;
UINTN       Length;

Status = mPciIo->AllocateBuffer (mPciIo, AllocateAnyPages, EfiBootServicesData,
                              BYTES_TO_PAGES (MSK_STAT_RING_SZ), (VOID**)&mSoftc->msk_stat_ring, 0);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate DMA'able memory for status ring\n"));
return Status;
}
ASSERT (mSoftc->msk_stat_ring != NULL);

Length = MSK_STAT_RING_SZ;
Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterCommonBuffer, mSoftc->msk_stat_ring,
                   &Length, &mSoftc->msk_stat_ring_paddr, &mSoftc->msk_stat_map);


ASSERT (Length == MSK_STAT_RING_SZ);

if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to map DMA'able memory for status ring\n"));
}

return Status;

+}



+static
+VOID
+msk_status_dma_free (

VOID
)

+{

if (mSoftc->msk_stat_map) {
mPciIo->Unmap (mPciIo, mSoftc->msk_stat_map);
if (mSoftc->msk_stat_ring) {
 mPciIo->FreeBuffer (mPciIo, BYTES_TO_PAGES (MSK_STAT_RING_SZ), mSoftc->msk_stat_ring);


 mSoftc->msk_stat_ring = NULL;


}
mSoftc->msk_stat_map = NULL;
}

+}



+static
+EFI_STATUS
+msk_txrx_dma_alloc (

struct msk_if_softc   *sc_if
)

+{

struct msk_txdesc   *txd;
struct msk_rxdesc   *rxd;
INTN                i;
UINTN               Length;
EFI_STATUS          Status;

Status = mPciIo->AllocateBuffer (mPciIo, AllocateAnyPages, EfiBootServicesData,
                              BYTES_TO_PAGES (MSK_TX_RING_SZ), (VOID**)&sc_if->msk_rdata.msk_tx_ring, 0);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate DMA'able memory for Tx ring\n"));
goto fail;
}
ASSERT (sc_if->msk_rdata.msk_tx_ring != NULL);

Length = MSK_TX_RING_SZ;
Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterCommonBuffer, sc_if->msk_rdata.msk_tx_ring,
                   &Length, &sc_if->msk_rdata.msk_tx_ring_paddr, &sc_if->msk_cdata.msk_tx_ring_map);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to map DMA'able memory for Tx ring\n"));
goto fail;
}
ASSERT (Length == MSK_TX_RING_SZ);

Status = mPciIo->AllocateBuffer (mPciIo, AllocateAnyPages, EfiBootServicesData,
                              BYTES_TO_PAGES (MSK_RX_RING_SZ), (VOID**)&sc_if->msk_rdata.msk_rx_ring, 0);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate DMA'able memory for Rx ring\n"));
goto fail;
}
ASSERT (sc_if->msk_rdata.msk_rx_ring != NULL);

Length = MSK_RX_RING_SZ;
Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterCommonBuffer, sc_if->msk_rdata.msk_rx_ring,
                   &Length, &sc_if->msk_rdata.msk_rx_ring_paddr, &sc_if->msk_cdata.msk_rx_ring_map);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to map DMA'able memory for Rx ring\n"));
goto fail;
}
ASSERT (Length == MSK_RX_RING_SZ);

// Create DMA maps for Tx buffers.
for (i = 0; i < MSK_TX_RING_CNT; i++) {
txd = &sc_if->msk_cdata.msk_txdesc[i];
ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF));
}
// Create DMA maps for Rx buffers.
for (i = 0; i < MSK_RX_RING_CNT; i++) {
rxd = &sc_if->msk_cdata.msk_rxdesc[i];
ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF));
}


+fail:

return (Status);

+}



+static
+VOID
+msk_txrx_dma_free (

struct msk_if_softc *sc_if
)

+{

struct msk_txdesc   *txd;
struct msk_rxdesc   *rxd;
INTN                i;

// Tx ring
if (sc_if->msk_cdata.msk_tx_ring_map) {
mPciIo->Unmap (mPciIo, sc_if->msk_cdata.msk_tx_ring_map);
if (sc_if->msk_rdata.msk_tx_ring) {
 mPciIo->FreeBuffer (mPciIo, BYTES_TO_PAGES (MSK_TX_RING_SZ), sc_if->msk_rdata.msk_tx_ring);


 sc_if->msk_rdata.msk_tx_ring = NULL;


}
sc_if->msk_cdata.msk_tx_ring_map = NULL;
}

// Rx ring
if (sc_if->msk_cdata.msk_rx_ring_map) {
mPciIo->Unmap (mPciIo, sc_if->msk_cdata.msk_rx_ring_map);
if (sc_if->msk_rdata.msk_rx_ring) {
 mPciIo->FreeBuffer (mPciIo, BYTES_TO_PAGES (MSK_RX_RING_SZ), sc_if->msk_rdata.msk_rx_ring);


 sc_if->msk_rdata.msk_rx_ring = NULL;


}
sc_if->msk_cdata.msk_rx_ring_map = NULL;
}

// Tx buffers
for (i = 0; i < MSK_TX_RING_CNT; i++) {
txd = &sc_if->msk_cdata.msk_txdesc[i];
if (txd->tx_m.DmaMapping) {
 mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping);


 ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF));


 // We don't own the transmit buffers so don't free them


}
}
// Rx buffers
for (i = 0; i < MSK_RX_RING_CNT; i++) {
rxd = &sc_if->msk_cdata.msk_rxdesc[i];
if (rxd->rx_m.DmaMapping) {
 mPciIo->Unmap (mPciIo, rxd->rx_m.DmaMapping);


 // Free Rx buffers as we own these


 if(rxd->rx_m.Buf != NULL) {


   mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf);


   rxd->rx_m.Buf = NULL;


 }


 ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF));


}
}

+}



+static
+EFI_STATUS
+msk_encap (

struct msk_if_softc   *sc_if,
MSK_SYSTEM_BUF        *m_head
)

+{

struct msk_txdesc     *txd;
struct msk_txdesc     *txd_last;
struct msk_tx_desc    *tx_le;
VOID                  *Mapping;
EFI_PHYSICAL_ADDRESS  BusPhysAddr;
UINTN                 BusLength;
UINT32                control;
UINT32                prod;
UINT32                si;
EFI_STATUS            Status;

prod = sc_if->msk_cdata.msk_tx_prod;
txd = &sc_if->msk_cdata.msk_txdesc[prod];
txd_last = txd;
BusLength = m_head->Length;
Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterRead, m_head->Buf,
                   &BusLength, &BusPhysAddr, &txd->tx_m.DmaMapping);



if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: failed to map DMA'able memory for Tx buffer\n"));
return Status;
}
ASSERT (BusLength == m_head->Length);

control = 0;

si = prod;
tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
tx_le->msk_addr = htole32 (MSK_ADDR_LO (BusPhysAddr));
tx_le->msk_control = htole32 (BusLength | control | OP_PACKET);
sc_if->msk_cdata.msk_tx_cnt++;
MSK_INC (prod, MSK_TX_RING_CNT);

// Update producer index
sc_if->msk_cdata.msk_tx_prod = prod;

// Set EOP on the last descriptor
prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
tx_le->msk_control |= htole32 (EOP);

// Turn the first descriptor ownership to hardware
tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
tx_le->msk_control |= htole32 (HW_OWNER);

txd = &sc_if->msk_cdata.msk_txdesc[prod];
Mapping = txd_last->tx_m.DmaMapping;
txd_last->tx_m.DmaMapping = txd->tx_m.DmaMapping;
txd->tx_m.DmaMapping = Mapping;
txd->tx_m.Buf = m_head->Buf;
txd->tx_m.Length = m_head->Length;

return EFI_SUCCESS;

+}



+EFI_STATUS
+mskc_transmit (

UINTN   BufferSize,
VOID    *Buffer
)

+{

MSK_LINKED_SYSTEM_BUF   *LinkedSystemBuf;

LinkedSystemBuf = AllocateZeroPool (sizeof (MSK_LINKED_SYSTEM_BUF));
if (LinkedSystemBuf == NULL) {
return EFI_OUT_OF_RESOURCES;
}
LinkedSystemBuf->Signature = TX_MBUF_SIGNATURE;
//
// Add the passed Buffer to the transmit queue. Don't copy.
//
LinkedSystemBuf->SystemBuf.Buf = Buffer;
LinkedSystemBuf->SystemBuf.Length = BufferSize;
InsertTailList (&mSoftc->TransmitQueueHead, &LinkedSystemBuf->Link);
msk_start (MSK_PORT_A);
return EFI_SUCCESS;

+}



+void
+mskc_getstatus (

OUT UINT32                     *InterruptStatus, OPTIONAL
OUT VOID                       **TxBuf           OPTIONAL
)

+{

//struct msk_chain_data* cdata;
MSK_LINKED_SYSTEM_BUF *m_head;

// Interrupt status is not read from the device when InterruptStatus is NULL
if (InterruptStatus != NULL) {
// Check the interrupt lines
msk_intr ();
}

// The transmit buffer status is not read when TxBuf is NULL
if (TxBuf != NULL) {
*((UINT8 **) TxBuf) = (UINT8 *) 0;
if( !IsListEmpty (&mSoftc->TransmitFreeQueueHead))
{
 m_head = CR (GetFirstNode (&mSoftc->TransmitFreeQueueHead), MSK_LINKED_SYSTEM_BUF, Link, TX_MBUF_SIGNATURE);


 if(m_head != NULL) {


   *TxBuf = m_head->SystemBuf.Buf;


   RemoveEntryList (&m_head->Link);


   FreePool (m_head);


 }


}
}

+}



+static
+VOID
+msk_start (

INT32   Port
)

+{

EFI_STATUS            Status;
struct msk_if_softc   *sc_if;
MSK_LINKED_SYSTEM_BUF *m_head;
INTN                  enq;

sc_if = mSoftc->msk_if[Port];
for (enq = 0; !IsListEmpty (&mSoftc->TransmitQueueHead) &&
  sc_if->msk_cdata.msk_tx_cnt < (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); )


{

m_head = CR (GetFirstNode (&mSoftc->TransmitQueueHead), MSK_LINKED_SYSTEM_BUF, Link, TX_MBUF_SIGNATURE);
if (m_head == NULL) {
 break;


}
//
// Pack the data into the transmit ring. If we
// don't have room, set the OACTIVE flag and wait
// for the NIC to drain the ring.
//
Status = msk_encap (sc_if, &m_head->SystemBuf);
if (EFI_ERROR (Status)) {
 break;


}

RemoveEntryList (&m_head->Link);
InsertTailList (&mSoftc->TransmitFreeQueueHead, &m_head->Link);
//FreePool (m_head);
enq++;
}

if (enq > 0) {
// Transmit
CSR_WRITE_2 (mSoftc, Y2_PREF_Q_ADDR (sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_tx_prod);

// Set a timeout in case the chip goes out to lunch.
//    sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
}

+}



+/*static VOID
+msk_watchdog (struct msk_if_softc *sc_if)
+{

struct ifnet *ifp;

MSK_IF_LOCK_ASSERT (sc_if);

if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
return;
ifp = sc_if->msk_ifp;
if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
if (bootverbose)
 if_printf (sc_if->msk_ifp, "watchdog timeout "


    "(missed link)\n");


ifp->if_oerrors++;
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
msk_init_locked (sc_if);
return;
}

if_printf (ifp, "watchdog timeout\n");
ifp->if_oerrors++;
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
msk_init_locked (sc_if);
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
msk_start_locked (ifp);

+}
+*/
+VOID
+mskc_shutdown (

VOID
)

+{

INTN i;

for (i = 0; i < mSoftc->msk_num_port; i++) {
if (mSoftc->msk_if[i] != NULL) {
 msk_stop (mSoftc->msk_if[i]);


}
}
gBS->SetTimer (mSoftc->Timer, TimerCancel, 0);

/* Put hardware reset. */
CSR_WRITE_2 (mSoftc, B0_CTST, CS_RST_SET);

+}



+/*static int
+mskc_suspend (device_t dev)
+{

struct msk_softc *sc;
int i;

sc = device_get_softc (dev);

MSK_LOCK(sc);

for (i = 0; i < sc->msk_num_port; i++) {
if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
   ((sc->msk_if[i]->msk_ifp->if_drv_flags &


   IFF_DRV_RUNNING) != 0))


 msk_stop (sc->msk_if[i]);


}

+*/
+/* Disable all interrupts. */
+/*  CSR_WRITE_4 (sc, B0_IMSK, 0);

CSR_READ_4 (sc, B0_IMSK);
CSR_WRITE_4 (sc, B0_HWE_IMSK, 0);
CSR_READ_4 (sc, B0_HWE_IMSK);

msk_phy_power (sc, MSK_PHY_POWERDOWN);

+*/
+/* Put hardware reset. */
+/*  CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);

sc->msk_pflags |= MSK_FLAG_SUSPEND;

MSK_UNLOCK(sc);

return (0);

+}



+static int
+mskc_resume (device_t dev)
+{

struct msk_softc *sc;
int i;

sc = device_get_softc (dev);

MSK_LOCK(sc);

mskc_reset (sc);
for (i = 0; i < sc->msk_num_port; i++) {
if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
   ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) {


 sc->msk_if[i]->msk_ifp->if_drv_flags &=


     ~IFF_DRV_RUNNING;


 msk_init_locked (sc->msk_if[i]);


}
}
sc->msk_pflags &= ~MSK_FLAG_SUSPEND;

MSK_UNLOCK(sc);

return (0);

+}*/



+EFI_STATUS
+mskc_receive (

IN OUT UINTN  *BufferSize,
OUT    VOID   *Buffer
)

+{

MSK_LINKED_DMA_BUF   *mBuf;

msk_intr (); // check the interrupt lines

if (IsListEmpty (&mSoftc->ReceiveQueueHead)) {
*BufferSize = 0;
return EFI_NOT_READY;
}

mBuf = CR (GetFirstNode (&mSoftc->ReceiveQueueHead), MSK_LINKED_DMA_BUF, Link, RX_MBUF_SIGNATURE);
if (mBuf->DmaBuf.Length > *BufferSize) {
*BufferSize = mBuf->DmaBuf.Length;
DEBUG ((EFI_D_NET, "Marvell Yukon: Receive buffer is too small: Provided = %d, Received = %d\n",
       *BufferSize, mBuf->DmaBuf.Length));


return EFI_BUFFER_TOO_SMALL;
}
*BufferSize = mBuf->DmaBuf.Length;
RemoveEntryList (&mBuf->Link);
CopyMem (Buffer, mBuf->DmaBuf.Buf, *BufferSize);
FreePool(mBuf->DmaBuf.Buf);
FreePool (mBuf);
return EFI_SUCCESS;

+}



+static VOID
+msk_rxeof (

struct msk_if_softc   *sc_if,
UINT32                status,
UINT32                control,
INTN                  len
)

+{

EFI_STATUS          Status;
MSK_LINKED_DMA_BUF  *m_link;
struct msk_rxdesc   *rxd;
INTN                cons;
INTN                rxlen;

DEBUG ((EFI_D_NET, "Marvell Yukon: rxeof\n"));

cons = sc_if->msk_cdata.msk_rx_cons;
do {
rxlen = status >> 16;
if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
 //


 // For controllers that returns bogus status code


 // just do minimal check and let upper stack


 // handle this frame.


 //


 if (len > MAX_SUPPORTED_PACKET_SIZE || len < NET_ETHER_ADDR_LEN) {


   msk_discard_rxbuf (sc_if, cons);


   break;


 }


} else if (len > sc_if->msk_framesize ||
          ((status & GMR_FS_ANY_ERR) != 0) ||


          ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {


 msk_discard_rxbuf (sc_if, cons);


 break;


}

Status = msk_newbuf (sc_if, cons);
if (EFI_ERROR (Status)) {
 // Reuse old buffer


 msk_discard_rxbuf (sc_if, cons);


}
m_link = AllocateZeroPool (sizeof (MSK_LINKED_DMA_BUF));
if (m_link != NULL) {
 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];



 m_link->Signature = RX_MBUF_SIGNATURE;


 m_link->DmaBuf.Buf = AllocateZeroPool (len);


 CopyMem (m_link->DmaBuf.Buf, rxd->rx_m.Buf, len);


 m_link->DmaBuf.Length = len;


 m_link->DmaBuf.DmaMapping = rxd->rx_m.DmaMapping;



 InsertTailList (&mSoftc->ReceiveQueueHead, &m_link->Link);


} else {
 DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate receive buffer link. Dropping Frame\n"));


}
} while (0);

MSK_INC (sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
MSK_INC (sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);

+}



+static
+VOID
+msk_txeof (

struct msk_if_softc   *sc_if,
INTN                  idx
)

+{

struct msk_txdesc   *txd;
struct msk_tx_desc  *cur_tx;
UINT32              control;
INTN                cons;
INTN                prog;

DEBUG ((EFI_D_NET, "Marvell Yukon: txeof\n"));
//
// Go through our tx ring and free mbufs for those
// frames that have been sent.
//
cons = sc_if->msk_cdata.msk_tx_cons;
prog = 0;
for (; cons != idx; MSK_INC (cons, MSK_TX_RING_CNT)) {
if (sc_if->msk_cdata.msk_tx_cnt <= 0) {
 break;


}
prog++;
cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
control = le32toh (cur_tx->msk_control);
sc_if->msk_cdata.msk_tx_cnt--;
if ((control & EOP) == 0) {
 continue;


}
txd = &sc_if->msk_cdata.msk_txdesc[cons];
mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping);
ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF));
// We don't own the transmit buffers so don't free them
}

if (prog > 0) {
sc_if->msk_cdata.msk_tx_cons = cons;
//    if (sc_if->msk_cdata.msk_tx_cnt == 0)
//      sc_if->msk_watchdog_timer = 0;
// No need to sync LEs as we didn't update LEs.
}

+}



+VOID
+mskc_tick (

IN EFI_EVENT  Event,
IN VOID       *Context
)

+{

e1000phy_tick ();
msk_handle_events ();

+}



+static
+VOID
+msk_intr_phy (

struct msk_if_softc   *sc_if
)

+{

UINT16  status;

msk_phy_readreg (sc_if->msk_md.port, PHY_MARV_INT_STAT);
status = msk_phy_readreg (sc_if->msk_md.port, PHY_MARV_INT_STAT);

// Handle FIFO Underrun/Overflow ?
if ((status & PHY_M_IS_FIFO_ERROR)) {
DEBUG ((EFI_D_NET, "Marvell Yukon: PHY FIFO underrun/overflow.\n"));
}

+}



+static
+VOID
+msk_intr_gmac (

struct msk_if_softc   *sc_if
)

+{

UINT8   status;

status = CSR_READ_1 (mSoftc, MR_ADDR (sc_if->msk_md.port, GMAC_IRQ_SRC));

// GMAC Rx FIFO overrun.
if ((status & GM_IS_RX_FF_OR) != 0) {
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
}
// GMAC Tx FIFO underrun.
if ((status & GM_IS_TX_FF_UR) != 0) {
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
//device_printf (sc_if->msk_if_dev, "Tx FIFO underrun!\n");*/
DEBUG ((EFI_D_NET, "Marvell Yukon: Tx FIFO underrun!\n"));
/*
* XXX


* In case of Tx underrun, we may need to flush/reset


* Tx MAC but that would also require resynchronization


* with status LEs. Reintializing status LEs would


* affect other port in dual MAC configuration so it


* should be aVOIDed as possible as we can.


* Due to lack of documentation it's all vague guess but


* it needs more investigation.


*/


}

+}



+static
+VOID
+msk_handle_hwerr (

struct msk_if_softc   *sc_if,
UINT32                status
)

+{

if ((status & Y2_IS_PAR_RD1) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: RAM buffer read parity error\n"));
// Clear IRQ.
CSR_WRITE_2 (mSoftc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_RD_PERR);
}
if ((status & Y2_IS_PAR_WR1) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: RAM buffer write parity error\n"));
// Clear IRQ
CSR_WRITE_2 (mSoftc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_WR_PERR);
}
if ((status & Y2_IS_PAR_MAC1) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Tx MAC parity error\n"));
// Clear IRQ
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
}
if ((status & Y2_IS_PAR_RX1) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Rx parity error\n"));
// Clear IRQ
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
}
if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: TCP segmentation error\n"));
// Clear IRQ
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
}

+}



+static
+VOID
+msk_intr_hwerr (

VOID
)

+{

UINT32  status;
UINT32  tlphead[4];

status = CSR_READ_4 (mSoftc, B0_HWE_ISRC);

// Time Stamp timer overflow.
if ((status & Y2_IS_TIST_OV) != 0) {
CSR_WRITE_1 (mSoftc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
}
if ((status & Y2_IS_PCI_NEXP) != 0) {
/*
* PCI Express Error occured which is not described in PEX


* spec.


* This error is also mapped either to Master Abort (


* Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and


* can only be cleared there.


*/


DEBUG ((EFI_D_NET, "Marvell Yukon: PCI Express protocol violation error\n"));
}

if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {

if ((status & Y2_IS_MST_ERR) != 0) {
 DEBUG ((EFI_D_NET, "Marvell Yukon: unexpected IRQ Status error\n"));


} else {
 DEBUG ((EFI_D_NET, "Marvell Yukon: unexpected IRQ Master error\n"));


}
// Reset all bits in the PCI status register
clear_pci_errors ();
}

// Check for PCI Express Uncorrectable Error.
if ((status & Y2_IS_PCI_EXP) != 0) {
UINT32 v32;

/*
* On PCI Express bus bridges are called root complexes (RC).


* PCI Express errors are recognized by the root complex too,


* which requests the system to handle the problem. After


* error occurrence it may be that no access to the adapter


* may be performed any longer.


*/



v32 = CSR_PCI_READ_4 (mSoftc, PEX_UNC_ERR_STAT);
if ((v32 & PEX_UNSUP_REQ) != 0) {
 // Ignore unsupported request error.


 DEBUG ((EFI_D_NET, "Marvell Yukon: Uncorrectable PCI Express error\n"));


}
if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
 INTN i;



 // Get TLP header form Log Registers.


 for (i = 0; i < 4; i++) {


   tlphead[i] = CSR_PCI_READ_4 (mSoftc, PEX_HEADER_LOG + i * 4);


 }


 // Check for vendor defined broadcast message.


 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {


   mSoftc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;


   CSR_WRITE_4 (mSoftc, B0_HWE_IMSK, mSoftc->msk_intrhwemask);


   CSR_READ_4 (mSoftc, B0_HWE_IMSK);


 }


}
// Clear the interrupt
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_PCI_WRITE_4 (mSoftc, PEX_UNC_ERR_STAT, 0xffffffff);
CSR_WRITE_1 (mSoftc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
}

if ((status & Y2_HWE_L1_MASK) != 0 && mSoftc->msk_if[MSK_PORT_A] != NULL) {
msk_handle_hwerr (mSoftc->msk_if[MSK_PORT_A], status);
}
if ((status & Y2_HWE_L2_MASK) != 0 && mSoftc->msk_if[MSK_PORT_B] != NULL) {
msk_handle_hwerr (mSoftc->msk_if[MSK_PORT_B], status >> 8);
}

+}



+static
+__inline
+VOID
+msk_rxput (

struct msk_if_softc   *sc_if
)

+{

CSR_WRITE_2 (mSoftc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);

+}



+static
+INTN
+msk_handle_events (

VOID
)

+{

struct msk_if_softc   *sc_if;
INTN                  rxput[2];
struct msk_stat_desc  *sd;
UINT32                control;
UINT32                status;
INTN                  cons;
INTN                  len;
INTN                  port;
INTN                  rxprog;

if (mSoftc->msk_stat_cons == CSR_READ_2 (mSoftc, STAT_PUT_IDX)) {
return (0);
}

rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
rxprog = 0;
cons = mSoftc->msk_stat_cons;
for (;;) {
sd = &mSoftc->msk_stat_ring[cons];
control = le32toh (sd->msk_control);
if ((control & HW_OWNER) == 0) {
 break;


}
control &= ~HW_OWNER;
sd->msk_control = htole32 (control);
status = le32toh (sd->msk_status);
len = control & STLE_LEN_MASK;
port = (control >> 16) & 0x01;
sc_if = mSoftc->msk_if[port];
if (sc_if == NULL) {
 DEBUG ((EFI_D_NET, "Marvell Yukon: invalid port opcode 0x%08x\n", control & STLE_OP_MASK));


 continue;


}

switch (control & STLE_OP_MASK) {
 case OP_RXSTAT:


   msk_rxeof (sc_if, status, control, len);


   rxprog++;


   //


   // Because there is no way to sync single Rx LE


   // put the DMA sync operation off until the end of


   // event processing.


   //


   rxput[port]++;


   // Update prefetch unit if we've passed water mark


   if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {


     msk_rxput (sc_if);


     rxput[port] = 0;


   }


   break;


 case OP_TXINDEXLE:


   if (mSoftc->msk_if[MSK_PORT_A] != NULL) {


     msk_txeof (mSoftc->msk_if[MSK_PORT_A], status & STLE_TXA1_MSKL);


   }


   if (mSoftc->msk_if[MSK_PORT_B] != NULL) {


     msk_txeof (mSoftc->msk_if[MSK_PORT_B],


                ((status & STLE_TXA2_MSKL) >>


                 STLE_TXA2_SHIFTL) |


                ((len & STLE_TXA2_MSKH) <<


                 STLE_TXA2_SHIFTH));


   }


   break;


 default:


   DEBUG ((EFI_D_NET, "Marvell Yukon: unhandled opcode 0x%08x\n", control & STLE_OP_MASK));


   break;


}
MSK_INC (cons, MSK_STAT_RING_CNT);
if (rxprog > mSoftc->msk_process_limit) {
 break;


}
}

mSoftc->msk_stat_cons = cons;

if (rxput[MSK_PORT_A] > 0) {
msk_rxput (mSoftc->msk_if[MSK_PORT_A]);
}
if (rxput[MSK_PORT_B] > 0) {
msk_rxput (mSoftc->msk_if[MSK_PORT_B]);
}

return (mSoftc->msk_stat_cons != CSR_READ_2 (mSoftc, STAT_PUT_IDX));

+}



+STATIC
+VOID
+msk_intr (

VOID
)

+{

struct msk_if_softc   *sc_if0;
struct msk_if_softc   *sc_if1;
UINT32                Status;
INTN                  domore;

// Reading B0_Y2_SP_ISRC2 masks further interrupts
Status = CSR_READ_4 (mSoftc, B0_Y2_SP_ISRC2);
if (Status == 0 || Status == 0xffffffff ||
 (mSoftc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||


 (Status & mSoftc->msk_intrmask) == 0)


{
// Leave ISR - Reenable interrupts
CSR_WRITE_4 (mSoftc, B0_Y2_SP_ICR, 2);
return;
}

sc_if0 = mSoftc->msk_if[MSK_PORT_A];
sc_if1 = mSoftc->msk_if[MSK_PORT_B];

if ((Status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) {
msk_intr_phy (sc_if0);
}
if ((Status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) {
msk_intr_phy (sc_if1);
}
if ((Status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) {
msk_intr_gmac (sc_if0);
}
if ((Status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) {
msk_intr_gmac (sc_if1);
}
if ((Status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Rx descriptor error\n"));
mSoftc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
CSR_WRITE_4 (mSoftc, B0_IMSK, mSoftc->msk_intrmask);
CSR_READ_4 (mSoftc, B0_IMSK);
}
if ((Status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Tx descriptor error\n"));
mSoftc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
CSR_WRITE_4 (mSoftc, B0_IMSK, mSoftc->msk_intrmask);
CSR_READ_4 (mSoftc, B0_IMSK);
}
if ((Status & Y2_IS_HW_ERR) != 0) {
msk_intr_hwerr ();
}

domore = msk_handle_events ();
if ((Status & Y2_IS_STAT_BMU) != 0 && domore == 0) {
CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_CLR_IRQ);
}

// Leave ISR - Reenable interrupts
CSR_WRITE_4 (mSoftc, B0_Y2_SP_ICR, 2);

+}



+static
+VOID
+msk_set_tx_stfwd (

struct msk_if_softc   *sc_if
)

+{

/*  struct msk_softc *sc;
struct ifnet *ifp;

ifp = sc_if->msk_ifp;
sc = sc_if->msk_softc;
switch (sc->msk_hw_id) {
case CHIP_ID_YUKON_EX:
if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
 goto yukon_ex_workaround;


if (ifp->if_mtu > ETHERMTU)
 CSR_WRITE_4 (sc,


     MR_ADDR (sc_if->msk_port, TX_GMF_CTRL_T),


     TX_JUMBO_ENA | TX_STFW_ENA);


else
 CSR_WRITE_4 (sc,


     MR_ADDR (sc_if->msk_port, TX_GMF_CTRL_T),


     TX_JUMBO_DIS | TX_STFW_ENA);


break;
default:

+yukon_ex_workaround:

if (ifp->if_mtu > ETHERMTU) {*/
/* Set Tx GMAC FIFO Almost Empty Threshold. */
/*      CSR_WRITE_4 (sc,
     MR_ADDR (sc_if->msk_port, TX_GMF_AE_THR),


     MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);*/


/* Disable Store & Forward mode for Tx. */
/*      CSR_WRITE_4 (sc,
     MR_ADDR (sc_if->msk_port, TX_GMF_CTRL_T),


     TX_JUMBO_ENA | TX_STFW_DIS);


} else {*/
/* Enable Store & Forward mode for Tx. */
/*      CSR_WRITE_4 (sc,
     MR_ADDR (sc_if->msk_port, TX_GMF_CTRL_T),


     TX_JUMBO_DIS | TX_STFW_ENA);


}
break;
}*/
// Disable jumbo frames for Tx
CSR_WRITE_4 (mSoftc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), TX_JUMBO_DIS | TX_STFW_ENA);

+}



+EFI_STATUS
+mskc_init (

VOID
)

+{

EFI_STATUS  Status;

// Just init port A
Status = msk_init (mSoftc->msk_if[MSK_PORT_A]);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->SetTimer (mSoftc->Timer, TimerPeriodic, TICKS_PER_SECOND);
if (EFI_ERROR (Status)) {
mskc_shutdown ();
}
return Status;

+}



+static
+EFI_STATUS
+msk_init (

IN struct msk_if_softc  *sc_if
)

+{

UINT8       *eaddr;
UINT16      gmac;
UINT32      reg;
EFI_STATUS  Status;
INTN        port = sc_if->msk_md.port;

// Cancel pending I/O and free all Rx/Tx buffers.
msk_stop (sc_if);

sc_if->msk_framesize = MAX_SUPPORTED_PACKET_SIZE;

// GMAC Control reset.
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), GMC_F_LOOPB_OFF);
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_EX) {
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);
}

//
// Initialize GMAC first such that speed/duplex/flow-control
// parameters are renegotiated when interface is brought up.
//
GMAC_WRITE_2 (mSoftc, port, GM_GP_CTRL, 0);

// Dummy read the Interrupt Source Register
CSR_READ_1 (mSoftc, MR_ADDR (port, GMAC_IRQ_SRC));

// Clear MIB stats
msk_stats_clear (sc_if);

// Disable FCS
GMAC_WRITE_2 (mSoftc, port, GM_RX_CTRL, GM_RXCR_CRC_DIS);

// Setup Transmit Control Register
GMAC_WRITE_2 (mSoftc, port, GM_TX_CTRL, TX_COL_THR (TX_COL_DEF));

// Setup Transmit Flow Control Register
GMAC_WRITE_2 (mSoftc, port, GM_TX_FLOW_CTRL, 0xffff);

// Setup Transmit Parameter Register
GMAC_WRITE_2 (mSoftc, port, GM_TX_PARAM,
           TX_JAM_LEN_VAL (TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL (TX_JAM_IPG_DEF) |


           TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));



gmac = DATA_BLIND_VAL (DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA | IPG_DATA_VAL (IPG_DATA_DEF);

//  if (ifp->if_mtu > ETHERMTU)
//    gmac |= GM_SMOD_JUMBO_ENA;
GMAC_WRITE_2 (mSoftc, port, GM_SERIAL_MODE, gmac);

// Set station address
eaddr = sc_if->MacAddress.Addr;
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_1L, eaddr[0] | (eaddr[1] << 8));
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_1M, eaddr[2] | (eaddr[3] << 8));
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_1H, eaddr[4] | (eaddr[5] << 8));
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_2L, eaddr[0] | (eaddr[1] << 8));
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_2M, eaddr[2] | (eaddr[3] << 8));
GMAC_WRITE_2 (mSoftc, port, GM_SRC_ADDR_2H, eaddr[4] | (eaddr[5] << 8));

// Disable interrupts for counter overflows
GMAC_WRITE_2 (mSoftc, port, GM_TX_IRQ_MSK, 0);
GMAC_WRITE_2 (mSoftc, port, GM_RX_IRQ_MSK, 0);
GMAC_WRITE_2 (mSoftc, port, GM_TR_IRQ_MSK, 0);

// Configure Rx MAC FIFO
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_CLR);
reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_FE_P || mSoftc->msk_hw_id == CHIP_ID_YUKON_EX) {
reg |= GMF_RX_OVER_ON;
}
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), reg);

if (mSoftc->msk_hw_id == CHIP_ID_YUKON_XL) {
// Clear flush mask - HW bug
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_FL_MSK), 0);
} else {
// Flush Rx MAC FIFO on any flow control or error
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
}

//
// Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
// due to hardware hang on receipt of pause frames.
//
reg = RX_GMF_FL_THR_DEF + 1;
// Another magic for Yukon FE+ - From Linux
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_FE_P && mSoftc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
reg = 0x178;
}
CSR_WRITE_2 (mSoftc, MR_ADDR (port, RX_GMF_FL_THR), reg);

// Configure Tx MAC FIFO
CSR_WRITE_4 (mSoftc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_CLR);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_OPER_ON);

// Configure hardware VLAN tag insertion/stripping
msk_setvlan (sc_if);

if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
// Set Rx Pause threshould.
CSR_WRITE_2 (mSoftc, MR_ADDR (port, RX_GMF_LP_THR), MSK_ECU_LLPP);
CSR_WRITE_2 (mSoftc, MR_ADDR (port, RX_GMF_UP_THR), MSK_ECU_ULPP);
// Configure store-and-forward for Tx.
msk_set_tx_stfwd (sc_if);
}

if (mSoftc->msk_hw_id == CHIP_ID_YUKON_FE_P && mSoftc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
// Disable dynamic watermark - from Linux
reg = CSR_READ_4 (mSoftc, MR_ADDR (port, TX_GMF_EA));
reg &= ~0x03;
CSR_WRITE_4 (mSoftc, MR_ADDR (port, TX_GMF_EA), reg);
}

//
// Disable Force Sync bit and Alloc bit in Tx RAM interface
// arbiter as we don't use Sync Tx queue.
//
CSR_WRITE_1 (mSoftc, MR_ADDR (port, TXA_CTRL), TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
// Enable the RAM Interface Arbiter
CSR_WRITE_1 (mSoftc, MR_ADDR (port, TXA_CTRL), TXA_ENA_ARB);

// Setup RAM buffer
msk_set_rambuffer (sc_if);

// Disable Tx sync Queue
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txsq, RB_CTRL), RB_RST_SET);

// Setup Tx Queue Bus Memory Interface
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
CSR_WRITE_2 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_WM),  MSK_BMU_TX_WM);
switch (mSoftc->msk_hw_id) {
case CHIP_ID_YUKON_EC_U:
 if (mSoftc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {


   // Fix for Yukon-EC Ultra: set BMU FIFO level


   CSR_WRITE_2 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);


 }


 break;


case CHIP_ID_YUKON_EX:
 //


 // Yukon Extreme seems to have silicon bug for


 // automatic Tx checksum calculation capability.


 //


 if (mSoftc->msk_hw_rev == CHIP_REV_YU_EX_B0) {


   CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_F), F_TX_CHK_AUTO_OFF);


 }


 break;


}

// Setup Rx Queue Bus Memory Interface
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
CSR_WRITE_2 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_WM),  MSK_BMU_RX_WM);
if (mSoftc->msk_hw_id == CHIP_ID_YUKON_EC_U && mSoftc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
// MAC Rx RAM Read is controlled by hardware
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
}

// truncate too-large frames - from linux
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_TR_THR), 0x17a);
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), RX_TRUNC_ON);

msk_set_prefetch (sc_if->msk_txq, sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
msk_init_tx_ring (sc_if);

// Disable Rx checksum offload and RSS hash
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
msk_set_prefetch (sc_if->msk_rxq, sc_if->msk_rdata.msk_rx_ring_paddr, MSK_RX_RING_CNT - 1);
Status = msk_init_rx_ring (sc_if);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_NET, "Initialization failed: no memory for Rx buffers\n"));
msk_stop (sc_if);
return Status;
}

if (mSoftc->msk_hw_id == CHIP_ID_YUKON_EX) {
// Disable flushing of non-ASF packets
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RX_MACSEC_FLUSH_OFF);
}

// Configure interrupt handling
if (port == MSK_PORT_A) {
mSoftc->msk_intrmask |= Y2_IS_PORT_A;
mSoftc->msk_intrhwemask |= Y2_HWE_L1_MASK;
} else {
mSoftc->msk_intrmask |= Y2_IS_PORT_B;
mSoftc->msk_intrhwemask |= Y2_HWE_L2_MASK;
}
// Configure IRQ moderation mask.
CSR_WRITE_4 (mSoftc, B2_IRQM_MSK, mSoftc->msk_intrmask);
if (mSoftc->msk_int_holdoff > 0) {
// Configure initial IRQ moderation timer value.
CSR_WRITE_4 (mSoftc, B2_IRQM_INI, MSK_USECS (mSoftc, mSoftc->msk_int_holdoff));
CSR_WRITE_4 (mSoftc, B2_IRQM_VAL, MSK_USECS (mSoftc, mSoftc->msk_int_holdoff));
// Start IRQ moderation.
CSR_WRITE_1 (mSoftc, B2_IRQM_CTRL, TIM_START);
}
CSR_WRITE_4 (mSoftc, B0_HWE_IMSK, mSoftc->msk_intrhwemask);
CSR_READ_4 (mSoftc, B0_HWE_IMSK);
CSR_WRITE_4 (mSoftc, B0_IMSK, mSoftc->msk_intrmask);
CSR_READ_4 (mSoftc, B0_IMSK);

sc_if->msk_flags &= ~MSK_FLAG_LINK;
e1000phy_mediachg ();

return Status;

+}



+STATIC
+VOID
+msk_set_rambuffer (

struct msk_if_softc *sc_if
)

+{

INTN ltpp, utpp;
INTN port = sc_if->msk_md.port;

if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
return;

// Setup Rx Queue
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_START), mSoftc->msk_rxqstart[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_END), mSoftc->msk_rxqend[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_WP), mSoftc->msk_rxqstart[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_RP), mSoftc->msk_rxqstart[port] / 8);

utpp = (mSoftc->msk_rxqend[port] + 1 - mSoftc->msk_rxqstart[port] - MSK_RB_ULPP) / 8;
ltpp = (mSoftc->msk_rxqend[port] + 1 - mSoftc->msk_rxqstart[port] - MSK_RB_LLPP_B) / 8;
if (mSoftc->msk_rxqsize < MSK_MIN_RXQ_SIZE) {
ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
}
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_RX_UTPP), utpp);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_RX_LTPP), ltpp);
// Set Rx priority (RB_RX_UTHP/RB_RX_LTHP) thresholds?

CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_CTRL));

// Setup Tx Queue.
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_START), mSoftc->msk_txqstart[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_END), mSoftc->msk_txqend[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_WP), mSoftc->msk_txqstart[port] / 8);
CSR_WRITE_4 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_RP), mSoftc->msk_txqstart[port] / 8);

// Enable Store & Forward for Tx side
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL));

+}



+STATIC
+VOID
+msk_set_prefetch (

INTN qaddr,
EFI_PHYSICAL_ADDRESS addr,
UINT32 count
)

+{

// Reset the prefetch unit
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
// Set LE base address
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_LOW_REG), MSK_ADDR_LO (addr));
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_HI_REG), MSK_ADDR_HI (addr));

// Set the list last index
CSR_WRITE_2 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_LAST_IDX_REG), count);
// Turn on prefetch unit
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
// Dummy read to ensure write
CSR_READ_4 (mSoftc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG));

+}



+static
+VOID
+msk_stop (

struct msk_if_softc *sc_if
)

+{

struct msk_txdesc   *txd;
struct msk_rxdesc   *rxd;
UINT32              val;
INTN                i;
INTN                port = sc_if->msk_md.port;

// Disable interrupts
if (port == MSK_PORT_A) {
mSoftc->msk_intrmask &= ~Y2_IS_PORT_A;
mSoftc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
} else {
mSoftc->msk_intrmask &= ~Y2_IS_PORT_B;
mSoftc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
}
CSR_WRITE_4 (mSoftc, B0_HWE_IMSK, mSoftc->msk_intrhwemask);
CSR_READ_4 (mSoftc, B0_HWE_IMSK);
CSR_WRITE_4 (mSoftc, B0_IMSK, mSoftc->msk_intrmask);
CSR_READ_4 (mSoftc, B0_IMSK);

// Disable Tx/Rx MAC.
val = GMAC_READ_2 (mSoftc, port, GM_GP_CTRL);
val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
GMAC_WRITE_2 (mSoftc, port, GM_GP_CTRL, val);
// Read again to ensure writing.
GMAC_READ_2 (mSoftc, port, GM_GP_CTRL);
// Update stats and clear counters
msk_stats_update (sc_if);

// Stop Tx BMU
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);
val = CSR_READ_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR));
for (i = 0; i < MSK_TIMEOUT; i++) {
if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
 CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);


 val = CSR_READ_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR));


} else {
 break;


}
MicroSecondDelay (1);
}
if (i == MSK_TIMEOUT) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Tx BMU stop failed\n"));
}
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);

// Disable all GMAC interrupt.
CSR_WRITE_1 (mSoftc, MR_ADDR (port, GMAC_IRQ_MSK), 0);
// Disable PHY interrupt. */
msk_phy_writereg (port, PHY_MARV_INT_MASK, 0);

// Disable the RAM Interface Arbiter.
CSR_WRITE_1 (mSoftc, MR_ADDR (port, TXA_CTRL), TXA_DIS_ARB);

// Reset the PCI FIFO of the async Tx queue
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

// Reset the Tx prefetch units
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (sc_if->msk_txq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);

// Reset the RAM Buffer async Tx queue
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET);

// Reset Tx MAC FIFO.
CSR_WRITE_4 (mSoftc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
// Set Pause Off.
CSR_WRITE_4 (mSoftc, MR_ADDR (port, GMAC_CTRL), GMC_PAUSE_OFF);

/*

The Rx Stop command will not work for Yukon-2 if the BMU does not



reach the end of packet and since we can't make sure that we have



incoming data, we must reset the BMU while it is not during a DMA



transfer. Since it is possible that the Rx path is still active,



the Rx RAM buffer will be stopped first, so any possible incoming



data will not trigger a DMA. After the RAM buffer is stopped, the



BMU is polled until any DMA in progress is ended and only then it



will be reset.


*/

// Disable the RAM Buffer receive queue
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
for (i = 0; i < MSK_TIMEOUT; i++) {
if (CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RSL)) == CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RL))) {
 break;


}
MicroSecondDelay (1);
}
if (i == MSK_TIMEOUT) {
DEBUG ((EFI_D_NET, "Marvell Yukon: Rx BMU stop failed\n"));
}
CSR_WRITE_4 (mSoftc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
// Reset the Rx prefetch unit.
CSR_WRITE_4 (mSoftc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
// Reset the RAM Buffer receive queue.
CSR_WRITE_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
// Reset Rx MAC FIFO.
CSR_WRITE_4 (mSoftc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);

// Free Rx and Tx mbufs still in the queues
for (i = 0; i < MSK_RX_RING_CNT; i++) {
rxd = &sc_if->msk_cdata.msk_rxdesc[i];
if (rxd->rx_m.Buf != NULL) {
 mPciIo->Unmap (mPciIo, rxd->rx_m.DmaMapping);


 if(rxd->rx_m.Buf != NULL) {


   mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf);


   rxd->rx_m.Buf = NULL;


 }


 ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF));


}
}

for (i = 0; i < MSK_TX_RING_CNT; i++) {
txd = &sc_if->msk_cdata.msk_txdesc[i];
if (txd->tx_m.Buf != NULL) {
 mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping);


 ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF));


 // We don't own the transmit buffers so don't free them


}
}

/*

Mark the interface down.


*/
sc_if->msk_flags &= ~MSK_FLAG_LINK;

+}



+/*


When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower



counter clears high 16 bits of the counter such that accessing



lower 16 bits should be the last operation.


*/

+#define  MSK_READ_MIB32(x, y)    (((UINT32)GMAC_READ_2 (mSoftc, x, (y) + 4)) << 16) +  (UINT32)GMAC_READ_2 (mSoftc, x, y)
+#define  MSK_READ_MIB64(x, y)    (((UINT64)MSK_READ_MIB32 (x, (y) + 8)) << 32) + (UINT64)MSK_READ_MIB32 (x, y)



+static
+VOID
+msk_stats_clear (

struct msk_if_softc   *sc_if
)

+{

UINT16      gmac;
INTN        val;
INTN        i;
INTN        port = sc_if->msk_md.port;

// Set MIB Clear Counter Mode.
gmac = GMAC_READ_2 (mSoftc, port, GM_PHY_ADDR);
GMAC_WRITE_2 (mSoftc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
// Read all MIB Counters with Clear Mode set
for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof (UINT32)) {
val = MSK_READ_MIB32 (port, i);
if (val); //Workaround: to prevent the GCC error: 'value computed is not used'
}
// Clear MIB Clear Counter Mode
gmac &= ~GM_PAR_MIB_CLR;
GMAC_WRITE_2 (mSoftc, port, GM_PHY_ADDR, gmac);

+}



+static
+VOID
+msk_stats_update (

struct msk_if_softc   *sc_if
)

+{

struct msk_hw_stats   *stats;
UINT16                gmac;
INTN                  val;
INTN                  port = sc_if->msk_md.port;

stats = &sc_if->msk_stats;
/* Set MIB Clear Counter Mode. */
gmac = GMAC_READ_2 (mSoftc, port, GM_PHY_ADDR);
GMAC_WRITE_2 (mSoftc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);

/* Rx stats. */
stats->rx_ucast_frames    += MSK_READ_MIB32 (port, GM_RXF_UC_OK);
stats->rx_bcast_frames    += MSK_READ_MIB32 (port, GM_RXF_BC_OK);
stats->rx_pause_frames    += MSK_READ_MIB32 (port, GM_RXF_MPAUSE);
stats->rx_mcast_frames    += MSK_READ_MIB32 (port, GM_RXF_MC_OK);
stats->rx_crc_errs        += MSK_READ_MIB32 (port, GM_RXF_FCS_ERR);
val = MSK_READ_MIB32 (port, GM_RXF_SPARE1);
stats->rx_good_octets     += MSK_READ_MIB64 (port, GM_RXO_OK_LO);
stats->rx_bad_octets      += MSK_READ_MIB64 (port, GM_RXO_ERR_LO);
stats->rx_runts           += MSK_READ_MIB32 (port, GM_RXF_SHT);
stats->rx_runt_errs       += MSK_READ_MIB32 (port, GM_RXE_FRAG);
stats->rx_pkts_64         += MSK_READ_MIB32 (port, GM_RXF_64B);
stats->rx_pkts_65_127     += MSK_READ_MIB32 (port, GM_RXF_127B);
stats->rx_pkts_128_255    += MSK_READ_MIB32 (port, GM_RXF_255B);
stats->rx_pkts_256_511    += MSK_READ_MIB32 (port, GM_RXF_511B);
stats->rx_pkts_512_1023   += MSK_READ_MIB32 (port, GM_RXF_1023B);
stats->rx_pkts_1024_1518  += MSK_READ_MIB32 (port, GM_RXF_1518B);
stats->rx_pkts_1519_max   += MSK_READ_MIB32 (port, GM_RXF_MAX_SZ);
stats->rx_pkts_too_long   += MSK_READ_MIB32 (port, GM_RXF_LNG_ERR);
stats->rx_pkts_jabbers    += MSK_READ_MIB32 (port, GM_RXF_JAB_PKT);
val = MSK_READ_MIB32 (port, GM_RXF_SPARE2);
stats->rx_fifo_oflows     += MSK_READ_MIB32 (port, GM_RXE_FIFO_OV);
val = MSK_READ_MIB32 (port, GM_RXF_SPARE3);

/* Tx stats. */
stats->tx_ucast_frames    += MSK_READ_MIB32 (port, GM_TXF_UC_OK);
stats->tx_bcast_frames    += MSK_READ_MIB32 (port, GM_TXF_BC_OK);
stats->tx_pause_frames    += MSK_READ_MIB32 (port, GM_TXF_MPAUSE);
stats->tx_mcast_frames    += MSK_READ_MIB32 (port, GM_TXF_MC_OK);
stats->tx_octets          += MSK_READ_MIB64 (port, GM_TXO_OK_LO);
stats->tx_pkts_64         += MSK_READ_MIB32 (port, GM_TXF_64B);
stats->tx_pkts_65_127     += MSK_READ_MIB32 (port, GM_TXF_127B);
stats->tx_pkts_128_255    += MSK_READ_MIB32 (port, GM_TXF_255B);
stats->tx_pkts_256_511    += MSK_READ_MIB32 (port, GM_TXF_511B);
stats->tx_pkts_512_1023   += MSK_READ_MIB32 (port, GM_TXF_1023B);
stats->tx_pkts_1024_1518  += MSK_READ_MIB32 (port, GM_TXF_1518B);
stats->tx_pkts_1519_max   += MSK_READ_MIB32 (port, GM_TXF_MAX_SZ);
val = MSK_READ_MIB32 (port, GM_TXF_SPARE1);
stats->tx_colls           += MSK_READ_MIB32 (port, GM_TXF_COL);
stats->tx_late_colls      += MSK_READ_MIB32 (port, GM_TXF_LAT_COL);
stats->tx_excess_colls    += MSK_READ_MIB32 (port, GM_TXF_ABO_COL);
stats->tx_multi_colls     += MSK_READ_MIB32 (port, GM_TXF_MUL_COL);
stats->tx_single_colls    += MSK_READ_MIB32 (port, GM_TXF_SNG_COL);
stats->tx_underflows      += MSK_READ_MIB32 (port, GM_TXE_FIFO_UR);

if (val); //Workaround: to prevent the GCC error: 'value computed is not used'

/* Clear MIB Clear Counter Mode. */
gmac &= ~GM_PAR_MIB_CLR;
GMAC_WRITE_2 (mSoftc, port, GM_PHY_ADDR, gmac);

+}



+#undef MSK_READ_MIB32
+#undef MSK_READ_MIB64
diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.h b/Drivers/Net/MarvellYukonDxe/if_msk.h
new file mode 100644
index 0000000..28ff046
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_msk.h
@@ -0,0 +1,52 @@
+/**  <at> file
+*  API to ported msk driver
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+#include <Uefi.h>



+//#define MAX_SUPPORTED_PACKET_SIZE   1500
+#define MAX_SUPPORTED_PACKET_SIZE   EFI_PAGE_SIZE



+EFI_STATUS mskc_probe (EFI_PCI_IO_PROTOCOL *PciIo);



+EFI_STATUS mskc_attach (EFI_PCI_IO_PROTOCOL  *PciIo, EFI_MAC_ADDRESS *Mac);
+void mskc_detach (void);



+EFI_STATUS mskc_init (void);
+void mskc_shutdown (void);



+void
+mskc_rxfilter (

IN UINT32                      FilterFlags,
IN UINTN                       MCastFilterCnt,
IN EFI_MAC_ADDRESS             *MCastFilter
);


+EFI_STATUS
+mskc_transmit (

IN UINTN                       BufferSize,
IN VOID                        *Buffer
);


+EFI_STATUS
+mskc_receive (

IN OUT UINTN                   *BufferSize,
OUT VOID                       *Buffer
);


+void
+mskc_getstatus (

OUT UINT32                     *InterruptStatus, OPTIONAL
OUT VOID                       **TxBuf           OPTIONAL
);

diff --git a/Drivers/Net/MarvellYukonDxe/if_mskreg.h b/Drivers/Net/MarvellYukonDxe/if_mskreg.h
new file mode 100644
index 0000000..a105919
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_mskreg.h
@@ -0,0 +1,2491 @@
+/**  <at> file
+*  Defines and macros for the PCIe Marvell Yukon gigabit ethernet adapter product family
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/******************************************************************************






LICENSE:



Copyright (C) Marvell International Ltd. and/or its affiliates







The computer program files contained in this folder ("Files")



are provided to you under the BSD-type license terms provided



below, and any use of such Files and any derivative works



thereof created by you shall be governed by the following terms



and conditions:








Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above





copyright notice, this list of conditions and the following



disclaimer in the documentation and/or other materials provided



with the distribution.




Neither the name of Marvell nor the names of its contributors





may be used to endorse or promote products derived from this



software without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS



"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT



LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS



FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE



COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,



INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,



BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;



LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)



HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,



STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)



ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED



OF THE POSSIBILITY OF SUCH DAMAGE.



/LICENSE






******************************************************************************/


+/*-


Copyright (c) 1997, 1998, 1999, 2000



Bill Paul <wpaul <at> ctr.columbia.edu>.  All rights reserved.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




All advertising materials mentioning features or use of this software





must display the following acknowledgement:



This product includes software developed by Bill Paul.




Neither the name of the author nor the names of any co-contributors





may be used to endorse or promote products derived from this software



without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND



ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE



IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE



ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD



BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR



CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF



SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS



INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN



CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)



ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF



THE POSSIBILITY OF SUCH DAMAGE.


*/


+/*-


Copyright (c) 2003 Nathan L. Binkert <binkertn <at> umich.edu>







Permission to use, copy, modify, and distribute this software for any



purpose with or without fee is hereby granted, provided that the above



copyright notice and this permission notice appear in all copies.







THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES



WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF



MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR



ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES



WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN



ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF



OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.


*/


+/*$FreeBSD: src/sys/dev/msk/if_mskreg.h,v 1.27.2.10.2.1 2010/06/14 02:09:06 kensmith Exp $*/



+/*


SysKonnect PCI vendor ID


*/

+#define VENDORID_SK                         0x1148



+/*


Marvell PCI vendor ID


*/

+#define VENDORID_MARVELL                    0x11AB



+/*


D-Link PCI vendor ID


*/

+#define  VENDORID_DLINK                     0x1186



+/*


SysKonnect ethernet device IDs


*/

+#define DEVICEID_SK_YUKON2                  0x9000
+#define DEVICEID_SK_YUKON2_EXPR             0x9e00



+/*


Marvell gigabit ethernet device IDs


*/

+#define DEVICEID_MRVL_8021CU                0x4340
+#define DEVICEID_MRVL_8022CU                0x4341
+#define DEVICEID_MRVL_8061CU                0x4342
+#define DEVICEID_MRVL_8062CU                0x4343
+#define DEVICEID_MRVL_8021X                 0x4344
+#define DEVICEID_MRVL_8022X                 0x4345
+#define DEVICEID_MRVL_8061X                 0x4346
+#define DEVICEID_MRVL_8062X                 0x4347
+#define DEVICEID_MRVL_8035                  0x4350
+#define DEVICEID_MRVL_8036                  0x4351
+#define DEVICEID_MRVL_8038                  0x4352
+#define DEVICEID_MRVL_8039                  0x4353
+#define DEVICEID_MRVL_8040                  0x4354
+#define DEVICEID_MRVL_8040T                 0x4355
+#define DEVICEID_MRVL_8042                  0x4357
+#define DEVICEID_MRVL_8048                  0x435A
+#define DEVICEID_MRVL_4360                  0x4360
+#define DEVICEID_MRVL_4361                  0x4361
+#define DEVICEID_MRVL_4362                  0x4362
+#define DEVICEID_MRVL_4363                  0x4363
+#define DEVICEID_MRVL_4364                  0x4364
+#define DEVICEID_MRVL_4365                  0x4365
+#define DEVICEID_MRVL_436A                  0x436A
+#define DEVICEID_MRVL_436B                  0x436B
+#define DEVICEID_MRVL_436C                  0x436C
+#define DEVICEID_MRVL_4380                  0x4380
+#define DEVICEID_MRVL_4381                  0x4381



+/*


D-Link gigabit ethernet device ID


*/

+#define DEVICEID_DLINK_DGE550SX             0x4001
+#define DEVICEID_DLINK_DGE560SX             0x4002
+#define DEVICEID_DLINK_DGE560T              0x4b00



+#define BIT_31                              ((UINT32)1 << 31)
+#define BIT_30                              (1 << 30)
+#define BIT_29                              (1 << 29)
+#define BIT_28                              (1 << 28)
+#define BIT_27                              (1 << 27)
+#define BIT_26                              (1 << 26)
+#define BIT_25                              (1 << 25)
+#define BIT_24                              (1 << 24)
+#define BIT_23                              (1 << 23)
+#define BIT_22                              (1 << 22)
+#define BIT_21                              (1 << 21)
+#define BIT_20                              (1 << 20)
+#define BIT_19                              (1 << 19)
+#define BIT_18                              (1 << 18)
+#define BIT_17                              (1 << 17)
+#define BIT_16                              (1 << 16)
+#define BIT_15                              (1 << 15)
+#define BIT_14                              (1 << 14)
+#define BIT_13                              (1 << 13)
+#define BIT_12                              (1 << 12)
+#define BIT_11                              (1 << 11)
+#define BIT_10                              (1 << 10)
+#define BIT_9                               (1 << 9)
+#define BIT_8                               (1 << 8)
+#define BIT_7                               (1 << 7)
+#define BIT_6                               (1 << 6)
+#define BIT_5                               (1 << 5)
+#define BIT_4                               (1 << 4)
+#define BIT_3                               (1 << 3)
+#define BIT_2                               (1 << 2)
+#define BIT_1                               (1 << 1)
+#define BIT_0                               (1 << 0)



+#define SHIFT31(x)                          ((x) << 31)
+#define SHIFT30(x)                          ((x) << 30)
+#define SHIFT29(x)                          ((x) << 29)
+#define SHIFT28(x)                          ((x) << 28)
+#define SHIFT27(x)                          ((x) << 27)
+#define SHIFT26(x)                          ((x) << 26)
+#define SHIFT25(x)                          ((x) << 25)
+#define SHIFT24(x)                          ((x) << 24)
+#define SHIFT23(x)                          ((x) << 23)
+#define SHIFT22(x)                          ((x) << 22)
+#define SHIFT21(x)                          ((x) << 21)
+#define SHIFT20(x)                          ((x) << 20)
+#define SHIFT19(x)                          ((x) << 19)
+#define SHIFT18(x)                          ((x) << 18)
+#define SHIFT17(x)                          ((x) << 17)
+#define SHIFT16(x)                          ((x) << 16)
+#define SHIFT15(x)                          ((x) << 15)
+#define SHIFT14(x)                          ((x) << 14)
+#define SHIFT13(x)                          ((x) << 13)
+#define SHIFT12(x)                          ((x) << 12)
+#define SHIFT11(x)                          ((x) << 11)
+#define SHIFT10(x)                          ((x) << 10)
+#define SHIFT9(x)                           ((x) << 9)
+#define SHIFT8(x)                           ((x) << 8)
+#define SHIFT7(x)                           ((x) << 7)
+#define SHIFT6(x)                           ((x) << 6)
+#define SHIFT5(x)                           ((x) << 5)
+#define SHIFT4(x)                           ((x) << 4)
+#define SHIFT3(x)                           ((x) << 3)
+#define SHIFT2(x)                           ((x) << 2)
+#define SHIFT1(x)                           ((x) << 1)
+#define SHIFT0(x)                           ((x) << 0)



+/*


PCI Configuration Space header


*/

+#define PCI_BASE_1ST                        0x10  /* 32 bit 1st Base address */
+#define PCI_BASE_2ND                        0x14  /* 32 bit 2nd Base address */
+#define PCI_OUR_REG_1                       0x40  /* 32 bit Our Register 1 */
+#define PCI_OUR_REG_2                       0x44  /* 32 bit Our Register 2 */
+#define PCI_OUR_STATUS                      0x7c  /* 32 bit Adapter Status Register */
+#define PCI_OUR_REG_3                       0x80  /* 32 bit Our Register 3 */
+#define PCI_OUR_REG_4                       0x84  /* 32 bit Our Register 4 */
+#define PCI_OUR_REG_5                       0x88  /* 32 bit Our Register 5 */
+#define PCI_CFG_REG_0                       0x90  /* 32 bit Config Register 0 */
+#define PCI_CFG_REG_1                       0x94  /* 32 bit Config Register 1 */



+/* PCI Express Capability */
+#define PEX_CAP_ID                          0xe0  /*  8 bit PEX Capability ID */
+#define PEX_NITEM                           0xe1  /*  8 bit PEX Next Item Pointer */
+#define PEX_CAP_REG                         0xe2  /* 16 bit PEX Capability Register */
+#define PEX_DEV_CAP                         0xe4  /* 32 bit PEX Device Capabilities */
+#define PEX_DEV_CTRL                        0xe8  /* 16 bit PEX Device Control */
+#define PEX_DEV_STAT                        0xea  /* 16 bit PEX Device Status */
+#define PEX_LNK_CAP                         0xec  /* 32 bit PEX Link Capabilities */
+#define PEX_LNK_CTRL                        0xf0  /* 16 bit PEX Link Control */
+#define PEX_LNK_STAT                        0xf2  /* 16 bit PEX Link Status */



+/* PCI Express Extended Capabilities */
+#define PEX_ADV_ERR_REP                     0x100  /* 32 bit PEX Advanced Error Reporting */
+#define PEX_UNC_ERR_STAT                    0x104  /* 32 bit PEX Uncorr. Errors Status */
+#define PEX_UNC_ERR_MASK                    0x108  /* 32 bit PEX Uncorr. Errors Mask */
+#define PEX_UNC_ERR_SEV                     0x10c  /* 32 bit PEX Uncorr. Errors Severity */
+#define PEX_COR_ERR_STAT                    0x110  /* 32 bit PEX Correc. Errors Status */
+#define PEX_COR_ERR_MASK                    0x114  /* 32 bit PEX Correc. Errors Mask */
+#define PEX_ADV_ERR_CAP_C                   0x118  /* 32 bit PEX Advanced Error Cap./Ctrl */
+#define PEX_HEADER_LOG                      0x11c  /* 4x32 bit PEX Header Log Register */



+/*  PCI_OUR_REG_1  32 bit  Our Register 1 */
+#define PCI_Y2_PIG_ENA                      BIT_31  /* Enable Plug-in-Go (YUKON-2) */
+#define PCI_Y2_DLL_DIS                      BIT_30  /* Disable PCI DLL (YUKON-2) */
+#define PCI_Y2_PHY2_COMA                    BIT_29  /* Set PHY 2 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY1_COMA                    BIT_28  /* Set PHY 1 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY2_POWD                    BIT_27  /* Set PHY 2 to Power Down (YUKON-2) */
+#define PCI_Y2_PHY1_POWD                    BIT_26  /* Set PHY 1 to Power Down (YUKON-2) */
+#define PCI_DIS_BOOT                        BIT_24  /* Disable BOOT via ROM */
+#define PCI_EN_IO                           BIT_23  /* Mapping to I/O space */
+#define PCI_EN_FPROM                        BIT_22  /* Enable FLASH mapping to memory */
+/* 1 = Map Flash to memory */
+/* 0 = Disable addr. dec */
+#define PCI_PAGESIZE                        (3L<<20)/* Bit 21..20:  FLASH Page Size  */
+#define PCI_PAGE_16                         (0L<<20)/*    16 k pages  */
+#define PCI_PAGE_32K                        (1L<<20)/*    32 k pages  */
+#define PCI_PAGE_64K                        (2L<<20)/*    64 k pages  */
+#define PCI_PAGE_128K                       (3L<<20)/*    128 k pages  */
+#define PCI_PAGEREG                         (7L<<16)/* Bit 18..16:  Page Register  */
+#define PCI_PEX_LEGNAT                      BIT_15  /* PEX PM legacy/native mode (YUKON-2) */
+#define PCI_FORCE_BE                        BIT_14  /* Assert all BEs on MR */
+#define PCI_DIS_MRL                         BIT_13  /* Disable Mem Read Line */
+#define PCI_DIS_MRM                         BIT_12  /* Disable Mem Read Multiple */
+#define PCI_DIS_MWI                         BIT_11  /* Disable Mem Write & Invalidate */
+#define PCI_DISC_CLS                        BIT_10  /* Disc: cacheLsz bound */
+#define PCI_BURST_DIS                       BIT_9  /* Burst Disable */
+#define PCI_DIS_PCI_CLK                     BIT_8  /* Disable PCI clock driving */
+#define PCI_SKEW_DAS                        (0xfL<<4)/* Bit  7.. 4:  Skew Ctrl, DAS Ext */
+#define PCI_SKEW_BASE                       0xfL  /* Bit  3.. 0:  Skew Ctrl, Base  */
+#define PCI_CLS_OPT                         BIT_3  /* Cache Line Size opt. PCI-X (YUKON-2) */



+/*  PCI_OUR_REG_2  32 bit  Our Register 2 */
+#define PCI_VPD_WR_THR                      (0xff<<24)  /* Bit 31..24:  VPD Write Threshold */
+#define PCI_DEV_SEL                         (0x7f<<17)  /* Bit 23..17:  EEPROM Device Select */
+#define PCI_VPD_ROM_SZ                      (0x07<<14)  /* Bit 16..14:  VPD ROM Size  */
+/* Bit 13..12:  reserved  */
+#define PCI_PATCH_DIR                       (0x0f<<8)  /* Bit 11.. 8:  Ext Patches dir 3..0 */
+#define PCI_PATCH_DIR_3                     BIT_11
+#define PCI_PATCH_DIR_2                     BIT_10
+#define PCI_PATCH_DIR_1                     BIT_9
+#define PCI_PATCH_DIR_0                     BIT_8
+#define PCI_EXT_PATCHS                      (0x0f<<4)  /* Bit  7.. 4:  Extended Patches 3..0 */
+#define PCI_EXT_PATCH_3                     BIT_7
+#define PCI_EXT_PATCH_2                     BIT_6
+#define PCI_EXT_PATCH_1                     BIT_5
+#define PCI_EXT_PATCH_0                     BIT_4
+#define PCI_EN_DUMMY_RD                     BIT_3    /* Enable Dummy Read */
+#define PCI_REV_DESC                        BIT_2    /* Reverse Desc. Bytes */
+#define PCI_USEDATA64                       BIT_0    /* Use 64Bit Data bus ext */



+/* PCI_OUR_STATUS  32 bit  Adapter Status Register (Yukon-2) */
+#define PCI_OS_PCI64B                       BIT_31    /* Conventional PCI 64 bits Bus */
+#define PCI_OS_PCIX                         BIT_30    /* PCI-X Bus */
+#define PCI_OS_MODE_MSK                     (3<<28)    /* Bit 29..28:  PCI-X Bus Mode Mask */
+#define PCI_OS_PCI66M                       BIT_27    /* PCI 66 MHz Bus */
+#define PCI_OS_PCI_X                        BIT_26    /* PCI/PCI-X Bus (0 = PEX) */
+#define PCI_OS_DLLE_MSK                     (3<<24)    /* Bit 25..24:  DLL Status Indication */
+#define PCI_OS_DLLR_MSK                     (0x0f<<20)  /* Bit 23..20:  DLL Row Counters Values */
+#define PCI_OS_DLLC_MSK                     (0x0f<<16)  /* Bit 19..16:  DLL Col. Counters Values */



+#define PCI_OS_SPEED(val)                   ((val & PCI_OS_MODE_MSK) >> 28)  /* PCI-X Speed */
+/* possible values for the speed field of the register */
+#define PCI_OS_SPD_PCI                      0  /* PCI Conventional Bus */
+#define PCI_OS_SPD_X66                      1  /* PCI-X 66MHz Bus */
+#define PCI_OS_SPD_X100                     2  /* PCI-X 100MHz Bus */
+#define PCI_OS_SPD_X133                     3  /* PCI-X 133MHz Bus */



+/* PCI_OUR_REG_4  32 bit  Our Register 4 (Yukon-ECU only) */
+#define  PCI_TIMER_VALUE_MSK                (0xff<<16)  /* Bit 23..16:  Timer Value Mask */
+#define  PCI_FORCE_ASPM_REQUEST             BIT_15  /* Force ASPM Request (A1 only) */
+#define  PCI_ASPM_GPHY_LINK_DOWN            BIT_14  /* GPHY Link Down (A1 only) */
+#define  PCI_ASPM_INT_FIFO_EMPTY            BIT_13  /* Internal FIFO Empty (A1 only) */
+#define  PCI_ASPM_CLKRUN_REQUEST            BIT_12  /* CLKRUN Request (A1 only) */
+#define  PCI_ASPM_FORCE_CLKREQ_ENA          BIT_4  /* Force CLKREQ Enable (A1b only) */
+#define  PCI_ASPM_CLKREQ_PAD_CTL            BIT_3  /* CLKREQ PAD Control (A1 only) */
+#define  PCI_ASPM_A1_MODE_SELECT            BIT_2  /* A1 Mode Select (A1 only) */
+#define  PCI_CLK_GATE_PEX_UNIT_ENA          BIT_1  /* Enable Gate PEX Unit Clock */
+#define  PCI_CLK_GATE_ROOT_COR_ENA          BIT_0  /* Enable Gate Root Core Clock */



+/* PCI_OUR_REG_5  32 bit  Our Register 5 (Yukon-ECU only) */
+/* Bit 31..27: for A3 & later */
+#define  PCI_CTL_DIV_CORE_CLK_ENA           BIT_31  /* Divide Core Clock Enable */
+#define  PCI_CTL_SRESET_VMAIN_AV            BIT_30  /* Soft Reset for Vmain_av De-Glitch */
+#define  PCI_CTL_BYPASS_VMAIN_AV            BIT_29  /* Bypass En. for Vmain_av De-Glitch */
+#define  PCI_CTL_TIM_VMAIN_AV1              BIT_28  /* Bit 28..27: Timer Vmain_av Mask */
+#define  PCI_CTL_TIM_VMAIN_AV0              BIT_27  /* Bit 28..27: Timer Vmain_av Mask */
+#define  PCI_CTL_TIM_VMAIN_AV_MSK           (BIT_28 | BIT_27)
+/* Bit 26..16: Release Clock on Event */
+#define  PCI_REL_PCIE_RST_DE_ASS            BIT_26  /* PCIe Reset De-Asserted */
+#define  PCI_REL_GPHY_REC_PACKET            BIT_25  /* GPHY Received Packet */
+#define  PCI_REL_INT_FIFO_N_EMPTY           BIT_24  /* Internal FIFO Not Empty */
+#define  PCI_REL_MAIN_PWR_AVAIL             BIT_23  /* Main Power Available */
+#define  PCI_REL_CLKRUN_REQ_REL             BIT_22  /* CLKRUN Request Release */
+#define  PCI_REL_PCIE_RESET_ASS             BIT_21  /* PCIe Reset Asserted */
+#define  PCI_REL_PME_ASSERTED               BIT_20  /* PME Asserted */
+#define  PCI_REL_PCIE_EXIT_L1_ST            BIT_19  /* PCIe Exit L1 State */
+#define  PCI_REL_LOADER_NOT_FIN             BIT_18  /* EPROM Loader Not Finished */
+#define  PCI_REL_PCIE_RX_EX_IDLE            BIT_17  /* PCIe Rx Exit Electrical Idle State */
+#define  PCI_REL_GPHY_LINK_UP               BIT_16  /* GPHY Link Up */
+/* Bit 10.. 0: Mask for Gate Clock */
+#define  PCI_GAT_PCIE_RST_ASSERTED          BIT_10  /* PCIe Reset Asserted */
+#define  PCI_GAT_GPHY_N_REC_PACKET          BIT_9  /* GPHY Not Received Packet */
+#define  PCI_GAT_INT_FIFO_EMPTY             BIT_8  /* Internal FIFO Empty */
+#define  PCI_GAT_MAIN_PWR_N_AVAIL           BIT_7  /* Main Power Not Available */
+#define  PCI_GAT_CLKRUN_REQ_REL             BIT_6  /* CLKRUN Not Requested */
+#define  PCI_GAT_PCIE_RESET_ASS             BIT_5  /* PCIe Reset Asserted */
+#define  PCI_GAT_PME_DE_ASSERTED            BIT_4  /* PME De-Asserted */
+#define  PCI_GAT_PCIE_ENTER_L1_ST           BIT_3  /* PCIe Enter L1 State */
+#define  PCI_GAT_LOADER_FINISHED            BIT_2  /* EPROM Loader Finished */
+#define  PCI_GAT_PCIE_RX_EL_IDLE            BIT_1  /* PCIe Rx Electrical Idle State */
+#define  PCI_GAT_GPHY_LINK_DOWN             BIT_0  /* GPHY Link Down */



+/* PCI_CFG_REG_1  32 bit  Config Register 1 */
+#define  PCI_CF1_DIS_REL_EVT_RST            BIT_24  /* Dis. Rel. Event during PCIE reset */
+/* Bit 23..21: Release Clock on Event */
+#define  PCI_CF1_REL_LDR_NOT_FIN            BIT_23  /* EEPROM Loader Not Finished */
+#define  PCI_CF1_REL_VMAIN_AVLBL            BIT_22  /* Vmain available */
+#define  PCI_CF1_REL_PCIE_RESET             BIT_21  /* PCI-E reset */
+/* Bit 20..18: Gate Clock       on Event */
+#define  PCI_CF1_GAT_LDR_NOT_FIN            BIT_20  /* EEPROM Loader Finished */
+#define  PCI_CF1_GAT_PCIE_RX_IDLE           BIT_19  /* PCI-E Rx Electrical idle */
+#define  PCI_CF1_GAT_PCIE_RESET             BIT_18  /* PCI-E Reset */
+#define  PCI_CF1_PRST_PHY_CLKREQ            BIT_17  /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
+#define  PCI_CF1_PCIE_RST_CLKREQ            BIT_16  /* Enable PCI-E rst generate CLKREQ */



+#define  PCI_CF1_ENA_CFG_LDR_DONE           BIT_8  /* Enable core level Config loader done */
+#define  PCI_CF1_ENA_TXBMU_RD_IDLE          BIT_1  /* Enable TX BMU Read  IDLE for ASPM */
+#define  PCI_CF1_ENA_TXBMU_WR_IDLE          BIT_0  /* Enable TX BMU Write IDLE for ASPM */



+/* PEX_DEV_CTRL  16 bit  PEX Device Control (Yukon-2) */
+#define PEX_DC_MAX_RRS_MSK                  (7<<12)  /* Bit 14..12:  Max. Read Request Size */
+#define PEX_DC_EN_NO_SNOOP                  BIT_11  /* Enable No Snoop */
+#define PEX_DC_EN_AUX_POW                   BIT_10  /* Enable AUX Power */
+#define PEX_DC_EN_PHANTOM                   BIT_9  /* Enable Phantom Functions */
+#define PEX_DC_EN_EXT_TAG                   BIT_8  /* Enable Extended Tag Field */
+#define PEX_DC_MAX_PLS_MSK                  (7<<5)  /* Bit  7.. 5:  Max. Payload Size Mask */
+#define PEX_DC_EN_REL_ORD                   BIT_4  /* Enable Relaxed Ordering */
+#define PEX_DC_EN_UNS_RQ_RP                 BIT_3  /* Enable Unsupported Request Reporting */
+#define PEX_DC_EN_FAT_ER_RP                 BIT_2  /* Enable Fatal Error Reporting */
+#define PEX_DC_EN_NFA_ER_RP                 BIT_1  /* Enable Non-Fatal Error Reporting */
+#define PEX_DC_EN_COR_ER_RP                 BIT_0  /* Enable Correctable Error Reporting */



+#define PEX_DC_MAX_RD_RQ_SIZE(x)            (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)



+/* PEX_LNK_STAT  16 bit  PEX Link Status (Yukon-2) */
+#define PEX_LS_SLOT_CLK_CFG                 BIT_12  /* Slot Clock Config */
+#define PEX_LS_LINK_TRAIN                   BIT_11  /* Link Training */
+#define PEX_LS_TRAIN_ERROR                  BIT_10  /* Training Error */
+#define PEX_LS_LINK_WI_MSK                  (0x3f<<4) /* Bit  9.. 4: Neg. Link Width Mask */
+#define PEX_LS_LINK_SP_MSK                  0x0f  /* Bit  3.. 0:  Link Speed Mask */



+/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
+#define PEX_UNSUP_REQ                       BIT_20    /* Unsupported Request Error */
+#define PEX_MALFOR_TLP                      BIT_18    /* Malformed TLP */
+#define  PEX_RX_OV                          BIT_17    /* Receiver Overflow (not supported) */
+#define PEX_UNEXP_COMP                      BIT_16    /* Unexpected Completion */
+#define PEX_COMP_TO                         BIT_14    /* Completion Timeout */
+#define PEX_FLOW_CTRL_P                     BIT_13    /* Flow Control Protocol Error */
+#define PEX_POIS_TLP                        BIT_12    /* Poisoned TLP */
+#define PEX_DATA_LINK_P                     BIT_4    /* Data Link Protocol Error */



+#define PEX_FATAL_ERRORS                    (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)



+/*  Control Register File (Address Map) */



+/*


Bank 0


*/

+#define B0_RAP                              0x0000  /*  8 bit Register Address Port */
+#define B0_CTST                             0x0004  /* 16 bit Control/Status register */
+#define B0_LED                              0x0006  /*  8 Bit LED register */
+#define B0_POWER_CTRL                       0x0007  /*  8 Bit Power Control reg (YUKON only) */
+#define B0_ISRC                             0x0008  /* 32 bit Interrupt Source Register */
+#define B0_IMSK                             0x000c  /* 32 bit Interrupt Mask Register */
+#define B0_HWE_ISRC                         0x0010  /* 32 bit HW Error Interrupt Src Reg */
+#define B0_HWE_IMSK                         0x0014  /* 32 bit HW Error Interrupt Mask Reg */
+#define B0_SP_ISRC                          0x0018  /* 32 bit Special Interrupt Source Reg 1 */



+/* Special ISR registers (Yukon-2 only) */
+#define B0_Y2_SP_ISRC2                      0x001c  /* 32 bit Special Interrupt Source Reg 2 */
+#define B0_Y2_SP_ISRC3                      0x0020  /* 32 bit Special Interrupt Source Reg 3 */
+#define B0_Y2_SP_EISR                       0x0024  /* 32 bit Enter ISR Reg */
+#define B0_Y2_SP_LISR                       0x0028  /* 32 bit Leave ISR Reg */
+#define B0_Y2_SP_ICR                        0x002c  /* 32 bit Interrupt Control Reg */



+/*


Bank 1




completely empty (this is the RAP Block window)





Note: if RAP = 1 this page is reserved


*/


+/*


Bank 2


*/

+/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
+#define B2_MAC_1                            0x0100  /* NA reg MAC Address 1 */
+#define B2_MAC_2                            0x0108  /* NA reg MAC Address 2 */
+#define B2_MAC_3                            0x0110  /* NA reg MAC Address 3 */
+#define B2_CONN_TYP                         0x0118  /*  8 bit Connector type */
+#define B2_PMD_TYP                          0x0119  /*  8 bit PMD type */
+#define B2_MAC_CFG                          0x011a  /*  8 bit MAC Configuration / Chip Revision */
+#define B2_CHIP_ID                          0x011b  /*  8 bit Chip Identification Number */
+#define B2_E_0                              0x011c  /*  8 bit EPROM Byte 0 (ext. SRAM size */
+#define B2_Y2_CLK_GATE                      0x011d  /*  8 bit Clock Gating (Yukon-2) */
+#define B2_Y2_HW_RES                        0x011e  /*  8 bit HW Resources (Yukon-2) */
+#define B2_E_3                              0x011f  /*  8 bit EPROM Byte 3 */
+#define B2_Y2_CLK_CTRL                      0x0120  /* 32 bit Core Clock Frequency Control */
+#define B2_TI_INI                           0x0130  /* 32 bit Timer Init Value */
+#define B2_TI_VAL                           0x0134  /* 32 bit Timer Value */
+#define B2_TI_CTRL                          0x0138  /*  8 bit Timer Control */
+#define B2_TI_TEST                          0x0139  /*  8 Bit Timer Test */
+#define B2_IRQM_INI                         0x0140  /* 32 bit IRQ Moderation Timer Init Reg.*/
+#define B2_IRQM_VAL                         0x0144  /* 32 bit IRQ Moderation Timer Value */
+#define B2_IRQM_CTRL                        0x0148  /*  8 bit IRQ Moderation Timer Control */
+#define B2_IRQM_TEST                        0x0149  /*  8 bit IRQ Moderation Timer Test */
+#define B2_IRQM_MSK                         0x014c  /* 32 bit IRQ Moderation Mask */
+#define B2_IRQM_HWE_MSK                     0x0150  /* 32 bit IRQ Moderation HW Error Mask */
+#define B2_TST_CTRL1                        0x0158  /*  8 bit Test Control Register 1 */
+#define B2_TST_CTRL2                        0x0159  /*  8 bit Test Control Register 2 */
+#define B2_GP_IO                            0x015c  /* 32 bit General Purpose I/O Register */
+#define B2_I2C_CTRL                         0x0160  /* 32 bit I2C HW Control Register */
+#define B2_I2C_DATA                         0x0164  /* 32 bit I2C HW Data Register */
+#define B2_I2C_IRQ                          0x0168  /* 32 bit I2C HW IRQ Register */
+#define B2_I2C_SW                           0x016c  /* 32 bit I2C SW Port Register */



+#define Y2_PEX_PHY_DATA                     0x0170  /* 16 bit PEX PHY Data Register */
+#define Y2_PEX_PHY_ADDR                     0x0172  /* 16 bit PEX PHY Address Register */



+/*


Bank 3


*/

+/* RAM Random Registers */
+#define B3_RAM_ADDR                         0x0180  /* 32 bit RAM Address, to read or write */
+#define B3_RAM_DATA_LO                      0x0184  /* 32 bit RAM Data Word (low dWord) */
+#define B3_RAM_DATA_HI                      0x0188  /* 32 bit RAM Data Word (high dWord) */



+#define SELECT_RAM_BUFFER(rb, addr)         (addr | (rb << 6))  /* Yukon-2 only */



+/* RAM Interface Registers */
+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
+/*


The HW-Spec. calls this registers Timeout Value 0..11. But this names are



not usable in SW. Please notice these are NOT real timeouts, these are



the number of qWords transferred continuously.


*/

+#define B3_RI_WTO_R1                        0x0190  /*  8 bit WR Timeout Queue R1 (TO0) */
+#define B3_RI_WTO_XA1                       0x0191  /*  8 bit WR Timeout Queue XA1 (TO1) */
+#define B3_RI_WTO_XS1                       0x0192  /*  8 bit WR Timeout Queue XS1 (TO2) */
+#define B3_RI_RTO_R1                        0x0193  /*  8 bit RD Timeout Queue R1 (TO3) */
+#define B3_RI_RTO_XA1                       0x0194  /*  8 bit RD Timeout Queue XA1 (TO4) */
+#define B3_RI_RTO_XS1                       0x0195  /*  8 bit RD Timeout Queue XS1 (TO5) */
+#define B3_RI_WTO_R2                        0x0196  /*  8 bit WR Timeout Queue R2 (TO6) */
+#define B3_RI_WTO_XA2                       0x0197  /*  8 bit WR Timeout Queue XA2 (TO7) */
+#define B3_RI_WTO_XS2                       0x0198  /*  8 bit WR Timeout Queue XS2 (TO8) */
+#define B3_RI_RTO_R2                        0x0199  /*  8 bit RD Timeout Queue R2 (TO9) */
+#define B3_RI_RTO_XA2                       0x019a  /*  8 bit RD Timeout Queue XA2 (TO10)*/
+#define B3_RI_RTO_XS2                       0x019b  /*  8 bit RD Timeout Queue XS2 (TO11)*/
+#define B3_RI_TO_VAL                        0x019c  /*  8 bit Current Timeout Count Val */
+#define B3_RI_CTRL                          0x01a0  /* 16 bit RAM Interface Control Register */
+#define B3_RI_TEST                          0x01a2  /*  8 bit RAM Interface Test Register */



+/*


Bank 4 - 5


*/

+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+#define TXA_ITI_INI                         0x0200  /* 32 bit Tx Arb Interval Timer Init Val*/
+#define TXA_ITI_VAL                         0x0204  /* 32 bit Tx Arb Interval Timer Value */
+#define TXA_LIM_INI                         0x0208  /* 32 bit Tx Arb Limit Counter Init Val */
+#define TXA_LIM_VAL                         0x020c  /* 32 bit Tx Arb Limit Counter Value */
+#define TXA_CTRL                            0x0210  /*  8 bit Tx Arbiter Control Register */
+#define TXA_TEST                            0x0211  /*  8 bit Tx Arbiter Test Register */
+#define TXA_STAT                            0x0212  /*  8 bit Tx Arbiter Status Register */



+#define MR_ADDR(Mac, Offs)                  (((Mac) << 7) + (Offs))



+/* RSS key registers for Yukon-2 Family */
+#define B4_RSS_KEY                          0x0220  /* 4x32 bit RSS Key register (Yukon-2) */
+/* RSS key register offsets */
+#define KEY_IDX_0                           0      /* offset for location of KEY 0 */
+#define KEY_IDX_1                           4      /* offset for location of KEY 1 */
+#define KEY_IDX_2                           8      /* offset for location of KEY 2 */
+#define KEY_IDX_3                           12    /* offset for location of KEY 3 */
+/* 0x0280 - 0x0292:  MAC 2 */
+#define RSS_KEY_ADDR(Port, KeyIndex)        ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))



+/*


Bank 8 - 15


*/

+/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
+#define B8_Q_REGS                           0x0400



+/* Queue Register Offsets, use Q_ADDR() to access */
+#define Q_D                                 0x00  /* 8*32  bit Current Descriptor */
+#define Q_DA_L                              0x20  /* 32 bit Current Descriptor Address Low dWord */
+#define Q_DONE                              0x24  /* 16 bit Done Index */
+#define Q_AC_L                              0x28  /* 32 bit Current Address Counter Low dWord */
+#define Q_AC_H                              0x2c  /* 32 bit Current Address Counter High dWord */
+#define Q_BC                                0x30  /* 32 bit Current Byte Counter */
+#define Q_CSR                               0x34  /* 32 bit BMU Control/Status Register */
+#define Q_F                                 0x38  /* 32 bit Flag Register */
+#define Q_T1                                0x3c  /* 32 bit Test Register 1 */
+#define Q_T1_TR                             0x3c  /*  8 bit Test Register 1 Transfer SM */
+#define Q_T1_WR                             0x3d  /*  8 bit Test Register 1 Write Descriptor SM */
+#define Q_T1_RD                             0x3e  /*  8 bit Test Register 1 Read Descriptor SM */
+#define Q_T1_SV                             0x3f  /*  8 bit Test Register 1 Supervisor SM */
+#define Q_WM                                0x40  /* 16 bit FIFO Watermark */
+#define Q_AL                                0x42  /*  8 bit FIFO Alignment */
+#define Q_RSP                               0x44  /* 16 bit FIFO Read Shadow Pointer */
+#define Q_RSL                               0x46  /*  8 bit FIFO Read Shadow Level */
+#define Q_RP                                0x48  /*  8 bit FIFO Read Pointer */
+#define Q_RL                                0x4a  /*  8 bit FIFO Read Level */
+#define Q_WP                                0x4c  /*  8 bit FIFO Write Pointer */
+#define Q_WSP                               0x4d  /*  8 bit FIFO Write Shadow Pointer */
+#define Q_WL                                0x4e  /*  8 bit FIFO Write Level */
+#define Q_WSL                               0x4f  /*  8 bit FIFO Write Shadow Level */



+#define Q_ADDR(Queue, Offs)                 (B8_Q_REGS + (Queue) + (Offs))



+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */
+#define Y2_B8_PREF_REGS                     0x0450



+#define PREF_UNIT_CTRL_REG                  0x00  /* 32 bit Prefetch Control register */
+#define PREF_UNIT_LAST_IDX_REG              0x04  /* 16 bit Last Index */
+#define PREF_UNIT_ADDR_LOW_REG              0x08  /* 32 bit List start addr, low part */
+#define PREF_UNIT_ADDR_HI_REG               0x0c  /* 32 bit List start addr, high part*/
+#define PREF_UNIT_GET_IDX_REG               0x10  /* 16 bit Get Index */
+#define PREF_UNIT_PUT_IDX_REG               0x14  /* 16 bit Put Index */
+#define PREF_UNIT_FIFO_WP_REG               0x20  /*  8 bit FIFO write pointer */
+#define PREF_UNIT_FIFO_RP_REG               0x24  /*  8 bit FIFO read pointer */
+#define PREF_UNIT_FIFO_WM_REG               0x28  /*  8 bit FIFO watermark */
+#define PREF_UNIT_FIFO_LEV_REG              0x2c  /*  8 bit FIFO level */



+#define PREF_UNIT_MASK_IDX                  0x0fff



+#define Y2_PREF_Q_ADDR(Queue, Offs)         (Y2_B8_PREF_REGS + (Queue) + (Offs))



+/*


Bank 16 - 23


*/

+/* RAM Buffer Registers */
+#define B16_RAM_REGS                        0x0800



+/* RAM Buffer Register Offsets, use RB_ADDR() to access */
+#define RB_START                            0x00  /* 32 bit RAM Buffer Start Address */
+#define RB_END                              0x04  /* 32 bit RAM Buffer End Address */
+#define RB_WP                               0x08  /* 32 bit RAM Buffer Write Pointer */
+#define RB_RP                               0x0c  /* 32 bit RAM Buffer Read Pointer */
+#define RB_RX_UTPP                          0x10  /* 32 bit Rx Upper Threshold, Pause Packet */
+#define RB_RX_LTPP                          0x14  /* 32 bit Rx Lower Threshold, Pause Packet */
+#define RB_RX_UTHP                          0x18  /* 32 bit Rx Upper Threshold, High Prio */
+#define RB_RX_LTHP                          0x1c  /* 32 bit Rx Lower Threshold, High Prio */
+#define RB_PC                               0x20  /* 32 bit RAM Buffer Packet Counter */
+#define RB_LEV                              0x24  /* 32 bit RAM Buffer Level Register */
+#define RB_CTRL                             0x28  /*  8 bit RAM Buffer Control Register */
+#define RB_TST1                             0x29  /*  8 bit RAM Buffer Test Register 1 */
+#define RB_TST2                             0x2a  /*  8 bit RAM Buffer Test Register 2 */



+/*


Bank 24


*/

+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define RX_GMF_EA                           0x0c40  /* 32 bit Rx GMAC FIFO End Address */
+#define RX_GMF_AF_THR                       0x0c44  /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
+#define RX_GMF_CTRL_T                       0x0c48  /* 32 bit Rx GMAC FIFO Control/Test */
+#define RX_GMF_FL_MSK                       0x0c4c  /* 32 bit Rx GMAC FIFO Flush Mask */
+#define RX_GMF_FL_THR                       0x0c50  /* 32 bit Rx GMAC FIFO Flush Threshold */
+#define RX_GMF_TR_THR                       0x0c54  /* 32 bit Rx Truncation Threshold (Yukon-2) */
+#define  RX_GMF_UP_THR                      0x0c58  /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
+#define  RX_GMF_LP_THR                      0x0c5a  /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
+#define RX_GMF_VLAN                         0x0c5c  /* 32 bit Rx VLAN Type Register (Yukon-2) */
+#define RX_GMF_WP                           0x0c60  /* 32 bit Rx GMAC FIFO Write Pointer */
+#define RX_GMF_WLEV                         0x0c68  /* 32 bit Rx GMAC FIFO Write Level */
+#define RX_GMF_RP                           0x0c70  /* 32 bit Rx GMAC FIFO Read Pointer */
+#define RX_GMF_RLEV                         0x0c78  /* 32 bit Rx GMAC FIFO Read Level */



+/*


Bank 25


*/

+/* 0x0c80 - 0x0cbf:  MAC 2 */
+/* 0x0cc0 - 0x0cff:  reserved */



+/*


Bank 26


*/

+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define TX_GMF_EA                           0x0d40  /* 32 bit Tx GMAC FIFO End Address */
+#define TX_GMF_AE_THR                       0x0d44  /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
+#define TX_GMF_CTRL_T                       0x0d48  /* 32 bit Tx GMAC FIFO Control/Test */
+#define TX_GMF_VLAN                         0x0d5c  /* 32 bit Tx VLAN Type Register (Yukon-2) */
+#define TX_GMF_WP                           0x0d60  /* 32 bit Tx GMAC FIFO Write Pointer */
+#define TX_GMF_WSP                          0x0d64  /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
+#define TX_GMF_WLEV                         0x0d68  /* 32 bit Tx GMAC FIFO Write Level */
+#define TX_GMF_RP                           0x0d70  /* 32 bit Tx GMAC FIFO Read Pointer */
+#define TX_GMF_RSTP                         0x0d74  /* 32 bit Tx GMAC FIFO Restart Pointer */
+#define TX_GMF_RLEV                         0x0d78  /* 32 bit Tx GMAC FIFO Read Level */



+/*


Bank 27


*/

+/* 0x0d80 - 0x0dbf:  MAC 2 */
+/* 0x0daa - 0x0dff:  reserved */



+/*


Bank 28


*/

+/* Descriptor Poll Timer Registers */
+#define B28_DPT_INI                         0x0e00  /* 24 bit Descriptor Poll Timer Init Val */
+#define B28_DPT_VAL                         0x0e04  /* 24 bit Descriptor Poll Timer Curr Val */
+#define B28_DPT_CTRL                        0x0e08  /*  8 bit Descriptor Poll Timer Ctrl Reg */
+#define B28_DPT_TST                         0x0e0a  /*  8 bit Descriptor Poll Timer Test Reg */
+/* Time Stamp Timer Registers (YUKON only) */
+#define GMAC_TI_ST_VAL                      0x0e14  /* 32 bit Time Stamp Timer Curr Val */
+#define GMAC_TI_ST_CTRL                     0x0e18  /*  8 bit Time Stamp Timer Ctrl Reg */
+#define GMAC_TI_ST_TST                      0x0e1a  /*  8 bit Time Stamp Timer Test Reg */
+/* Polling Unit Registers (Yukon-2 only) */
+#define POLL_CTRL                           0x0e20  /* 32 bit Polling Unit Control Reg */
+#define POLL_LAST_IDX                       0x0e24  /* 16 bit Polling Unit List Last Index */
+#define POLL_LIST_ADDR_LO                   0x0e28  /* 32 bit Poll. List Start Addr (low) */
+#define POLL_LIST_ADDR_HI                   0x0e2c  /* 32 bit Poll. List Start Addr (high) */
+/* ASF Subsystem Registers (Yukon-2 only) */
+#define B28_Y2_SMB_CONFIG                   0x0e40  /* 32 bit ASF SMBus Config Register */
+#define B28_Y2_SMB_CSD_REG                  0x0e44  /* 32 bit ASF SMB Control/Status/Data */
+#define B28_Y2_ASF_IRQ_V_BASE               0x0e60  /* 32 bit ASF IRQ Vector Base */
+#define B28_Y2_ASF_STAT_CMD                 0x0e68  /* 32 bit ASF Status and Command Reg */
+#define B28_Y2_ASF_HCU_CCSR                 0x0e68  /* 32 bit ASF HCU CCSR (Yukon EX) */
+#define B28_Y2_ASF_HOST_COM                 0x0e6c  /* 32 bit ASF Host Communication Reg */
+#define B28_Y2_DATA_REG_1                   0x0e70  /* 32 bit ASF/Host Data Register 1 */
+#define B28_Y2_DATA_REG_2                   0x0e74  /* 32 bit ASF/Host Data Register 2 */
+#define B28_Y2_DATA_REG_3                   0x0e78  /* 32 bit ASF/Host Data Register 3 */
+#define B28_Y2_DATA_REG_4                   0x0e7c  /* 32 bit ASF/Host Data Register 4 */



+/*


Bank 29


*/


+/* Status BMU Registers (Yukon-2 only)*/
+#define STAT_CTRL                           0x0e80  /* 32 bit Status BMU Control Reg */
+#define STAT_LAST_IDX                       0x0e84  /* 16 bit Status BMU Last Index */
+#define STAT_LIST_ADDR_LO                   0x0e88  /* 32 bit Status List Start Addr (low) */
+#define STAT_LIST_ADDR_HI                   0x0e8c  /* 32 bit Status List Start Addr (high) */
+#define STAT_TXA1_RIDX                      0x0e90  /* 16 bit Status TxA1 Report Index Reg */
+#define STAT_TXS1_RIDX                      0x0e92  /* 16 bit Status TxS1 Report Index Reg */
+#define STAT_TXA2_RIDX                      0x0e94  /* 16 bit Status TxA2 Report Index Reg */
+#define STAT_TXS2_RIDX                      0x0e96  /* 16 bit Status TxS2 Report Index Reg */
+#define STAT_TX_IDX_TH                      0x0e98  /* 16 bit Status Tx Index Threshold Reg */
+#define STAT_PUT_IDX                        0x0e9c  /* 16 bit Status Put Index Reg */
+/* FIFO Control/Status Registers (Yukon-2 only)*/
+#define STAT_FIFO_WP                        0x0ea0  /*  8 bit Status FIFO Write Pointer Reg */
+#define STAT_FIFO_RP                        0x0ea4  /*  8 bit Status FIFO Read Pointer Reg */
+#define STAT_FIFO_RSP                       0x0ea6  /*  8 bit Status FIFO Read Shadow Ptr */
+#define STAT_FIFO_LEVEL                     0x0ea8  /*  8 bit Status FIFO Level Reg */
+#define STAT_FIFO_SHLVL                     0x0eaa  /*  8 bit Status FIFO Shadow Level Reg */
+#define STAT_FIFO_WM                        0x0eac  /*  8 bit Status FIFO Watermark Reg */
+#define STAT_FIFO_ISR_WM                    0x0ead  /*  8 bit Status FIFO ISR Watermark Reg */
+/* Level and ISR Timer Registers (Yukon-2 only)*/
+#define STAT_LEV_TIMER_INI                  0x0eb0  /* 32 bit Level Timer Init. Value Reg */
+#define STAT_LEV_TIMER_CNT                  0x0eb4  /* 32 bit Level Timer Counter Reg */
+#define STAT_LEV_TIMER_CTRL                 0x0eb8  /*  8 bit Level Timer Control Reg */
+#define STAT_LEV_TIMER_TEST                 0x0eb9  /*  8 bit Level Timer Test Reg */
+#define STAT_TX_TIMER_INI                   0x0ec0  /* 32 bit Tx Timer Init. Value Reg */
+#define STAT_TX_TIMER_CNT                   0x0ec4  /* 32 bit Tx Timer Counter Reg */
+#define STAT_TX_TIMER_CTRL                  0x0ec8  /*  8 bit Tx Timer Control Reg */
+#define STAT_TX_TIMER_TEST                  0x0ec9  /*  8 bit Tx Timer Test Reg */
+#define STAT_ISR_TIMER_INI                  0x0ed0  /* 32 bit ISR Timer Init. Value Reg */
+#define STAT_ISR_TIMER_CNT                  0x0ed4  /* 32 bit ISR Timer Counter Reg */
+#define STAT_ISR_TIMER_CTRL                 0x0ed8  /*  8 bit ISR Timer Control Reg */
+#define STAT_ISR_TIMER_TEST                 0x0ed9  /*  8 bit ISR Timer Test Reg */



+#define  ST_LAST_IDX_MASK                   0x007f  /* Last Index Mask */
+#define  ST_TXRP_IDX_MASK                   0x0fff  /* Tx Report Index Mask */
+#define  ST_TXTH_IDX_MASK                   0x0fff  /* Tx Threshold Index Mask */
+#define  ST_WM_IDX_MASK                     0x3f    /* FIFO Watermark Index Mask */



+/*


Bank 30


*/

+/* GMAC and GPHY Control Registers (YUKON only) */
+#define GMAC_CTRL                           0x0f00  /* 32 bit GMAC Control Reg */
+#define GPHY_CTRL                           0x0f04  /* 32 bit GPHY Control Reg */
+#define GMAC_IRQ_SRC                        0x0f08  /*  8 bit GMAC Interrupt Source Reg */
+#define GMAC_IRQ_MSK                        0x0f0c  /*  8 bit GMAC Interrupt Mask Reg */
+#define GMAC_LINK_CTRL                      0x0f10  /* 16 bit Link Control Reg */



+/* Wake-up Frame Pattern Match Control Registers (YUKON only) */



+#define WOL_REG_OFFS                        0x20  /* HW-Bug: Address is + 0x20 against spec. */



+#define WOL_CTRL_STAT                       0x0f20  /* 16 bit WOL Control/Status Reg */
+#define WOL_MATCH_CTL                       0x0f22  /*  8 bit WOL Match Control Reg */
+#define WOL_MATCH_RES                       0x0f23  /*  8 bit WOL Match Result Reg */
+#define WOL_MAC_ADDR_LO                     0x0f24  /* 32 bit WOL MAC Address Low */
+#define WOL_MAC_ADDR_HI                     0x0f28  /* 16 bit WOL MAC Address High */
+#define WOL_PATT_PME                        0x0f2a  /*  8 bit WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_ASFM                       0x0f2b  /*  8 bit WOL ASF Match Enable (Yukon-2) */
+#define WOL_PATT_RPTR                       0x0f2c  /*  8 bit WOL Pattern Read Pointer */



+/* WOL Pattern Length Registers (YUKON only) */



+#define WOL_PATT_LEN_LO                     0x0f30  /* 32 bit WOL Pattern Length 3..0 */
+#define WOL_PATT_LEN_HI                     0x0f34  /* 24 bit WOL Pattern Length 6..4 */



+/* WOL Pattern Counter Registers (YUKON only) */



+#define WOL_PATT_CNT_0                      0x0f38  /* 32 bit WOL Pattern Counter 3..0 */
+#define WOL_PATT_CNT_4                      0x0f3c  /* 24 bit WOL Pattern Counter 6..4 */



+/*


Bank 32  - 33


*/

+#define WOL_PATT_RAM_1                      0x1000  /*  WOL Pattern RAM Link 1 */
+#define WOL_PATT_RAM_2                      0x1400  /*  WOL Pattern RAM Link 2 */



+/* offset to configuration space on Yukon-2 */
+#define Y2_CFG_SPC                          0x1c00
+#define BASE_GMAC_1                         0x2800  /* GMAC 1 registers */
+#define BASE_GMAC_2                         0x3800  /* GMAC 2 registers */



+/*


Control Register Bit Definitions:


*/

+/*  B0_CTST  24 bit  Control/Status register */
+#define Y2_VMAIN_AVAIL                      BIT_17  /* VMAIN available (YUKON-2 only) */
+#define Y2_VAUX_AVAIL                       BIT_16  /* VAUX available (YUKON-2 only) */
+#define  Y2_HW_WOL_ON                       BIT_15  /* HW WOL On  (Yukon-EC Ultra A1 only) */
+#define  Y2_HW_WOL_OFF                      BIT_14  /* HW WOL Off (Yukon-EC Ultra A1 only) */
+#define Y2_ASF_ENABLE                       BIT_13  /* ASF Unit Enable (YUKON-2 only) */
+#define Y2_ASF_DISABLE                      BIT_12  /* ASF Unit Disable (YUKON-2 only) */
+#define Y2_CLK_RUN_ENA                      BIT_11  /* CLK_RUN Enable  (YUKON-2 only) */
+#define Y2_CLK_RUN_DIS                      BIT_10  /* CLK_RUN Disable (YUKON-2 only) */
+#define Y2_LED_STAT_ON                      BIT_9  /* Status LED On  (YUKON-2 only) */
+#define Y2_LED_STAT_OFF                     BIT_8  /* Status LED Off (YUKON-2 only) */
+#define CS_ST_SW_IRQ                        BIT_7  /* Set IRQ SW Request */
+#define CS_CL_SW_IRQ                        BIT_6  /* Clear IRQ SW Request */
+#define CS_STOP_DONE                        BIT_5  /* Stop Master is finished */
+#define CS_STOP_MAST                        BIT_4  /* Command Bit to stop the master */
+#define CS_MRST_CLR                         BIT_3  /* Clear Master Reset */
+#define CS_MRST_SET                         BIT_2  /* Set   Master Reset */
+#define CS_RST_CLR                          BIT_1  /* Clear Software Reset  */
+#define CS_RST_SET                          BIT_0  /* Set   Software Reset  */
+#define Y_ULTRA_2_PLUG_IN_GO_EN             BIT_15



+#define LED_STAT_ON                         BIT_1  /* Status LED On  */
+#define LED_STAT_OFF                        BIT_0  /* Status LED Off  */



+/* B0_POWER_CTRL   8 Bit  Power Control reg (YUKON only) */
+#define PC_VAUX_ENA                         BIT_7  /* Switch VAUX Enable  */
+#define PC_VAUX_DIS                         BIT_6  /* Switch VAUX Disable */
+#define PC_VCC_ENA                          BIT_5  /* Switch VCC Enable  */
+#define PC_VCC_DIS                          BIT_4  /* Switch VCC Disable */
+#define PC_VAUX_ON                          BIT_3  /* Switch VAUX On  */
+#define PC_VAUX_OFF                         BIT_2  /* Switch VAUX Off */
+#define PC_VCC_ON                           BIT_1  /* Switch VCC On  */
+#define PC_VCC_OFF                          BIT_0  /* Switch VCC Off */



+/*  B0_ISRC    32 bit  Interrupt Source Register */
+/*  B0_IMSK    32 bit  Interrupt Mask Register */
+/*  B0_SP_ISRC  32 bit  Special Interrupt Source Reg */
+/*  B2_IRQM_MSK  32 bit  IRQ Moderation Mask */
+/*  B0_Y2_SP_ISRC2  32 bit  Special Interrupt Source Reg 2 */
+/*  B0_Y2_SP_ISRC3  32 bit  Special Interrupt Source Reg 3 */
+/*  B0_Y2_SP_EISR  32 bit  Enter ISR Reg */
+/*  B0_Y2_SP_LISR  32 bit  Leave ISR Reg */
+#define Y2_IS_PORT_MASK(Port, Mask)         ((Mask) << (Port*8))
+#define Y2_IS_HW_ERR                        BIT_31  /* Interrupt HW Error */
+#define Y2_IS_STAT_BMU                      BIT_30  /* Status BMU Interrupt */
+#define Y2_IS_ASF                           BIT_29  /* ASF subsystem Interrupt */
+#define Y2_IS_POLL_CHK                      BIT_27  /* Check IRQ from polling unit */
+#define Y2_IS_TWSI_RDY                      BIT_26  /* IRQ on end of TWSI Tx */
+#define Y2_IS_IRQ_SW                        BIT_25  /* SW forced IRQ  */
+#define Y2_IS_TIMINT                        BIT_24  /* IRQ from Timer  */
+#define Y2_IS_IRQ_PHY2                      BIT_12  /* Interrupt from PHY 2 */
+#define Y2_IS_IRQ_MAC2                      BIT_11  /* Interrupt from MAC 2 */
+#define Y2_IS_CHK_RX2                       BIT_10  /* Descriptor error Rx 2 */
+#define Y2_IS_CHK_TXS2                      BIT_9  /* Descriptor error TXS 2 */
+#define Y2_IS_CHK_TXA2                      BIT_8  /* Descriptor error TXA 2 */
+#define Y2_IS_PSM_ACK                       BIT_7  /* PSM Ack (Yukon Optima) */
+#define Y2_IS_PTP_TIST                      BIT_6  /* PTP TIme Stamp (Yukon Optima) */
+#define Y2_IS_PHY_QLNK                      BIT_5  /* PHY Quick Link (Yukon Optima) */
+#define Y2_IS_IRQ_PHY1                      BIT_4  /* Interrupt from PHY 1 */
+#define Y2_IS_IRQ_MAC1                      BIT_3  /* Interrupt from MAC 1 */
+#define Y2_IS_CHK_RX1                       BIT_2  /* Descriptor error Rx 1 */
+#define Y2_IS_CHK_TXS1                      BIT_1  /* Descriptor error TXS 1 */
+#define Y2_IS_CHK_TXA1                      BIT_0  /* Descriptor error TXA 1 */



+#define Y2_IS_L1_MASK                       0x0000001f  /* IRQ Mask for port 1 */



+#define Y2_IS_L2_MASK                       0x00001f00  /* IRQ Mask for port 2 */



+#define Y2_IS_ALL_MSK                       0xef001f1f  /* All Interrupt bits */



+#define  Y2_IS_PORT_A                       (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1)
+#define  Y2_IS_PORT_B                       (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2)



+/*  B0_HWE_ISRC  32 bit  HW Error Interrupt Src Reg */
+/*  B0_HWE_IMSK  32 bit  HW Error Interrupt Mask Reg */
+/*  B2_IRQM_HWE_MSK  32 bit  IRQ Moderation HW Error Mask */
+#define Y2_IS_TIST_OV                       BIT_29  /* Time Stamp Timer overflow interrupt */
+#define Y2_IS_SENSOR                        BIT_28  /* Sensor interrupt */
+#define Y2_IS_MST_ERR                       BIT_27  /* Master error interrupt */
+#define Y2_IS_IRQ_STAT                      BIT_26  /* Status exception interrupt */
+#define Y2_IS_PCI_EXP                       BIT_25  /* PCI-Express interrupt */
+#define Y2_IS_PCI_NEXP                      BIT_24  /* PCI-Express error similar to PCI error */
+#define Y2_IS_PAR_RD2                       BIT_13  /* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR2                       BIT_12  /* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC2                      BIT_11  /* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX2                       BIT_10  /* Parity Error Rx Queue 2 */
+#define Y2_IS_TCP_TXS2                      BIT_9  /* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA2                      BIT_8  /* TCP length mismatch async Tx queue IRQ */
+#define Y2_IS_PAR_RD1                       BIT_5  /* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR1                       BIT_4  /* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC1                      BIT_3  /* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX1                       BIT_2  /* Parity Error Rx Queue 1 */
+#define Y2_IS_TCP_TXS1                      BIT_1  /* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA1                      BIT_0  /* TCP length mismatch async Tx queue IRQ */



+#define Y2_HWE_L1_MASK                      (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
+#define Y2_HWE_L2_MASK                      (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)



+#define Y2_HWE_ALL_MSK                      (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR  | Y2_IS_IRQ_STAT | \

Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP  |    Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)


+/*  B2_MAC_CFG   8 bit  MAC Configuration / Chip Revision */
+#define CFG_CHIP_R_MSK                      (0x0f<<4) /* Bit 7.. 4: Chip Revision */
+#define CFG_DIS_M2_CLK                      BIT_1  /* Disable Clock for 2nd MAC */
+#define CFG_SNG_MAC                         BIT_0  /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */



+/*  B2_CHIP_ID   8 bit  Chip Identification Number */
+#define CHIP_ID_GENESIS                     0x0a /* Chip ID for GENESIS */
+#define CHIP_ID_YUKON                       0xb0 /* Chip ID for YUKON */
+#define CHIP_ID_YUKON_LITE                  0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
+#define CHIP_ID_YUKON_LP                    0xb2 /* Chip ID for YUKON-LP */
+#define CHIP_ID_YUKON_XL                    0xb3 /* Chip ID for YUKON-2 XL */
+#define CHIP_ID_YUKON_EC_U                  0xb4 /* Chip ID for YUKON-2 EC Ultra */
+#define CHIP_ID_YUKON_EX                    0xb5 /* Chip ID for YUKON-2 Extreme */
+#define CHIP_ID_YUKON_EC                    0xb6 /* Chip ID for YUKON-2 EC */
+#define CHIP_ID_YUKON_FE                    0xb7 /* Chip ID for YUKON-2 FE */
+#define CHIP_ID_YUKON_FE_P                  0xb8 /* Chip ID for YUKON-2 FE+ */
+#define CHIP_ID_YUKON_SUPR                  0xb9 /* Chip ID for YUKON-2 Supreme */
+#define CHIP_ID_YUKON_UL_2                  0xba /* Chip ID for YUKON-2 Ultra 2 */
+#define CHIP_ID_YUKON_UNKNOWN               0xbb
+#define CHIP_ID_YUKON_OPT                   0xbc /* Chip ID for YUKON-2 Optima */



+#define  CHIP_REV_YU_XL_A0                  0 /* Chip Rev. for Yukon-2 A0 */
+#define  CHIP_REV_YU_XL_A1                  1 /* Chip Rev. for Yukon-2 A1 */
+#define  CHIP_REV_YU_XL_A2                  2 /* Chip Rev. for Yukon-2 A2 */
+#define  CHIP_REV_YU_XL_A3                  3 /* Chip Rev. for Yukon-2 A3 */



+#define CHIP_REV_YU_EC_A1                   0 /* Chip Rev. for Yukon-EC A1/A0 */
+#define CHIP_REV_YU_EC_A2                   1 /* Chip Rev. for Yukon-EC A2 */
+#define CHIP_REV_YU_EC_A3                   2 /* Chip Rev. for Yukon-EC A3 */



+#define  CHIP_REV_YU_EC_U_A0                1
+#define  CHIP_REV_YU_EC_U_A1                2



+#define  CHIP_REV_YU_FE_P_A0                0 /* Chip Rev. for Yukon-2 FE+ A0 */



+#define  CHIP_REV_YU_EX_A0                  1 /* Chip Rev. for Yukon-2 EX A0 */
+#define  CHIP_REV_YU_EX_B0                  2 /* Chip Rev. for Yukon-2 EX B0 */



+/*  B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
+#define Y2_STATUS_LNK2_INAC                 BIT_7  /* Status Link 2 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK2_DIS                 BIT_6  /* Disable clock gating Link 2 */
+#define Y2_COR_CLK_LNK2_DIS                 BIT_5  /* Disable Core clock Link 2 */
+#define Y2_PCI_CLK_LNK2_DIS                 BIT_4  /* Disable PCI clock Link 2 */
+#define Y2_STATUS_LNK1_INAC                 BIT_3  /* Status Link 1 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK1_DIS                 BIT_2  /* Disable clock gating Link 1 */
+#define Y2_COR_CLK_LNK1_DIS                 BIT_1  /* Disable Core clock Link 1 */
+#define Y2_PCI_CLK_LNK1_DIS                 BIT_0  /* Disable PCI clock Link 1 */



+/*  B2_Y2_HW_RES  8 bit  HW Resources (Yukon-2 only) */
+#define CFG_LED_MODE_MSK                    (0x07<<2)  /* Bit  4.. 2:  LED Mode Mask */
+#define CFG_LINK_2_AVAIL                    BIT_1  /* Link 2 available */
+#define CFG_LINK_1_AVAIL                    BIT_0  /* Link 1 available */



+#define CFG_LED_MODE(x)                     (((x) & CFG_LED_MODE_MSK) >> 2)
+#define CFG_DUAL_MAC_MSK                    (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)



+/*  B2_E_3     8 bit  lower 4 bits used for HW self test result */
+#define B2_E3_RES_MASK                      0x0f



+/*  B2_Y2_CLK_CTRL  32 bit  Core Clock Frequency Control Register (Yukon-2/EC) */
+/* Yukon-EC/FE */
+#define Y2_CLK_DIV_VAL_MSK                  (0xff<<16) /* Bit 23..16: Clock Divisor Value */
+#define Y2_CLK_DIV_VAL(x)                   (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
+/* Yukon-2 */
+#define Y2_CLK_DIV_VAL2_MSK                 (0x07<<21) /* Bit 23..21: Clock Divisor Value */
+#define Y2_CLK_SELECT2_MSK                  (0x1f<<16) /* Bit 20..16: Clock Select */
+#define Y2_CLK_DIV_VAL_2(x)                 (SHIFT21 (x) & Y2_CLK_DIV_VAL2_MSK)
+#define Y2_CLK_SEL_VAL_2(x)                 (SHIFT16 (x) & Y2_CLK_SELECT2_MSK)
+#define Y2_CLK_DIV_ENA                      BIT_1  /* Enable  Core Clock Division */
+#define Y2_CLK_DIV_DIS                      BIT_0  /* Disable Core Clock Division */



+/*  B2_TI_CTRL   8 bit  Timer control */
+/*  B2_IRQM_CTRL   8 bit  IRQ Moderation Timer Control */
+#define TIM_START                           BIT_2  /* Start Timer */
+#define TIM_STOP                            BIT_1  /* Stop  Timer */
+#define TIM_CLR_IRQ                         BIT_0  /* Clear Timer IRQ (!IRQM) */



+/*  B2_TI_TEST   8 Bit  Timer Test */
+/*  B2_IRQM_TEST   8 bit  IRQ Moderation Timer Test */
+/*  B28_DPT_TST   8 bit  Descriptor Poll Timer Test Reg */
+#define TIM_T_ON                            BIT_2  /* Test mode on */
+#define TIM_T_OFF                           BIT_1  /* Test mode off */
+#define TIM_T_STEP                          BIT_0  /* Test step */



+/*  B28_DPT_INI  32 bit  Descriptor Poll Timer Init Val */
+/*  B28_DPT_VAL  32 bit  Descriptor Poll Timer Curr Val */
+#define DPT_MSK                             0x00ffffff  /* Bit 23.. 0:  Desc Poll Timer Bits */



+/*  B28_DPT_CTRL   8 bit  Descriptor Poll Timer Ctrl Reg */
+#define DPT_START                           BIT_1  /* Start Descriptor Poll Timer */
+#define DPT_STOP                            BIT_0  /* Stop  Descriptor Poll Timer */



+/*  B2_TST_CTRL1   8 bit  Test Control Register 1 */
+#define TST_FRC_DPERR_MR                    BIT_7  /* force DATAPERR on MST RD */
+#define TST_FRC_DPERR_MW                    BIT_6  /* force DATAPERR on MST WR */
+#define TST_FRC_DPERR_TR                    BIT_5  /* force DATAPERR on TRG RD */
+#define TST_FRC_DPERR_TW                    BIT_4  /* force DATAPERR on TRG WR */
+#define TST_FRC_APERR_M                     BIT_3  /* force ADDRPERR on MST */
+#define TST_FRC_APERR_T                     BIT_2  /* force ADDRPERR on TRG */
+#define TST_CFG_WRITE_ON                    BIT_1  /* Enable  Config Reg WR */
+#define TST_CFG_WRITE_OFF                   BIT_0  /* Disable Config Reg WR */



+/*  B2_GP_IO */
+#define  GLB_GPIO_CLK_DEB_ENA               BIT_31  /* Clock Debug Enable */
+#define  GLB_GPIO_CLK_DBG_MSK               0x3c000000  /* Clock Debug */



+#define  GLB_GPIO_INT_RST_D3_DIS            BIT_15  /* Disable Internal Reset After D3 to D0 */
+#define  GLB_GPIO_LED_PAD_SPEED_UP          BIT_14  /* LED PAD Speed Up */
+#define  GLB_GPIO_STAT_RACE_DIS             BIT_13  /* Status Race Disable */
+#define  GLB_GPIO_TEST_SEL_MSK              0x00001800  /* Testmode Select */
+#define  GLB_GPIO_TEST_SEL_BASE             BIT_11
+#define  GLB_GPIO_RAND_ENA                  BIT_10  /* Random Enable */
+#define  GLB_GPIO_RAND_BIT_1                BIT_9  /* Random Bit 1 */



+/*  B2_I2C_CTRL  32 bit  I2C HW Control Register */
+#define I2C_FLAG                            BIT_31    /* Start read/write if WR */
+#define I2C_ADDR                            (0x7fff<<16)  /* Bit 30..16:  Addr to be RD/WR */
+#define I2C_DEV_SEL                         (0x7f<<9)  /* Bit 15.. 9:  I2C Device Select */
+#define I2C_BURST_LEN                       BIT_4    /* Burst Len, 1/4 bytes */
+#define I2C_DEV_SIZE                        (7<<1)    /* Bit  3.. 1:  I2C Device Size  */
+#define I2C_025K_DEV                        (0<<1)    /*    0: 256 Bytes or smal. */
+#define I2C_05K_DEV                         (1<<1)    /*     1: 512  Bytes  */
+#define I2C_1K_DEV                          (2<<1)    /*    2: 1024 Bytes  */
+#define I2C_2K_DEV                          (3<<1)    /*    3: 2048  Bytes  */
+#define I2C_4K_DEV                          (4<<1)    /*    4: 4096 Bytes  */
+#define I2C_8K_DEV                          (5<<1)    /*    5: 8192 Bytes  */
+#define I2C_16K_DEV                         (6<<1)    /*    6: 16384 Bytes  */
+#define I2C_32K_DEV                         (7<<1)    /*    7: 32768 Bytes  */
+#define I2C_STOP                            BIT_0    /* Interrupt I2C transfer */



+/*  B2_I2C_IRQ  32 bit  I2C HW IRQ Register */
+#define I2C_CLR_IRQ                         BIT_0    /* Clear I2C IRQ */



+/*  B2_I2C_SW  32 bit (8 bit access)  I2C HW SW Port Register */
+#define I2C_DATA_DIR                        BIT_2    /* direction of I2C_DATA */
+#define I2C_DATA                            BIT_1    /* I2C Data Port  */
+#define I2C_CLK                             BIT_0    /* I2C Clock Port  */



+/* I2C Address */
+#define I2C_SENS_ADDR                       LM80_ADDR  /* I2C Sensor Address (Volt and Temp) */




+/*  B2_BSC_CTRL   8 bit  Blink Source Counter Control */
+#define BSC_START                           BIT_1    /* Start Blink Source Counter */
+#define BSC_STOP                            BIT_0    /* Stop  Blink Source Counter */



+/*  B2_BSC_STAT   8 bit  Blink Source Counter Status */
+#define BSC_SRC                             BIT_0    /* Blink Source, 0=Off / 1=On */



+/*  B2_BSC_TST  16 bit  Blink Source Counter Test Reg */
+#define BSC_T_ON                            BIT_2    /* Test mode on */
+#define BSC_T_OFF                           BIT_1    /* Test mode off */
+#define BSC_T_STEP                          BIT_0    /* Test step */



+/*  Y2_PEX_PHY_ADDR/DATA  PEX PHY address and data reg  (Yukon-2 only) */
+#define PEX_RD_ACCESS                       BIT_31  /* Access Mode Read = 1, Write = 0 */
+#define PEX_DB_ACCESS                       BIT_30  /* Access to debug register */



+/*  B3_RAM_ADDR    32 bit  RAM Address, to read or write */
+#define RAM_ADR_RAN                         0x0007ffff  /* Bit 18.. 0:  RAM Address Range */



+/* RAM Interface Registers */
+/*  B3_RI_CTRL    16 bit  RAM Interface Control Register */
+#define RI_CLR_RD_PERR                      BIT_9  /* Clear IRQ RAM Read  Parity Err */
+#define RI_CLR_WR_PERR                      BIT_8  /* Clear IRQ RAM Write Parity Err */
+#define RI_RST_CLR                          BIT_1  /* Clear RAM Interface Reset */
+#define RI_RST_SET                          BIT_0  /* Set   RAM Interface Reset */



+#define  MSK_RI_TO_53                       36  /* RAM interface timeout */



+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+/*  TXA_ITI_INI  32 bit  Tx Arb Interval Timer Init Val */
+/*  TXA_ITI_VAL  32 bit  Tx Arb Interval Timer Value */
+/*  TXA_LIM_INI  32 bit  Tx Arb Limit Counter Init Val */
+/*  TXA_LIM_VAL  32 bit  Tx Arb Limit Counter Value */
+#define TXA_MAX_VAL                         0x00ffffff/* Bit 23.. 0:  Max TXA Timer/Cnt Val */



+/*  TXA_CTRL   8 bit  Tx Arbiter Control Register */
+#define TXA_ENA_FSYNC                       BIT_7  /* Enable  force of sync Tx queue */
+#define TXA_DIS_FSYNC                       BIT_6  /* Disable force of sync Tx queue */
+#define TXA_ENA_ALLOC                       BIT_5  /* Enable  alloc of free bandwidth */
+#define TXA_DIS_ALLOC                       BIT_4  /* Disable alloc of free bandwidth */
+#define TXA_START_RC                        BIT_3  /* Start sync Rate Control */
+#define TXA_STOP_RC                         BIT_2  /* Stop  sync Rate Control */
+#define TXA_ENA_ARB                         BIT_1  /* Enable  Tx Arbiter */
+#define TXA_DIS_ARB                         BIT_0  /* Disable Tx Arbiter */



+/*  TXA_TEST   8 bit  Tx Arbiter Test Register */
+#define TXA_INT_T_ON                        BIT_5  /* Tx Arb Interval Timer Test On */
+#define TXA_INT_T_OFF                       BIT_4  /* Tx Arb Interval Timer Test Off */
+#define TXA_INT_T_STEP                      BIT_3  /* Tx Arb Interval Timer Step */
+#define TXA_LIM_T_ON                        BIT_2  /* Tx Arb Limit Timer Test On */
+#define TXA_LIM_T_OFF                       BIT_1  /* Tx Arb Limit Timer Test Off */
+#define TXA_LIM_T_STEP                      BIT_0  /* Tx Arb Limit Timer Step */



+/*  TXA_STAT   8 bit  Tx Arbiter Status Register */
+#define TXA_PRIO_XS                         BIT_0  /* sync queue has prio to send */



+/*  Q_BC    32 bit  Current Byte Counter */
+#define BC_MAX                              0xffff  /* Bit 15.. 0:  Byte counter */



+/* Rx BMU Control / Status Registers (Yukon-2) */
+#define BMU_IDLE                            BIT_31  /* BMU Idle State */
+#define BMU_RX_TCP_PKT                      BIT_30  /* Rx TCP Packet (when RSS Hash enabled) */
+#define BMU_RX_IP_PKT                       BIT_29  /* Rx IP  Packet (when RSS Hash enabled) */
+#define BMU_ENA_RX_RSS_HASH                 BIT_15  /* Enable  Rx RSS Hash */
+#define BMU_DIS_RX_RSS_HASH                 BIT_14  /* Disable Rx RSS Hash */
+#define BMU_ENA_RX_CHKSUM                   BIT_13  /* Enable  Rx TCP/IP Checksum Check */
+#define BMU_DIS_RX_CHKSUM                   BIT_12  /* Disable Rx TCP/IP Checksum Check */
+#define BMU_CLR_IRQ_PAR                     BIT_11  /* Clear IRQ on Parity errors (Rx) */
+#define BMU_CLR_IRQ_TCP                     BIT_11  /* Clear IRQ on TCP segmen. error (Tx) */
+#define BMU_CLR_IRQ_CHK                     BIT_10  /* Clear IRQ Check */
+#define BMU_STOP                            BIT_9  /* Stop  Rx/Tx Queue */
+#define BMU_START                           BIT_8  /* Start Rx/Tx Queue */
+#define BMU_FIFO_OP_ON                      BIT_7  /* FIFO Operational On */
+#define BMU_FIFO_OP_OFF                     BIT_6  /* FIFO Operational Off */
+#define BMU_FIFO_ENA                        BIT_5  /* Enable FIFO */
+#define BMU_FIFO_RST                        BIT_4  /* Reset  FIFO */
+#define BMU_OP_ON                           BIT_3  /* BMU Operational On */
+#define BMU_OP_OFF                          BIT_2  /* BMU Operational Off */
+#define BMU_RST_CLR                         BIT_1  /* Clear BMU Reset (Enable) */
+#define BMU_RST_SET                         BIT_0  /* Set   BMU Reset */



+#define BMU_CLR_RESET                       (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
+#define BMU_OPER_INIT                       (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | BMU_FIFO_ENA | BMU_OP_ON)



+/* Tx BMU Control / Status Registers (Yukon-2) */
+/* Bit 31: same as for Rx */
+#define BMU_TX_IPIDINCR_ON                  BIT_13  /* Enable  IP ID Increment */
+#define BMU_TX_IPIDINCR_OFF                 BIT_12  /* Disable IP ID Increment */
+#define BMU_TX_CLR_IRQ_TCP                  BIT_11  /* Clear IRQ on TCP segm. length mism. */
+/* Bit 10..0: same as for Rx */



+/*  Q_F    32 bit  Flag Register */
+#define F_TX_CHK_AUTO_OFF                   BIT_31  /* Tx checksum auto-calc Off(Yukon EX)*/
+#define F_TX_CHK_AUTO_ON                    BIT_30  /* Tx checksum auto-calc On(Yukon EX)*/
+#define F_ALM_FULL                          BIT_28  /* Rx FIFO: almost full */
+#define F_EMPTY                             BIT_27  /* Tx FIFO: empty flag */
+#define F_FIFO_EOF                          BIT_26  /* Tag (EOF Flag) bit in FIFO */
+#define F_WM_REACHED                        BIT_25  /* Watermark reached */
+#define F_M_RX_RAM_DIS                      BIT_24  /* MAC Rx RAM Read Port disable */
+#define F_FIFO_LEVEL                        (0x1f<<16)
+/* Bit 23..16:  # of Qwords in FIFO */
+#define F_WATER_MARK                        0x0007ff/* Bit 10.. 0:  Watermark */



+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
+/* PREF_UNIT_CTRL_REG  32 bit  Prefetch Control register */
+#define PREF_UNIT_OP_ON                     BIT_3  /* prefetch unit operational */
+#define PREF_UNIT_OP_OFF                    BIT_2  /* prefetch unit not operational */
+#define PREF_UNIT_RST_CLR                   BIT_1  /* Clear Prefetch Unit Reset */
+#define PREF_UNIT_RST_SET                   BIT_0  /* Set   Prefetch Unit Reset */



+/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
+/*  RB_START  32 bit  RAM Buffer Start Address */
+/*  RB_END    32 bit  RAM Buffer End Address */
+/*  RB_WP    32 bit  RAM Buffer Write Pointer */
+/*  RB_RP    32 bit  RAM Buffer Read Pointer */
+/*  RB_RX_UTPP  32 bit  Rx Upper Threshold, Pause Pack */
+/*  RB_RX_LTPP  32 bit  Rx Lower Threshold, Pause Pack */
+/*  RB_RX_UTHP  32 bit  Rx Upper Threshold, High Prio */
+/*  RB_RX_LTHP  32 bit  Rx Lower Threshold, High Prio */
+/*  RB_PC    32 bit  RAM Buffer Packet Counter */
+/*  RB_LEV    32 bit  RAM Buffer Level Register */
+#define RB_MSK                              0x0007ffff  /* Bit 18.. 0:  RAM Buffer Pointer Bits */



+/*  RB_TST2     8 bit  RAM Buffer Test Register 2 */
+#define RB_PC_DEC                           BIT_3  /* Packet Counter Decrement */
+#define RB_PC_T_ON                          BIT_2  /* Packet Counter Test On */
+#define RB_PC_T_OFF                         BIT_1  /* Packet Counter Test Off */
+#define RB_PC_INC                           BIT_0  /* Packet Counter Increment */



+/*  RB_TST1     8 bit  RAM Buffer Test Register 1 */
+#define RB_WP_T_ON                          BIT_6  /* Write Pointer Test On */
+#define RB_WP_T_OFF                         BIT_5  /* Write Pointer Test Off */
+#define RB_WP_INC                           BIT_4  /* Write Pointer Increment */
+#define RB_RP_T_ON                          BIT_2  /* Read Pointer Test On */
+#define RB_RP_T_OFF                         BIT_1  /* Read Pointer Test Off */
+#define RB_RP_INC                           BIT_0  /* Read Pointer Increment */



+/*  RB_CTRL     8 bit  RAM Buffer Control Register */
+#define RB_ENA_STFWD                        BIT_5  /* Enable  Store & Forward */
+#define RB_DIS_STFWD                        BIT_4  /* Disable Store & Forward */
+#define RB_ENA_OP_MD                        BIT_3  /* Enable  Operation Mode */
+#define RB_DIS_OP_MD                        BIT_2  /* Disable Operation Mode */
+#define RB_RST_CLR                          BIT_1  /* Clear RAM Buf STM Reset */
+#define RB_RST_SET                          BIT_0  /* Set   RAM Buf STM Reset */



+/* RAM Buffer High Pause Threshold values */
+#define  MSK_RB_ULPP                          (8 * 1024)  /* Upper Level in kB/8 */
+#define  MSK_RB_LLPP_S                        (10 * 1024)  /* Lower Level for small Queues */
+#define  MSK_RB_LLPP_B                        (16 * 1024)  /* Lower Level for big Queues */



+/* Threshold values for Yukon-EC Ultra */
+#define  MSK_ECU_ULPP                       0x0080  /* Upper Pause Threshold (multiples of 8) */
+#define  MSK_ECU_LLPP                       0x0060  /* Lower Pause Threshold (multiples of 8) */
+#define  MSK_ECU_AE_THR                     0x0070  /* Almost Empty Threshold */
+#define  MSK_ECU_TXFF_LEV                   0x01a0  /* Tx BMU FIFO Level */
+#define  MSK_ECU_JUMBO_WM                   0x01



+#define MSK_BMU_RX_WM                       0x80  /* BMU Rx Watermark */
+#define MSK_BMU_TX_WM                       0x600  /* BMU Tx Watermark */
+/* performance sensitive drivers should set this define to 0x80 */
+#define MSK_BMU_RX_WM_PEX                   0x600  /* BMU Rx Watermark for PEX */



+/* Receive and Transmit Queues */
+#define Q_R1                                0x0000  /* Receive Queue 1 */
+#define Q_R2                                0x0080  /* Receive Queue 2 */
+#define Q_XS1                               0x0200  /* Synchronous Transmit Queue 1 */
+#define Q_XA1                               0x0280  /* Asynchronous Transmit Queue 1 */
+#define Q_XS2                               0x0300  /* Synchronous Transmit Queue 2 */
+#define Q_XA2                               0x0380  /* Asynchronous Transmit Queue 2 */



+#define Q_ASF_R1                            0x100  /* ASF Rx Queue 1 */
+#define Q_ASF_R2                            0x180  /* ASF Rx Queue 2 */
+#define Q_ASF_T1                            0x140  /* ASF Tx Queue 1 */
+#define Q_ASF_T2                            0x1c0  /* ASF Tx Queue 2 */



+#define RB_ADDR(Queue, Offs)                (B16_RAM_REGS + (Queue) + (Offs))



+/* Minimum RAM Buffer Rx Queue Size */
+#define  MSK_MIN_RXQ_SIZE                   10
+/* Minimum RAM Buffer Tx Queue Size */
+#define  MSK_MIN_TXQ_SIZE                   10
+/* Percentage of queue size from whole memory. 80 % for receive */
+#define  MSK_RAM_QUOTA_RX                   80



+/*  WOL_CTRL_STAT  16 bit  WOL Control/Status Reg */
+#define WOL_CTL_LINK_CHG_OCC                BIT_15
+#define WOL_CTL_MAGIC_PKT_OCC               BIT_14
+#define WOL_CTL_PATTERN_OCC                 BIT_13
+#define WOL_CTL_CLEAR_RESULT                BIT_12
+#define WOL_CTL_ENA_PME_ON_LINK_CHG         BIT_11
+#define WOL_CTL_DIS_PME_ON_LINK_CHG         BIT_10
+#define WOL_CTL_ENA_PME_ON_MAGIC_PKT        BIT_9
+#define WOL_CTL_DIS_PME_ON_MAGIC_PKT        BIT_8
+#define WOL_CTL_ENA_PME_ON_PATTERN          BIT_7
+#define WOL_CTL_DIS_PME_ON_PATTERN          BIT_6
+#define WOL_CTL_ENA_LINK_CHG_UNIT           BIT_5
+#define WOL_CTL_DIS_LINK_CHG_UNIT           BIT_4
+#define WOL_CTL_ENA_MAGIC_PKT_UNIT          BIT_3
+#define WOL_CTL_DIS_MAGIC_PKT_UNIT          BIT_2
+#define WOL_CTL_ENA_PATTERN_UNIT            BIT_1
+#define WOL_CTL_DIS_PATTERN_UNIT            BIT_0



+#define WOL_CTL_DEFAULT                     (WOL_CTL_DIS_PME_ON_LINK_CHG  |  WOL_CTL_DIS_PME_ON_PATTERN |  \

WOL_CTL_DIS_PME_ON_MAGIC_PKT |  WOL_CTL_DIS_LINK_CHG_UNIT  |  \
WOL_CTL_DIS_PATTERN_UNIT     | WOL_CTL_DIS_MAGIC_PKT_UNIT)


+/*  WOL_MATCH_CTL   8 bit  WOL Match Control Reg */
+#define WOL_CTL_PATT_ENA(x)                  (BIT_0 << (x))



+/*  WOL_PATT_PME  8 bit  WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_FORCE_PME                  BIT_7  /* Generates a PME */
+#define WOL_PATT_MATCH_PME_ALL              0x7f




+/*


Marvel-PHY Registers, indirect addressed over GMAC


*/

+#define PHY_MARV_CTRL                       0x00  /* 16 bit r/w  PHY Control Register */
+#define PHY_MARV_STAT                       0x01  /* 16 bit r/o  PHY Status Register */
+#define PHY_MARV_ID0                        0x02  /* 16 bit r/o  PHY ID0 Register */
+#define PHY_MARV_ID1                        0x03  /* 16 bit r/o  PHY ID1 Register */
+#define PHY_MARV_AUNE_ADV                   0x04  /* 16 bit r/w  Auto-Neg. Advertisement */
+#define PHY_MARV_AUNE_LP                    0x05  /* 16 bit r/o  Link Part Ability Reg */
+#define PHY_MARV_AUNE_EXP                   0x06  /* 16 bit r/o  Auto-Neg. Expansion Reg */
+#define PHY_MARV_NEPG                       0x07  /* 16 bit r/w  Next Page Register */
+#define PHY_MARV_NEPG_LP                    0x08  /* 16 bit r/o  Next Page Link Partner */
+/* Marvel-specific registers */
+#define PHY_MARV_1000T_CTRL                 0x09  /* 16 bit r/w  1000Base-T Control Reg */
+#define PHY_MARV_1000T_STAT                 0x0a  /* 16 bit r/o  1000Base-T Status Reg */
+/* 0x0b - 0x0e:    reserved */
+#define PHY_MARV_EXT_STAT                   0x0f  /* 16 bit r/o  Extended Status Reg */
+#define PHY_MARV_PHY_CTRL                   0x10  /* 16 bit r/w  PHY Specific Control Reg */
+#define PHY_MARV_PHY_STAT                   0x11  /* 16 bit r/o  PHY Specific Status Reg */
+#define PHY_MARV_INT_MASK                   0x12  /* 16 bit r/w  Interrupt Mask Reg */
+#define PHY_MARV_INT_STAT                   0x13  /* 16 bit r/o  Interrupt Status Reg */
+#define PHY_MARV_EXT_CTRL                   0x14  /* 16 bit r/w  Ext. PHY Specific Ctrl */
+#define PHY_MARV_RXE_CNT                    0x15  /* 16 bit r/w  Receive Error Counter */
+#define PHY_MARV_EXT_ADR                    0x16  /* 16 bit r/w  Ext. Ad. for Cable Diag. */
+#define PHY_MARV_PORT_IRQ                   0x17  /* 16 bit r/o  Port 0 IRQ (88E1111 only) */
+#define PHY_MARV_LED_CTRL                   0x18  /* 16 bit r/w  LED Control Reg */
+#define PHY_MARV_LED_OVER                   0x19  /* 16 bit r/w  Manual LED Override Reg */
+#define PHY_MARV_EXT_CTRL_2                 0x1a  /* 16 bit r/w  Ext. PHY Specific Ctrl 2 */
+#define PHY_MARV_EXT_P_STAT                 0x1b  /* 16 bit r/w  Ext. PHY Spec. Stat Reg */
+#define PHY_MARV_CABLE_DIAG                 0x1c  /* 16 bit r/o  Cable Diagnostic Reg */
+#define PHY_MARV_PAGE_ADDR                  0x1d  /* 16 bit r/w  Extended Page Address Reg */
+#define PHY_MARV_PAGE_DATA                  0x1e  /* 16 bit r/w  Extended Page Data Reg */



+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_MARV_FE_LED_PAR                 0x16  /* 16 bit r/w  LED Parallel Select Reg. */
+#define PHY_MARV_FE_LED_SER                 0x17  /* 16 bit r/w  LED Stream Select S. LED */
+#define PHY_MARV_FE_VCT_TX                  0x1a  /* 16 bit r/w  VCT Reg. for TXP/N Pins */
+#define PHY_MARV_FE_VCT_RX                  0x1b  /* 16 bit r/o  VCT Reg. for RXP/N Pins */
+#define PHY_MARV_FE_SPEC_2                  0x1c  /* 16 bit r/w  Specific Control Reg. 2 */



+#define PHY_CT_RESET                        (1<<15)  /* Bit 15: (sc)  clear all PHY related regs */
+#define PHY_CT_LOOP                         (1<<14)  /* Bit 14:  enable Loopback over PHY */
+#define PHY_CT_SPS_LSB                      (1<<13) /* Bit 13:  Speed select, lower bit */
+#define PHY_CT_ANE                          (1<<12)  /* Bit 12:  Auto-Negotiation Enabled */
+#define PHY_CT_PDOWN                        (1<<11)  /* Bit 11:  Power Down Mode */
+#define PHY_CT_ISOL                         (1<<10)  /* Bit 10:  Isolate Mode */
+#define PHY_CT_RE_CFG                       (1<<9)  /* Bit  9:  (sc) Restart Auto-Negotiation */
+#define PHY_CT_DUP_MD                       (1<<8)  /* Bit  8:  Duplex Mode */
+#define PHY_CT_COL_TST                      (1<<7)  /* Bit  7:  Collision Test enabled */
+#define PHY_CT_SPS_MSB                      (1<<6)  /* Bit  6:  Speed select, upper bit */



+#define PHY_CT_SP1000                       PHY_CT_SPS_MSB  /* enable speed of 1000 Mbps */
+#define PHY_CT_SP100                        PHY_CT_SPS_LSB  /* enable speed of  100 Mbps */
+#define PHY_CT_SP10                         (0)    /* enable speed of   10 Mbps */



+#define PHY_ST_EXT_ST                       (1<<8)  /* Bit  8:  Extended Status Present */
+#define PHY_ST_PRE_SUP                      (1<<6)  /* Bit  6:  Preamble Suppression */
+#define PHY_ST_AN_OVER                      (1<<5)  /* Bit  5:  Auto-Negotiation Over */
+#define PHY_ST_REM_FLT                      (1<<4)  /* Bit  4:  Remote Fault Condition Occured */
+#define PHY_ST_AN_CAP                       (1<<3)  /* Bit  3:  Auto-Negotiation Capability */
+#define PHY_ST_LSYNC                        (1<<2)  /* Bit  2:  Link Synchronized */
+#define PHY_ST_JAB_DET                      (1<<1)  /* Bit  1:  Jabber Detected */
+#define PHY_ST_EXT_REG                      (1<<0)  /* Bit  0:  Extended Register available */



+#define PHY_I1_OUI_MSK                      (0x3f<<10)  /* Bit 15..10:  Organization Unique ID */
+#define PHY_I1_MOD_NUM                      (0x3f<<4)  /* Bit  9.. 4:  Model Number */
+#define PHY_I1_REV_MSK                      0xf    /* Bit  3.. 0:  Revision Number */



+/* different Marvell PHY Ids */
+#define PHY_MARV_ID0_VAL                    0x0141  /* Marvell Unique Identifier */



+#define PHY_MARV_ID1_B0                     0x0C23  /* Yukon (PHY 88E1011) */
+#define PHY_MARV_ID1_B2                     0x0C25  /* Yukon-Plus (PHY 88E1011) */
+#define PHY_MARV_ID1_C2                     0x0CC2  /* Yukon-EC (PHY 88E1111) */
+#define PHY_MARV_ID1_Y2                     0x0C91  /* Yukon-2 (PHY 88E1112) */
+#define PHY_MARV_ID1_FE                     0x0C83  /* Yukon-FE (PHY 88E3082 Rev.A1) */
+#define PHY_MARV_ID1_ECU                    0x0CB0  /* Yukon-2 (PHY 88E1149 Rev.B2?) */



+/*****  PHY_MARV_1000T_STAT  16 bit r/o  1000Base-T Status Reg *****/
+#define PHY_B_1000S_MSF                     (1<<15)  /* Bit 15:  Master/Slave Fault */
+#define PHY_B_1000S_MSR                     (1<<14)  /* Bit 14:  Master/Slave Result */
+#define PHY_B_1000S_LRS                     (1<<13)  /* Bit 13:  Local Receiver Status */
+#define PHY_B_1000S_RRS                     (1<<12)  /* Bit 12:  Remote Receiver Status */
+#define PHY_B_1000S_LP_FD                   (1<<11)  /* Bit 11:  Link Partner can FD */
+#define PHY_B_1000S_LP_HD                   (1<<10)  /* Bit 10:  Link Partner can HD */
+#define PHY_B_1000S_IEC                     0xff  /* Bit  7..0:  Idle Error Count */



+/*****  PHY_MARV_AUNE_ADV  16 bit r/w  Auto-Negotiation Advertisement *****/
+/*****  PHY_MARV_AUNE_LP  16 bit r/w  Link Part Ability Reg *****/
+#define PHY_M_AN_NXT_PG                     BIT_15  /* Request Next Page */
+#define PHY_M_AN_ACK                        BIT_14  /* (ro)  Acknowledge Received */
+#define PHY_M_AN_RF                         BIT_13  /* Remote Fault */
+#define PHY_M_AN_ASP                        BIT_11  /* Asymmetric Pause */
+#define PHY_M_AN_PC                         BIT_10  /* MAC Pause implemented */
+#define PHY_M_AN_100_T4                     BIT_9  /* Not cap. 100Base-T4 (always 0) */
+#define PHY_M_AN_100_FD                     BIT_8  /* Advertise 100Base-TX Full Duplex */
+#define PHY_M_AN_100_HD                     BIT_7  /* Advertise 100Base-TX Half Duplex */
+#define PHY_M_AN_10_FD                      BIT_6  /* Advertise 10Base-TX Full Duplex */
+#define PHY_M_AN_10_HD                      BIT_5  /* Advertise 10Base-TX Half Duplex */
+#define PHY_M_AN_SEL_MSK                    (0x1f<<4)  /* Bit  4.. 0: Selector Field Mask */



+/* special defines for FIBER (88E1011S only) */
+#define PHY_M_AN_ASP_X                      BIT_8  /* Asymmetric Pause */
+#define PHY_M_AN_PC_X                       BIT_7  /* MAC Pause implemented */
+#define PHY_M_AN_1000X_AHD                  BIT_6  /* Advertise 10000Base-X Half Duplex */
+#define PHY_M_AN_1000X_AFD                  BIT_5  /* Advertise 10000Base-X Full Duplex */



+/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
+#define PHY_M_P_NO_PAUSE_X                  (0<<7)  /* Bit  8.. 7:  no Pause Mode */
+#define PHY_M_P_SYM_MD_X                    (1<<7)  /* Bit  8.. 7:  symmetric Pause Mode */
+#define PHY_M_P_ASYM_MD_X                   (2<<7)  /* Bit  8.. 7:  asymmetric Pause Mode */
+#define PHY_M_P_BOTH_MD_X                   (3<<7)  /* Bit  8.. 7:  both Pause Mode */



+/*****  PHY_MARV_1000T_CTRL  16 bit r/w  1000Base-T Control Reg *****/
+#define PHY_M_1000C_TEST                    (7<<13)  /* Bit 15..13:  Test Modes */
+#define PHY_M_1000C_MSE                     BIT_12  /* Manual Master/Slave Enable */
+#define PHY_M_1000C_MSC                     BIT_11  /* M/S Configuration (1=Master) */
+#define PHY_M_1000C_MPD                     BIT_10  /* Multi-Port Device */
+#define PHY_M_1000C_AFD                     BIT_9  /* Advertise Full Duplex */
+#define PHY_M_1000C_AHD                     BIT_8  /* Advertise Half Duplex */



+/*****  PHY_MARV_PHY_CTRL  16 bit r/w  PHY Specific Ctrl Reg *****/
+#define PHY_M_PC_TX_FFD_MSK                 (3<<14)  /* Bit 15..14: Tx FIFO Depth Mask */
+#define PHY_M_PC_RX_FFD_MSK                 (3<<12)  /* Bit 13..12: Rx FIFO Depth Mask */
+#define PHY_M_PC_ASS_CRS_TX                 BIT_11  /* Assert CRS on Transmit */
+#define PHY_M_PC_FL_GOOD                    BIT_10  /* Force Link Good */
+#define PHY_M_PC_EN_DET_MSK                 (3<<8)  /* Bit  9.. 8: Energy Detect Mask */
+#define PHY_M_PC_ENA_EXT_D                  BIT_7  /* Enable Ext. Distance (10BT) */
+#define PHY_M_PC_MDIX_MSK                   (3<<5)  /* Bit  6.. 5: MDI/MDIX Config. Mask */
+#define PHY_M_PC_DIS_125CLK                 BIT_4  /* Disable 125 CLK */
+#define PHY_M_PC_MAC_POW_UP                 BIT_3  /* MAC Power up */
+#define PHY_M_PC_SQE_T_ENA                  BIT_2  /* SQE Test Enabled */
+#define PHY_M_PC_POL_R_DIS                  BIT_1  /* Polarity Reversal Disabled */
+#define PHY_M_PC_DIS_JABBER                 BIT_0  /* Disable Jabber */



+#define PHY_M_PC_EN_DET                     SHIFT8(2)  /* Energy Detect (Mode 1) */
+#define PHY_M_PC_EN_DET_PLUS                SHIFT8(3)  /* Energy Detect Plus (Mode 2) */



+#define PHY_M_PC_MDI_XMODE(x)               (SHIFT5(x) & PHY_M_PC_MDIX_MSK)



+#define PHY_M_PC_MAN_MDI                    0  /* 00 = Manual MDI configuration */
+#define PHY_M_PC_MAN_MDIX                   1  /* 01 = Manual MDIX configuration */
+#define PHY_M_PC_ENA_AUTO                   3  /* 11 = Enable Automatic Crossover */



+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
+#define PHY_M_PC_DIS_LINK_P                 BIT_15  /* Disable Link Pulses */
+#define PHY_M_PC_DSC_MSK                    (7<<12)  /* Bit 14..12:  Downshift Counter */
+#define PHY_M_PC_DOWN_S_ENA                 BIT_11  /* Downshift Enable */
+/* !!! Errata in spec. (1 = disable) */



+#define PHY_M_PC_DSC(x)                     (SHIFT12(x) & PHY_M_PC_DSC_MSK)
+/* 000=1x; 001=2x; 010=3x; 011=4x */
+/* 100=5x; 101=6x; 110=7x; 111=8x */



+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PC_ENA_DTE_DT                 BIT_15  /* Enable Data Terminal Equ. (DTE) Detect */
+#define PHY_M_PC_ENA_ENE_DT                 BIT_14  /* Enable Energy Detect (sense & pulse) */
+#define PHY_M_PC_DIS_NLP_CK                 BIT_13  /* Disable Normal Link Puls (NLP) Check */
+#define PHY_M_PC_ENA_LIP_NP                 BIT_12  /* Enable Link Partner Next Page Reg. */
+#define PHY_M_PC_DIS_NLP_GN                 BIT_11  /* Disable Normal Link Puls Generation */
+#define PHY_M_PC_DIS_SCRAMB                 BIT_9  /* Disable Scrambler */
+#define PHY_M_PC_DIS_FEFI                   BIT_8  /* Disable Far End Fault Indic. (FEFI) */
+#define PHY_M_PC_SH_TP_SEL                  BIT_6  /* Shielded Twisted Pair Select */
+#define PHY_M_PC_RX_FD_MSK                  (3<<2)  /* Bit  3.. 2: Rx FIFO Depth Mask */



+/*****  PHY_MARV_PHY_STAT  16 bit r/o  PHY Specific Status Reg *****/
+#define PHY_M_PS_SPEED_MSK                  (3<<14)  /* Bit 15..14: Speed Mask */
+#define PHY_M_PS_SPEED_1000                 BIT_15  /*  10 = 1000 Mbps */
+#define PHY_M_PS_SPEED_100                  BIT_14  /*  01 =  100 Mbps */
+#define PHY_M_PS_SPEED_10                   0  /*  00 =   10 Mbps */
+#define PHY_M_PS_FULL_DUP                   BIT_13  /* Full Duplex */
+#define PHY_M_PS_PAGE_REC                   BIT_12  /* Page Received */
+#define PHY_M_PS_SPDUP_RES                  BIT_11  /* Speed & Duplex Resolved */
+#define PHY_M_PS_LINK_UP                    BIT_10  /* Link Up */
+#define PHY_M_PS_CABLE_MSK                  (7<<7)  /* Bit  9.. 7: Cable Length Mask */
+#define PHY_M_PS_MDI_X_STAT                 BIT_6  /* MDI Crossover Stat (1=MDIX) */
+#define PHY_M_PS_DOWNS_STAT                 BIT_5  /* Downshift Status (1=downsh.) */
+#define PHY_M_PS_ENDET_STAT                 BIT_4  /* Energy Detect Status (1=act) */
+#define PHY_M_PS_TX_P_EN                    BIT_3  /* Tx Pause Enabled */
+#define PHY_M_PS_RX_P_EN                    BIT_2  /* Rx Pause Enabled */
+#define PHY_M_PS_POL_REV                    BIT_1  /* Polarity Reversed */
+#define PHY_M_PS_JABBER                     BIT_0  /* Jabber */



+#define PHY_M_PS_PAUSE_MSK                  (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)



+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PS_DTE_DETECT                 BIT_15  /* Data Terminal Equipment (DTE) Detected */
+#define PHY_M_PS_RES_SPEED                  BIT_14  /* Resolved Speed (1=100 Mbps, 0=10 Mbps */



+/*****  PHY_MARV_INT_MASK  16 bit r/w  Interrupt Mask Reg *****/
+/*****  PHY_MARV_INT_STAT  16 bit r/o  Interrupt Status Reg *****/
+#define PHY_M_IS_AN_ERROR                   BIT_15  /* Auto-Negotiation Error */
+#define PHY_M_IS_LSP_CHANGE                 BIT_14  /* Link Speed Changed */
+#define PHY_M_IS_DUP_CHANGE                 BIT_13  /* Duplex Mode Changed */
+#define PHY_M_IS_AN_PR                      BIT_12  /* Page Received */
+#define PHY_M_IS_AN_COMPL                   BIT_11  /* Auto-Negotiation Completed */
+#define PHY_M_IS_LST_CHANGE                 BIT_10  /* Link Status Changed */
+#define PHY_M_IS_SYMB_ERROR                 BIT_9  /* Symbol Error */
+#define PHY_M_IS_FALSE_CARR                 BIT_8  /* False Carrier */
+#define PHY_M_IS_FIFO_ERROR                 BIT_7  /* FIFO Overflow/Underrun Error */
+#define PHY_M_IS_MDI_CHANGE                 BIT_6  /* MDI Crossover Changed */
+#define PHY_M_IS_DOWNSH_DET                 BIT_5  /* Downshift Detected */
+#define PHY_M_IS_END_CHANGE                 BIT_4  /* Energy Detect Changed */
+#define PHY_M_IS_DTE_CHANGE                 BIT_2  /* DTE Power Det. Status Changed */
+#define PHY_M_IS_POL_CHANGE                 BIT_1  /* Polarity Changed */
+#define PHY_M_IS_JABBER                     BIT_0  /* Jabber */



+#define PHY_M_DEF_MSK                       (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)



+/*****  PHY_MARV_EXT_CTRL  16 bit r/w  Ext. PHY Specific Ctrl *****/
+#define PHY_M_EC_ENA_BC_EXT                 BIT_15  /* Enable Block Carr. Ext. (88E1111 only) */
+#define PHY_M_EC_ENA_LIN_LB                 BIT_14  /* Enable Line Loopback (88E1111 only) */
+#define PHY_M_EC_DIS_LINK_P                 BIT_12  /* Disable Link Pulses (88E1111 only) */
+#define PHY_M_EC_M_DSC_MSK                  (3<<10)  /* Bit 11..10:  Master Downshift Counter */
+/* (88E1011 only) */
+#define PHY_M_EC_S_DSC_MSK                  (3<<8)  /* Bit  9.. 8:  Slave  Downshift Counter */
+/* (88E1011 only) */
+#define PHY_M_EC_DSC_MSK_2                  (7<<9)  /* Bit 11.. 9:  Downshift Counter */
+/* (88E1111 only) */
+#define PHY_M_EC_DOWN_S_ENA                 BIT_8  /* Downshift Enable (88E1111 only) */
+/* !!! Errata in spec. (1 = disable) */
+#define PHY_M_EC_RX_TIM_CT                  BIT_7  /* RGMII Rx Timing Control*/
+#define PHY_M_EC_MAC_S_MSK                  (7<<4)  /* Bit  6.. 4:  Def. MAC interface speed */
+#define PHY_M_EC_FIB_AN_ENA                 BIT_3  /* Fiber Auto-Neg. Enable (88E1011S only) */
+#define PHY_M_EC_DTE_D_ENA                  BIT_2  /* DTE Detect Enable (88E1111 only) */
+#define PHY_M_EC_TX_TIM_CT                  BIT_1  /* RGMII Tx Timing Control */
+#define PHY_M_EC_TRANS_DIS                  BIT_0  /* Transmitter Disable (88E1111 only) */



+#define PHY_M_EC_M_DSC(x)                    (SHIFT10 (x) & PHY_M_EC_M_DSC_MSK)
+/* 00=1x; 01=2x; 10=3x; 11=4x */
+#define PHY_M_EC_S_DSC(x)                   (SHIFT8 (x) & PHY_M_EC_S_DSC_MSK)
+/* 00=dis; 01=1x; 10=2x; 11=3x */
+#define PHY_M_EC_MAC_S(x)                   (SHIFT4 (x) & PHY_M_EC_MAC_S_MSK)
+/* 01X=0; 110=2.5; 111=25 (MHz) */



+#define PHY_M_EC_DSC_2(x)                   (SHIFT9 (x) & PHY_M_EC_DSC_MSK_2)
+/* 000=1x; 001=2x; 010=3x; 011=4x */
+/* 100=5x; 101=6x; 110=7x; 111=8x */
+#define MAC_TX_CLK_0_MHZ                    2
+#define MAC_TX_CLK_2_5_MHZ                  6
+#define MAC_TX_CLK_25_MHZ                   7



+/*****  PHY_MARV_LED_CTRL  16 bit r/w  LED Control Reg *****/
+#define PHY_M_LEDC_DIS_LED                  BIT_15  /* Disable LED */
+#define PHY_M_LEDC_PULS_MSK                 (7<<12)  /* Bit 14..12: Pulse Stretch Mask */
+#define PHY_M_LEDC_F_INT                    BIT_11  /* Force Interrupt */
+#define PHY_M_LEDC_BL_R_MSK                 (7<<8)  /* Bit 10.. 8: Blink Rate Mask */
+#define PHY_M_LEDC_DP_C_LSB                 BIT_7  /* Duplex Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_TX_C_LSB                 BIT_6  /* Tx Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_LK_C_MSK                 (7<<3)  /* Bit  5.. 3: Link Control Mask */
+/* (88E1111 only) */
+#define PHY_M_LEDC_LINK_MSK                 (3<<3)  /* Bit  4.. 3: Link Control Mask */
+/* (88E1011 only) */
+#define PHY_M_LEDC_DP_CTRL                  BIT_2  /* Duplex Control */
+#define PHY_M_LEDC_DP_C_MSB                 BIT_2  /* Duplex Control (MSB, 88E1111 only) */
+#define PHY_M_LEDC_RX_CTRL                  BIT_1  /* Rx Activity / Link */
+#define PHY_M_LEDC_TX_CTRL                  BIT_0  /* Tx Activity / Link */
+#define PHY_M_LEDC_TX_C_MSB                 BIT_0  /* Tx Control (MSB, 88E1111 only) */



+#define PHY_M_LED_PULS_DUR(x)               (SHIFT12 (x) & PHY_M_LEDC_PULS_MSK)



+#define PULS_NO_STR                         0  /* no pulse stretching */
+#define PULS_21MS                           1  /* 21 ms to 42 ms */
+#define PULS_42MS                           2  /* 42 ms to 84 ms */
+#define PULS_84MS                           3  /* 84 ms to 170 ms */
+#define PULS_170MS                          4  /* 170 ms to 340 ms */
+#define PULS_340MS                          5  /* 340 ms to 670 ms */
+#define PULS_670MS                          6  /* 670 ms to 1.3 s */
+#define PULS_1300MS                         7  /* 1.3 s to 2.7 s */



+#define PHY_M_LED_BLINK_RT(x)                (SHIFT8 (x) & PHY_M_LEDC_BL_R_MSK)



+#define BLINK_42MS                          0  /* 42 ms */
+#define BLINK_84MS                          1  /* 84 ms */
+#define BLINK_170MS                         2  /* 170 ms */
+#define BLINK_340MS                         3  /* 340 ms */
+#define BLINK_670MS                         4  /* 670 ms */



+/*****  PHY_MARV_LED_OVER  16 bit r/w  Manual LED Override Reg *****/
+#define PHY_M_LED_MO_SGMII(x)               SHIFT14 (x)  /* Bit 15..14:  SGMII AN Timer */
+#define PHY_M_LED_MO_DUP(x)                 SHIFT10 (x)  /* Bit 11..10:  Duplex */
+#define PHY_M_LED_MO_10(x)                  SHIFT8 (x)  /* Bit  9.. 8:  Link 10 */
+#define PHY_M_LED_MO_100(x)                 SHIFT6 (x)  /* Bit  7.. 6:  Link 100 */
+#define PHY_M_LED_MO_1000(x)                SHIFT4 (x)  /* Bit  5.. 4:  Link 1000 */
+#define PHY_M_LED_MO_RX(x)                  SHIFT2 (x)  /* Bit  3.. 2:  Rx */
+#define PHY_M_LED_MO_TX(x)                  SHIFT0 (x)  /* Bit  1.. 0:  Tx */



+#define MO_LED_NORM                         0
+#define MO_LED_BLINK                        1
+#define MO_LED_OFF                          2
+#define MO_LED_ON                           3



+/*****  PHY_MARV_EXT_CTRL_2  16 bit r/w  Ext. PHY Specific Ctrl 2 *****/
+#define PHY_M_EC2_FI_IMPED                  BIT_6  /* Fiber Input  Impedance */
+#define PHY_M_EC2_FO_IMPED                  BIT_5  /* Fiber Output Impedance */
+#define PHY_M_EC2_FO_M_CLK                  BIT_4  /* Fiber Mode Clock Enable */
+#define PHY_M_EC2_FO_BOOST                  BIT_3  /* Fiber Output Boost */
+#define PHY_M_EC2_FO_AM_MSK                  7  /* Bit  2.. 0:  Fiber Output Amplitude */



+/*****  PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
+#define PHY_M_FC_AUTO_SEL                   BIT_15  /* Fiber/Copper Auto Sel. Dis. */
+#define PHY_M_FC_AN_REG_ACC                 BIT_14  /* Fiber/Copper AN Reg. Access */
+#define PHY_M_FC_RESOLUTION                 BIT_13  /* Fiber/Copper Resolution */
+#define PHY_M_SER_IF_AN_BP                  BIT_12  /* Ser. IF AN Bypass Enable */
+#define PHY_M_SER_IF_BP_ST                  BIT_11  /* Ser. IF AN Bypass Status */
+#define PHY_M_IRQ_POLARITY                  BIT_10  /* IRQ polarity */
+#define PHY_M_DIS_AUT_MED                   BIT_9  /* Disable Aut. Medium Reg. Selection */
+/* (88E1111 only) */
+#define PHY_M_UNDOC1                        BIT_7  /* undocumented bit !! */
+#define PHY_M_DTE_POW_STAT                  BIT_4  /* DTE Power Status (88E1111 only) */
+#define PHY_M_MODE_MASK                     0xf  /* Bit  3.. 0: copy of HWCFG MODE[3:0] */



+/*****  PHY_MARV_CABLE_DIAG  16 bit r/o  Cable Diagnostic Reg *****/
+#define PHY_M_CABD_ENA_TEST                 BIT_15  /* Enable Test (Page 0) */
+#define PHY_M_CABD_DIS_WAIT                 BIT_15  /* Disable Waiting Period (Page 1) */
+/* (88E1111 only) */
+#define PHY_M_CABD_STAT_MSK                 (3<<13)    /* Bit 14..13: Status Mask */
+#define PHY_M_CABD_AMPL_MSK                 (0x1f<<8)  /* Bit 12.. 8: Amplitude Mask */
+/* (88E1111 only) */
+#define PHY_M_CABD_DIST_MSK                 0xff    /* Bit  7.. 0: Distance Mask */



+/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
+#define CABD_STAT_NORMAL                    0
+#define CABD_STAT_SHORT                     1
+#define CABD_STAT_OPEN                      2
+#define CABD_STAT_FAIL                      3



+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+/*****  PHY_MARV_FE_LED_PAR  16 bit r/w  LED Parallel Select Reg. *****/
+#define PHY_M_FELP_LED2_MSK                 (0xf<<8)  /* Bit 11.. 8: LED2 Mask (LINK) */
+#define PHY_M_FELP_LED1_MSK                 (0xf<<4)  /* Bit  7.. 4: LED1 Mask (ACT) */
+#define PHY_M_FELP_LED0_MSK                 0xf    /* Bit  3.. 0: LED0 Mask (SPEED) */



+#define PHY_M_FELP_LED2_CTRL(x)             (SHIFT8 (x) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x)             (SHIFT4 (x) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x)             (SHIFT0 (x) & PHY_M_FELP_LED0_MSK)



+#define LED_PAR_CTRL_COLX                   0x00
+#define LED_PAR_CTRL_ERROR                  0x01
+#define LED_PAR_CTRL_DUPLEX                 0x02
+#define LED_PAR_CTRL_DP_COL                 0x03
+#define LED_PAR_CTRL_SPEED                  0x04
+#define LED_PAR_CTRL_LINK                   0x05
+#define LED_PAR_CTRL_TX                     0x06
+#define LED_PAR_CTRL_RX                     0x07
+#define LED_PAR_CTRL_ACT                    0x08
+#define LED_PAR_CTRL_LNK_RX                 0x09
+#define LED_PAR_CTRL_LNK_AC                 0x0a
+#define LED_PAR_CTRL_ACT_BL                 0x0b
+#define LED_PAR_CTRL_TX_BL                  0x0c
+#define LED_PAR_CTRL_RX_BL                  0x0d
+#define LED_PAR_CTRL_COL_BL                 0x0e
+#define LED_PAR_CTRL_INACT                  0x0f



+/*****  PHY_MARV_FE_SPEC_2  16 bit r/w Specific Control Reg. 2 *****/
+#define PHY_M_FESC_DIS_WAIT                 BIT_2  /* Disable TDR Waiting Period */
+#define PHY_M_FESC_ENA_MCLK                 BIT_1  /* Enable MAC Rx Clock in sleep mode */
+#define PHY_M_FESC_SEL_CL_A                 BIT_0  /* Select Class A driver (100B-TX) */



+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
+/*****  PHY_MARV_PHY_CTRL (page 1)  16 bit r/w Fiber Specific Ctrl *****/
+#define PHY_M_FIB_FORCE_LNK                 BIT_10  /* Force Link Good */
+#define PHY_M_FIB_SIGD_POL                  BIT_9  /* SIGDET Polarity */
+#define PHY_M_FIB_TX_DIS                    BIT_3  /* Transmitter Disable */



+/*****  PHY_MARV_PHY_CTRL (page 2)  16 bit r/w MAC Specific Ctrl *****/
+#define PHY_M_MAC_MD_MSK                    (7<<7)  /* Bit  9.. 7: Mode Select Mask */
+#define PHY_M_MAC_MD_AUTO                   3  /* Auto Copper/1000Base-X */
+#define PHY_M_MAC_MD_COPPER                 5  /* Copper only */
+#define PHY_M_MAC_MD_1000BX                 7  /* 1000Base-X only */
+#define PHY_M_MAC_MODE_SEL(x)               (SHIFT7 (x) & PHY_M_MAC_MD_MSK)



+/*****  PHY_MARV_PHY_CTRL (page 3)  16 bit r/w LED Control Reg. *****/
+#define PHY_M_LEDC_LOS_MSK                  (0xf<<12)  /* Bit 15..12: LOS LED Ctrl. Mask */
+#define PHY_M_LEDC_INIT_MSK                 (0xf<<8)  /* Bit 11.. 8: INIT LED Ctrl. Mask */
+#define PHY_M_LEDC_STA1_MSK                 (0xf<<4)  /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
+#define PHY_M_LEDC_STA0_MSK                 0xf    /* Bit  3.. 0: STAT0 LED Ctrl. Mask */



+#define PHY_M_LEDC_LOS_CTRL(x)              (SHIFT12 (x) & PHY_M_LEDC_LOS_MSK)
+#define PHY_M_LEDC_INIT_CTRL(x)             (SHIFT8 (x) & PHY_M_LEDC_INIT_MSK)
+#define PHY_M_LEDC_STA1_CTRL(x)             (SHIFT4 (x) & PHY_M_LEDC_STA1_MSK)
+#define PHY_M_LEDC_STA0_CTRL(x)             (SHIFT0 (x) & PHY_M_LEDC_STA0_MSK)



+/*****  PHY_MARV_PHY_STAT (page 3)  16 bit r/w Polarity Control Reg. *****/
+#define PHY_M_POLC_LS1M_MSK                 (0xf<<12)  /* Bit 15..12: LOS,STAT1 Mix % Mask */
+#define PHY_M_POLC_IS0M_MSK                 (0xf<<8)  /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
+#define PHY_M_POLC_LOS_MSK                  (0x3<<6)  /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
+#define PHY_M_POLC_INIT_MSK                 (0x3<<4)  /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA1_MSK                 (0x3<<2)  /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA0_MSK                 0x3    /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */



+#define PHY_M_POLC_LS1_P_MIX(x)             (SHIFT12 (x) & PHY_M_POLC_LS1M_MSK)
+#define PHY_M_POLC_IS0_P_MIX(x)             (SHIFT8 (x) & PHY_M_POLC_IS0M_MSK)
+#define PHY_M_POLC_LOS_CTRL(x)              (SHIFT6 (x) & PHY_M_POLC_LOS_MSK)
+#define PHY_M_POLC_INIT_CTRL(x)             (SHIFT4 (x) & PHY_M_POLC_INIT_MSK)
+#define PHY_M_POLC_STA1_CTRL(x)             (SHIFT2 (x) & PHY_M_POLC_STA1_MSK)
+#define PHY_M_POLC_STA0_CTRL(x)             (SHIFT0 (x) & PHY_M_POLC_STA0_MSK)



+/*


GMAC registers







The GMAC registers are 16 or 32 bits wide.



The GMACs host processor interface is 16 bits wide,



therefore ALL registers will be addressed with 16 bit accesses.







Note:  NA reg  = Network Address e.g DA, SA etc.


*/


+/* Port Registers */
+#define GM_GP_STAT                          0x0000  /* 16 bit r/o  General Purpose Status */
+#define GM_GP_CTRL                          0x0004  /* 16 bit r/w  General Purpose Control */
+#define GM_TX_CTRL                          0x0008  /* 16 bit r/w  Transmit Control Reg. */
+#define GM_RX_CTRL                          0x000c  /* 16 bit r/w  Receive Control Reg. */
+#define GM_TX_FLOW_CTRL                     0x0010  /* 16 bit r/w  Transmit Flow-Control */
+#define GM_TX_PARAM                         0x0014  /* 16 bit r/w  Transmit Parameter Reg. */
+#define GM_SERIAL_MODE                      0x0018  /* 16 bit r/w  Serial Mode Register */



+/* Source Address Registers */
+#define GM_SRC_ADDR_1L                      0x001c  /* 16 bit r/w  Source Address 1 (low) */
+#define GM_SRC_ADDR_1M                      0x0020  /* 16 bit r/w  Source Address 1 (middle) */
+#define GM_SRC_ADDR_1H                      0x0024  /* 16 bit r/w  Source Address 1 (high) */
+#define GM_SRC_ADDR_2L                      0x0028  /* 16 bit r/w  Source Address 2 (low) */
+#define GM_SRC_ADDR_2M                      0x002c  /* 16 bit r/w  Source Address 2 (middle) */
+#define GM_SRC_ADDR_2H                      0x0030  /* 16 bit r/w  Source Address 2 (high) */



+/* Multicast Address Hash Registers */
+#define GM_MC_ADDR_H1                       0x0034  /* 16 bit r/w  Multicast Address Hash 1 */
+#define GM_MC_ADDR_H2                       0x0038  /* 16 bit r/w  Multicast Address Hash 2 */
+#define GM_MC_ADDR_H3                       0x003c  /* 16 bit r/w  Multicast Address Hash 3 */
+#define GM_MC_ADDR_H4                       0x0040  /* 16 bit r/w  Multicast Address Hash 4 */



+/* Interrupt Source Registers */
+#define GM_TX_IRQ_SRC                       0x0044  /* 16 bit r/o  Tx Overflow IRQ Source */
+#define GM_RX_IRQ_SRC                       0x0048  /* 16 bit r/o  Rx Overflow IRQ Source */
+#define GM_TR_IRQ_SRC                       0x004c  /* 16 bit r/o  Tx/Rx Over. IRQ Source */



+/* Interrupt Mask Registers */
+#define GM_TX_IRQ_MSK                       0x0050  /* 16 bit r/w  Tx Overflow IRQ Mask */
+#define GM_RX_IRQ_MSK                       0x0054  /* 16 bit r/w  Rx Overflow IRQ Mask */
+#define GM_TR_IRQ_MSK                       0x0058  /* 16 bit r/w  Tx/Rx Over. IRQ Mask */



+/* Serial Management Interface (SMI) Registers */
+#define GM_SMI_CTRL                         0x0080  /* 16 bit r/w  SMI Control Register */
+#define GM_SMI_DATA                         0x0084  /* 16 bit r/w  SMI Data Register */
+#define GM_PHY_ADDR                         0x0088  /* 16 bit r/w  GPHY Address Register */



+/* MIB Counters */
+#define GM_MIB_CNT_BASE                     0x0100  /* Base Address of MIB Counters */
+#define GM_MIB_CNT_SIZE                     44  /* Number of MIB Counters */



+/*


MIB Counters base address definitions (low word) -



use offset 4 for access to high word  (32 bit r/o)


*/

+#define GM_RXF_UC_OK                        (GM_MIB_CNT_BASE + 0)  /* Unicast Frames Received OK */
+#define GM_RXF_BC_OK                        (GM_MIB_CNT_BASE + 8)  /* Broadcast Frames Received OK */
+#define GM_RXF_MPAUSE                       (GM_MIB_CNT_BASE + 16)  /* Pause MAC Ctrl Frames Received */
+#define GM_RXF_MC_OK                        (GM_MIB_CNT_BASE + 24)  /* Multicast Frames Received OK */
+#define GM_RXF_FCS_ERR                      (GM_MIB_CNT_BASE + 32)  /* Rx Frame Check Seq. Error */
+#define GM_RXF_SPARE1                       (GM_MIB_CNT_BASE + 40)  /* Rx spare 1 */
+#define GM_RXO_OK_LO                        (GM_MIB_CNT_BASE + 48)  /* Octets Received OK Low */
+#define GM_RXO_OK_HI                        (GM_MIB_CNT_BASE + 56)  /* Octets Received OK High */
+#define GM_RXO_ERR_LO                       (GM_MIB_CNT_BASE + 64)  /* Octets Received Invalid Low */
+#define GM_RXO_ERR_HI                       (GM_MIB_CNT_BASE + 72)  /* Octets Received Invalid High */
+#define GM_RXF_SHT                          (GM_MIB_CNT_BASE + 80)  /* Frames <64 Byte Received OK */
+#define GM_RXE_FRAG                         (GM_MIB_CNT_BASE + 88)  /* Frames <64 Byte Received with FCS Err */
+#define GM_RXF_64B                          (GM_MIB_CNT_BASE + 96)  /* 64 Byte Rx Frame */
+#define GM_RXF_127B                         (GM_MIB_CNT_BASE + 104)  /* 65-127 Byte Rx Frame */
+#define GM_RXF_255B                         (GM_MIB_CNT_BASE + 112)  /* 128-255 Byte Rx Frame */
+#define GM_RXF_511B                         (GM_MIB_CNT_BASE + 120)  /* 256-511 Byte Rx Frame */
+#define GM_RXF_1023B                        (GM_MIB_CNT_BASE + 128)  /* 512-1023 Byte Rx Frame */
+#define GM_RXF_1518B                        (GM_MIB_CNT_BASE + 136)  /* 1024-1518 Byte Rx Frame */
+#define GM_RXF_MAX_SZ                       (GM_MIB_CNT_BASE + 144)  /* 1519-MaxSize Byte Rx Frame */
+#define GM_RXF_LNG_ERR                      (GM_MIB_CNT_BASE + 152)  /* Rx Frame too Long Error */
+#define GM_RXF_JAB_PKT                      (GM_MIB_CNT_BASE + 160)  /* Rx Jabber Packet Frame */
+#define GM_RXF_SPARE2                       (GM_MIB_CNT_BASE + 168)  /* Rx spare 2 */
+#define GM_RXE_FIFO_OV                      (GM_MIB_CNT_BASE + 176)  /* Rx FIFO overflow Event */
+#define GM_RXF_SPARE3                       (GM_MIB_CNT_BASE + 184)  /* Rx spare 3 */
+#define GM_TXF_UC_OK                        (GM_MIB_CNT_BASE + 192)  /* Unicast Frames Xmitted OK */
+#define GM_TXF_BC_OK                        (GM_MIB_CNT_BASE + 200)  /* Broadcast Frames Xmitted OK */
+#define GM_TXF_MPAUSE                       (GM_MIB_CNT_BASE + 208)  /* Pause MAC Ctrl Frames Xmitted */
+#define GM_TXF_MC_OK                        (GM_MIB_CNT_BASE + 216)  /* Multicast Frames Xmitted OK */
+#define GM_TXO_OK_LO                        (GM_MIB_CNT_BASE + 224)  /* Octets Transmitted OK Low */
+#define GM_TXO_OK_HI                        (GM_MIB_CNT_BASE + 232)  /* Octets Transmitted OK High */
+#define GM_TXF_64B                          (GM_MIB_CNT_BASE + 240)  /* 64 Byte Tx Frame */
+#define GM_TXF_127B                         (GM_MIB_CNT_BASE + 248)  /* 65-127 Byte Tx Frame */
+#define GM_TXF_255B                         (GM_MIB_CNT_BASE + 256)  /* 128-255 Byte Tx Frame */
+#define GM_TXF_511B                         (GM_MIB_CNT_BASE + 264)  /* 256-511 Byte Tx Frame */
+#define GM_TXF_1023B                        (GM_MIB_CNT_BASE + 272)  /* 512-1023 Byte Tx Frame */
+#define GM_TXF_1518B                        (GM_MIB_CNT_BASE + 280)  /* 1024-1518 Byte Tx Frame */
+#define GM_TXF_MAX_SZ                       (GM_MIB_CNT_BASE + 288)  /* 1519-MaxSize Byte Tx Frame */
+#define GM_TXF_SPARE1                       (GM_MIB_CNT_BASE + 296)  /* Tx spare 1 */
+#define GM_TXF_COL                          (GM_MIB_CNT_BASE + 304)  /* Tx Collision */
+#define GM_TXF_LAT_COL                      (GM_MIB_CNT_BASE + 312)  /* Tx Late Collision */
+#define GM_TXF_ABO_COL                      (GM_MIB_CNT_BASE + 320)  /* Tx aborted due to Exces. Col. */
+#define GM_TXF_MUL_COL                      (GM_MIB_CNT_BASE + 328)  /* Tx Multiple Collision */
+#define GM_TXF_SNG_COL                      (GM_MIB_CNT_BASE + 336)  /* Tx Single Collision */
+#define GM_TXE_FIFO_UR                      (GM_MIB_CNT_BASE + 344)  /* Tx FIFO Underrun Event */



+/*----------------------------------------------------------------------------*/
+/*


GMAC Bit Definitions







If the bit access behaviour differs from the register access behaviour



(r/w, r/o) this is documented after the bit number.



The following bit access behaviours are used:



(sc)  self clearing



(r/o)  read only


*/


+/*  GM_GP_STAT  16 bit r/o  General Purpose Status Register */
+#define GM_GPSR_SPEED                       BIT_15  /* Port Speed (1 = 100 Mbps) */
+#define GM_GPSR_DUPLEX                      BIT_14  /* Duplex Mode (1 = Full) */
+#define GM_GPSR_FC_TX_DIS                   BIT_13  /* Tx Flow-Control Mode Disabled */
+#define GM_GPSR_LINK_UP                     BIT_12  /* Link Up Status */
+#define GM_GPSR_PAUSE                       BIT_11  /* Pause State */
+#define GM_GPSR_TX_ACTIVE                   BIT_10  /* Tx in Progress */
+#define GM_GPSR_EXC_COL                     BIT_9  /* Excessive Collisions Occured */
+#define GM_GPSR_LAT_COL                     BIT_8  /* Late Collisions Occured */
+#define GM_GPSR_PHY_ST_CH                   BIT_5  /* PHY Status Change */
+#define GM_GPSR_GIG_SPEED                   BIT_4  /* Gigabit Speed (1 = 1000 Mbps) */
+#define GM_GPSR_PART_MODE                   BIT_3  /* Partition mode */
+#define GM_GPSR_FC_RX_DIS                   BIT_2  /* Rx Flow-Control Mode Disabled */



+/*  GM_GP_CTRL  16 bit r/w  General Purpose Control Register */
+#define GM_GPCR_RMII_PH_ENA                 BIT_15  /* Enable RMII for PHY (Yukon-FE only) */
+#define GM_GPCR_RMII_LB_ENA                 BIT_14  /* Enable RMII Loopback (Yukon-FE only) */
+#define GM_GPCR_FC_TX_DIS                   BIT_13  /* Disable Tx Flow-Control Mode */
+#define GM_GPCR_TX_ENA                      BIT_12  /* Enable Transmit */
+#define GM_GPCR_RX_ENA                      BIT_11  /* Enable Receive */
+#define GM_GPCR_LOOP_ENA                    BIT_9  /* Enable MAC Loopback Mode */
+#define GM_GPCR_PART_ENA                    BIT_8  /* Enable Partition Mode */
+#define GM_GPCR_GIGS_ENA                    BIT_7  /* Gigabit Speed (1000 Mbps) */
+#define GM_GPCR_FL_PASS                     BIT_6  /* Force Link Pass */
+#define GM_GPCR_DUP_FULL                    BIT_5  /* Full Duplex Mode */
+#define GM_GPCR_FC_RX_DIS                   BIT_4  /* Disable Rx Flow-Control Mode */
+#define GM_GPCR_SPEED_100                   BIT_3  /* Port Speed 100 Mbps */
+#define GM_GPCR_AU_DUP_DIS                  BIT_2  /* Disable Auto-Update Duplex */
+#define GM_GPCR_AU_FCT_DIS                  BIT_1  /* Disable Auto-Update Flow-C. */
+#define GM_GPCR_AU_SPD_DIS                  BIT_0  /* Disable Auto-Update Speed */



+#define GM_GPCR_SPEED_1000                  (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
+#define GM_GPCR_AU_ALL_DIS                  (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | GM_GPCR_AU_SPD_DIS)



+/*  GM_TX_CTRL  16 bit r/w  Transmit Control Register */
+#define GM_TXCR_FORCE_JAM                    BIT_15  /* Force Jam / Flow-Control */
+#define GM_TXCR_CRC_DIS                      BIT_14  /* Disable insertion of CRC */
+#define GM_TXCR_PAD_DIS                      BIT_13  /* Disable padding of packets */
+#define GM_TXCR_COL_THR_MSK                  (7<<10)  /* Bit 12..10: Collision Threshold Mask */
+#define GM_TXCR_PAD_PAT_MSK                  0xff  /* Bit  7.. 0: Padding Pattern Mask */
+/* (Yukon-2 only) */



+#define TX_COL_THR(x)                       (SHIFT10 (x) & GM_TXCR_COL_THR_MSK)
+#define TX_COL_DEF                          0x04



+/*  GM_RX_CTRL  16 bit r/w  Receive Control Register */
+#define GM_RXCR_UCF_ENA                      BIT_15  /* Enable Unicast filtering */
+#define GM_RXCR_MCF_ENA                      BIT_14  /* Enable Multicast filtering */
+#define GM_RXCR_CRC_DIS                      BIT_13  /* Remove 4-byte CRC */
+#define GM_RXCR_PASS_FC                      BIT_12  /* Pass FC packets to FIFO (Yukon-1 only) */



+/*  GM_TX_PARAM  16 bit r/w  Transmit Parameter Register */
+#define GM_TXPA_JAMLEN_MSK                  (3<<14)    /* Bit 15..14: Jam Length Mask */
+#define GM_TXPA_JAMIPG_MSK                  (0x1f<<9)  /* Bit 13.. 9: Jam IPG Mask */
+#define GM_TXPA_JAMDAT_MSK                  (0x1f<<4)  /* Bit  8.. 4: IPG Jam to Data Mask */
+#define GM_TXPA_BO_LIM_MSK                  0x0f    /* Bit  3.. 0: Backoff Limit Mask */
+/* (Yukon-2 only) */



+#define TX_JAM_LEN_VAL(x)                   (SHIFT14 (x) & GM_TXPA_JAMLEN_MSK)
+#define TX_JAM_IPG_VAL(x)                   (SHIFT9 (x) & GM_TXPA_JAMIPG_MSK)
+#define TX_IPG_JAM_DATA(x)                  (SHIFT4  (x) & GM_TXPA_JAMDAT_MSK)
+#define TX_BACK_OFF_LIM(x)                  ((x) & GM_TXPA_BO_LIM_MSK)



+#define TX_JAM_LEN_DEF                      0x03
+#define TX_JAM_IPG_DEF                      0x0b
+#define TX_IPG_JAM_DEF                      0x1c
+#define TX_BOF_LIM_DEF                      0x04



+/*  GM_SERIAL_MODE  16 bit r/w  Serial Mode Register */
+#define GM_SMOD_DATABL_MSK                  (0x1f<<11)  /* Bit 15..11:  Data Blinder */
+/* r/o on Yukon, r/w on Yukon-EC */
+#define GM_SMOD_LIMIT_4                     BIT_10  /* 4 consecutive Tx trials */
+#define GM_SMOD_VLAN_ENA                    BIT_9  /* Enable VLAN  (Max. Frame Len) */
+#define GM_SMOD_JUMBO_ENA                   BIT_8  /* Enable Jumbo (Max. Frame Len) */
+#define GM_SMOD_IPG_MSK                     0x1f  /* Bit  4.. 0:  Inter-Packet Gap (IPG) */



+#define DATA_BLIND_VAL(x)                   (SHIFT11 (x) & GM_SMOD_DATABL_MSK)
+#define IPG_DATA_VAL(x)                     ((x) & GM_SMOD_IPG_MSK)



+#define DATA_BLIND_DEF                      0x04
+#define IPG_DATA_DEF                        0x1e



+/*  GM_SMI_CTRL  16 bit r/w  SMI Control Register */
+#define GM_SMI_CT_PHY_A_MSK                 (0x1f<<11)  /* Bit 15..11:  PHY Device Address */
+#define GM_SMI_CT_REG_A_MSK                 (0x1f<<6)  /* Bit 10.. 6:  PHY Register Address */
+#define GM_SMI_CT_OP_RD                     BIT_5  /* OpCode Read (0=Write)*/
+#define GM_SMI_CT_RD_VAL                    BIT_4  /* Read Valid (Read completed) */
+#define GM_SMI_CT_BUSY                      BIT_3  /* Busy (Operation in progress) */



+#define GM_SMI_CT_PHY_AD(x)                 (SHIFT11 (x) & GM_SMI_CT_PHY_A_MSK)
+#define GM_SMI_CT_REG_AD(x)                 (SHIFT6 (x) & GM_SMI_CT_REG_A_MSK)



+/*  GM_PHY_ADDR  16 bit r/w  GPHY Address Register */
+#define GM_PAR_MIB_CLR                      BIT_5  /* Set MIB Clear Counter Mode */
+#define GM_PAR_MIB_TST                      BIT_4  /* MIB Load Counter (Test Mode) */



+/* Receive Frame Status Encoding */
+#define GMR_FS_LEN_MSK                      (0xffff<<16)  /* Bit 31..16:  Rx Frame Length */
+#define GMR_FS_VLAN                         BIT_13  /* VLAN Packet */
+#define GMR_FS_JABBER                       BIT_12  /* Jabber Packet */
+#define GMR_FS_UN_SIZE                      BIT_11  /* Undersize Packet */
+#define GMR_FS_MC                           BIT_10  /* Multicast Packet */
+#define GMR_FS_BC                           BIT_9  /* Broadcast Packet */
+#define GMR_FS_RX_OK                        BIT_8  /* Receive OK (Good Packet) */
+#define GMR_FS_GOOD_FC                      BIT_7  /* Good Flow-Control Packet */
+#define GMR_FS_BAD_FC                       BIT_6  /* Bad  Flow-Control Packet */
+#define GMR_FS_MII_ERR                      BIT_5  /* MII Error */
+#define GMR_FS_LONG_ERR                     BIT_4  /* Too Long Packet */
+#define GMR_FS_FRAGMENT                     BIT_3  /* Fragment */
+#define GMR_FS_CRC_ERR                      BIT_1  /* CRC Error */
+#define GMR_FS_RX_FF_OV                     BIT_0  /* Rx FIFO Overflow */



+#define GMR_FS_LEN_SHIFT                    16



+#define GMR_FS_ANY_ERR    ( \

GMR_FS_RX_FF_OV | \
GMR_FS_CRC_ERR | \
GMR_FS_FRAGMENT | \
GMR_FS_LONG_ERR | \
GMR_FS_MII_ERR | \
GMR_FS_BAD_FC | \
GMR_FS_GOOD_FC | \
GMR_FS_UN_SIZE | \
GMR_FS_JABBER)


+/* Rx GMAC FIFO Flush Mask (default) */
+#define RX_FF_FL_DEF_MSK                    GMR_FS_ANY_ERR



+/*  Receive and Transmit GMAC FIFO Registers (YUKON only) */



+/*  RX_GMF_EA      32 bit  Rx GMAC FIFO End Address */
+/*  RX_GMF_AF_THR  32 bit  Rx GMAC FIFO Almost Full Thresh. */
+/*  RX_GMF_WP      32 bit  Rx GMAC FIFO Write Pointer */
+/*  RX_GMF_WLEV    32 bit  Rx GMAC FIFO Write Level */
+/*  RX_GMF_RP      32 bit  Rx GMAC FIFO Read Pointer */
+/*  RX_GMF_RLEV    32 bit  Rx GMAC FIFO Read Level */
+/*  TX_GMF_EA      32 bit  Tx GMAC FIFO End Address */
+/*  TX_GMF_AE_THR  32 bit  Tx GMAC FIFO Almost Empty Thresh.*/
+/*  TX_GMF_WP      32 bit  Tx GMAC FIFO Write Pointer */
+/*  TX_GMF_WSP    32 bit  Tx GMAC FIFO Write Shadow Pointer */
+/*  TX_GMF_WLEV    32 bit  Tx GMAC FIFO Write Level */
+/*  TX_GMF_RP      32 bit  Tx GMAC FIFO Read Pointer */
+/*  TX_GMF_RSTP    32 bit  Tx GMAC FIFO Restart Pointer */
+/*  TX_GMF_RLEV    32 bit  Tx GMAC FIFO Read Level */



+/*  RX_GMF_CTRL_T  32 bit  Rx GMAC FIFO Control/Test */
+#define RX_TRUNC_ON                         BIT_27  /* enable  packet truncation */
+#define RX_TRUNC_OFF                        BIT_26  /* disable packet truncation */
+#define RX_VLAN_STRIP_ON                    BIT_25  /* enable  VLAN stripping */
+#define RX_VLAN_STRIP_OFF                   BIT_24  /* disable VLAN stripping */
+#define GMF_RX_MACSEC_FLUSH_ON              BIT_23
+#define GMF_RX_MACSEC_FLUSH_OFF             BIT_22
+#define GMF_RX_OVER_ON                      BIT_19  /* enable flushing on receive overrun */
+#define GMF_RX_OVER_OFF                     BIT_18  /* disable flushing on receive overrun */
+#define GMF_ASF_RX_OVER_ON                  BIT_17  /* enable flushing of ASF when overrun */
+#define GMF_ASF_RX_OVER_OFF                 BIT_16  /* disable flushing of ASF when overrun */
+#define GMF_WP_TST_ON                       BIT_14  /* Write Pointer Test On */
+#define GMF_WP_TST_OFF                      BIT_13  /* Write Pointer Test Off */
+#define GMF_WP_STEP                         BIT_12  /* Write Pointer Step/Increment */
+#define GMF_RP_TST_ON                       BIT_10  /* Read Pointer Test On */
+#define GMF_RP_TST_OFF                      BIT_9  /* Read Pointer Test Off */
+#define GMF_RP_STEP                         BIT_8  /* Read Pointer Step/Increment */
+#define GMF_RX_F_FL_ON                      BIT_7  /* Rx FIFO Flush Mode On */
+#define GMF_RX_F_FL_OFF                     BIT_6  /* Rx FIFO Flush Mode Off */
+#define GMF_CLI_RX_FO                       BIT_5  /* Clear IRQ Rx FIFO Overrun */
+#define GMF_CLI_RX_FC                       BIT_4  /* Clear IRQ Rx Frame Complete */
+#define GMF_OPER_ON                         BIT_3  /* Operational Mode On */
+#define GMF_OPER_OFF                        BIT_2  /* Operational Mode Off */
+#define GMF_RST_CLR                         BIT_1  /* Clear GMAC FIFO Reset */
+#define GMF_RST_SET                         BIT_0  /* Set   GMAC FIFO Reset */



+/*  TX_GMF_CTRL_T  32 bit  Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
+#define  TX_STFW_DIS                        BIT_31  /* Disable Store & Forward (Yukon-EC Ultra) */
+#define  TX_STFW_ENA                        BIT_30  /* Enable Store & Forward (Yukon-EC Ultra) */
+#define TX_VLAN_TAG_ON                      BIT_25  /* enable  VLAN tagging */
+#define TX_VLAN_TAG_OFF                     BIT_24  /* disable VLAN tagging */
+#define  TX_JUMBO_ENA                       BIT_23  /* Enable Jumbo Mode (Yukon-EC Ultra) */
+#define  TX_JUMBO_DIS                       BIT_22  /* Disable Jumbo Mode (Yukon-EC Ultra) */
+#define GMF_WSP_TST_ON                      BIT_18  /* Write Shadow Pointer Test On */
+#define GMF_WSP_TST_OFF                     BIT_17  /* Write Shadow Pointer Test Off */
+#define GMF_WSP_STEP                        BIT_16  /* Write Shadow Pointer Step/Increment */
+/* Bits 15..8: same as for RX_GMF_CTRL_T */
+#define GMF_CLI_TX_FU                       BIT_6  /* Clear IRQ Tx FIFO Underrun */
+#define GMF_CLI_TX_FC                       BIT_5  /* Clear IRQ Tx Frame Complete */
+#define GMF_CLI_TX_PE                       BIT_4  /* Clear IRQ Tx Parity Error */
+/* Bits 3..0: same as for RX_GMF_CTRL_T */



+#define GMF_RX_CTRL_DEF                     (GMF_OPER_ON | GMF_RX_F_FL_ON)
+#define GMF_TX_CTRL_DEF                     GMF_OPER_ON



+#define RX_GMF_AF_THR_MIN                    0x0c  /* Rx GMAC FIFO Almost Full Thresh. min. */
+#define RX_GMF_FL_THR_DEF                    0x0a  /* Rx GMAC FIFO Flush Threshold default */



+/*  GMAC_TI_ST_CTRL   8 bit  Time Stamp Timer Ctrl Reg (YUKON only) */
+#define GMT_ST_START                        BIT_2  /* Start Time Stamp Timer */
+#define GMT_ST_STOP                         BIT_1  /* Stop  Time Stamp Timer */
+#define GMT_ST_CLR_IRQ                      BIT_0  /* Clear Time Stamp Timer IRQ */



+/*  POLL_CTRL  32 bit  Polling Unit control register (Yukon-2 only) */
+#define PC_CLR_IRQ_CHK                      BIT_5  /* Clear IRQ Check */
+#define PC_POLL_RQ                          BIT_4  /* Poll Request Start */
+#define PC_POLL_OP_ON                       BIT_3  /* Operational Mode On */
+#define PC_POLL_OP_OFF                      BIT_2  /* Operational Mode Off */
+#define PC_POLL_RST_CLR                     BIT_1  /* Clear Polling Unit Reset (Enable) */
+#define PC_POLL_RST_SET                     BIT_0  /* Set   Polling Unit Reset */



+/* B28_Y2_ASF_STAT_CMD    32 bit  ASF Status and Command Reg */
+/* This register is used by the host driver software */
+#define Y2_ASF_OS_PRES                      BIT_4  /* ASF operation system present */
+#define Y2_ASF_RESET                        BIT_3  /* ASF system in reset state */
+#define Y2_ASF_RUNNING                      BIT_2  /* ASF system operational */
+#define Y2_ASF_CLR_HSTI                     BIT_1  /* Clear ASF IRQ */
+#define Y2_ASF_IRQ                          BIT_0  /* Issue an IRQ to ASF system */



+#define Y2_ASF_UC_STATE                     (3<<2)  /* ASF uC State */
+#define Y2_ASF_CLK_HALT                     0  /* ASF system clock stopped */



+/* B28_Y2_ASF_HCU_CCSR  32bit CPU Control and Status Register (Yukon EX) */
+#define  Y2_ASF_HCU_CCSR_SMBALERT_MONITOR    BIT_27  /* SMBALERT pin monitor */
+#define  Y2_ASF_HCU_CCSR_CPU_SLEEP           BIT_26  /* CPU sleep status */
+#define  Y2_ASF_HCU_CCSR_CS_TO               BIT_25  /* Clock Stretching Timeout */
+#define  Y2_ASF_HCU_CCSR_WDOG                BIT_24  /* Watchdog Reset */
+#define  Y2_ASF_HCU_CCSR_CLR_IRQ_HOST        BIT_17  /* Clear IRQ_HOST */
+#define  Y2_ASF_HCU_CCSR_SET_IRQ_HCU         BIT_16  /* Set IRQ_HCU */
+#define  Y2_ASF_HCU_CCSR_AHB_RST             BIT_9  /* Reset AHB bridge */
+#define  Y2_ASF_HCU_CCSR_CPU_RST_MODE        BIT_8  /* CPU Reset Mode */
+#define  Y2_ASF_HCU_CCSR_SET_SYNC_CPU        BIT_5
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1     BIT_4
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0     BIT_3
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK  (BIT_4 | BIT_3)  /* CPU Clock Divide */
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
+#define  Y2_ASF_HCU_CCSR_OS_PRSNT            BIT_2  /* ASF OS Present */
+/* Microcontroller State */
+#define  Y2_ASF_HCU_CCSR_UC_STATE_MSK        3
+#define  Y2_ASF_HCU_CCSR_UC_STATE_BASE       BIT_0
+#define  Y2_ASF_HCU_CCSR_ASF_RESET           0
+#define  Y2_ASF_HCU_CCSR_ASF_HALTED          BIT_1
+#define  Y2_ASF_HCU_CCSR_ASF_RUNNING         BIT_0



+/* B28_Y2_ASF_HOST_COM  32 bit  ASF Host Communication Reg */
+/* This register is used by the ASF firmware */
+#define Y2_ASF_CLR_ASFI                      BIT_1  /* Clear host IRQ */
+#define Y2_ASF_HOST_IRQ                      BIT_0  /* Issue an IRQ to HOST system */



+/*  STAT_CTRL  32 bit  Status BMU control register (Yukon-2 only) */
+#define SC_STAT_CLR_IRQ                     BIT_4  /* Status Burst IRQ clear */
+#define SC_STAT_OP_ON                       BIT_3  /* Operational Mode On */
+#define SC_STAT_OP_OFF                      BIT_2  /* Operational Mode Off */
+#define SC_STAT_RST_CLR                     BIT_1  /* Clear Status Unit Reset (Enable) */
+#define SC_STAT_RST_SET                     BIT_0  /* Set   Status Unit Reset */



+/*  GMAC_CTRL  32 bit  GMAC Control Reg (YUKON only) */
+#define GMC_SEC_RST                         BIT_15  /* MAC SEC RST */
+#define GMC_SEC_RST_OFF                     BIT_14  /* MAC SEC RST Off */
+#define GMC_BYP_MACSECRX_ON                 BIT_13  /* Bypass MAC SEC RX */
+#define GMC_BYP_MACSECRX_OFF                BIT_12  /* Bypass MAC SEC RX Off */
+#define GMC_BYP_MACSECTX_ON                 BIT_11  /* Bypass MAC SEC TX */
+#define GMC_BYP_MACSECTX_OFF                BIT_10  /* Bypass MAC SEC TX Off */
+#define GMC_BYP_RETR_ON                     BIT_9  /* Bypass MAC retransmit FIFO On */
+#define GMC_BYP_RETR_OFF                    BIT_8  /* Bypass MAC retransmit FIFO Off */
+#define GMC_H_BURST_ON                      BIT_7  /* Half Duplex Burst Mode On */
+#define GMC_H_BURST_OFF                     BIT_6  /* Half Duplex Burst Mode Off */
+#define GMC_F_LOOPB_ON                      BIT_5  /* FIFO Loopback On */
+#define GMC_F_LOOPB_OFF                     BIT_4  /* FIFO Loopback Off */
+#define GMC_PAUSE_ON                        BIT_3  /* Pause On */
+#define GMC_PAUSE_OFF                       BIT_2  /* Pause Off */
+#define GMC_RST_CLR                         BIT_1  /* Clear GMAC Reset */
+#define GMC_RST_SET                         BIT_0  /* Set   GMAC Reset */



+/*  GPHY_CTRL  32 bit  GPHY Control Reg (YUKON only) */
+#define GPC_SEL_BDT                         BIT_28  /* Select Bi-Dir. Transfer for MDC/MDIO */
+#define GPC_INT_POL                         BIT_27  /* IRQ Polarity is Active Low */
+#define GPC_75_OHM                          BIT_26  /* Use 75 Ohm Termination instead of 50 */
+#define GPC_DIS_FC                          BIT_25  /* Disable Automatic Fiber/Copper Detection */
+#define GPC_DIS_SLEEP                       BIT_24  /* Disable Energy Detect */
+#define GPC_HWCFG_M_3                       BIT_23  /* HWCFG_MODE[3] */
+#define GPC_HWCFG_M_2                       BIT_22  /* HWCFG_MODE[2] */
+#define GPC_HWCFG_M_1                       BIT_21  /* HWCFG_MODE[1] */
+#define GPC_HWCFG_M_0                       BIT_20  /* HWCFG_MODE[0] */
+#define GPC_ANEG_0                          BIT_19  /* ANEG[0] */
+#define GPC_ENA_XC                          BIT_18  /* Enable MDI crossover */
+#define GPC_DIS_125                         BIT_17  /* Disable 125 MHz clock */
+#define GPC_ANEG_3                          BIT_16  /* ANEG[3] */
+#define GPC_ANEG_2                          BIT_15  /* ANEG[2] */
+#define GPC_ANEG_1                          BIT_14  /* ANEG[1] */
+#define GPC_ENA_PAUSE                       BIT_13  /* Enable Pause (SYM_OR_REM) */
+#define GPC_PHYADDR_4                       BIT_12  /* Bit 4 of Phy Addr */
+#define GPC_PHYADDR_3                       BIT_11  /* Bit 3 of Phy Addr */
+#define GPC_PHYADDR_2                       BIT_10  /* Bit 2 of Phy Addr */
+#define GPC_PHYADDR_1                       BIT_9  /* Bit 1 of Phy Addr */
+#define GPC_PHYADDR_0                       BIT_8  /* Bit 0 of Phy Addr */
+#define GPC_RST_CLR                         BIT_1  /* Clear GPHY Reset */
+#define GPC_RST_SET                         BIT_0  /* Set   GPHY Reset */



+/*  GMAC_IRQ_SRC   8 bit  GMAC Interrupt Source Reg (YUKON only) */
+/*  GMAC_IRQ_MSK   8 bit  GMAC Interrupt Mask   Reg (YUKON only) */
+#define GM_IS_RX_CO_OV                      BIT_5  /* Receive Counter Overflow IRQ */
+#define GM_IS_TX_CO_OV                      BIT_4  /* Transmit Counter Overflow IRQ */
+#define GM_IS_TX_FF_UR                      BIT_3  /* Transmit FIFO Underrun */
+#define GM_IS_TX_COMPL                      BIT_2  /* Frame Transmission Complete */
+#define GM_IS_RX_FF_OR                      BIT_1  /* Receive FIFO Overrun */
+#define GM_IS_RX_COMPL                      BIT_0  /* Frame Reception Complete */



+#define GMAC_DEF_MSK                        (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR)



+//  GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only)
+#define GMLC_RST_CLR                        BIT_1  // Clear GMAC Link Reset
+#define GMLC_RST_SET                        BIT_0  // Set   GMAC Link Reset



+#define MSK_PORT_A                          0
+#define MSK_PORT_B                          1



+// Register access macros
+#define CSR_WRITE_4(sc, reg, val)            MmioWrite32 ((sc)->RegBase + (reg), (val))
+#define CSR_WRITE_2(sc, reg, val)            MmioWrite16 ((sc)->RegBase + (reg), (val))
+#define CSR_WRITE_1(sc, reg, val)            MmioWrite8 ((sc)->RegBase + (reg), (val))



+#define CSR_READ_4(sc, reg)                  MmioRead32 ((sc)->RegBase + (reg))
+#define CSR_READ_2(sc, reg)                  MmioRead16 ((sc)->RegBase + (reg))
+#define CSR_READ_1(sc, reg)                  MmioRead8 ((sc)->RegBase + (reg))



+#define CSR_PCI_WRITE_4(sc, reg, val)        MmioWrite32 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))
+#define CSR_PCI_WRITE_2(sc, reg, val)        MmioWrite16 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))
+#define CSR_PCI_WRITE_1(sc, reg, val)        MmioWrite8 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))



+#define CSR_PCI_READ_4(sc, reg)              MmioRead32 ((sc)->RegBase + Y2_CFG_SPC + (reg))
+#define CSR_PCI_READ_2(sc, reg)              MmioRead16 ((sc)->RegBase + Y2_CFG_SPC + (reg))
+#define CSR_PCI_READ_1(sc, reg)              MmioRead8 ((sc)->RegBase + Y2_CFG_SPC + (reg))



+#define GMAC_REG(port, reg)                  ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
+#define  GMAC_WRITE_2(sc, port, reg, val)    CSR_WRITE_2 ((sc), GMAC_REG((port), (reg)), (val))
+#define  GMAC_READ_2(sc, port, reg)          CSR_READ_2 ((sc), GMAC_REG((port), (reg)))



+// GPHY address (bits 15..11 of SMI control reg)
+#define PHY_ADDR_MARV                        0



+#define MSK_ADDR_LO(x)                      ((UINT64) (x) & 0xffffffffUL)
+#define MSK_ADDR_HI(x)                      ((UINT64) (x) >> 32)



+// PCI Status error definitions (not all of these are defined in MdePkg/Include/IndustryStandard/Pci22.h
+#define PCIM_STATUS_CAPPRESENT              0x0010
+#define PCIM_STATUS_66CAPABLE               0x0020
+#define PCIM_STATUS_BACKTOBACK              0x0080
+#define PCIM_STATUS_PERRREPORT              0x0100
+#define PCIM_STATUS_SEL_FAST                0x0000
+#define PCIM_STATUS_SEL_MEDIMUM             0x0200
+#define PCIM_STATUS_SEL_SLOW                0x0400
+#define PCIM_STATUS_SEL_MASK                0x0600
+#define PCIM_STATUS_STABORT                 0x0800
+#define PCIM_STATUS_RTABORT                 0x1000
+#define PCIM_STATUS_RMABORT                 0x2000
+#define PCIM_STATUS_SERR                    0x4000
+#define PCIM_STATUS_PERR                    0x8000



+//
+// At first I guessed 8 bytes, the size of a single descriptor, would be
+// required alignment constraints. But, it seems that Yukon II have 4096
+// bytes boundary alignment constraints.
+//
+#define MSK_RING_ALIGN                      4096
+#define MSK_STAT_ALIGN                      4096



+// Rx descriptor data structure
+struct msk_rx_desc {

UINT32  msk_addr;
UINT32  msk_control;

+};



+// Tx descriptor data structure
+struct msk_tx_desc {

UINT32  msk_addr;
UINT32  msk_control;

+};



+// Status descriptor data structure
+struct msk_stat_desc {

UINT32  msk_status;
UINT32  msk_control;

+};



+// Mask and shift value to get Tx async queue status for port 1
+#define STLE_TXA1_MSKL                      0x00000fff
+#define STLE_TXA1_SHIFTL                    0



+// Mask and shift value to get Tx sync queue status for port 1
+#define STLE_TXS1_MSKL                      0x00fff000
+#define STLE_TXS1_SHIFTL                    12



+// Mask and shift value to get Tx async queue status for port 2
+#define STLE_TXA2_MSKL                      0xff000000
+#define STLE_TXA2_SHIFTL                    24
+#define STLE_TXA2_MSKH                      0x000f
+// This one shifts up
+#define STLE_TXA2_SHIFTH                    8



+// Mask and shift value to get Tx sync queue status for port 2
+#define STLE_TXS2_MSKL                      0x00000000
+#define STLE_TXS2_SHIFTL                    0
+#define STLE_TXS2_MSKH                      0xfff0
+#define STLE_TXS2_SHIFTH                    4



+// YUKON-2 bit values
+#define HW_OWNER                            0x80000000
+#define SW_OWNER                            0x00000000



+#define PU_PUTIDX_VALID                     0x10000000



+// YUKON-2 Control flags
+#define UDPTCP                              0x00010000
+#define CALSUM                              0x00020000
+#define WR_SUM                              0x00040000
+#define INIT_SUM                            0x00080000
+#define LOCK_SUM                            0x00100000
+#define INS_VLAN                            0x00200000
+#define FRC_STAT                            0x00400000
+#define EOP                                 0x00800000



+#define TX_LOCK                             0x01000000
+#define BUF_SEND                            0x02000000
+#define PACKET_SEND                         0x04000000



+#define NO_WARNING                          0x40000000
+#define NO_UPDATE                           0x80000000



+// YUKON-2 Rx/Tx opcodes defines
+#define OP_TCPWRITE                         0x11000000
+#define OP_TCPSTART                         0x12000000
+#define OP_TCPINIT                          0x14000000
+#define OP_TCPLCK                           0x18000000
+#define OP_TCPCHKSUM                        OP_TCPSTART
+#define OP_TCPIS                            (OP_TCPINIT | OP_TCPSTART)
+#define OP_TCPLW                            (OP_TCPLCK | OP_TCPWRITE)
+#define OP_TCPLSW                           (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
+#define OP_TCPLISW                          (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
+#define OP_ADDR64                           0x21000000
+#define OP_VLAN                             0x22000000
+#define OP_ADDR64VLAN                       (OP_ADDR64 | OP_VLAN)
+#define OP_LRGLEN                           0x24000000
+#define OP_LRGLENVLAN                       (OP_LRGLEN | OP_VLAN)
+#define OP_MSS                              0x28000000
+#define OP_MSSVLAN                          (OP_MSS | OP_VLAN)
+#define OP_BUFFER                           0x40000000
+#define OP_PACKET                           0x41000000
+#define OP_LARGESEND                        0x43000000



+// YUKON-2 STATUS opcodes defines
+#define OP_RXSTAT                           0x60000000
+#define OP_RXTIMESTAMP                      0x61000000
+#define OP_RXVLAN                           0x62000000
+#define OP_RXCHKS                           0x64000000
+#define OP_RXCHKSVLAN                       (OP_RXCHKS | OP_RXVLAN)
+#define OP_RXTIMEVLAN                       (OP_RXTIMESTAMP | OP_RXVLAN)
+#define OP_RSS_HASH                         0x65000000
+#define OP_TXINDEXLE                        0x68000000



+// YUKON-2 SPECIAL opcodes defines
+#define OP_PUTIDX                           0x70000000



+#define  STLE_OP_MASK                       0xff000000
+#define  STLE_CSS_MASK                      0x00ff0000
+#define  STLE_LEN_MASK                      0x0000ffff



+// CSS defined in status LE(valid for       descriptor V2 format)
+#define  CSS_TCPUDP_CSUM_OK                  0x00800000
+#define  CSS_UDP                             0x00400000
+#define  CSS_TCP                             0x00200000
+#define  CSS_IPFRAG                          0x00100000
+#define  CSS_IPV6                            0x00080000
+#define  CSS_IPV4_CSUM_OK                    0x00040000
+#define  CSS_IPV4                            0x00020000
+#define  CSS_PORT                            0x00010000



+// Descriptor Bit Definition
+//  TxCtrl    Transmit Buffer Control Field
+//  RxCtrl    Receive  Buffer Control Field
+#define BMU_OWN                             BIT_31  // OWN bit: 0=host/1=BMU
+#define BMU_STF                             BIT_30  // Start of Frame
+#define BMU_EOF                             BIT_29  // End of Frame
+#define BMU_IRQ_EOB                         BIT_28  // Req "End of Buffer" IRQ
+#define BMU_IRQ_EOF                         BIT_27  // Req "End of Frame" IRQ
+// TxCtrl specific bits
+#define BMU_STFWD                           BIT_26  // (Tx)  Store & Forward Frame
+#define BMU_NO_FCS                          BIT_25  // (Tx) Disable MAC FCS (CRC) generation
+#define BMU_SW                              BIT_24  // (Tx)  1 bit res. for SW use
+// RxCtrl specific bits
+#define BMU_DEV_0                           BIT_26  // (Rx)  Transfer data to Dev0
+#define BMU_STAT_VAL                        BIT_25  // (Rx)  Rx Status Valid
+#define BMU_TIST_VAL                        BIT_24  // (Rx)  Rx TimeStamp Valid
+// Bit 23..16:  BMU Check Opcodes
+#define BMU_CHECK                           (0x55<<16)  // Default BMU check
+#define BMU_TCP_CHECK                       (0x56<<16)  // Descr with TCP ext
+#define BMU_UDP_CHECK                       (0x57<<16)  // Descr with UDP ext (YUKON only)
+#define BMU_BBC                             0xffff  // Bit 15.. 0:  Buffer Byte Counter



+#define MSK_TX_RING_CNT                     512
+#define MSK_RX_RING_CNT                     512
+#define MSK_RX_BUF_ALIGN                    8
+#define MSK_JUMBO_RX_RING_CNT               MSK_RX_RING_CNT
+#define MSK_STAT_RING_CNT                   512
+#define MSK_MAXTXSEGS                       32
+#define MSK_TSO_MAXSGSIZE                   4096
+#define MSK_TSO_MAXSIZE                     (65535 + sizeof (struct ether_vlan_header))



+/*


It seems that the hardware requires extra decriptors(LEs) to offload



TCP/UDP checksum, VLAN hardware tag inserstion and TSO.







1 descriptor for TCP/UDP checksum offload.



1 descriptor VLAN hardware tag insertion.



1 descriptor for TSO(TCP Segmentation Offload)



1 descriptor for 64bits DMA : Not applicatable due to the use of



BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation.


*/

+#define  MSK_RESERVED_TX_DESC_CNT            3



+/*


Jumbo buffer stuff. Note that we must allocate more jumbo



buffers than there are descriptors in the receive ring. This



is because we don't know how long it will take for a packet



to be released after we hand it off to the upper protocol



layers. To be safe, we allocate 1.5 times the number of



receive descriptors.


*/

+/*#define MSK_JUMBO_FRAMELEN  9022
+#define MSK_JUMBO_MTU    (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define MSK_MAX_FRAMELEN    \

(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)

+#define MSK_MIN_FRAMELEN  (ETHER_MIN_LEN - ETHER_CRC_LEN)
+*/



+#define PAGE_SIZE                           0x1000
+#define BYTES_TO_PAGES(BYTES)               ((((BYTES) - 1) / PAGE_SIZE) + 1)
+#define htole32(x)                          (x) // All UEFI platforms are little endian
+#define le32toh(x)                          (x)
+#define ACPI_SPECFLAG_PREFETCHABLE          0x06
+#define TX_MBUF_SIGNATURE                   SIGNATURE_32 ('t','x','m','b')
+#define RX_MBUF_SIGNATURE                   SIGNATURE_32 ('r','x','m','b')
+#define ETHER_CRC_POLY_LE                   0xedb88320
+#define ETHER_CRC_POLY_BE                   0x04c11db6
+//#define JUMBO_RX_MBUF_SIGNATURE   SIGNATURE_32('j','r','x','m')



+typedef struct {

VOID            *Buf;
UINTN           Length;

+} MSK_SYSTEM_BUF;



+typedef struct {

UINTN           Signature;
LIST_ENTRY      Link;
MSK_SYSTEM_BUF  SystemBuf;

+} MSK_LINKED_SYSTEM_BUF;



+typedef struct {

VOID            *Buf;
UINTN           Length;
VOID            *DmaMapping;

+} MSK_DMA_BUF;



+typedef struct {

UINTN           Signature;
LIST_ENTRY      Link;
MSK_DMA_BUF     DmaBuf;

+} MSK_LINKED_DMA_BUF;



+struct msk_txdesc {

MSK_DMA_BUF          tx_m;
struct msk_tx_desc  *tx_le;

+};



+struct msk_rxdesc {

MSK_DMA_BUF         rx_m;
struct msk_rx_desc  *rx_le;

+};



+struct msk_chain_data {

struct msk_txdesc  msk_txdesc[MSK_TX_RING_CNT];
struct msk_rxdesc  msk_rxdesc[MSK_RX_RING_CNT];
void              *msk_tx_ring_map;
void              *msk_rx_ring_map;
//  struct msk_rxdesc  msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT];
INTN     msk_tx_prod;
INTN     msk_tx_cons;
INTN     msk_tx_cnt;
INTN     msk_tx_put;
INTN     msk_rx_cons;
INTN     msk_rx_prod;
INTN     msk_rx_putwm;

+};



+struct msk_ring_data {

struct msk_tx_desc      *msk_tx_ring;
EFI_PHYSICAL_ADDRESS    msk_tx_ring_paddr;
struct msk_rx_desc      *msk_rx_ring;
EFI_PHYSICAL_ADDRESS    msk_rx_ring_paddr;
//  struct msk_rx_desc      *msk_jumbo_rx_ring;
//  EFI_PHYSICAL_ADDRESS    msk_jumbo_rx_ring_paddr;

+};



+#define MSK_TX_RING_ADDR(sc, i)  \

((sc)->msk_rdata.msk_tx_ring_paddr + sizeof (struct msk_tx_desc) * (i))

+#define MSK_RX_RING_ADDR(sc, i) \

((sc)->msk_rdata.msk_rx_ring_paddr + sizeof (struct msk_rx_desc) * (i))


+#define MSK_TX_RING_SZ                      (sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT)
+#define MSK_RX_RING_SZ                      (sizeof (struct msk_rx_desc) * MSK_RX_RING_CNT)
+#define MSK_JUMBO_RX_RING_SZ                (sizeof (struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT)
+#define MSK_STAT_RING_SZ                    (sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT)



+#define MSK_INC(x, y)                       ((x) = (x + 1) % y)



+#define  MSK_PCI_BUS                         0
+#define  MSK_PCIX_BUS                        1
+#define  MSK_PEX_BUS                         2



+#define  MSK_PROC_DEFAULT                    (MSK_RX_RING_CNT / 2)
+#define  MSK_PROC_MIN                        30
+#define  MSK_PROC_MAX                        (MSK_RX_RING_CNT - 1)



+#define  MSK_INT_HOLDOFF_DEFAULT             100



+#define  MSK_TX_TIMEOUT                      5
+#define  MSK_PUT_WM                          10



+/* Forward decl. */
+struct msk_if_softc;



+struct msk_hw_stats {

/* Rx stats. */
UINT32 rx_ucast_frames;
UINT32 rx_bcast_frames;
UINT32 rx_pause_frames;
UINT32 rx_mcast_frames;
UINT32 rx_crc_errs;
UINT32 rx_spare1;
UINT64 rx_good_octets;
UINT64 rx_bad_octets;
UINT32 rx_runts;
UINT32 rx_runt_errs;
UINT32 rx_pkts_64;
UINT32 rx_pkts_65_127;
UINT32 rx_pkts_128_255;
UINT32 rx_pkts_256_511;
UINT32 rx_pkts_512_1023;
UINT32 rx_pkts_1024_1518;
UINT32 rx_pkts_1519_max;
UINT32 rx_pkts_too_long;
UINT32 rx_pkts_jabbers;
UINT32 rx_spare2;
UINT32 rx_fifo_oflows;
UINT32 rx_spare3;
/* Tx stats. */
UINT32 tx_ucast_frames;
UINT32 tx_bcast_frames;
UINT32 tx_pause_frames;
UINT32 tx_mcast_frames;
UINT64 tx_octets;
UINT32 tx_pkts_64;
UINT32 tx_pkts_65_127;
UINT32 tx_pkts_128_255;
UINT32 tx_pkts_256_511;
UINT32 tx_pkts_512_1023;
UINT32 tx_pkts_1024_1518;
UINT32 tx_pkts_1519_max;
UINT32 tx_spare1;
UINT32 tx_colls;
UINT32 tx_late_colls;
UINT32 tx_excess_colls;
UINT32 tx_multi_colls;
UINT32 tx_single_colls;
UINT32 tx_underflows;

+};



+/* Softc for the Marvell Yukon II controller. */
+struct msk_softc {

UINT32    RegBase;
UINT64    OriginalPciAttributes;
UINT8      msk_hw_id;
UINT8      msk_hw_rev;
UINT8      msk_bustype;
UINT8      msk_num_port;
INTN      msk_expcap;
//  INTN      msk_pcixcap;
INTN      msk_ramsize;  /* amount of SRAM on NIC */
UINT32    msk_pmd;  /* physical media type */
UINT32    msk_intrmask;
UINT32    msk_intrhwemask;
UINT32    msk_pflags;
INTN      msk_clock;
struct msk_if_softc  *msk_if[2];
INTN      msk_txqsize;
INTN      msk_rxqsize;
INTN      msk_txqstart[2];
INTN      msk_txqend[2];
INTN      msk_rxqstart[2];
INTN      msk_rxqend[2];
void                  *msk_stat_map;
struct msk_stat_desc  *msk_stat_ring;
EFI_PHYSICAL_ADDRESS  msk_stat_ring_paddr;
INTN      msk_int_holdoff;
INTN      msk_process_limit;
INTN      msk_stat_cons;
LIST_ENTRY TransmitQueueHead;
LIST_ENTRY TransmitFreeQueueHead;
LIST_ENTRY ReceiveQueueHead;
EFI_EVENT Timer;

+};



+#define  MSK_USECS(sc, us)                   ((sc)->msk_clock * (us))



+/* Softc for each logical interface. */
+struct msk_if_softc {

//  INT32      msk_port;  /* port # on controller */
struct msk_mii_data msk_md;
struct mii_data mii_d;
INTN      msk_framesize;
INTN      msk_phytype;
INTN      msk_phyaddr;
UINT32    msk_flags;

+#define  MSK_FLAG_MSI                        0x0001
+#define  MSK_FLAG_FASTETHER                  0x0004
+#define  MSK_FLAG_JUMBO                      0x0008
+#define  MSK_FLAG_JUMBO_NOCSUM               0x0010
+#define  MSK_FLAG_RAMBUF                     0x0020
+#define  MSK_FLAG_DESCV2                     0x0040
+#define  MSK_FLAG_AUTOTX_CSUM                0x0080
+#define  MSK_FLAG_NOHWVLAN                   0x0100
+#define  MSK_FLAG_NORXCHK                    0x0200
+#define  MSK_FLAG_NORX_CSUM                  0x0400
+#define  MSK_FLAG_SUSPEND                    0x2000
+#define  MSK_FLAG_DETACH                     0x4000
+#define  MSK_FLAG_LINK                       0x8000

//  INTN      msk_watchdog_timer;
UINT32    msk_txq;  /* Tx. Async Queue offset */
UINT32    msk_txsq;  /* Tx. Syn Queue offset */
UINT32    msk_rxq;  /* Rx. Qeueue offset */
struct msk_chain_data  msk_cdata;
struct msk_ring_data  msk_rdata;
struct msk_hw_stats  msk_stats;
EFI_MAC_ADDRESS MacAddress;

+};



+#define MSK_TIMEOUT                          1000
+#define  MSK_PHY_POWERUP                     1
+#define  MSK_PHY_POWERDOWN                   0
diff --git a/Drivers/Net/MarvellYukonDxe/miivar.h b/Drivers/Net/MarvellYukonDxe/miivar.h
new file mode 100644
index 0000000..62607f3
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/miivar.h
@@ -0,0 +1,198 @@
+/**  <at> file
+*  Media Independent Interface configuration definitions. Ported from FreeBSD.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*-


Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.



All rights reserved.







This code is derived from software contributed to The NetBSD Foundation



by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,



NASA Ames Research Center.







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions and the following disclaimer.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




All advertising materials mentioning features or use of this software





must display the following acknowledgement:



This product includes software developed by the NetBSD



Foundation, Inc. and its contributors.




Neither the name of The NetBSD Foundation nor the names of its





contributors may be used to endorse or promote products derived



from this software without specific prior written permission.







THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS



``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED



TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS



BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR



CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF



SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS



INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN



CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)



ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE



POSSIBILITY OF SUCH DAMAGE.







$FreeBSD: src/sys/dev/mii/miivar.h,v 1.21.10.1.4.1 2010/06/14 02:09:06 kensmith Exp $


*/


+#ifndef _DEV_MII_MIIVAR_H_
+#define  _DEV_MII_MIIVAR_H_



+/*


Callbacks from MII layer into network interface device driver.


*/

+INTN msk_phy_readreg (INTN, INTN);
+INTN msk_phy_writereg (INTN, INTN, INTN);
+void msk_miibus_statchg (INTN);



+/*


A network interface driver has one of these structures in its softc.



It is the interface from the network interface driver to the MII



layer.


*/

+struct mii_data {

/*

PHY driver fills this in with active media status.


*/
INTN mii_media_status;
INTN mii_media_active;

+};



+/*


Requests that can be made to the downcall.


*/

+#define  MII_TICK                    1  /* once-per-second tick */
+#define  MII_MEDIACHG                2  /* user changed media; perform the switch */
+#define  MII_POLLSTAT                3  /* user requested media status; fill it in */



+/*


Each PHY driver's softc has one of these as the first member.



XXX This would be better named "phy_softc", but this is the name



XXX BSDI used, and we would like to have the same interface.


*/

+struct mii_softc {

struct mii_data *mii_pdata;  /* pointer to parent's mii_data */

INTN mii_flags;           /* misc. flags; see below */
INTN mii_capabilities;    /* capabilities from BMSR */
INTN mii_extcapabilities; /* extended capabilities */
INTN mii_ticks;           /* MII_TICK counter */
INTN mii_anegticks;       /* ticks before retrying aneg */
INTN mii_media_active;    /* last active media */
INTN mii_media_status;    /* last active status */

+};



+/* mii_flags */
+#define  MIIF_INITDONE              0x0001    /* has been initialized (mii_data) */
+#define  MIIF_NOISOLATE             0x0002    /* do not isolate the PHY */
+#define  MIIF_NOLOOP                0x0004    /* no loopback capability */
+#define MIIF_AUTOTSLEEP             0x0010    /* use tsleep(), not callout() */
+#define MIIF_HAVEFIBER              0x0020    /* from parent: has fiber interface */
+#define  MIIF_HAVE_GTCR             0x0040    /* has 100base-T2/1000base-T CR */
+#define  MIIF_IS_1000X              0x0080    /* is a 1000BASE-X device */
+#define  MIIF_DOPAUSE               0x0100    /* advertise PAUSE capability */
+#define  MIIF_IS_HPNA               0x0200    /* is a HomePNA device */
+#define  MIIF_FORCEANEG             0x0400    /* force auto-negotiation */



+/* Default mii_anegticks values */
+#define  MII_ANEGTICKS              5
+#define  MII_ANEGTICKS_GIGE         17



+#define  MIIF_INHERIT_MASK          (MIIF_NOISOLATE|MIIF_NOLOOP|MIIF_AUTOTSLEEP)



+#define MII_OUI_MARVELL             0x005043
+#define MII_OUI_xxMARVELL           0x000ac2



+#define MII_MODEL_MARVELL_E1000     0x0000
+#define MII_MODEL_MARVELL_E1011     0x0002
+#define MII_MODEL_MARVELL_E1000_3   0x0003
+#define MII_MODEL_MARVELL_E1000S    0x0004
+#define MII_MODEL_MARVELL_E1000_5   0x0005
+#define MII_MODEL_MARVELL_E1000_6   0x0006
+#define MII_MODEL_MARVELL_E3082     0x0008
+#define MII_MODEL_MARVELL_E1112     0x0009
+#define MII_MODEL_MARVELL_E1149     0x000b
+#define MII_MODEL_MARVELL_E1111     0x000c
+#define MII_MODEL_MARVELL_E1116     0x0021
+#define MII_MODEL_MARVELL_E1116R    0x0024
+#define MII_MODEL_MARVELL_E1118     0x0022
+#define MII_MODEL_MARVELL_E3016     0x0026
+#define MII_MODEL_MARVELL_PHYG65G   0x0027
+#define MII_MODEL_xxMARVELL_E1000   0x0000
+#define MII_MODEL_xxMARVELL_E1011   0x0002
+#define MII_MODEL_xxMARVELL_E1000_3 0x0003
+#define MII_MODEL_xxMARVELL_E1000_5 0x0005
+#define MII_MODEL_xxMARVELL_E1111   0x000c



+#define MII_STR_MARVELL_E1000       "Marvell 88E1000 Gigabit PHY"
+#define MII_STR_MARVELL_E1011       "Marvell 88E1011 Gigabit PHY"
+#define MII_STR_MARVELL_E1000_3     "Marvell 88E1000_3 Gigabit PHY"
+#define MII_STR_MARVELL_E1000S      "Marvell 88E1000S Gigabit PHY"
+#define MII_STR_MARVELL_E1000_5     "Marvell 88E1000_5 Gigabit PHY"
+#define MII_STR_MARVELL_E1000_6     "Marvell 88E1000_6 Gigabit PHY"
+#define MII_STR_MARVELL_E3082       "Marvell 88E3082 10/100 Fast Ethernet PHY"
+#define MII_STR_MARVELL_E1112       "Marvell 88E1112 Gigabit PHY"
+#define MII_STR_MARVELL_E1149       "Marvell 88E1149 Gigabit PHY"
+#define MII_STR_MARVELL_E1111       "Marvell 88E1111 Gigabit PHY"
+#define MII_STR_MARVELL_E1116       "Marvell 88E1116 Gigabit PHY"
+#define MII_STR_MARVELL_E1116R      "Marvell 88E1116R Gigabit PHY"
+#define MII_STR_MARVELL_E1118       "Marvell 88E1118 Gigabit PHY"
+#define MII_STR_MARVELL_E3016       "Marvell 88E3016 10/100 Fast Ethernet PHY"
+#define MII_STR_MARVELL_PHYG65G     "Marvell PHYG65G Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000     "Marvell 88E1000 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1011     "Marvell 88E1011 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000_3   "Marvell 88E1000_3 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000_5   "Marvell 88E1000_5 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1111     "Marvell 88E1111 Gigabit PHY"



+/*


Used to attach a PHY to a parent.


*/

+struct mii_attach_args {

struct mii_data *mii_data;  /* pointer to parent data */
INTN mii_id1;      /* PHY ID register 1 */
INTN mii_id2;      /* PHY ID register 2 */

+};



+/*


Used to match a PHY.


*/

+struct mii_phydesc {

UINT32      mpd_oui;    /* the PHY's OUI */
UINT32      mpd_model;  /* the PHY's model */
const CHAR8 *mpd_name;  /* the PHY's name */

+};
+#define MII_PHY_DESC(a, b)          { MII_OUI_ ## a, MII_MODEL_ ## a ## _ ## b, MII_STR_ ## a ## _ ## b }
+#define MII_PHY_END                 { 0, 0, NULL }



+#define PHY_READ(p, r)              msk_phy_readreg ((p)->mmd->port, (r))



+#define PHY_WRITE(p, r, v)          msk_phy_writereg ((p)->mmd->port, (r), (v))



+struct msk_mii_data {

INTN    port;
UINT32  pmd;
INTN    mii_flags;

+};



+EFI_STATUS e1000_probe_and_attach (struct mii_data *mii, const struct msk_mii_data *mmd);
+void e1000phy_tick (void);
+void e1000phy_mediachg (void);



+#endif /* _DEV_MII_MIIVAR_H_ */
diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc
index 7f030a7..bedbfb8 100644
--- a/Platforms/ARM/Juno/ArmJuno.dsc
+++ b/Platforms/ARM/Juno/ArmJuno.dsc
@@ -133,6 +133,9 @@
    gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628
    gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|40000

# MarvellYukonDxe Ethernet Driver
# gEmbeddedTokenSpaceGuid.PcdYukonMacAddress|0x0000A26000F70200
#
  # ARM General Interrupt Controller
  #

@@ -197,6 +200,11 @@
    # PCI support.
    gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE

#
# Set boot timeout for Boot Manager
#
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|7
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform

@@ -285,6 +293,7 @@
    # Networking stack
    #
    EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf

OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
#
 # Usb Support


diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf
index db2cfa9..e486a33 100644
--- a/Platforms/ARM/Juno/ArmJuno.fdf
+++ b/Platforms/ARM/Juno/ArmJuno.fdf
@@ -187,6 +187,7 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
    INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
    INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
    INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf

INF OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
#
 # UEFI applications


--
2.7.4

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Re: [Linaro-uefi] [edk2] [PATCH] OpenPlatformPkg/MarvellYukonDxe : Marvell Yukon driver