So, I had another look at a bit of this patch that concerns me.
*trimming down*
On Tue, Oct 18, 2016 at 09:09:49PM +0800, Heyi Guo wrote:
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 730bdb0..dd851bc 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -25,17 +25,20 @@ static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; -UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000};
UINT64 io_sub0_base = 0xa0000000; UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) -UINT64 PCIE_APB_SLAVE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
{0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
-UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
{0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
+//The extern pcie addresses will be initialized by oemmisclib +extern UINT64 pcie_subctrl_base_1610[2][8]; +extern UINT64 PCIE_APB_SLAVE_BASE_1610[2][8]; +extern UINT64 PCIE_PHY_BASE_1610[2][8]; +extern UINT64 PCIE_ITS_1610[2][8];
All of these declarations live in a C file rather than a shared header.
UINT32 loop_test_flag[4] = {0,0,0,0}; UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; #define PcieMaxLanNum 8 +#define PCIE_PORT_NUM_IN_SICL 4 extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
...
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index c709f8b..75b23d5 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -30,6 +30,15 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, {0xFFFF,0xFFFF,0xFFFF,0xFFFF} }; +UINT64 pcie_subctrl_base_1610[2][8] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},
{0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000,}};
+UINT64 PCIE_APB_SLAVE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
{0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
+UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
{0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
+UINT64 PCIE_ITS_1610[2][4] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},
{0xc6010040,0xc6010040, 0xc6010040, 0xc6010040}};
Yet in the .c file where they are actually defined, most of these describe a different geometry than the definition.
The prototypes need to move out of C files and live in a shared header. The hard-coded geometry needs to be replaced by platform-specific defines that are used both in that shared header and in the particular OemLib implementation.
/ Leif
// Right now we only support 1P BOOLEAN OemIsSocketPresent (UINTN Socket)