Re: [Linaro-uefi] [linaro-uefi v5 10/44] Platforms/Hisilicon: add D05 platform modules and files

2 Dec 2016

None of my comments on v4 appear to have been addressed.
Regards,
Leif
On Fri, Dec 02, 2016 at 12:13:03PM +0800, Heyi Guo wrote:
...
D05 is a new Hisilicon reference hardware platform, which is a dual
socket SMP system and has 32 cores on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo heyi.guo@linaro.org

Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h |  78 +++
 Chips/Hisilicon/HisiPkg.dec                        |   3 +
 Platforms/Hisilicon/D05/D05.dsc                    | 674 +++++++++++++++++++++
 Platforms/Hisilicon/D05/D05.fdf                    | 366 +++++++++++
 .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c       |  61 ++
 .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf     |  53 ++
 .../D05/Library/OemMiscLibD05/BoardFeatureD05.c    | 218 +++++++
 .../OemMiscLibD05/BoardFeatureD05Strings.uni       |  56 ++
 .../D05/Library/OemMiscLibD05/OemMiscLibD05.c      | 107 ++++
 .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf    |  55 ++
 .../D05/Library/PlatformPciLib/PlatformPciLib.c    | 279 +++++++++
 .../D05/Library/PlatformPciLib/PlatformPciLib.inf  | 183 ++++++
 12 files changed, 2133 insertions(+)
 create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
 create mode 100644 Platforms/Hisilicon/D05/D05.dsc
 create mode 100644 Platforms/Hisilicon/D05/D05.fdf
 create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
 create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
 create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
 create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
 create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
 create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
 create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
 create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf

diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..4bc1c91
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
@@ -0,0 +1,78 @@
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_



+typedef enum hilink0_mode_type
+{

EM_HILINK0_HCCS1_8LANE = 0,
EM_HILINK0_PCIE1_8LANE = 2,
EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
EM_HILINK0_SAS2_8LANE = 4,
EM_HILINK0_HCCS1_8LANE_16,
EM_HILINK0_HCCS1_8LANE_32,
EM_HILINK0_HCCS1_8LANE_5000,

+}hilink0_mode_type_e;



+typedef enum hilink1_mode_type
+{

EM_HILINK1_SAS2_1LANE = 0,
EM_HILINK1_HCCS0_8LANE = 1,
EM_HILINK1_PCIE0_8LANE = 2,
EM_HILINK1_HCCS0_8LANE_16,
EM_HILINK1_HCCS0_8LANE_32,
EM_HILINK1_HCCS0_8LANE_5000,

+}hilink1_mode_type_e;



+typedef enum hilink2_mode_type
+{

EM_HILINK2_PCIE2_8LANE = 0,
EM_HILINK2_HCCS2_8LANE = 1,
EM_HILINK2_SAS0_8LANE = 2,
EM_HILINK2_HCCS2_8LANE_16,
EM_HILINK2_HCCS2_8LANE_32,
EM_HILINK2_HCCS2_8LANE_5000,

+}hilink2_mode_type_e;



+typedef enum hilink5_mode_type
+{

EM_HILINK5_PCIE3_4LANE = 0,
EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
EM_HILINK5_SAS1_4LANE = 2,


+}hilink5_mode_type_e;




+typedef struct serdes_param
+{

hilink0_mode_type_e hilink0_mode;
hilink1_mode_type_e hilink1_mode;
hilink2_mode_type_e hilink2_mode;
UINT32 hilink3_mode;
UINT32 hilink4_mode;
hilink5_mode_type_e hilink5_mode;
UINT32 hilink6_mode;
UINT32 use_ssc;
//board_type_e board_type;

+}serdes_param_t;



+#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
+#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF



+typedef struct {

UINT32 MacroId;
UINT32 DsNum;
UINT32 DsCfg;

+} SERDES_POLARITY_INVERT;



+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+void serdes_enable_ctle_dfe(UINT32 nimbus_id, UINT32 macro, UINT32 lane, UINT32 lane_mode);



+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+INT32 SerdesReset(UINT32 SiclId, UINT32 Macro);
+VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);



+#endif
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec
index 0faa100..2c02e14 100644
--- a/Chips/Hisilicon/HisiPkg.dec
+++ b/Chips/Hisilicon/HisiPkg.dec
@@ -104,7 +104,10 @@
   gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008
   gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009
   gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a

gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b


gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c
gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d

gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc
new file mode 100644
index 0000000..edaad18
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.dsc
@@ -0,0 +1,674 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#



+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]

PLATFORM_NAME                  = D05
PLATFORM_GUID                  = D0D445F1-B2CA-4101-9986-1B23525CBEA6
PLATFORM_VERSION               = 0.1
DSC_SPECIFICATION              = 0x00010019
OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
SUPPORTED_ARCHITECTURES        = AARCH64
BUILD_TARGETS                  = DEBUG|RELEASE
SKUID_IDENTIFIER               = DEFAULT
FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
DEFINE EDK2_SKIP_PEICORE=0
DEFINE INCLUDE_TFTP_COMMAND=1
DEFINE NETWORK_IP6_ENABLE      = FALSE
DEFINE HTTP_BOOT_ENABLE        = FALSE


+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc



+[LibraryClasses.common]

ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf


I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf

IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf

NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf


+!if $(NETWORK_IP6_ENABLE) == TRUE

TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf

+!endif



+!if $(HTTP_BOOT_ENABLE) == TRUE

HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf

+!endif



+!ifdef $(FDT_ENABLE)

#FDTUpdateLib
FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf

+!endif #$(FDT_ENABLE)


CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf

SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf

EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
#D05 RTC hardware is same as D03
RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf

OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf

CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf

# USB Requirements
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf

LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf


+[LibraryClasses.common.SEC]

ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf



+[LibraryClasses.common.DXE_RUNTIME_DRIVER]

I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf


+[BuildOptions]

GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include


+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################



+[PcdsFeatureFlag.common]



+!if $(EDK2_SKIP_PEICORE) == 1

gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE

+!endif


## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
#  It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE


+[PcdsFixedAtBuild.common]

gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"

gArmPlatformTokenSpaceGuid.PcdCoreCount|8

gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000

# Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000

# Stacks for MPCores in Monitor Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100

# Stacks for MPCores in Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00

gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000


gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000


# Size of the region used by UEFI in permanent memory (Reserved 64MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000

gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1


#
# ARM Pcds
#
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000

gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2


gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
                                           # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15


gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
                                           # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15



## SP805 Watchdog - Motherboard Watchdog
gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000

## Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200

gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000

gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
# use the TTY terminal type (which has a working backspace)
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4


gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000


gHisiTokenSpaceGuid.PcdIsMPBoot|1
gHisiTokenSpaceGuid.PcdSocketMask|0x3
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"

gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"

gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"

gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"

gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"


gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000


# Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"

#
# ARM Architectual Timer Frequency
#
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000


gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }

gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8

gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000

gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000


gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128


gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000


gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000

## DTB address at spi flash
gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000

gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1

gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000

gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000

gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000

gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000

gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
gHisiTokenSpaceGuid.PcdNumaEnable|1
gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000

gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000


gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000

gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000

gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K

gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K

gHisiTokenSpaceGuid.Pcdsoctype|0x1610


+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]


#
# SEC
#

#
# PEI Phase modules
#
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf

ArmPlatformPkg/PlatformPei/PlatformPeim.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf

MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>

 NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf


}

#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>

 NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf


}
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf

#
# Architectural Protocols
#
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf

MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
# Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
#MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>

 NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf


}
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf

MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>

 CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf


}
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

# Simple TextIn/TextOut for UEFI Terminal
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf

MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

ArmPkg/Drivers/ArmGic/ArmGicDxe.inf

ArmPkg/Drivers/TimerDxe/TimerDxe.inf

ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
#
#ACPI
#
OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf

OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf

#
# Usb Support
#
OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf

#
#network
#
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf

MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf

+!if $(NETWORK_IP6_ENABLE) == TRUE

NetworkPkg/Ip6Dxe/Ip6Dxe.inf
NetworkPkg/TcpDxe/TcpDxe.inf
NetworkPkg/Udp6Dxe/Udp6Dxe.inf
NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf

+!else

MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf

+!endif

MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf

+!if $(HTTP_BOOT_ENABLE) == TRUE

NetworkPkg/DnsDxe/DnsDxe.inf
NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
NetworkPkg/HttpDxe/HttpDxe.inf
NetworkPkg/HttpBootDxe/HttpBootDxe.inf

+!endif



OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf

#
# FAT filesystem + GPT/MBR partitioning
#

OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
#
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf

MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf


+!ifdef $(FDT_ENABLE)

OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf

+!endif #$(FDT_ENABLE)


#PCIe Support
OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>

 NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf


}
OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>

 NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf


}

MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf


OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf

#
# Memory test
#
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>

 ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf


 NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf


 NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf


 HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf


 PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf


 BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf



+!if $(NETWORK_IP6_ENABLE) == TRUE

 NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf



+!endif



+!ifdef $(INCLUDE_DP)

 NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf



+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)

 NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf



+!endif #$(INCLUDE_TFTP_COMMAND)


<PcdsFixedAtBuild>

 gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF


 gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE


 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000


}

diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf
new file mode 100644
index 0000000..bdfb211
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.fdf
@@ -0,0 +1,366 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#



+[DEFINES]



+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.D05]



+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.



+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1



+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30



+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################



+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv



+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT



+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin
+0x002A0000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin



+0x002D0000|0x0000E000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {

## This is the EFI_FIRMWARE_VOLUME_HEADER
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
# FileSystemGuid: gEfiSystemNvDataFvGuid         =
0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
# FvLength: 0x20000
0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
#Signature "_FVH"       #Attributes
0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
#HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
#Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
#Blockmap[1]: End
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
#Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
0xB8, 0xdF, 0x00, 0x00,
#FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+}



+0x002DE000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {

# EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
# Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
# WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+}



+0x002E0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize



+0x002F0000|0x00010000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv



+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################



+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE


APRIORI DXE {
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
}

INF MdeModulePkg/Core/Dxe/DxeMain.inf
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf

INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf


INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf

INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

#
# Multiple Console IO support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

# Simple TextIn/TextOut for UEFI Terminal

INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf

INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf

#
# FAT filesystem + GPT/MBR partitioning
#
INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatBinPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf

#
# Usb Support
#

INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf

INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf


INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf

INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf

#
#ACPI
#
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf

INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf

#
#Network
#

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf

INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf

+!if $(NETWORK_IP6_ENABLE) == TRUE

INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
INF NetworkPkg/TcpDxe/TcpDxe.inf
INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf

+!else

INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf

+!endif

INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf

+!if $(HTTP_BOOT_ENABLE) == TRUE

INF NetworkPkg/DnsDxe/DnsDxe.inf
INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
INF NetworkPkg/HttpDxe/HttpDxe.inf
INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf

+!endif



+!ifdef $(FDT_ENABLE)

INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf

+!endif #$(FDT_ENABLE)


#
# PCI Support
#
INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
# VGA Driver
#
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf

#
# Build Shell from latest source code instead of prebuilt binary
#
INF ShellPkg/Application/Shell/Shell.inf

#
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf


+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE


APRIORI PEI {
INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
}
INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf

INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf

INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
 SECTION FV_IMAGE = FVMAIN


}
}



+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc



diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
new file mode 100644
index 0000000..55aacc8
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
@@ -0,0 +1,61 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/




+#include <PiPei.h>
+#include <PlatformArch.h>
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>



+VOID QResetAp(VOID)
+{

MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
(VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);

if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
   StartupAp();


}

+}




+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (

IN       EFI_PEI_FILE_HANDLE  FileHandle,
IN CONST EFI_PEI_SERVICES     **PeiServices
)

+{

DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
(VOID)SmmuConfigForBios();
DEBUG((DEBUG_INFO,"Done\n"));

DEBUG((DEBUG_INFO,"AP CONFIG........."));
(VOID)QResetAp();
DEBUG((DEBUG_INFO,"Done\n"));

DEBUG((DEBUG_INFO,"MN CONFIG........."));
(VOID)MN_CONFIG();
DEBUG((DEBUG_INFO,"Done\n"));

return EFI_SUCCESS;

+}



diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
new file mode 100644
index 0000000..5fdf555
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/




+[Defines]

INF_VERSION                    = 0x00010019
BASE_NAME                      = EarlyConfigPeimD05
FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
MODULE_TYPE                    = PEIM
VERSION_STRING                 = 1.0
ENTRY_POINT                    = EarlyConfigEntry


+[Sources.common]

EarlyConfigPeimD05.c


+[Packages]

ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec


+[LibraryClasses]

ArmLib
CacheMaintenanceLib
DebugLib
IoLib
PcdLib
PeimEntryPoint
PlatformSysCtrlLib


+[Pcd]

gHisiTokenSpaceGuid.PcdMailBoxAddress
gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable


+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete

gEfiPeiMemoryDiscoveredPpiGuid


+[BuildOptions]



diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
new file mode 100644
index 0000000..f49b2bc
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
@@ -0,0 +1,218 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+#include <PlatformArch.h>
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Protocol/Smbios.h>




+I2C_DEVICE gDS3231RtcDevice = {

.Socket = 0,
.Port = 4,
.DeviceType = DEVICE_TYPE_SPD,
.SlaveDeviceAddress = 0x68

+};



+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {

{SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}

+};



+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {

{SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}

+};



+serdes_param_t gSerdesParamNA = {

.hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
.hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
.hilink2_mode = EM_HILINK2_PCIE2_8LANE,
.hilink3_mode = 0x0,
.hilink4_mode = 0xF,
.hilink5_mode = EM_HILINK5_SAS1_4LANE,
.hilink6_mode = 0x0,
.use_ssc      = 0,
};


+serdes_param_t gSerdesParamNB = {

.hilink0_mode = EM_HILINK0_PCIE1_8LANE,
.hilink1_mode = EM_HILINK1_PCIE0_8LANE,
.hilink2_mode = EM_HILINK2_SAS0_8LANE,
.hilink3_mode = 0x0,
.hilink4_mode = 0xF,
.hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
.hilink6_mode = 0xF,
.use_ssc      = 0,
};


+serdes_param_t gSerdesParamS1NA = {

.hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
.hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
.hilink2_mode = EM_HILINK2_PCIE2_8LANE,
.hilink3_mode = 0x0,
.hilink4_mode = 0xF,
.hilink5_mode = EM_HILINK5_SAS1_4LANE,
.hilink6_mode = 0x0,
.use_ssc      = 0,
};


+serdes_param_t gSerdesParamS1NB = {

.hilink0_mode = EM_HILINK0_PCIE1_8LANE,
.hilink1_mode = EM_HILINK1_PCIE0_8LANE,
.hilink2_mode = EM_HILINK2_SAS0_8LANE,
.hilink3_mode = 0x0,
.hilink4_mode = 0xF,
.hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
.hilink6_mode = 0xF,
.use_ssc      = 0,
};



+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId)
+{

if ( ParamA == NULL) {
DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
return EFI_INVALID_PARAMETER;
}
if (ParamB == NULL) {
DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
return EFI_INVALID_PARAMETER;
}

if(SocketId == 0) {
(VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
(VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
} else {
(VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
(VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
}

return EFI_SUCCESS;

+}



+VOID OemPcieResetAndOffReset(VOID)
+{

return;

+}



+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {

// PCIe0 Slot 1
{
   {                                                     // Hdr


       EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,


       0,                                                    // Length,


       0                                                     // Handle


   },


   1,                                                    // SlotDesignation


   SlotTypePciExpressX8,     // SlotType


   SlotDataBusWidth8X,       // SlotDataBusWidth


   SlotUsageAvailable,       // SlotUsage


   SlotLengthOther,          // SlotLength


   0x0001,                   // SlotId


   {                         // SlotCharacteristics1


       0,                      // CharacteristicsUnknown  :1;


       0,                      // Provides50Volts         :1;


       0,                      // Provides33Volts         :1;


       0,                      // SharedSlot              :1;


       0,                      // PcCard16Supported       :1;


       0,                      // CardBusSupported        :1;


       0,                      // ZoomVideoSupported      :1;


       0                       // ModemRingResumeSupported:1;


   },


   {                         // SlotCharacteristics2


       0,                      // PmeSignalSupported      :1;


       0,                      // HotPlugDevicesSupported  :1;


       0,                      // SmbusSignalSupported    :1;


       0                       // Reserved                :5;


   },


   0x00,                     // SegmentGroupNum


   0x00,                     // BusNum


   0                         // DevFuncNum


},

// PCIe0 Slot 4
{
   {                                                     // Hdr


       EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,


       0,                                                    // Length,


       0                                                     // Handle


   },


   1,                                                    // SlotDesignation


   SlotTypePciExpressX8,     // SlotType


   SlotDataBusWidth8X,       // SlotDataBusWidth


   SlotUsageAvailable,       // SlotUsage


   SlotLengthOther,          // SlotLength


   0x0004,                   // SlotId


   {                         // SlotCharacteristics1


       0,                      // CharacteristicsUnknown  :1;


       0,                      // Provides50Volts         :1;


       0,                      // Provides33Volts         :1;


       0,                      // SharedSlot              :1;


       0,                      // PcCard16Supported       :1;


       0,                      // CardBusSupported        :1;


       0,                      // ZoomVideoSupported      :1;


       0                       // ModemRingResumeSupported:1;


   },


   {                         // SlotCharacteristics2


       0,                      // PmeSignalSupported      :1;


       0,                      // HotPlugDevicesSupported  :1;


       0,                      // SmbusSignalSupported    :1;


       0                       // Reserved                :5;


   },


   0x00,                     // SegmentGroupNum


   0x00,                     // BusNum


   0                         // DevFuncNum


}

+};




+UINT8 OemGetPcieSlotNumber ()
+{

return  sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);

+}



+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {

{{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},

{{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
{STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}

+};



+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (

)

+{

return HiiAddPackages (
                   &gEfiCallerIdGuid,


                   NULL,


                   OemMiscLibHi1616EvbStrings,


                   NULL,


                   NULL


                   );



+}




diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
new file mode 100644
index 0000000..9f5be02
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
@@ -0,0 +1,56 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/



+/=#



+#langdef en-US "English"



+//
+// Begin English Language Strings
+//
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"



+//
+// DIMM Device Locator strings



+#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
+#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
+#string STR_LEMON_C10_DIMM_002     #language en-US "J7"
+#string STR_LEMON_C10_DIMM_010     #language en-US "J8"
+#string STR_LEMON_C10_DIMM_011     #language en-US "J9"
+#string STR_LEMON_C10_DIMM_012     #language en-US "J10"
+#string STR_LEMON_C10_DIMM_020     #language en-US "J11"
+#string STR_LEMON_C10_DIMM_021     #language en-US "J12"
+#string STR_LEMON_C10_DIMM_022     #language en-US "J13"
+#string STR_LEMON_C10_DIMM_030     #language en-US "J14"
+#string STR_LEMON_C10_DIMM_031     #language en-US "J15"
+#string STR_LEMON_C10_DIMM_032     #language en-US "J16"
+#string STR_LEMON_C10_DIMM_100     #language en-US "J17"
+#string STR_LEMON_C10_DIMM_101     #language en-US "J18"
+#string STR_LEMON_C10_DIMM_102     #language en-US "J19"
+#string STR_LEMON_C10_DIMM_110     #language en-US "J20"
+#string STR_LEMON_C10_DIMM_111     #language en-US "J21"
+#string STR_LEMON_C10_DIMM_112     #language en-US "J22"
+#string STR_LEMON_C10_DIMM_120     #language en-US "J23"
+#string STR_LEMON_C10_DIMM_121     #language en-US "J24"
+#string STR_LEMON_C10_DIMM_122     #language en-US "J25"
+#string STR_LEMON_C10_DIMM_130     #language en-US "J26"
+#string STR_LEMON_C10_DIMM_131     #language en-US "J27"
+#string STR_LEMON_C10_DIMM_132     #language en-US "J28"



+//
+// End English Language Strings
+//



diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
new file mode 100644
index 0000000..149bb7d
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
@@ -0,0 +1,107 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/



+#include <PlatformArch.h>
+#include <Uefi.h>



+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/LpcLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>



+#define OEM_SINGLE_SOCKET 1
+#define OEM_DUAL_SOCKET 2



+REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {

 {67,0,0,0},


 {225,0,0,3},


 {0xFFFF,0xFFFF,0xFFFF,0xFFFF},


 {0xFFFF,0xFFFF,0xFFFF,0xFFFF}



+};




+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{

if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
return TRUE;
} else {
return FALSE;
}

+}




+UINTN OemGetSocketNumber (VOID)
+{


if(!OemIsMpBoot()) {
return OEM_SINGLE_SOCKET;
}

return OEM_DUAL_SOCKET;

+}




+UINTN OemGetDdrChannel (VOID)
+{

return 4;

+}




+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{

return 2;

+}



+VOID CoreSelectBoot(VOID)
+{

if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
 StartupAp ();


}

return;

+}



+BOOLEAN OemIsMpBoot()
+{

return PcdGet32(PcdIsMPBoot);

+}



+VOID OemLpcInit(VOID)
+{

LpcInit();
return;

+}



+UINT32 OemIsWarmBoot(VOID)
+{

return 0;

+}



+VOID OemBiosSwitch(UINT32 Master)
+{

(VOID)Master;
return;

+}



+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID)
+{

return TRUE;

+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
new file mode 100644
index 0000000..b2f41b8
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -0,0 +1,55 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/



+[Defines]

INF_VERSION                    = 0x00010019
BASE_NAME                      = OemMiscLibHi1616Evb
FILE_GUID                      = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
MODULE_TYPE                    = BASE
VERSION_STRING                 = 1.0
LIBRARY_CLASS                  = OemMiscLib


+[Sources.common]

BoardFeatureD05.c
BoardFeatureD05Strings.uni
OemMiscLibD05.c


+[Packages]

ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec


+[LibraryClasses]

PcdLib
TimerLib


+[BuildOptions]



+[Ppis]

gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES


+[Pcd]

gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
gHisiTokenSpaceGuid.PcdIsMPBoot
gHisiTokenSpaceGuid.PcdSocketMask
gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable


+[FixedPcd.common]



+[Guids]



+[Protocols]



diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000..57283a1
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,279 @@
+/** @file


Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>

This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution.  The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.


+**/



+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>



+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},

                                   {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};



+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},

                                    {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};



+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},

                            {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};



+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},

                      {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};




+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {

{// HostBridge 0
/* Port 0 */
{
 PCI_HB0RB0_ECAM_BASE, //ecam


 0x80,  //BusBase


 0x87, //BusLimit


 PCI_HB0RB0_PCIREGION_BASE, //Membase


 PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit


 PCI_HB0RB0_IO_BASE,  //IoBase


 (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB0_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB0_PCI_BASE),//RbPciBar


 PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 1 */
{
 PCI_HB0RB1_ECAM_BASE,//ecam


 0x90,  //BusBase


 0x97, //BusLimit


 PCI_HB0RB1_PCIREGION_BASE, //Membase


 PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit


 (PCI_HB0RB1_IO_BASE),  //IoBase


 (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit


 PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB1_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB1_PCI_BASE),  //RbPciBar


 PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 2 */
{
 PCI_HB0RB2_ECAM_BASE,


 0x80,  //BusBase


 0x87, //BusLimit


 PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase


 PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit


 (PCI_HB0RB2_IO_BASE),  //IOBase


 (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit


 PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB2_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB2_PCI_BASE),  //RbPciBar


 PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit


},

/* Port 3 */
{
 PCI_HB0RB3_ECAM_BASE,


 0xb0,  //BusBase


 0xb7, //BusLimit


 (PCI_HB0RB3_ECAM_BASE),  //MemBase


 (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit


 (PCI_HB0RB3_IO_BASE), //IoBase


 (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1),  //IoLimit


 PCI_HB0RB3_CPUMEMREGIONBASE,


 PCI_HB0RB3_CPUIOREGIONBASE,


 (PCI_HB0RB3_PCI_BASE),  //RbPciBar


 PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 4 */
{
 PCI_HB0RB4_ECAM_BASE, //ecam


 0x88,  //BusBase


 0x8f, //BusLimit


 PCI_HB0RB4_CPUMEMREGIONBASE, //Membase


 PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit


 PCI_HB0RB4_IO_BASE,  //IoBase


 (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit


 PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB4_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB4_PCI_BASE),  //RbPciBar


 PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 5 */
{
 PCI_HB0RB5_ECAM_BASE,//ecam


 0x0,  //BusBase


 0x7, //BusLimit


 PCI_HB0RB5_CPUMEMREGIONBASE, //Membase


 PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit


 (PCI_HB0RB5_IO_BASE),  //IoBase


 (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit


 PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB5_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB5_PCI_BASE),  //RbPciBar


 PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 6 */
{
 PCI_HB0RB6_ECAM_BASE,


 0xC0,  //BusBase


 0xC7, //BusLimit


 PCI_HB0RB6_PCIREGION_BASE ,//MemBase


 PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit


 (PCI_HB0RB6_IO_BASE),  //IOBase


 (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit


 PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB0RB6_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB0RB6_PCI_BASE),  //RbPciBar


 PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit


},

/* Port 7 */
{
 PCI_HB0RB7_ECAM_BASE,


 0x90,  //BusBase


 0x97, //BusLimit


 PCI_HB0RB7_CPUMEMREGIONBASE,  //MemBase


 PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit


 (PCI_HB0RB7_IO_BASE), //IoBase


 (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1),  //IoLimit


 PCI_HB0RB7_CPUMEMREGIONBASE,


 PCI_HB0RB7_CPUIOREGIONBASE,


 (PCI_HB0RB7_PCI_BASE),  //RbPciBar


 PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase


 PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit


}
},

+{// HostBridge 1

/* Port 0 */
{
 PCI_HB1RB0_ECAM_BASE,


 0x80,  //BusBase


 0x87, //BusLimit


 (PCI_HB1RB0_ECAM_BASE),  //MemBase


 (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit


 PCI_HB1RB0_IO_BASE, //IoBase


 (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB0_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB0_PCI_BASE),  //RbPciBar


 PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 1 */
{
 PCI_HB1RB1_ECAM_BASE,


 0x90,  //BusBase


 0x97, //BusLimit


 (PCI_HB1RB1_ECAM_BASE),  //MemBase


 (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit


 PCI_HB1RB1_IO_BASE, //IoBase


 (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB1_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB1_PCI_BASE),  //RbPciBar


 PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 2 */
{
 PCI_HB1RB2_ECAM_BASE,


 0x10,  //BusBase


 0x1f, //BusLimit


 PCI_HB1RB2_CPUMEMREGIONBASE,  //MemBase


 PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit


 PCI_HB1RB2_IO_BASE, //IoBase


 (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB2_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB2_PCI_BASE),  //RbPciBar


 PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit


},

/* Port 3 */
{
 PCI_HB1RB3_ECAM_BASE,


 0xb0,  //BusBase


 0xb7, //BusLimit


 (PCI_HB1RB3_ECAM_BASE),  //MemBase


 (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit


 PCI_HB1RB3_IO_BASE, //IoBase


 (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB3_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB3_PCI_BASE),  //RbPciBar


 PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 4 */
{
 PCI_HB1RB4_ECAM_BASE,


 0x20,  //BusBase


 0x2f, //BusLimit


 PCI_HB1RB4_CPUMEMREGIONBASE,  //MemBase


 PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit


 PCI_HB1RB4_IO_BASE, //IoBase


 (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB4_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB4_PCI_BASE),  //RbPciBar


 PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 5 */
{
 PCI_HB1RB5_ECAM_BASE,


 0x30,  //BusBase


 0x3f, //BusLimit


 PCI_HB1RB5_CPUMEMREGIONBASE,  //MemBase


 PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit


 PCI_HB1RB5_IO_BASE, //IoBase


 (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB5_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB5_PCI_BASE),  //RbPciBar


 PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit


},
/* Port 6 */
{
 PCI_HB1RB6_ECAM_BASE,


 0xa8,  //BusBase


 0xaf, //BusLimit


 (PCI_HB1RB6_ECAM_BASE),  //MemBase


 PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit


 PCI_HB1RB6_IO_BASE, //IoBase


 (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB6_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB6_PCI_BASE),  //RbPciBar


 PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit


},

/* Port 7 */
{
 PCI_HB1RB7_ECAM_BASE,


 0xb8,  //BusBase


 0xbf, //BusLimit


 (PCI_HB1RB7_ECAM_BASE),  //MemBase


 PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit


 PCI_HB1RB7_IO_BASE, //IoBase


 (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit


 PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase


 PCI_HB1RB7_CPUIOREGIONBASE,  //CpuIoRegionBase


 (PCI_HB1RB7_PCI_BASE),  //RbPciBar


 PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase


 PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit


}

}

+};



diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000..8e013ca
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,183 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##



+[Defines]

INF_VERSION                    = 0x00010019
BASE_NAME                      = PlatformPciLib
FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
MODULE_TYPE                    = BASE
VERSION_STRING                 = 1.0


+[Sources]

PlatformPciLib.c


+[Packages]

MdePkg/MdePkg.dec
OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec


+[LibraryClasses]

PcdLib


+[FixedPcd]

gHisiTokenSpaceGuid.PcdHb1BaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
gHisiTokenSpaceGuid.PciHb0Rb0Base
gHisiTokenSpaceGuid.PciHb0Rb1Base
gHisiTokenSpaceGuid.PciHb0Rb2Base
gHisiTokenSpaceGuid.PciHb0Rb3Base
gHisiTokenSpaceGuid.PciHb0Rb4Base
gHisiTokenSpaceGuid.PciHb0Rb5Base
gHisiTokenSpaceGuid.PciHb0Rb6Base
gHisiTokenSpaceGuid.PciHb0Rb7Base
gHisiTokenSpaceGuid.PciHb1Rb0Base
gHisiTokenSpaceGuid.PciHb1Rb1Base
gHisiTokenSpaceGuid.PciHb1Rb2Base
gHisiTokenSpaceGuid.PciHb1Rb3Base
gHisiTokenSpaceGuid.PciHb1Rb4Base
gHisiTokenSpaceGuid.PciHb1Rb5Base
gHisiTokenSpaceGuid.PciHb1Rb6Base
gHisiTokenSpaceGuid.PciHb1Rb7Base
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
gHisiTokenSpaceGuid.PcdHb1Rb7IoSize


-- 
1.9.1

    

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Re: [Linaro-uefi] [linaro-uefi v5 10/44] Platforms/Hisilicon: add D05 platform modules and files