2 Aug
2018
2 Aug
'18
6:24 p.m.
On 2 August 2018 at 20:13, Leif Lindholm leif.lindholm@linaro.org wrote:
Graeme, Ard, do either of you have the stamina to go through all this, or will wi settle for testing it?
Well, without a SoC manual, it is rather difficult to review this in great detail.
I did give it a quick skim, and the only thing that looked peculiar to me is that all PCI root complexes use IRQs 640-643 for the legacy INTx interrupts for all slots. Also, there's a cacheline size value of 32 bytes somewhere. In summary, the code does not look wrong per se, but it does not necessarily look like it was put together with great diligence.