On 6 May 2016 at 12:08, Jan Dąbroś jsd@semihalf.com wrote:
Hi Shaveta,
I also use mmio not DMA for writing to SATA controller's registers.
Despite timeout (I comment out above code), it looks like problem with exchange of Frame Information Structures, memory isn't updated by hardware properly.
When you say 'memory isn't updated by hardware properly', that suggests there is some kind of bus mastering going on. Which memory are you talking about here? Is this memory that has been allocated by ArmDmaLib's AllocateBuffer()?
2016-05-06 11:15 GMT+02:00 Shaveta Leekha shaveta.leekha@nxp.com:
Hi,
I too am facing same error while running AHCI mode for SATA controller on my platform. I am not using DMA for any SATA controller's register read/write, instead using mmio read and write which is working fine.
What can be the probable issue. When in the code:
Status = AhciWaitMmioSet ( PciIo, Offset, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT );
Value "400010" is written on command register at offset 0x18h of Port 0 (MMIO address 3200118 for SATA 1 controller in my platform)
Though no hang occur bur FR bit is not getting set in "AhciWaitMmioSet"
"FIS Receive Running (FR): When set, the FIS Receive DMA engine for the port is running"
Thanks and Regards, Shaveta
-----Original Message----- From: Linaro-uefi [mailto:linaro-uefi-bounces@lists.linaro.org] On Behalf Of Ard Biesheuvel Sent: Thursday, May 05, 2016 12:59 AM To: Jan Dąbroś jsd@semihalf.com Cc: Haim Boot hayim@marvell.com; Neta Zur Hershkovits neta@marvell.com; Linaro UEFI Mailman List linaro-uefi@lists.linaro.org Subject: Re: [Linaro-uefi] PciEmulation - problem with AHCI
On 4 May 2016 at 19:21, Jan Dąbroś jsd@semihalf.com wrote:
Thanks for quick response.
I am using ArmDmaLib as DmaLib (also for XHCI), so it looks like problem other than cache coherency.
Indeed. Also, it seems the operation where the hang occurs does not involve a DMA transaction, does it? Can you confirm that the AHCI MMIO space is mapped correctly?
W dniu środa, 4 maja 2016 Ard Biesheuvel ard.biesheuvel@linaro.org napisał(a):
On 4 May 2016 at 18:52, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
On 4 May 2016 at 18:42, Jan Dąbroś jsd@semihalf.com wrote:
Hi Ard,
I am working on support for AHCI controller for my ARMv8 platform and I decide to use PciEmulation approach. I was able to run XHCI via PciEmulation without problems, but unfortunately with AHCI it isn't working.
Controller is compatible with AHCI specification. It isn't dma-coherent and I think that problem lies here. Initialization timeouts in below part of code:
// // Enable FIS Receive DMA engine for the first D2H FIS. // Offset = EFI_AHCI_PORT_START + Port *EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD; AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); Status = AhciWaitMmioSet ( PciIo, Offset, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT ); if (EFI_ERROR (Status)) { continue; }
Where do you think may be problem? Do you have any tips what should I try to do?
Are you using DmaLib? If you are, it is simply a matter of using ArmDmaLib, which uses uncached memory and/or explicit cache maintenance to perform non-coherent DMA. Basically, you need to implement the Allocate, free, map and unmap functions in the PCI I/O protocol using DmaLib methods, so you can use either coherent or non-coherent DMA depending on which version of the library you bind your driver to.
Also, make sure you set any I/O align fields in the protocol structures according to the CWG (max cacheline size) of your SoC. This will result in fewer cases where ArmDmaLib needs to use bounce buffering for streaming DMA.
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