PatchCheck.py also discovered an issue (on the opp-r20160712-upstream branch):
On Tue, Jul 12, 2016 at 09:44:36PM +0200, Marcin Wojtas wrote:
From: Jan Dąbroś jsd@semihalf.com
Marvell SoC's comprise multiplexed pins for SerDes lanes (XHCI, AHCI, SGMII, PCIe) called ComPhy.
ComPhyLib initialize ComPhy and ComPhy Mux. All configurable parameters are provided via set of PCDs.
In order to satisfy preprocessor demands, there are ComPhy PCDs for all of 4 possible chips.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/ComPhy.txt | 82 +++ Platforms/Marvell/Armada/Armada70x0.dsc | 1 + Platforms/Marvell/Include/Library/ComPhyLib.h | 43 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c | 290 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 812 ++++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 277 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 457 ++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 111 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 ++++ Platforms/Marvell/Marvell.dec | 51 ++ 10 files changed, 2256 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Platforms/Marvell/Include/Library/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c
diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/Marvell/PortingGuide/ComPhy.txt new file mode 100644 index 0000000..152671c --- /dev/null +++ b/Documentation/Marvell/PortingGuide/ComPhy.txt @@ -0,0 +1,82 @@ +COMPHY configuration +--------------------------- +In order to configure ComPhy library, following PCDs are available:
- gMarvellTokenSpaceGuid.PcdComPhyChipCount
+Indicates how many different chips are placed on board. So far, up to 4 chips +are supported.
- gMarvellTokenSpaceGuid.PcdIsZVersionChip
+Indicates if Z1 chip version is used.
+Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not +important, but configuration will be set for first PcdComPhyChipCount chips).
+Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this +chip. Below is example for the first chip (Chip0).
+General PCDs:
- gMarvellTokenSpaceGuid.PcdChip0Compatible
+Unicode string indicating type of chip - currently supported are +{ L"Ap806", L"Cp110"}
- gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress
+Indicates COMPHY unit base address.
- gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress
+Indicates Hpipe3 unit base address.
- gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount
+Indicates number of bits that are allocated for every MUX in the +COMPHY-selector register.
- gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes
+Indicates maximum ComPhy lanes number.
+Next three PCDs are in unicode string format containing settings for up to 10 +lanes. Setting for each one is separated with semicolon. Below is example for +the first chip (Chip0).
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+Unicode string indicating PHY types. Currently supported are:
+{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", +L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", +L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", +L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", +L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", +L"RXAUI1", L"KR" }
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+Indicates PHY speeds in MHz. Currently supported are:
+{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 }
- gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+Indicates lane polarity invert.
+Example +-------
From here
- #ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
- gMarvellTokenSpaceGuid.PcdIsZVersionChip|FALSE
- gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
- gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
- gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
- gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
- gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
to here - double CR line endings.
/ Leif