The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org --- Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + 3 files changed, 3 insertions(+)
diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 8cf0ada..7f030a7 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -121,6 +121,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|4 gArmPlatformTokenSpaceGuid.PL011UartFractional|0
diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 44e2105..c6d0b13 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -139,6 +139,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index fffbf28..78330d6 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -145,6 +145,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
On 30 March 2016 at 16:18, Ryan Harkin ryan.harkin@linaro.org wrote:
The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + 3 files changed, 3 insertions(+)
diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 8cf0ada..7f030a7 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -121,6 +121,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|4 gArmPlatformTokenSpaceGuid.PL011UartFractional|0
diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 44e2105..c6d0b13 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -139,6 +139,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index fffbf28..78330d6 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -145,6 +145,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
-- 2.5.0
On 03/30/16 16:23, Ard Biesheuvel wrote:
On 30 March 2016 at 16:18, Ryan Harkin ryan.harkin@linaro.org wrote:
The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
So, do you guys have good test results with this patch in Platforms/... and Ray's patch http://thread.gmane.org/gmane.comp.bios.edk2.devel/9880 in edk2? If so, please state it in the edk2-devel thread, so I can ACK Ray's patch.
Thanks Laszlo
Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + 3 files changed, 3 insertions(+)
diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 8cf0ada..7f030a7 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -121,6 +121,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|4 gArmPlatformTokenSpaceGuid.PL011UartFractional|0
diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 44e2105..c6d0b13 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -139,6 +139,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index fffbf28..78330d6 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -145,6 +145,7 @@ [PcdsFixedAtBuild.common] ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
-- 2.5.0
On 30 March 2016 at 23:16, Laszlo Ersek lersek@redhat.com wrote:
On 03/30/16 16:23, Ard Biesheuvel wrote:
On 30 March 2016 at 16:18, Ryan Harkin ryan.harkin@linaro.org wrote:
The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
So, do you guys have good test results with this patch in Platforms/... and Ray's patch http://thread.gmane.org/gmane.comp.bios.edk2.devel/9880 in edk2? If so, please state it in the edk2-devel thread, so I can ACK Ray's patch.
Yes, after applying Ryan's patch to FVP and reverting 31ae446b1a039a55d0336f2201d77d1032533413, my cursor keys still work
Copy/paste is another matter though, but that requires Heyi's changes as well.
Thanks, Ard.
On 31 March 2016 at 10:26, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
On 30 March 2016 at 23:16, Laszlo Ersek lersek@redhat.com wrote:
On 03/30/16 16:23, Ard Biesheuvel wrote:
On 30 March 2016 at 16:18, Ryan Harkin ryan.harkin@linaro.org wrote:
The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
So, do you guys have good test results with this patch in Platforms/... and Ray's patch http://thread.gmane.org/gmane.comp.bios.edk2.devel/9880 in edk2? If so, please state it in the edk2-devel thread, so I can ACK Ray's patch.
Yes, after applying Ryan's patch to FVP and reverting 31ae446b1a039a55d0336f2201d77d1032533413, my cursor keys still work
Sorry for the delay in testing.
I've pushed my PCD patch to OpenPlatformPkg and tested with 31ae446b1a039a55d0336f2201d77d1032533413 reverted and everything works the same as before.
Copy/paste is another matter though, but that requires Heyi's changes as well.
Thanks, Ard.
-----Original Message----- From: Ryan Harkin [mailto:ryan.harkin@linaro.org] Sent: Thursday, March 31, 2016 8:39 PM To: Ard Biesheuvel ard.biesheuvel@linaro.org Cc: Laszlo Ersek lersek@redhat.com; Linaro UEFI Mailman List linaro-uefi@lists.linaro.org; Leif Lindholm leif.lindholm@linaro.org; Ni, Ruiyu ruiyu.ni@intel.com; Heyi Guo heyi.guo@linaro.org Subject: Re: [PATCH] Platforms/ARM: add PcdUartDefaultReceiveFifoDepth
On 31 March 2016 at 10:26, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
On 30 March 2016 at 23:16, Laszlo Ersek lersek@redhat.com wrote:
On 03/30/16 16:23, Ard Biesheuvel wrote:
On 30 March 2016 at 16:18, Ryan Harkin ryan.harkin@linaro.org wrote:
The upstream code uses a PCD to set the FIFO depth:
f423d76 2016-03-17 MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Add a sensible default for the PCD before the code becomes more widely used.
The PL011UartInitializePort function in the PL011 driver expects the receive FIFO depth to be set to a sane value or zero to use the appropriate default for the version of PL011 present on the device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin ryan.harkin@linaro.org
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
So, do you guys have good test results with this patch in Platforms/... and Ray's patch http://thread.gmane.org/gmane.comp.bios.edk2.devel/9880 in edk2? If so, please state it in the edk2-devel thread, so I can ACK Ray's patch.
Yes, after applying Ryan's patch to FVP and reverting 31ae446b1a039a55d0336f2201d77d1032533413, my cursor keys still work
Sorry for the delay in testing.
I've pushed my PCD patch to OpenPlatformPkg and tested with 31ae446b1a039a55d0336f2201d77d1032533413 reverted and everything works the same as before.
Thank you all of you (Ryan, Ard, Laszlo) for the confirmation of the patch.
Copy/paste is another matter though, but that requires Heyi's changes as well.
Thanks, Ard.
-
Ard Biesheuvel -
Laszlo Ersek -
Ni, Ruiyu -
Ryan Harkin