DriverHealthManagerDxe Collect driver health form of third party drivers to repair no healthy card.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/D03.dsc | 1 + Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D06/D06.dsc | 1 + Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 1 + 6 files changed, 6 insertions(+)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 3f59be22ec8e..fe443dd929ad 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -492,6 +492,7 @@ [Components.common]

MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 25db1c38d287..0c4f21fbe056 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -638,6 +638,7 @@ [Components.common] MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 396bd03c9d24..3856578e74be 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -437,6 +437,7 @@ [Components.common] Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index f453f9e46321..3f07b2e57778 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -295,6 +295,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 85dd791564a4..9632aea4b00e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -314,6 +314,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index fda29ab322e9..a937660a09e2 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -319,6 +319,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT]

From: Jason Zhang zhangjinsong2@huawei.com

BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA, - attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );

Since NVMe riser width is 6*X4, need add the related port's INT-x support to match OS driver.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 37 +++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 0f2d11bb952b..4d9d9d95be68 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -41,11 +41,21 @@ Scope(_SB) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D

+ Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -56,6 +66,11 @@ Scope(_SB) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D

+ Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C @@ -759,11 +774,21 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D

+ Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -774,11 +799,21 @@ Device (PCI6) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D

+ Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C Package () {0x10FFFF,3,0,643}, // INT_D - }) + + Package () {0x12FFFF,0,0,640}, // INT_A + Package () {0x12FFFF,1,0,641}, // INT_B + Package () {0x12FFFF,2,0,642}, // INT_C + Package () {0x12FFFF,3,0,643}, // INT_D + })

Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,

As suggestion of community, 'AP' is a bit unfortunate to use in EDK2 context. PI specifies 'BSP' for Boot-strap Processor, as the one executing all of the EDK2 code. It then uses 'AP' to refer to Additional Processors, which can be assigned tasks using the EFI_MP_SERVICES_PROTOCOL. In a TianoCore context, this should be 'BSP'. So, Rename StartupAp() to StartUpBSP.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 2 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 ++- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- 6 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h index a232e52ed719..712b77c44fc8 100644 --- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -76,7 +76,7 @@ VOID MN_CONFIG (VOID); VOID SmmuConfigForOS (VOID); VOID SmmuConfigForBios (VOID);

-VOID StartupAp (VOID); +VOID StartUpBSP (VOID);

VOID LlcCleanInvalidate (VOID);

diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c index 97cf6b8d8757..dacd9e871faf 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c @@ -83,7 +83,7 @@ void QResetAp(VOID) //SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } }

diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index b57fdfa68e45..c8a9da73bbca 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -133,7 +133,7 @@ VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); }

return; diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c index 76a055cbe980..b374347e5c4d 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -35,7 +35,7 @@ QResetAp ( (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);

if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } }

diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c index 4c4c944dbead..a1458da7f0a3 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -96,7 +96,7 @@ UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); }

return; @@ -128,3 +128,4 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) { return TRUE; } + diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c index 0790f7941ae7..a8261d370626 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c @@ -78,7 +78,7 @@ QResetAp (

//SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); } }

Add PCI_OSC_SUPPORT for remaining host bridges to remove fail output in kernel: [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);

Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 200 +++++++++++--------- 1 file changed, 106 insertions(+), 94 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 4d9d9d95be68..6dc380f27fa2 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -17,6 +17,90 @@ **/

//#include "ArmPlatform.h" + +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + +#define PCI_OSC_SUPPORT_HOTPLUG() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Always allow native PME, AER (no dependencies) */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x1D,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + Scope(_SB) { Device (PCI0) @@ -139,53 +223,7 @@ Scope(_SB) Return (RBUF) } // Method(_CRS), this method return RBUF!

- // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG ()

Method (_HPX, 0) { Return (Package(2) { @@ -270,6 +308,8 @@ Device (PCI1) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -333,6 +373,8 @@ Device (PCI2) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -382,6 +424,8 @@ Device (PCI3) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -431,6 +475,8 @@ Device (PCI4) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -505,6 +551,8 @@ Device (PCI5) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -870,53 +918,7 @@ Device (PCI6) Return (RBUF) } // Method(_CRS), this method return RBUF!

- // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG ()

Method (_HPX, 0) { Return (Package(2) { @@ -1002,6 +1004,8 @@ Device (PCI7) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1066,6 +1070,8 @@ Device (PCI8) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1115,6 +1121,8 @@ Device (PCI9) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1164,6 +1172,8 @@ Device (PCIA) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -1238,6 +1248,8 @@ Device (PCIB) Return (RBUF) } // Method(_CRS), this method return RBUF!

+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf)

Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment).

The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-)

diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);

- suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif;

goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);

- goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof;

endform;

-form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"

As secure boot is not ready, remove SECURE_BOOT_ENABLE and relative code.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D06/D06.dsc | 12 ------------ Platform/Hisilicon/D06/D06.fdf | 11 ----------- 2 files changed, 23 deletions(-)

diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 3856578e74be..d762230768e9 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -30,7 +30,6 @@ [Defines] FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE NETWORK_IP6_ENABLE = FALSE DEFINE HTTP_BOOT_ENABLE = FALSE - DEFINE SECURE_BOOT_ENABLE = FALSE

!include Silicon/Hisilicon/Hisilicon.dsc.inc

@@ -89,9 +88,6 @@ [LibraryClasses.common] LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf -!endif PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf

@@ -292,15 +288,7 @@ [Components.common] MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf

-!if $(SECURE_BOOT_ENABLE) == TRUE - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { - <LibraryClasses> - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf - } - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!else MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -!endif Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index f72b513352fb..e402628a1b35 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -88,17 +88,10 @@ [FD.D06] #Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER -!if $(SECURE_BOOT_ENABLE) == TRUE - #Signature: gEfiAuthenticatedVariableGuid = - # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else #Signature: gEfiVariableGuid = # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 0xB8, 0xdF, 0x00, 0x00, #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 @@ -183,10 +176,6 @@ [FV.FvMain] INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf

-!if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!endif - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

Last patch "Modify IORT" change revision id of node type 2 to 1, and 4.19 later kernel will judge the revision id to get root pci bridge DMA informations from IORT. As Hi1620 USB 2.0 don't support 64 bit DMA, but the DMA attribute get from IORT node type 2 is 64 bit. So add _DMA method in USB pci bridge 3 and pci bridge 8 to fix usb crash when usb device is present issue.

https://bugs.linaro.org/show_bug.cgi?id=4079

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 6dc380f27fa2..c1083dc16a2a 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -375,6 +375,29 @@ Device (PCI2)

PCI_OSC_SUPPORT ()

+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1077,6 +1100,29 @@ Device (PCI8) Return (0xf) }

+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_PXM, 0, NotSerialized) { Return(0x02)

As some interfaces exposed only by implementations in edk2-non-osi, so delete corresponding header files and modify code to make build.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf | 1 + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 1 + Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 ------------------- Silicon/Hisilicon/Include/Library/LpcLib.h | 113 -------------------- Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 -------- Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 ------------------- 20 files changed, 14 insertions(+), 426 deletions(-)

diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf index c65cf7b6dd9f..90e40ae2b393 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf @@ -30,6 +30,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec

ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf index 0fa7fdf80fa8..c0195b2fa9cf 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -30,7 +30,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf index 0f6b68d4c88d..e82c9204d5d6 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index 022c3e940a31..7ec577530610 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -30,6 +30,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf index 8296ee02de4e..715a4efadde8 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf index 75c5054bbfd1..9bc6eb549c41 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Platform/Hisilicon/D06/D06.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf index 93a2bcac3726..94f6fe404c6d 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf @@ -31,6 +31,7 @@ [Packages] IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec

+ Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf index 2275586ff324..808da65cd429 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf @@ -32,6 +32,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec

+ Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 669e6a2d52cc..0c37b53af987 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -58,7 +58,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf index c07a5b8aa250..5b917fd3fdea 100644 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf +++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf @@ -30,6 +30,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf index 89447cc52d76..aa8e3c9c0b63 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -35,6 +35,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf index b603523100ae..d6b5248fcdbf 100644 --- a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf +++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf @@ -27,6 +27,7 @@ [Sources.common] [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses] diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf index 9bca88fe8702..e9520b39530e 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf index 1bb4f5c703bb..6211373ce7ba 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec

diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h deleted file mode 100755 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h deleted file mode 100644 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h deleted file mode 100644 index b956ee6d072a..000000000000 --- a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _IPMI_CMD_LIB_H_ -#define _IPMI_CMD_LIB_H_ - -#define BOOT_OPTION_BOOT_FLAG_VALID 1 -#define BOOT_OPTION_BOOT_FLAG_INVALID 0 - -typedef enum { - EfiReserved, - EfiBiosFrb2, - EfiBiosPost, - EfiOsLoad, - EfiSmsOs, - EfiOem, - EfiFrbReserved1, - EfiFrbReserved2 -} EFI_WDT_USER_TYPE; - -typedef enum { - NoOverride = 0x0, - ForcePxe, - ForceDefaultHardDisk, - ForceDefaultHardDiskSafeMode, - ForceDefaultDiagnosticPartition, - ForceDefaultCD, - ForceSetupUtility, - ForceRemoteRemovableMedia, - ForceRemoteCD, - ForcePrimaryRemoteMedia, - ForceRemoteHardDisk = 0xB, - ForcePrimaryRemovableMedia = 0xF -} BOOT_DEVICE_SELECTOR; - -// -// Get System Boot Option data structure -// -typedef struct { - UINT8 ParameterVersion :4; - UINT8 Reserved1 :4; - UINT8 ParameterSelector :7; - UINT8 ParameterValid :1; - // - // Boot Flags Data 1 - // - UINT8 Reserved2 :5; - UINT8 BiosBootType :1; - UINT8 Persistent :1; - UINT8 BootFlagsValid :1; - // - // Boot Flags Data 2 - // - UINT8 LockResetBtn :1; - UINT8 ScreenBlank :1; - UINT8 BootDeviceSelector :4; - UINT8 LockKeyboard :1; - UINT8 ClearCmos :1; - // - // Boot Flags Data 3 - // - UINT8 ConsoleRedirectionControl :2; - UINT8 LockSleepBtn :1; - UINT8 UserPasswordByPass :1; - UINT8 Reserved3 :1; - UINT8 FirmwareVerbosity :2; - UINT8 LockPowerBtn :1; - // - // Boot Flags Data 4 - // - UINT8 MuxControlOverride :3; - UINT8 ShareModeOverride :1; - UINT8 Reserved4 :4; - // - // Boot Flags Data 5 - // - UINT8 DeviceInstanceSelector :5; - UINT8 Reserved5 :3; -} IPMI_GET_BOOT_OPTION; - -EFI_STATUS -EFIAPI -IpmiCmdSetSysBootOptions ( - OUT IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -EFIAPI -IpmiCmdGetSysBootOptions ( - IN IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -IpmiCmdStopWatchdogTimer ( - IN EFI_WDT_USER_TYPE UserType - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h deleted file mode 100755 index 236a52ba45a7..000000000000 --- a/Silicon/Hisilicon/Include/Library/LpcLib.h +++ /dev/null @@ -1,113 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _LPC_LIB_H_ -#define _LPC_LIB_H_ - -#include <Uefi.h> - -#define PCIE_SUBSYS_IO_MUX 0xA0170000 -#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) -#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) -#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90) -#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4) -#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8) -#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC) -#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0) -#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4) -#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8) - -#define IO_WRAP_CTRL_BASE 0xA0100000 -#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0) -#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4) -#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8) -#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac) -#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8) -#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc) -#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0) -#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4) -#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028) - - -#define LPC_BASE 0xA01B0000 -#define LPC_START_REG (LPC_BASE + 0x00) -#define LPC_OP_STATUS_REG (LPC_BASE + 0x04) -#define LPC_IRQ_ST_REG (LPC_BASE + 0x08) -#define LPC_OP_LEN_REG (LPC_BASE + 0x10) -#define LPC_CMD_REG (LPC_BASE + 0x14) -#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18) -#define LPC_ADDR_REG (LPC_BASE + 0x20) -#define LPC_WDATA_REG (LPC_BASE + 0x24) -#define LPC_RDATA_REG (LPC_BASE + 0x28) -#define LPC_LONG_CNT_REG (LPC_BASE + 0x30) -#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50) -#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54) -#define LPC_TIME_OUT_REG (LPC_BASE + 0x58) -#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80) -#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84) -#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90) -#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94) -#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0) - -#define LPC_FIFO_LEN (16) - -typedef enum{ - LPC_ADDR_MODE_INCREASE, - LPC_ADDR_MODE_SINGLE -}LPC_ADDR_MODE; - -typedef enum{ - LPC_TYPE_IO, - LPC_TYPE_MEM, - LPC_TYPE_FWH -}LPC_TYPE; - - -typedef union { - struct{ - UINT32 lpc_wr:1; - UINT32 lpc_type:2; - UINT32 same_addr:1; - UINT32 resv:28; - }bits; - UINT32 u32; -}LPC_CMD_STRUCT; - -typedef union { - struct{ - UINT32 op_len:5; - UINT32 resv:27; - }bits; - UINT32 u32; -}LPC_OP_LEN_STRUCT; - - -VOID LpcInit(VOID); -BOOLEAN LpcIdle(VOID); -EFI_STATUS LpcByteWrite( - IN UINT32 Addr, - IN UINT8 Data); -EFI_STATUS LpcByteRead( - IN UINT32 Addr, - IN OUT UINT8 *Data); - -EFI_STATUS LpcWrite( - IN UINT32 Addr, - IN UINT8 *Data, - IN UINT8 Len); - -#endif - - diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h deleted file mode 100644 index b5de34f5facb..000000000000 --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _OEM_ADDRESS_MAP_LIB_H_ -#define _OEM_ADDRESS_MAP_LIB_H_ - -#include <PlatformArch.h> - -typedef struct _DDRC_BASE_ID{ - UINTN Base; - UINTN Id; -}DDRC_BASE_ID; - -// Invalid address, will cause exception when accessed by bug code -#define ADDRESS_MAP_INVALID ((UINTN)(-1)) - -UINTN OemGetPoeSubBase (UINT32 NodeId); -UINTN OemGetPeriSubBase (UINT32 NodeId); -UINTN OemGetAlgSubBase (UINT32 NodeId); -UINTN OemGetCfgbusBase (UINT32 NodeId); -UINTN OemGetGicSubBase (UINT32 NodeId); -UINTN OemGetHACSubBase (UINT32 NodeId); -UINTN OemGetIOMGMTSubBase (UINT32 NodeId); -UINTN OemGetNetworkSubBase (UINT32 NodeId); -UINTN OemGetM3SubBase (UINT32 NodeId); -UINTN OemGetPCIeSubBase (UINT32 NodeId); - -VOID OemAddressMapInit(VOID); - -extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL]; - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h deleted file mode 100644 index 712b77c44fc8..000000000000 --- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ /dev/null @@ -1,112 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _PLATFORM_SYS_CTRL_LIB_H_ -#define _PLATFORM_SYS_CTRL_LIB_H_ - -#define PACKAGE_16CORE 0 -#define PACKAGE_32CORE 1 -#define PACKAGE_RESERVED 2 -#define PACKAGE_TYPE_NUM 3 - -UINT32 PlatformGetPackageType (VOID); - -VOID DisplayCpuInfo (VOID); -UINT32 CheckChipIsEc(VOID); - -UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll); - -#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF -#define DJTAG_CHAIN_ID_AA 1 -#define DJTAG_CHAIN_ID_LLC 4 - - -#define SC_DJTAG_MSTR_EN_OFFSET 0x6800 -#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804 -#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808 -#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C -#define SC_DJTAG_MSTR_WR_OFFSET 0x6810 -#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814 -#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818 -#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C -#define SC_DJTAG_TMOUT_OFFSET 0x6820 -#define SC_TDRE_OP_ADDR_OFFSET 0x6824 -#define SC_TDRE_WDATA_OFFSET 0x6828 -#define SC_TDRE_REPAIR_EN_OFFSET 0x682C -#define SC_DJTAG_RD_DATA0_OFFSET 0xE800 -#define SC_TDRE_RDATA0_OFFSET 0xE830 - - -UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port); - -VOID PlatformAddressMapCleanUp (VOID); -VOID PlatformDisableDdrWindow (VOID); - -VOID PlatformEnableArchTimer (VOID); - -EFI_STATUS -DawFindFreeWindow (UINTN Socket, UINTN *DawIndex); - -VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value); - -VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -VOID RemoveRoceReset(VOID); - -UINTN PlatformGetDdrChannel (VOID); - -VOID ITSCONFIG (VOID); - -VOID MN_CONFIG (VOID); - -VOID SmmuConfigForOS (VOID); -VOID SmmuConfigForBios (VOID); - -VOID StartUpBSP (VOID); - -VOID LlcCleanInvalidate (VOID); - -UINTN PlatformGetCpuFreq (UINT8 Socket); -VOID ClearInterruptStatus(VOID); - -UINTN PlatformGetCoreCount (VOID); -VOID DAWConfigEn(UINT32 socket); - -VOID DResetUsb (); -UINT32 PlatformGetEhciBase (); -UINT32 PlatformGetOhciBase (); -VOID PlatformPllInit(); -// PLL initialization for super IO clusters. -VOID SiclPllInit(UINT32 SclId); -VOID PlatformDeviceDReset(); -VOID PlatformGicdInit(); -VOID PlatformLpcInit(); -// Synchronize architecture timer counter between different super computing -// clusters. -VOID PlatformArchTimerSynchronize(VOID); -VOID PlatformEventBroadcastConfig(VOID); -UINTN GetDjtagRegBase(UINT32 NodeId); -VOID LlcCleanInvalidateAsm(VOID); -VOID PlatformMdioInit(VOID); -VOID DisableClusterClock(UINTN CpuClusterBase); -VOID EnableClusterClock(UINTN CpuClusterBase); -VOID DisableSocketClock (UINT8 Skt); - -EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port); -EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket); - -#endif