This is what I have queued up for AMD Overdrive over the past couple of months. Some fixes and some features that would be good to get merged.
Note that this only contains the SMMU support for the OS, not for UEFI itself. Most notably, there is now a dynamic PCD + UEFI var that needs to be set for the DT SMMU nodes and the ACPI IORT table to appear.
Ard Biesheuvel (6): Platforms/AMD/Styx: remove unused PCD 'PcdStyxFdt' Platforms/AMD/Overdrive: add dynamic PCD to control SMMU availibility Platforms/AMD/Styx: enable SMMUs in the ACPI IORT table Platforms/AMD/Styx: enable SMMUs in the device tree Platforms/AMD/Overdrive: fix GIC MMIO region sizes Platforms/AMD/Styx: align UEFI PCI bus range with DT/ACPI descriptions
Platforms/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Platforms/AMD/Styx/AcpiTables/Iort.c | 375 ++++++++++++++++++++ Platforms/AMD/Styx/AmdStyx.dec | 10 +- Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 6 +- Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 6 +- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 51 +++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 3 +- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8293 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 76 +++- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 6 +- 11 files changed, 523 insertions(+), 12 deletions(-) create mode 100644 Platforms/AMD/Styx/AcpiTables/Iort.c
Remove the PCD 'PcdStyxFdt' which is no longer used now that we have switched to the generic DtPlatformDxe driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/AmdStyx.dec | 3 --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 1 - 2 files changed, 4 deletions(-)
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 6624f8ca74a7..8d4b4927c6b1 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -46,9 +46,6 @@ # CPUID Register gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200
- # FDT support - gAmdStyxTokenSpaceGuid.PcdStyxFdt|{ 0xe4, 0x08, 0x0d, 0x04, 0x9a, 0x47, 0x4b, 0x42, 0x8c, 0x42, 0x36, 0x64, 0xdf, 0x79, 0x3f, 0x4b }|VOID*|0x00010000 - # Synopsys SATA Controller gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort|0xE0300000|UINT32|0x00020000 gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8|UINT8|0x00020001 diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index f5ba5f1d1335..8bb6e9fa41cb 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -41,7 +41,6 @@ UefiBootServicesTableLib
[Pcd] - gAmdStyxTokenSpaceGuid.PcdStyxFdt gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB
On Thu, Jun 01, 2017 at 09:43:48AM +0000, Ard Biesheuvel wrote:
Remove the PCD 'PcdStyxFdt' which is no longer used now that we have switched to the generic DtPlatformDxe driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/AMD/Styx/AmdStyx.dec | 3 --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 1 - 2 files changed, 4 deletions(-)
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 6624f8ca74a7..8d4b4927c6b1 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -46,9 +46,6 @@ # CPUID Register gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200
- # FDT support
- gAmdStyxTokenSpaceGuid.PcdStyxFdt|{ 0xe4, 0x08, 0x0d, 0x04, 0x9a, 0x47, 0x4b, 0x42, 0x8c, 0x42, 0x36, 0x64, 0xdf, 0x79, 0x3f, 0x4b }|VOID*|0x00010000
- # Synopsys SATA Controller gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort|0xE0300000|UINT32|0x00020000 gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8|UINT8|0x00020001
diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index f5ba5f1d1335..8bb6e9fa41cb 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -41,7 +41,6 @@ UefiBootServicesTableLib [Pcd]
- gAmdStyxTokenSpaceGuid.PcdStyxFdt gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB
-- 2.9.3
Introduce a PCD that can be linked to a EFI variable 'StyxEnableSmmus', controlling whether the SMMU descriptions will be exposed to the OS via the DT or ACPI tables.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/AmdStyx.dec | 7 +++++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 8d4b4927c6b1..ddd5bf4c3609 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -35,6 +35,10 @@ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } } gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
+ # 2a5e4deb-4445-4fb6-8b14-366b8e779b69 + # EFI variable scope for Styx + gAmdStyxVariableGuid = { 0x2a5e4deb, 0x4445, 0x4fb6, { 0x8b, 0x14, 0x36, 0x6b, 0x8e, 0x77, 0x9b, 0x69 } } + [PcdsDynamic] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100 gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101 @@ -108,3 +112,6 @@ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000 # block size to use when invoking the ISCP FV methods gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001 + +[PcdsFixedAtBuild,PcdsDynamic] + gAmdStyxTokenSpaceGuid.PcdEnableSmmus|FALSE|BOOLEAN|0xe0000000 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 65d229884aa7..b4893ca34587 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -515,9 +515,11 @@ DEFINE DO_KCS = 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
-[PcdsDynamicExHii.common.DEFAULT] +[PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+ gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform
On Thu, Jun 01, 2017 at 09:43:49AM +0000, Ard Biesheuvel wrote:
Introduce a PCD that can be linked to a EFI variable 'StyxEnableSmmus', controlling whether the SMMU descriptions will be exposed to the OS via the DT or ACPI tables.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/AMD/Styx/AmdStyx.dec | 7 +++++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 8d4b4927c6b1..ddd5bf4c3609 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -35,6 +35,10 @@ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } } gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
- # 2a5e4deb-4445-4fb6-8b14-366b8e779b69
- # EFI variable scope for Styx
- gAmdStyxVariableGuid = { 0x2a5e4deb, 0x4445, 0x4fb6, { 0x8b, 0x14, 0x36, 0x6b, 0x8e, 0x77, 0x9b, 0x69 } }
This is strictly a question of style (by which I don't mean strict coding style), but is this new GUID necessary? I mean, all it needs to be is a GUID to distinguish component ... namespaces(?) ... I see both variants in edk2: have a special VariableGuid, or just reuse the TokenSpaceGuid.
Just trying to gauge preferences.
I'm happy with the patch either way: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
[PcdsDynamic] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100 gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101 @@ -108,3 +112,6 @@ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000 # block size to use when invoking the ISCP FV methods gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001
+[PcdsFixedAtBuild,PcdsDynamic]
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus|FALSE|BOOLEAN|0xe0000000
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 65d229884aa7..b4893ca34587 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -515,9 +515,11 @@ DEFINE DO_KCS = 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 -[PcdsDynamicExHii.common.DEFAULT] +[PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE
################################################################################ #
# Components Section - list of all EDK II Modules needed by this Platform
2.9.3
On 1 June 2017 at 13:36, Leif Lindholm leif.lindholm@linaro.org wrote:
On Thu, Jun 01, 2017 at 09:43:49AM +0000, Ard Biesheuvel wrote:
Introduce a PCD that can be linked to a EFI variable 'StyxEnableSmmus', controlling whether the SMMU descriptions will be exposed to the OS via the DT or ACPI tables.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/AMD/Styx/AmdStyx.dec | 7 +++++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 8d4b4927c6b1..ddd5bf4c3609 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -35,6 +35,10 @@ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } } gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
- # 2a5e4deb-4445-4fb6-8b14-366b8e779b69
- # EFI variable scope for Styx
- gAmdStyxVariableGuid = { 0x2a5e4deb, 0x4445, 0x4fb6, { 0x8b, 0x14, 0x36, 0x6b, 0x8e, 0x77, 0x9b, 0x69 } }
This is strictly a question of style (by which I don't mean strict coding style), but is this new GUID necessary? I mean, all it needs to be is a GUID to distinguish component ... namespaces(?) ... I see both variants in edk2: have a special VariableGuid, or just reuse the TokenSpaceGuid.
Just trying to gauge preferences.
I am leaning towards keeping it, since everything is a GUID anyway in UEFI, and having a dedicated one avoids confusion. But I don't feel strongly about it.
I'm happy with the patch either way: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
OK, so let's just keep it as is then.
[PcdsDynamic] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100 gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101 @@ -108,3 +112,6 @@ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000 # block size to use when invoking the ISCP FV methods gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001
+[PcdsFixedAtBuild,PcdsDynamic]
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus|FALSE|BOOLEAN|0xe0000000
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 65d229884aa7..b4893ca34587 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -515,9 +515,11 @@ DEFINE DO_KCS = 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
-[PcdsDynamicExHii.common.DEFAULT] +[PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE
################################################################################ #
# Components Section - list of all EDK II Modules needed by this Platform
2.9.3
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Platforms/AMD/Styx/AcpiTables/Iort.c | 375 ++++++++++++++++++++ Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 6 +- Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 6 +- 5 files changed, 387 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf index 12e0444009ef..3615d7fc0279 100644 --- a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf @@ -37,6 +37,7 @@ Mcfg.c Csrt.c Dsdt.c + Iort.c
[Packages] ArmPkg/ArmPkg.dec diff --git a/Platforms/AMD/Styx/AcpiTables/Iort.c b/Platforms/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 000000000000..80872773ba7d --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,375 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <AmdStyxAcpiLib.h> +#include <IndustryStandard/IoRemappingTable.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#define STYX_PCIE_SMMU_BASE 0xE0A00000 +#define STYX_PCIE_SMMU_SIZE 0x10000 +#define STYX_PCIE_SMMU_INTERRUPT 0x16d + +#define STYX_ETH0_SMMU_BASE 0xE0600000 +#define STYX_ETH0_SMMU_SIZE 0x10000 +#define STYX_ETH0_SMMU_INTERRUPT 0x170 + +#define STYX_ETH1_SMMU_BASE 0xE0800000 +#define STYX_ETH1_SMMU_SIZE 0x10000 +#define STYX_ETH1_SMMU_INTERRUPT 0x16f + +#define STYX_SATA0_SMMU_BASE 0xE0200000 +#define STYX_SATA0_SMMU_SIZE 0x10000 +#define STYX_SATA0_SMMU_INTERRUPT 0x16c + +#define STYX_SATA1_SMMU_BASE 0xE0C00000 +#define STYX_SATA1_SMMU_SIZE 0x10000 +#define STYX_SATA1_SMMU_INTERRUPT 0x16b + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1]; +} STYX_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; +} STYX_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32]; +} STYX_NC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + STYX_SMMU_NODE PciSmmuNode; + STYX_RC_NODE PciRcNode; + +#if DO_XGBE + STYX_SMMU_NODE Eth0SmmuNode; + STYX_NC_NODE Eth0NamedNode; + STYX_SMMU_NODE Eth1SmmuNode; + STYX_NC_NODE Eth1NamedNode; +#endif + + STYX_SMMU_NODE Sata0SmmuNode; + STYX_NC_NODE Sata0NamedNode; + STYX_SMMU_NODE Sata1SmmuNode; + STYX_NC_NODE Sata1NamedNode; +} STYX_IO_REMAPPING_STRUCTURE; + +#define __STYX_SMMU_NODE(Base, Size, Irq) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_SMMUv1v2, \ + sizeof(STYX_SMMU_NODE), \ + 0x0, \ + 0x0, \ + 0x0, \ + 0x0, \ + }, \ + Base, \ + Size, \ + EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \ + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ + SMMU_NSgIrpt), \ + 0x1, \ + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ + 0x0, \ + 0x0, \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + 0x0, \ + 0x0, \ + }, { \ + { \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + }, \ + } + +#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \ + { \ + 0x0, \ + 0x0, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \ + } + +#define __STYX_NAMED_COMPONENT_NODE(Name) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_NAMED_COMP, \ + sizeof(STYX_NC_NODE), \ + 0x0, \ + 0x0, \ + 0x20, \ + FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \ + }, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \ + 0x0, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \ + 40, \ + }, \ + Name + +STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + STYX_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), +#if DO_XGBE + 10, // NumNodes +#else + 6, // NumNodes +#endif + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // PciSmmuNode + __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE, + STYX_PCIE_SMMU_SIZE, + STYX_PCIE_SMMU_INTERRUPT) + }, { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof(STYX_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, { + __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0), + } +#if DO_XGBE + }, { + // Eth0SmmuNode + __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE, + STYX_ETH0_SMMU_SIZE, + STYX_ETH0_SMMU_INTERRUPT) + }, { + // Eth0NamedNode + __STYX_NAMED_COMPONENT_NODE("\_SB_.ETH0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode), + } + }, { + // Eth1SmmuNode + __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE, + STYX_ETH1_SMMU_SIZE, + STYX_ETH1_SMMU_INTERRUPT) + }, { + // Eth1NamedNode + __STYX_NAMED_COMPONENT_NODE("\_SB_.ETH1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode), + } +#endif + }, { + // Sata0SmmuNode + __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE, + STYX_SATA0_SMMU_SIZE, + STYX_SATA0_SMMU_INTERRUPT) + }, { + // Sata0NamedNode + __STYX_NAMED_COMPONENT_NODE("\_SB_.AHC0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode), + } + }, { + // Sata1SmmuNode + __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE, + STYX_SATA1_SMMU_SIZE, + STYX_SATA1_SMMU_INTERRUPT) + }, { + // Sata1NamedNode + __STYX_NAMED_COMPONENT_NODE("\_SB_.AHC1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode), + } + } +}; + +#pragma pack() + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 + +EFI_ACPI_DESCRIPTION_HEADER * +IortHeader ( + VOID + ) +{ + if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + // + // Silicon revisions prior to B1 have only one SATA port, + // so omit the nodes of the second port in this case. + // + AcpiIort.Iort.NumNodes -= 2; + } + return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header; +} diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h index 698a5d3f90f8..9438b8b0c27e 100644 --- a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -27,6 +27,7 @@ EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void);
#define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 1bad597a8eaa..15b38bbf89c6 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -23,8 +23,9 @@ #include <Protocol/AcpiTable.h>
#include <Library/BaseMemoryLib.h> -#include <Library/UefiBootServicesTableLib.h> #include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h>
#define MAX_ACPI_TABLES 12
@@ -65,6 +66,9 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex++] = SpcrHeader(); AcpiTableList[TableIndex++] = McfgHeader(); AcpiTableList[TableIndex++] = CsrtHeader(); + if (PcdGetBool (PcdEnableSmmus)) { + AcpiTableList[TableIndex++] = IortHeader(); + } AcpiTableList[TableIndex++] = NULL;
DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 9f4c3eaf582d..23f1cb60903a 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -37,10 +37,14 @@ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
[LibraryClasses] + AmdStyxAcpiLib DebugLib + PcdLib UefiBootServicesTableLib UefiDriverEntryPoint - AmdStyxAcpiLib + +[Pcd] + gAmdStyxTokenSpaceGuid.PcdEnableSmmus
[Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED
On Thu, Jun 01, 2017 at 09:43:50AM +0000, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Did we want a comment from Graeme on this? (added to cc)
Platforms/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Platforms/AMD/Styx/AcpiTables/Iort.c | 375 ++++++++++++++++++++ Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 6 +- Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 6 +- 5 files changed, 387 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf index 12e0444009ef..3615d7fc0279 100644 --- a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf @@ -37,6 +37,7 @@ Mcfg.c Csrt.c Dsdt.c
- Iort.c
[Packages] ArmPkg/ArmPkg.dec diff --git a/Platforms/AMD/Styx/AcpiTables/Iort.c b/Platforms/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 000000000000..80872773ba7d --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,375 @@ +/** @file
- Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <AmdStyxAcpiLib.h> +#include <IndustryStandard/IoRemappingTable.h>
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+#define STYX_PCIE_SMMU_BASE 0xE0A00000 +#define STYX_PCIE_SMMU_SIZE 0x10000 +#define STYX_PCIE_SMMU_INTERRUPT 0x16d
+#define STYX_ETH0_SMMU_BASE 0xE0600000 +#define STYX_ETH0_SMMU_SIZE 0x10000 +#define STYX_ETH0_SMMU_INTERRUPT 0x170
+#define STYX_ETH1_SMMU_BASE 0xE0800000 +#define STYX_ETH1_SMMU_SIZE 0x10000 +#define STYX_ETH1_SMMU_INTERRUPT 0x16f
+#define STYX_SATA0_SMMU_BASE 0xE0200000 +#define STYX_SATA0_SMMU_SIZE 0x10000 +#define STYX_SATA0_SMMU_INTERRUPT 0x16c
+#define STYX_SATA1_SMMU_BASE 0xE0C00000 +#define STYX_SATA1_SMMU_SIZE 0x10000 +#define STYX_SATA1_SMMU_INTERRUPT 0x16b
+#pragma pack(1) +typedef struct {
- EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
- EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1];
+} STYX_SMMU_NODE;
+typedef struct {
- EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
- EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
+} STYX_RC_NODE;
+typedef struct {
- EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node;
- CONST CHAR8 Name[11];
- EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32];
+} STYX_NC_NODE;
+typedef struct {
- EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
- STYX_SMMU_NODE PciSmmuNode;
- STYX_RC_NODE PciRcNode;
+#if DO_XGBE
- STYX_SMMU_NODE Eth0SmmuNode;
- STYX_NC_NODE Eth0NamedNode;
- STYX_SMMU_NODE Eth1SmmuNode;
- STYX_NC_NODE Eth1NamedNode;
+#endif
- STYX_SMMU_NODE Sata0SmmuNode;
- STYX_NC_NODE Sata0NamedNode;
- STYX_SMMU_NODE Sata1SmmuNode;
- STYX_NC_NODE Sata1NamedNode;
+} STYX_IO_REMAPPING_STRUCTURE;
+#define __STYX_SMMU_NODE(Base, Size, Irq) \
- { \
- { \
EFI_ACPI_IORT_TYPE_SMMUv1v2, \sizeof(STYX_SMMU_NODE), \0x0, \0x0, \0x0, \0x0, \- }, \
- Base, \
- Size, \
- EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \
- EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \
- FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
SMMU_NSgIrpt), \- 0x1, \
- sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
- 0x0, \
- 0x0, \
- Irq, \
- EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
- 0x0, \
- 0x0, \
- }, { \
- { \
Irq, \EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \- }, \
- }
+#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \
- { \
- In, \
- Num, \
- Out, \
- FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
- Flags \
- }
+#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \
- { \
- 0x0, \
- 0x0, \
- Out, \
- FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
- EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \
- }
+#define __STYX_NAMED_COMPONENT_NODE(Name) \
- { \
{ \EFI_ACPI_IORT_TYPE_NAMED_COMP, \sizeof(STYX_NC_NODE), \0x0, \0x0, \0x20, \FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \}, \0x0, \EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \0x0, \0x0, \EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \40, \- }, \
- Name
+STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = {
- {
- AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
STYX_IO_REMAPPING_STRUCTURE,EFI_ACPI_IO_REMAPPING_TABLE_REVISION),+#if DO_XGBE
- 10, // NumNodes
+#else
- 6, // NumNodes
+#endif
- sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
- 0 // Reserved
- }, {
- // PciSmmuNode
- __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE,
STYX_PCIE_SMMU_SIZE,STYX_PCIE_SMMU_INTERRUPT)- }, {
- // PciRcNode
- {
{EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Typesizeof(STYX_RC_NODE), // Length0x0, // Revision0x0, // Reserved0x1, // NumIdMappingsFIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference},EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent0x0, // AllocationHints0x0, // ReservedEFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlagsEFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute0x0, // PciSegmentNumber- }, {
__STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0),- }
+#if DO_XGBE
- }, {
- // Eth0SmmuNode
- __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE,
STYX_ETH0_SMMU_SIZE,STYX_ETH0_SMMU_INTERRUPT)- }, {
- // Eth0NamedNode
- __STYX_NAMED_COMPONENT_NODE("\_SB_.ETH0"),
- {
__STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode),- }
- }, {
- // Eth1SmmuNode
- __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE,
STYX_ETH1_SMMU_SIZE,STYX_ETH1_SMMU_INTERRUPT)- }, {
- // Eth1NamedNode
- __STYX_NAMED_COMPONENT_NODE("\_SB_.ETH1"),
- {
__STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode),- }
+#endif
- }, {
- // Sata0SmmuNode
- __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE,
STYX_SATA0_SMMU_SIZE,STYX_SATA0_SMMU_INTERRUPT)- }, {
- // Sata0NamedNode
- __STYX_NAMED_COMPONENT_NODE("\_SB_.AHC0"),
- {
__STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode),- }
- }, {
- // Sata1SmmuNode
- __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE,
STYX_SATA1_SMMU_SIZE,STYX_SATA1_SMMU_INTERRUPT)- }, {
- // Sata1NamedNode
- __STYX_NAMED_COMPONENT_NODE("\_SB_.AHC1"),
- {
__STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode),__STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode),- }
- }
+};
+#pragma pack()
+#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011
+EFI_ACPI_DESCRIPTION_HEADER * +IortHeader (
- VOID
- )
+{
- if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
- //
- // Silicon revisions prior to B1 have only one SATA port,
- // so omit the nodes of the second port in this case.
- //
- AcpiIort.Iort.NumNodes -= 2;
- }
- return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header;
+} diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h index 698a5d3f90f8..9438b8b0c27e 100644 --- a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -27,6 +27,7 @@ EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 1bad597a8eaa..15b38bbf89c6 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -23,8 +23,9 @@ #include <Protocol/AcpiTable.h> #include <Library/BaseMemoryLib.h> -#include <Library/UefiBootServicesTableLib.h> #include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> #define MAX_ACPI_TABLES 12 @@ -65,6 +66,9 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex++] = SpcrHeader(); AcpiTableList[TableIndex++] = McfgHeader(); AcpiTableList[TableIndex++] = CsrtHeader();
- if (PcdGetBool (PcdEnableSmmus)) {
- AcpiTableList[TableIndex++] = IortHeader();
- } AcpiTableList[TableIndex++] = NULL;
DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 9f4c3eaf582d..23f1cb60903a 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -37,10 +37,14 @@ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec [LibraryClasses]
- AmdStyxAcpiLib DebugLib
- PcdLib UefiBootServicesTableLib UefiDriverEntryPoint
- AmdStyxAcpiLib
+[Pcd]
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus
[Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED -- 2.9.3
On 1 June 2017 at 13:40, Leif Lindholm leif.lindholm@linaro.org wrote:
On Thu, Jun 01, 2017 at 09:43:50AM +0000, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Did we want a comment from Graeme on this? (added to cc)
He did comment on it tangentially, by observing that AMD never contributed an IORT table, probably because the Stream IDs are different between B0 and B1 silicon. This table works on both, though.
On Fri, Jun 02, 2017 at 12:04:10PM +0000, Ard Biesheuvel wrote:
On 1 June 2017 at 13:40, Leif Lindholm leif.lindholm@linaro.org wrote:
On Thu, Jun 01, 2017 at 09:43:50AM +0000, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Did we want a comment from Graeme on this? (added to cc)
He did comment on it tangentially, by observing that AMD never contributed an IORT table, probably because the Stream IDs are different between B0 and B1 silicon. This table works on both, though.
I don't have time (or hardware) to check the table so I am happy if it works for Ard.
Graeme
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 51 ++++++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 + Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8293 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 72 +++++++++++++++++++- 4 files changed, 123 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index b18caf19985b..093db6517c1a 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -22,6 +22,7 @@ #include <Library/DebugLib.h> #include <Library/DxeServicesLib.h> #include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> #include <Library/PrintLib.h> #include <Library/UefiBootServicesTableLib.h>
@@ -189,6 +190,46 @@ SetMacAddress (
#endif
+STATIC +VOID +DisableSmmu ( + IN VOID *Fdt, + IN CONST CHAR8 *IommuPropName, + IN CONST CHAR8 *SmmuNodeName, + IN CONST CHAR8 *DeviceNodeName + ) +{ + INT32 Node; + INT32 Error; + + Node = fdt_path_offset (Fdt, DeviceNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, DeviceNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_delprop (Fdt, Node, IommuPropName); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n", + __FUNCTION__, IommuPropName, fdt_strerror (Error))); + return; + } + + Node = fdt_path_offset (Fdt, SmmuNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_del_node (Fdt, Node); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Error))); + } +} + #define STYX_SOC_VERSION_MASK 0xFFF #define STYX_SOC_VERSION_A0 0x000 #define STYX_SOC_VERSION_B0 0x010 @@ -216,6 +257,16 @@ SetSocIdStatus ( #else SetDeviceStatus (Fdt, "kcs@e0010000", FALSE); #endif + + if (!PcdGetBool (PcdEnableSmmus)) { + DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000"); +#if DO_XGBE + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000"); +#endif + } }
STATIC diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 8bb6e9fa41cb..fcf2f058fbdf 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -37,6 +37,7 @@ DxeServicesLib FdtLib MemoryAllocationLib + PcdLib PrintLib UefiBootServicesTableLib
@@ -44,6 +45,7 @@ gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB + gAmdStyxTokenSpaceGuid.PcdEnableSmmus gArmTokenSpaceGuid.PcdSystemMemoryBase
[FixedPcd] diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index d380ea8714b85ec14f593b3795529c952e988df3..7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd 100644 GIT binary patch delta 2262 zcmcImOK1~O6rJ~?Z4;9;X;PDZG-^w!+G;FTi;6_STG84f{&qHwv4$pXX!=nUQt-bh zh<BwczdOZGRTLDv5UDHc)`e84D-{)7i4^adnHOScv0ZrK&b<3SbKko!`4k!6Q9JIM z`l@Nw!<wcwY1+~be%CU4nLW%*wtCjrKB&D|kVz){Be8Hp7-Sjw<zz01_9pAtT)#HF z1{NDL;&liUOYme8#uK)A%<n7><REh=Gn3fG57?QqYa=GZnn`BK3<c;1vr2e^*X|q{ z{*d7>(k6I)&frHm8YDF2%NCmn{Z95#=+#;Q{1^D*oct&T*#sZ$i$-Gfq#(9@%F^XG zfOkR6XB$2k6r#GqWl}h)y|DA2K_~<Y(OBW2n4(D0Nq#;r%9NrUN-6eo86UOV2c%$U zdzClW!EP9T+q+>*IHogRa|FaHdg|zkHHtNSvdqjy9JrlN(vYUPS}YwmQS65Ulhr_R z)D*MwK%RUyPrgDI7PN`GH0t!zmjwawjKZRVLeA=GU~h6&Qp#C^mL*&pji8m;06$f@ zJktiP$_*%`7p{d?&^OmiRU+>7M*313b}R3f?&-XLx=*`uPPlkOXNm{6@nDJf)|Z+? z`qyBI$&?<48C^qXzgxaIQmT``sM@na%K6mpDVH)hlJI;M;s+fpxs<UcB|7Ixxn|Y* z3(bsU-pbx;P}Cae8ll9bAPp3toF-@(b9}b-DaKfOXrkntdD??C<ZG6)hQ@piQikcb zuLg!{|7tNwd;QHTWH_Em#t(JrX=G-y63Ga!RZ#{ZcZ|I9AC(BM3y^moTS4&VVUs$I z2Lfftfe{54GArx(%fUd|RaRiMz>XZ_9SR2n;x)AdcbnOp=|iyfe^hu>wpQ)ux;gJ> z2SWzUZa>@EQ|+f(qZ=8upJ)*jp#1&hYej8?v7eC5o6o$qo8}CDh%<nMacgIjzk`Yy zKyrU{+E`ZT)fzst0bgR}gD<K<Hozb6Oh$G3T2_i(K2@=Wwv~4`POuf33)tzGynf^6 zt=lY_I-XVy7b-4twi|wY)cMBks4U-XgNpB16>jr#fw(d1rjAY7&Z^%7bP^Pzri!g5 zj(d3+9y}a*^w@9$E`<T78EfeBFsQT4cxHtG4FQGde&uFqE2r<32Sg3EEc&>isx#4Z zIGU)BclX75d;3#;X{{>WgMSiwERjfSN0QNcz2{i0H`d*!>4_e_E3Fy!G;Lb^)^55c Pqp1-`XuY64OMHI-={_7_
delta 1263 zcmcIj-%C?*6hGfv&8fTlVRO#SAInMjYiMF31Q{k`52X=QPujY>xwXw*+{!@9J@ppE z4*da{Jr$^}pohTMd@`Xx=w&@fM*0|xi0quZAB~~VO9#%q-*Z0aoX_{1@Av!Y!uGkg z5AyFl0FMd)0|1TJ>EA|bBejx}9FfWI!A`q-_58E}+l{wvo8*=lVw_|P-x*sZ*v5=; z>HtuyoE4k6Q#nW9K-EGmr*mpSnQRxcRd*%GqE_wIOBBFL22<5;T&upqxZUJ!FD;<s ze(mO@rbNON%fh)w0YnAfFojjKIOQvNjpX$Jn34eUDEy7=rZr0;b1-KX?Xfa@qRgJb z9(hbW#H8FQQrIKhxNNrLXW4pCFLtz=T|BNX^BKw+x76Z&v!j^TdRUGzWvMAmE2Vm2 zIfN=>86*ymwKRCndPwk!H70MBjA0SGY_sh=%Cx40xMv;^4{?nRk_FPj(AIIs*3l$B z0_^Kp{!@_)5gAJRn(nFjF2oi#*dJrC_CfB_I8%-hN&LW3N3SIIao%x~{Y#E+Lpr2I zLx7i!cHDFLI>bKPlVK&EubrosEM$uu51+i`Ob^%HlDNvtdbG8cM4Jfh#c@|%{SbNi z7PIE}2#j9EB%$0bS7ogtWhO@FaK%+8p5S}erCj+DoN!<KFBE+ZeVA#~Z_2O6<<rag zT^MK=>(bN3XG_n?Q#=yjS8<G#aDBJ@es?j`<m#6`(UKnuH^J$ddsESnex5lWkL(*^ z&U_60=ur<e4{?k0&E?#yuhOsIaExA%u7l3aGvqaslyMgZ`0w0rJ!d89CuTj@gaOA- zd^xT}VoEp;fvDf7#DeOKI-S69%SL+G+b>$Z@x+YkkNQFZpQ1)0afl}Zu{#N$=1&A6 KswRT50Q><AjNWko
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index b462910b3bf0..c896bba18056 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -122,12 +122,39 @@ phandle = <0x3>; };
+ sata0_smmu: smmu@e0200000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0200000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 332 4>, + <0 332 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0c00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 331 4>, + <0 331 4>; + #iommu-cells = <2>; + dma-coherent; + }; + sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0x0 0xe0300000 0x0 0xf0000>; interrupts = <0x0 0x163 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ };
sata@e0d00000 { @@ -137,6 +164,7 @@ interrupts = <0x0 0x162 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ };
i2c@e1000000 { @@ -257,6 +285,7 @@ #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; device_type = "pci"; bus-range = <0x0 0x7f>; msi-parent = <0x4>; @@ -283,6 +312,19 @@ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ };
+ pcie_smmu: smmu@e0a00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0a00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 333 4>, + <0 333 4>; + #iommu-cells = <1>; + dma-coherent; + }; + ccn@0xe8000000 { compatible = "arm,ccn-504"; reg = <0x0 0xe8000000 0x0 0x1000000>; @@ -382,6 +424,32 @@ phandle = <0xa>; };
+ xgmac0_smmu: smmu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 336 4>, + <0 336 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 335 4>, + <0 335 4>; + #iommu-cells = <2>; + dma-coherent; + }; + xgmac@e0700000 { status = "disabled"; compatible = "amd,xgbe-seattle-v1a"; @@ -397,8 +465,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0x9>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xb>; phandle = <0xb>; }; @@ -418,8 +486,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0xa>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xc>; phandle = <0xc>; };
On Thu, Jun 01, 2017 at 09:43:51AM +0000, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 51 ++++++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 + Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8293 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 72 +++++++++++++++++++- 4 files changed, 123 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index b18caf19985b..093db6517c1a 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -22,6 +22,7 @@ #include <Library/DebugLib.h> #include <Library/DxeServicesLib.h> #include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> #include <Library/PrintLib.h> #include <Library/UefiBootServicesTableLib.h> @@ -189,6 +190,46 @@ SetMacAddress ( #endif +STATIC +VOID +DisableSmmu (
- IN VOID *Fdt,
- IN CONST CHAR8 *IommuPropName,
- IN CONST CHAR8 *SmmuNodeName,
- IN CONST CHAR8 *DeviceNodeName
- )
+{
- INT32 Node;
- INT32 Error;
- Node = fdt_path_offset (Fdt, DeviceNodeName);
- if (Node <= 0) {
- DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
__FUNCTION__, DeviceNodeName, fdt_strerror (Node)));- return;
- }
- Error = fdt_delprop (Fdt, Node, IommuPropName);
- if (Error != 0) {
- DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n",
__FUNCTION__, IommuPropName, fdt_strerror (Error)));- return;
- }
- Node = fdt_path_offset (Fdt, SmmuNodeName);
- if (Node <= 0) {
- DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
__FUNCTION__, SmmuNodeName, fdt_strerror (Node)));- return;
- }
- Error = fdt_del_node (Fdt, Node);
- if (Error != 0) {
- DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n",
__FUNCTION__, SmmuNodeName, fdt_strerror (Error)));- }
+}
#define STYX_SOC_VERSION_MASK 0xFFF #define STYX_SOC_VERSION_A0 0x000 #define STYX_SOC_VERSION_B0 0x010 @@ -216,6 +257,16 @@ SetSocIdStatus ( #else SetDeviceStatus (Fdt, "kcs@e0010000", FALSE); #endif
- if (!PcdGetBool (PcdEnableSmmus)) {
- DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");
- DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");
- DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");
+#if DO_XGBE
- DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000");
- DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000");
+#endif
- }
} STATIC diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 8bb6e9fa41cb..fcf2f058fbdf 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -37,6 +37,7 @@ DxeServicesLib FdtLib MemoryAllocationLib
- PcdLib PrintLib UefiBootServicesTableLib
@@ -44,6 +45,7 @@ gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB
- gAmdStyxTokenSpaceGuid.PcdEnableSmmus gArmTokenSpaceGuid.PcdSystemMemoryBase
[FixedPcd] diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index d380ea8714b85ec14f593b3795529c952e988df3..7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd 100644 GIT binary patch delta 2262 zcmcImOK1~O6rJ~?Z4;9;X;PDZG-^w!+G;FTi;6_STG84f{&qHwv4$pXX!=nUQt-bh zh<BwczdOZGRTLDv5UDHc)`e84D-{)7i4^adnHOScv0ZrK&b<3SbKko!`4k!6Q9JIM z`l@Nw!<wcwY1+~be%CU4nLW%*wtCjrKB&D|kVz){Be8Hp7-Sjw<zz01_9pAtT)#HF z1{NDL;&liUOYme8#uK)A%<n7><REh=Gn3fG57?QqYa=GZnn`BK3<c;1vr2e^*X|q{ z{*d7>(k6I)&frHm8YDF2%NCmn{Z95#=+#;Q{1^D*oct&T*#sZ$i$-Gfq#(9@%F^XG zfOkR6XB$2k6r#GqWl}h)y|DA2K_~<Y(OBW2n4(D0Nq#;r%9NrUN-6eo86UOV2c%$U zdzClW!EP9T+q+>*IHogRa|FaHdg|zkHHtNSvdqjy9JrlN(vYUPS}YwmQS65Ulhr_R z)D*MwK%RUyPrgDI7PN`GH0t!zmjwawjKZRVLeA=GU~h6&Qp#C^mL*&pji8m;06$f@ zJktiP$_*%`7p{d?&^OmiRU+>7M*313b}R3f?&-XLx=*`uPPlkOXNm{6@nDJf)|Z+? z`qyBI$&?<48C^qXzgxaIQmT``sM@na%K6mpDVH)hlJI;M;s+fpxs<UcB|7Ixxn|Y* z3(bsU-pbx;P}Cae8ll9bAPp3toF-@(b9}b-DaKfOXrkntdD??C<ZG6)hQ@piQikcb zuLg!{|7tNwd;QHTWH_Em#t(JrX=G-y63Ga!RZ#{ZcZ|I9AC(BM3y^moTS4&VVUs$I z2Lfftfe{54GArx(%fUd|RaRiMz>XZ_9SR2n;x)AdcbnOp=|iyfe^hu>wpQ)ux;gJ> z2SWzUZa>@EQ|+f(qZ=8upJ)*jp#1&hYej8?v7eC5o6o$qo8}CDh%<nMacgIjzk`Yy zKyrU{+E`ZT)fzst0bgR}gD<K<Hozb6Oh$G3T2_i(K2@=Wwv~4`POuf33)tzGynf^6 zt=lY_I-XVy7b-4twi|wY)cMBks4U-XgNpB16>jr#fw(d1rjAY7&Z^%7bP^Pzri!g5 zj(d3+9y}a*^w@9$E`<T78EfeBFsQT4cxHtG4FQGde&uFqE2r<32Sg3EEc&>isx#4Z zIGU)BclX75d;3#;X{{>WgMSiwERjfSN0QNcz2{i0H`d*!>4_e_E3Fy!G;Lb^)^55c Pqp1-`XuY64OMHI-={_7_
delta 1263 zcmcIj-%C?*6hGfv&8fTlVRO#SAInMjYiMF31Q{k`52X=QPujY>xwXw*+{!@9J@ppE z4*da{Jr$^}pohTMd@`Xx=w&@fM*0|xi0quZAB~~VO9#%q-*Z0aoX_{1@Av!Y!uGkg z5AyFl0FMd)0|1TJ>EA|bBejx}9FfWI!A`q-_58E}+l{wvo8*=lVw_|P-x*sZ*v5=; z>HtuyoE4k6Q#nW9K-EGmr*mpSnQRxcRd*%GqE_wIOBBFL22<5;T&upqxZUJ!FD;<s ze(mO@rbNON%fh)w0YnAfFojjKIOQvNjpX$Jn34eUDEy7=rZr0;b1-KX?Xfa@qRgJb z9(hbW#H8FQQrIKhxNNrLXW4pCFLtz=T|BNX^BKw+x76Z&v!j^TdRUGzWvMAmE2Vm2 zIfN=>86*ymwKRCndPwk!H70MBjA0SGY_sh=%Cx40xMv;^4{?nRk_FPj(AIIs*3l$B z0_^Kp{!@_)5gAJRn(nFjF2oi#*dJrC_CfB_I8%-hN&LW3N3SIIao%x~{Y#E+Lpr2I zLx7i!cHDFLI>bKPlVK&EubrosEM$uu51+i`Ob^%HlDNvtdbG8cM4Jfh#c@|%{SbNi z7PIE}2#j9EB%$0bS7ogtWhO@FaK%+8p5S}erCj+DoN!<KFBE+ZeVA#~Z_2O6<<rag zT^MK=>(bN3XG_n?Q#=yjS8<G#aDBJ@es?j`<m#6`(UKnuH^J$ddsESnex5lWkL(*^ z&U_60=ur<e4{?k0&E?#yuhOsIaExA%u7l3aGvqaslyMgZ`0w0rJ!d89CuTj@gaOA- zd^xT}VoEp;fvDf7#DeOKI-S69%SL+G+b>$Z@x+YkkNQFZpQ1)0afl}Zu{#N$=1&A6 KswRT50Q><AjNWko
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index b462910b3bf0..c896bba18056 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -122,12 +122,39 @@ phandle = <0x3>; };
sata0_smmu: smmu@e0200000 {compatible = "arm,mmu-401";reg = <0 0xe0200000 0 0x10000>;#global-interrupts = <1>;interrupts = /* Uses combined intr for both* global and context*/<0 332 4>,<0 332 4>;#iommu-cells = <2>;dma-coherent;};sata1_smmu: smmu@e0c00000 {compatible = "arm,mmu-401";reg = <0 0xe0c00000 0 0x10000>;#global-interrupts = <1>;interrupts = /* Uses combined intr for both* global and context*/<0 331 4>,<0 331 4>;#iommu-cells = <2>;dma-coherent;};- sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0x0 0xe0300000 0x0 0xf0000>; interrupts = <0x0 0x163 0x4>; clocks = <0x2>; dma-coherent;
iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */sata@e0d00000 { @@ -137,6 +164,7 @@ interrupts = <0x0 0x162 0x4>; clocks = <0x2>; dma-coherent;
iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */i2c@e1000000 { @@ -257,6 +285,7 @@ #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>;
iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; device_type = "pci"; bus-range = <0x0 0x7f>; msi-parent = <0x4>;@@ -283,6 +312,19 @@ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ };
pcie_smmu: smmu@e0a00000 {compatible = "arm,mmu-401";reg = <0 0xe0a00000 0 0x10000>;#global-interrupts = <1>;interrupts = /* Uses combined intr for both* global and context*/<0 333 4>,<0 333 4>;#iommu-cells = <1>;dma-coherent;};- ccn@0xe8000000 { compatible = "arm,ccn-504"; reg = <0x0 0xe8000000 0x0 0x1000000>;
@@ -382,6 +424,32 @@ phandle = <0xa>; };
xgmac0_smmu: smmu@e0600000 {compatible = "arm,mmu-401";reg = <0 0xe0600000 0 0x10000>;#global-interrupts = <1>;interrupts = /* Uses combined intr for both* global and context*/<0 336 4>,<0 336 4>;#iommu-cells = <2>;dma-coherent;};xgmac1_smmu: smmu@e0800000 {compatible = "arm,mmu-401";reg = <0 0xe0800000 0 0x10000>;#global-interrupts = <1>;interrupts = /* Uses combined intr for both* global and context*/<0 335 4>,<0 335 4>;#iommu-cells = <2>;dma-coherent;};- xgmac@e0700000 { status = "disabled"; compatible = "amd,xgbe-seattle-v1a";
@@ -397,8 +465,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0x9>; phy-mode = "xgmii";
#stream-id-cells = <0x18>; dma-coherent;
iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xb>; phandle = <0xb>;@@ -418,8 +486,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0xa>; phy-mode = "xgmii";
#stream-id-cells = <0x18>; dma-coherent;
iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xc>; phandle = <0xc>;-- 2.9.3
As reported by Punit, Xen panics in the following way when booted on Overdrive when using this firmware:
(XEN) **************************************** (XEN) Panic on CPU 0: (XEN) GICv2: Sizes of GICC (0x00000000002000) and GICV (0x00000000010000) don't match (XEN) (XEN) ****************************************
This is due to the fact that the MMIO region sizes deviate from the Linux upstream version of the DTS for no good reason. So fix that.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index 7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd..c8e5fd980bce305186214aab10a7d399faa22500 100644 GIT binary patch delta 31 fcmeD6?DgERlu?L5fdK>_ih(I0p|E*7<25A!an=T}
delta 31 fcmeD6?DgERlu?M00Sq3BL1+d>hRxd<uPFflZgd85
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index c896bba18056..4039f666004a 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -31,8 +31,8 @@ #size-cells = <0x2>; reg = <0x0 0xe1110000 0x0 0x1000>, <0x0 0xe112f000 0x0 0x2000>, - <0x0 0xe1140000 0x0 0x10000>, - <0x0 0xe1160000 0x0 0x10000>; + <0x0 0xe1140000 0x0 0x2000>, + <0x0 0xe1160000 0x0 0x2000>; interrupts = <0x1 0x9 0xf04>; ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; linux,phandle = <0x1>;
On Thu, Jun 01, 2017 at 09:43:52AM +0000, Ard Biesheuvel wrote:
As reported by Punit, Xen panics in the following way when booted on Overdrive when using this firmware:
(XEN) **************************************** (XEN) Panic on CPU 0: (XEN) GICv2: Sizes of GICC (0x00000000002000) and GICV (0x00000000010000) don't match (XEN) (XEN) ****************************************
This is due to the fact that the MMIO region sizes deviate from the Linux upstream version of the DTS for no good reason. So fix that.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org But don't we also want a comment from Punit? (added to cc)
Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index 7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd..c8e5fd980bce305186214aab10a7d399faa22500 100644 GIT binary patch delta 31 fcmeD6?DgERlu?L5fdK>_ih(I0p|E*7<25A!an=T}
delta 31 fcmeD6?DgERlu?M00Sq3BL1+d>hRxd<uPFflZgd85
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index c896bba18056..4039f666004a 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -31,8 +31,8 @@ #size-cells = <0x2>; reg = <0x0 0xe1110000 0x0 0x1000>, <0x0 0xe112f000 0x0 0x2000>,
<0x0 0xe1140000 0x0 0x10000>,<0x0 0xe1160000 0x0 0x10000>;
<0x0 0xe1140000 0x0 0x2000>,<0x0 0xe1160000 0x0 0x2000>;-- 2.9.3
Leif Lindholm leif.lindholm@linaro.org writes:
On Thu, Jun 01, 2017 at 09:43:52AM +0000, Ard Biesheuvel wrote:
As reported by Punit, Xen panics in the following way when booted on Overdrive when using this firmware:
(XEN) **************************************** (XEN) Panic on CPU 0: (XEN) GICv2: Sizes of GICC (0x00000000002000) and GICV (0x00000000010000) don't match (XEN) (XEN) ****************************************
This is due to the fact that the MMIO region sizes deviate from the Linux upstream version of the DTS for no good reason. So fix that.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org But don't we also want a comment from Punit? (added to cc)
Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index 7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd..c8e5fd980bce305186214aab10a7d399faa22500 100644 GIT binary patch delta 31 fcmeD6?DgERlu?L5fdK>_ih(I0p|E*7<25A!an=T}
delta 31 fcmeD6?DgERlu?M00Sq3BL1+d>hRxd<uPFflZgd85
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index c896bba18056..4039f666004a 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -31,8 +31,8 @@ #size-cells = <0x2>; reg = <0x0 0xe1110000 0x0 0x1000>, <0x0 0xe112f000 0x0 0x2000>,
<0x0 0xe1140000 0x0 0x10000>,<0x0 0xe1160000 0x0 0x10000>;
<0x0 0xe1140000 0x0 0x2000>,<0x0 0xe1160000 0x0 0x2000>;-- 2.9.3
Overriding the device tree with one containing a similar change made Xen boot for me.
Acked-by: Punit Agrawal punit.agrawal@arm.com
Thanks!
The DT and ACPI descriptions of the PCIe root complex only specify a bus range of [0x0, 0x7f]. So let's use the same range in UEFI.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index b4893ca34587..98f5c9452dcd 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -423,7 +423,7 @@ DEFINE DO_KCS = 1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
gArmTokenSpaceGuid.PcdPciBusMin|0x0 - gArmTokenSpaceGuid.PcdPciBusMax|0xFF + gArmTokenSpaceGuid.PcdPciBusMax|0x7F
gArmTokenSpaceGuid.PcdPciIoBase|0x1000 gArmTokenSpaceGuid.PcdPciIoSize|0xF000
On Thu, Jun 01, 2017 at 09:43:53AM +0000, Ard Biesheuvel wrote:
The DT and ACPI descriptions of the PCIe root complex only specify a bus range of [0x0, 0x7f]. So let's use the same range in UEFI.
Sounds like a good idea... Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index b4893ca34587..98f5c9452dcd 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -423,7 +423,7 @@ DEFINE DO_KCS = 1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 gArmTokenSpaceGuid.PcdPciBusMin|0x0
- gArmTokenSpaceGuid.PcdPciBusMax|0xFF
- gArmTokenSpaceGuid.PcdPciBusMax|0x7F
gArmTokenSpaceGuid.PcdPciIoBase|0x1000 gArmTokenSpaceGuid.PcdPciIoSize|0xF000 -- 2.9.3
-
Ard Biesheuvel -
Graeme Gregory -
Leif Lindholm -
Punit Agrawal