As some definitions are about OemMiscLib, so move them from SerdesLib.h to OemMiscLib.h and drop some useless function definitions. After doing this, some unnecessary references can be removed for D03/D05.

SerdesLib is useless for SmbiosMiscDxe and D06, so remove it and delete SerdesLib.h for D06.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/D06.dsc | 2 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 109 -------------------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 64 ------------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 --------------- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 ++++++++++++++ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 1 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- 11 files changed, 77 insertions(+), 266 deletions(-)

diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 396bd03c9d24..cbbd99e4a659 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -64,8 +64,6 @@ [LibraryClasses.common]

CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf

- SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 61cead7779b9..669e6a2d52cc 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -69,6 +69,7 @@ [LibraryClasses] BaseMemoryLib BaseLib DebugLib + OemMiscLib UefiBootServicesTableLib UefiRuntimeServicesTableLib UefiDriverEntryPoint @@ -77,7 +78,6 @@ [LibraryClasses]

IpmiCmdLib

- SerdesLib

[Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 077dd5edc847..b493dd9ac090 100755 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -16,116 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_

-typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Sas0X8 = 2, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - -typedef enum { - Em32coreEvbBoard = 0, - Em16coreEvbBoard = 1, - EmV2R1CO5Borad = 2, - EmOtherBorad -} BOARD_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); - EFI_STATUS EfiSerdesInitWrap (VOID);

-void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg); - -//EYE test -UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData); - -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - -//PRBS test -int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype); - -int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane); - -//CTLE/DFE -void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane); -//int serdes_reset(UINT32 macro); -//int serdes_release_reset(UINT32 macro); -void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode); -void serdes_ffe_show(UINT32 macro,UINT32 lane); -void serdes_dfe_show(UINT32 macro,UINT32 lane); -int serdes_read_bert(UINT8 macro, UINT8 lane); -void serdes_clean_bert(UINT8 macro, UINT8 lane); -int serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate); -void serdes_release_mcu(UINT32 macro,UINT32 val); -int hilink_write(UINT32 macro, UINT32 reg, UINT32 value); -int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value); -int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN -int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val); -int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val); -void serdes_ctle_show(UINT32 macro,UINT32 lane); -int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num); -int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num); -int report_serdes_mux(void); -int serdes_key_reg_show(UINT32 macro); -void serdes_state_show(UINT32 macro); -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - #endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h index 7ff924bd8954..b493dd9ac090 100644 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -16,71 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_

-typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); -VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - EFI_STATUS EfiSerdesInitWrap (VOID); -INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);

#endif diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h deleted file mode 100644 index 05f0f7020e82..000000000000 --- a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType (UINT8 EthChannel); -VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - -EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode); -INT32 SerdesReset (UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro); -INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode); -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index 86ea6a1b3deb..b5a768856484 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,67 @@ #include <PlatformArch.h> #include <Library/I2CLib.h>

+#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + +typedef enum { + EmHilink0Hccs1X8 = 0, + EmHilink0Pcie1X8 = 2, + EmHilink0Pcie1X4Pcie2X4 = 3, + EmHilink0Sas2X8 = 4, + EmHilink0Hccs1X8Width16, + EmHilink0Hccs1X8Width32, + EmHilink0Hccs1X8Speed5G, +} HILINK0_MODE_TYPE; + +typedef enum { + EmHilink1Sas2X1 = 0, + EmHilink1Hccs0X8 = 1, + EmHilink1Pcie0X8 = 2, + EmHilink1Hccs0X8Width16, + EmHilink1Hccs0X8Width32, + EmHilink1Hccs0X8Speed5G, +} HILINK1_MODE_TYPE; + +typedef enum { + EmHilink2Pcie2X8 = 0, + EmHilink2Hccs2X8 = 1, + EmHilink2Sas0X8 = 2, + EmHilink2Hccs2X8Width16, + EmHilink2Hccs2X8Width32, + EmHilink2Hccs2X8Speed5G, +} HILINK2_MODE_TYPE; + +typedef enum { + EmHilink5Pcie3X4 = 0, + EmHilink5Pcie2X2Pcie3X2 = 1, + EmHilink5Sas1X4 = 2, +} HILINK5_MODE_TYPE; + + +typedef struct { + HILINK0_MODE_TYPE Hilink0Mode; + HILINK1_MODE_TYPE Hilink1Mode; + HILINK2_MODE_TYPE Hilink2Mode; + UINT32 Hilink3Mode; + UINT32 Hilink4Mode; + HILINK5_MODE_TYPE Hilink5Mode; + UINT32 Hilink6Mode; + UINT32 UseSsc; +} SERDES_PARAM; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -53,4 +114,18 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);

extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); +UINTN OemGetCpuFreq (UINT8 Socket); + +UINTN +OemGetHccsFreq ( + VOID + ); + +EFI_STATUS +OemGetSerdesParam ( + SERDES_PARAM *ParamA, + SERDES_PARAM *ParamB, + UINT32 SocketId + ); + #endif diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 4771cb900c82..218b3540eb7f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -21,7 +21,6 @@

#include <PlatformArch.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Library/I2CLib.h> #include <Library/HiiLib.h>

diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c index ae4c194070e8..1a9ed620c80c 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -22,7 +22,6 @@ #include <Library/I2CLib.h> #include <Library/IoLib.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Protocol/Smbios.h>

diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c index 7e3f2e2a0e7d..c28ac6266fc6 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c @@ -21,7 +21,6 @@ #include <Library/I2CLib.h> #include <Library/IoLib.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Protocol/Smbios.h>

#include <PlatformArch.h> diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 2a9db46d1ff9..c5cb77696031 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -24,7 +24,6 @@ #include <Library/OemMiscLib.h> #include <Library/PcdLib.h> #include <Library/PlatformSysCtrlLib.h> -#include <Library/SerdesLib.h> #include <Library/SerialPortLib.h> #include <Library/TimerLib.h>

diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index bc33639ac51d..945fd4c6e3c0 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -17,7 +17,7 @@

#include "SmbiosMisc.h"

-#include <Library/SerdesLib.h> +#include <Library/OemMiscLib.h>

extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data; extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data;

DriverHealthManagerDxe Collect driver health form of third party drivers to repair no healthy card.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/D03.dsc | 1 + Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D06/D06.dsc | 1 + Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 1 + 6 files changed, 6 insertions(+)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 3f59be22ec8e..fe443dd929ad 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -492,6 +492,7 @@ [Components.common]

MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 25db1c38d287..0c4f21fbe056 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -638,6 +638,7 @@ [Components.common] MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index cbbd99e4a659..6d581337f199 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -435,6 +435,7 @@ [Components.common] Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index f453f9e46321..3f07b2e57778 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -295,6 +295,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 85dd791564a4..9632aea4b00e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -314,6 +314,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index fda29ab322e9..a937660a09e2 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -319,6 +319,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

[FV.FVMAIN_COMPACT]

From: Jason Zhang zhangjinsong2@huawei.com

BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA, - attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 27fde2e09bfe..0f2d11bb952b 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -759,20 +759,20 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added - Package () {0x04FFFF,0,0,640}, // INT_A - Package () {0x04FFFF,1,0,641}, // INT_B - Package () {0x04FFFF,2,0,642}, // INT_C - Package () {0x04FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A + Package () {0x4FFFF,1,0,641}, // INT_B + Package () {0x4FFFF,2,0,642}, // INT_C + Package () {0x4FFFF,3,0,643}, // INT_D

- Package () {0x08FFFF,0,0,640}, // INT_A - Package () {0x08FFFF,1,0,641}, // INT_B - Package () {0x08FFFF,2,0,642}, // INT_C - Package () {0x08FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A + Package () {0x8FFFF,1,0,641}, // INT_B + Package () {0x8FFFF,2,0,642}, // INT_C + Package () {0x8FFFF,3,0,643}, // INT_D

- Package () {0x0CFFFF,0,0,640}, // INT_A - Package () {0x0CFFFF,1,0,641}, // INT_B - Package () {0x0CFFFF,2,0,642}, // INT_C - Package () {0x0CFFFF,3,0,643}, // INT_D + Package () {0xCFFFF,0,0,640}, // INT_A + Package () {0xCFFFF,1,0,641}, // INT_B + Package () {0xCFFFF,2,0,642}, // INT_C + Package () {0xCFFFF,3,0,643}, // INT_D

Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B

From: xingjiang tang tangxingjiang@huawei.com

Implementation OemGetCpuFreq() to get cpu frequency from cpld to encapsulate project difference, for some projects don't support get cpu frequency by this way.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 ++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)

diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h index ec9b49f4e70d..8eb333de529c 100644 --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h @@ -36,4 +36,8 @@ #define CPLD_X8_X8_X8_BOARD_ID 0x92 #define CPLD_X16_X8_BOARD_ID 0x93

+#define CPLD_CLOCK_FLAG 0xFD +#define CPLD_BOM_VER_FLAG 0x0B +#define CPLD_BOARD_REVISION_4TH 0x4 + #endif /* __CPLDD06_H__ */ diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c5cb77696031..c8f71ecf890a 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -206,3 +206,19 @@ OemIsNeedDisableExpanderBuffer ( { return TRUE; } + +UINTN OemGetCpuFreq (UINT8 Socket) +{ + UINT8 BoardRevision; + + BoardRevision = MmioRead8 (CPLD_BASE_ADDRESS + CPLD_BOM_VER_FLAG); + + // Board revision 4 and higher run at 2.5GHz + // Earlier revisions run at 2GHz + if (BoardRevision >= CPLD_BOARD_REVISION_4TH) { + return 2500000000; + } else { + return 2000000000; + } +} +

Follow chip team suggestion, HCCS(Huawei Cache-Coherent System) may be unstable while speed is 3.0G, so use 2.6G to avoid some unstable stress issue.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c8f71ecf890a..758157525f40 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -222,3 +222,11 @@ UINTN OemGetCpuFreq (UINT8 Socket) } }

+UINTN +OemGetHccsFreq ( + VOID + ) +{ + return HCCS_PLL_VALUE_2600; +} +

As new IMP(Cortex-M7) firmware support self-adapte, so do not need BIOS to implement some function, remove useless funtions and report CPU0/CPU1 Nic NCL offset to IMP.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++---------------- 1 file changed, 54 insertions(+), 227 deletions(-)

diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c index aaf990216982..678c2107bdd3 100644 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c +++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c @@ -21,44 +21,21 @@ #include <Library/OemNicLib.h>

#define CPU2_SFP2_100G_CARD_OFFSET 0x25 -#define CPU1_SFP1_LOCATE_OFFSET 0x16 -#define CPU1_SFP0_LOCATE_OFFSET 0x12 -#define CPU2_SFP1_LOCATE_OFFSET 0x21 -#define CPU2_SFP0_LOCATE_OFFSET 0x19 -#define CPU2_SFP2_10G_GE_CARD_OFFSET 0x25

-#define SFP_10G_SPEED 10 -#define SFP_25G_SPEED 25 -#define SFP_100G_SPEED 100 -#define SFP_GE_SPEED 1 - -#define SFP_GE_SPEED_VAL_VENDOR_FINISAR 0x0C -#define SFP_GE_SPEED_VAL 0x0D -#define SFP_10G_SPEED_VAL 0x67 -#define SFP_25G_SPEED_VAL 0xFF +#define SOCKET1_NET_PORT_100G 1 +#define SOCKET0_NET_PORT_NUM 4 +#define SOCKET1_NET_PORT_NUM 2

#define CARD_PRESENT_100G (BIT7) -#define CARD_PRESENT_10G (BIT0) -#define SELECT_SFP_BY_INDEX(index) (1 << (index - 1)) -#define SPF_SPEED_OFFSET 12 - -#define SFP_DEVICE_ADDRESS 0x50 -#define CPU1_9545_I2C_ADDR 0x70 -#define CPU2_9545_I2C_ADDR 0x71 - -#define FIBER_PRESENT 0 -#define CARD_PRESENT 1 -#define I2C_PORT_SFP 4 -#define CPU2_I2C_PORT_SFP 5 - -#define SOCKET_0 0 -#define SOCKET_1 1 #define EEPROM_I2C_PORT 4 #define EEPROM_PAGE_SIZE 0x40 #define MAC_ADDR_LEN 6 #define I2C_OFFSET_EEPROM_ETH0 (0xc00) #define I2C_SLAVEADDR_EEPROM (0x52)

+#define SRAM_NIC_NCL1_OFFSET_ADDRESS 0xA0E87FE0 +#define SRAM_NIC_NCL2_OFFSET_ADDRESS 0xA0E87FE4 + #pragma pack(1) typedef struct { UINT16 Crc16; @@ -114,204 +91,6 @@ UINT16 CrcTable16[256] = { 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, };

-EFI_STATUS -GetSfpSpeed ( - UINT16 Socket, - UINT16 SfpNum, - UINT8* FiberSpeed - ) -{ - EFI_STATUS Status; - I2C_DEVICE SpdDev; - UINT8 SfpSelect; - UINT8 SfpSpeed; - UINT32 RegAddr; - UINT16 I2cAddr; - UINT32 SfpPort; - - SfpSpeed = 0x0; - if (Socket == SOCKET_1) { - I2cAddr = CPU2_9545_I2C_ADDR; - SfpPort = CPU2_I2C_PORT_SFP; - } else { - I2cAddr = CPU1_9545_I2C_ADDR; - SfpPort = I2C_PORT_SFP; - } - - Status = I2CInit (Socket, SfpPort, Normal); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Socket%d Call I2CInit failed! p1=0x%x.\n", - __FUNCTION__, __LINE__, Socket, Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = I2cAddr; - RegAddr = 0x0; - SfpSelect = SELECT_SFP_BY_INDEX (SfpNum); - - Status = I2CWrite (&SpdDev, RegAddr, 1, &SfpSelect); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CWrite Error =%r.\n", Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = SFP_DEVICE_ADDRESS; - - RegAddr = SPF_SPEED_OFFSET; - Status = I2CRead (&SpdDev, RegAddr, 1, &SfpSpeed); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CRead Error =%r.\n", Status)); - return Status; - } - - DEBUG ((DEBUG_INFO, "BR, Nominal, Nominal signalling rate, SfpSpeed: 0x%x\n", - SfpSpeed)); - - if (SfpSpeed == SFP_10G_SPEED_VAL) { - *FiberSpeed = SFP_10G_SPEED; - } else if (SfpSpeed == SFP_25G_SPEED_VAL) { - *FiberSpeed = SFP_25G_SPEED; - } else if ((SfpSpeed == SFP_GE_SPEED_VAL) || - (SfpSpeed == SFP_GE_SPEED_VAL_VENDOR_FINISAR)) { - *FiberSpeed = SFP_GE_SPEED; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type/Fiber3Type return: SFP_10G_SPEED, SFP_100G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu2FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type, - UINT8* Fiber100Ge - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - - if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { - // 100 Ge card - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = SFP_100G_SPEED; - DEBUG ((DEBUG_ERROR,"Detect Fiber SFP_100G is Present, Set 100Ge\n")); - } else if ((ReadCpldReg (CPU2_SFP2_10G_GE_CARD_OFFSET) & CARD_PRESENT_10G) != 0) { - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - if (ReadCpldReg (CPU2_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot0, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG((DEBUG_ERROR, - "Get Socket1 Sfp%d Speed Error: %r.\n", - SfpNum1, - Status)); - return Status; - } - if (SfpSpeed1 == SFP_25G_SPEED) { - // P1 don't support 25G, so set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } else { - *Fiber1Type = SfpSpeed1; - } - } else { - // No fiber, set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } - - if (ReadCpldReg (CPU2_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot1, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - if (SfpSpeed2 == SFP_25G_SPEED) { - *Fiber2Type = SFP_10G_SPEED; - } else { - *Fiber2Type = SfpSpeed2; - } - } else { - // No fiber, set speed to 10G - *Fiber2Type = SFP_10G_SPEED; - } - } else { - // 100Ge/10Ge/Ge Fiber is not found. - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type return: SFP_10G_SPEED, SFP_25G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu1FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - // Fiber detected in CPU1 slot0, read speed via i2c - if (ReadCpldReg (CPU1_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Socket0 Sfp%d Speed Error: %r.\n", - SfpNum1, Status)); - return Status; - } - *Fiber1Type = SfpSpeed1; - } else { - *Fiber1Type = SFP_10G_SPEED; - } - - // Fiber detected in CPU1 slot1, read speed via i2c - if (ReadCpldReg (CPU1_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - *Fiber2Type = SFP_10G_SPEED; - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - *Fiber2Type = SfpSpeed2; - } else { - *Fiber2Type = SFP_10G_SPEED; - } - - return EFI_SUCCESS; -} - UINT16 MakeCrcCheckSum ( UINT8 *Buffer, UINT32 Length @@ -567,3 +346,51 @@ OemIsInitEth ( { return TRUE; } + +EFI_STATUS +ConfigCDR ( + UINT32 Socket + ) +{ + return EFI_SUCCESS; +} + +UINT32 +OemGetNclConfOffset ( + UINT32 Socket + ) +{ + UINT32 ConfigurationOffset; + + if (Socket == 0) { + // For 1st socket, the NCL configuration offset is 0 + ConfigurationOffset = 0; + MmioWrite32 (SRAM_NIC_NCL1_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; + } + + // For 2nd Socket + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + ConfigurationOffset = SIZE_128KB; + } else { + ConfigurationOffset = SIZE_64KB; + } + MmioWrite32 (SRAM_NIC_NCL2_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; +} + +UINT32 +OemGetNetPortNum ( + UINT32 Socket + ) +{ + if (Socket == 0){ + return SOCKET0_NET_PORT_NUM; + } + + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + return SOCKET1_NET_PORT_100G; + } else { + return SOCKET1_NET_PORT_NUM; + } +}

Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment).

The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-)

diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);

- suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif;

goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);

- goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof;

endform;

-form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"

As secure boot is not ready, remove SECURE_BOOT_ENABLE and relative code.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D06/D06.dsc | 12 ------------ Platform/Hisilicon/D06/D06.fdf | 11 ----------- 2 files changed, 23 deletions(-)

diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 6d581337f199..a3a01bfb1e23 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -30,7 +30,6 @@ [Defines] FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE NETWORK_IP6_ENABLE = FALSE DEFINE HTTP_BOOT_ENABLE = FALSE - DEFINE SECURE_BOOT_ENABLE = FALSE

!include Silicon/Hisilicon/Hisilicon.dsc.inc

@@ -87,9 +86,6 @@ [LibraryClasses.common] LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf -!endif PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf

@@ -290,15 +286,7 @@ [Components.common] MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf

-!if $(SECURE_BOOT_ENABLE) == TRUE - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { - <LibraryClasses> - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf - } - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!else MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -!endif Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index f72b513352fb..e402628a1b35 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -88,17 +88,10 @@ [FD.D06] #Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER -!if $(SECURE_BOOT_ENABLE) == TRUE - #Signature: gEfiAuthenticatedVariableGuid = - # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else #Signature: gEfiVariableGuid = # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 0xB8, 0xdF, 0x00, 0x00, #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 @@ -183,10 +176,6 @@ [FV.FvMain] INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf

-!if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!endif - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

Last patch "Modify IORT" change revision id of node type 2 to 1, and 4.19 later kernel will judge the revision id to get root pci bridge DMA informations from IORT. As Hi1620 USB 2.0 don't support 64 bit DMA, but the DMA attribute get from IORT node type 2 is 64 bit. So add _DMA method in USB pci bridge 3 and pci bridge 8 to fix usb crash when usb device is present issue.

https://bugs.linaro.org/show_bug.cgi?id=4079

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+)

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 6dc380f27fa2..c1083dc16a2a 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -375,6 +375,29 @@ Device (PCI2)

PCI_OSC_SUPPORT ()

+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1077,6 +1100,29 @@ Device (PCI8) Return (0xf) }

+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_PXM, 0, NotSerialized) { Return(0x02)