The upcoming RISC-V Ssdtso specification introduces a bit in the senvcfg CSR to switch the memory consistency model of user mode at run-time from RVWMO to TSO. The active consistency model can therefore be switched on a per-hart base and managed by the kernel on a per-process base.
This patchset implements basic Ssdtso support and adds a prctl API on top so that user-space processes can switch to a stronger memory consistency model (than the kernel was written for) at run-time. The patchset also comes with a short documentation of the prctl API.
This series is based on the third draft of the Ssdtso specification which can be found here: https://github.com/riscv/riscv-ssdtso/releases/tag/v1.0-draft3 Note, that the Ssdtso specification is in development state (i.e., not frozen or even ratified) which is also the reason why this series is marked as RFC.
This series saw the following changes since v1: * Reordered/restructured patches * Fixed build issues * Addressed typos * Removed ability to switch TSO->WMO * Moved the state from per-thread to per-process * Reschedule all CPUs after switching * Some cleanups in the documentation * Adding compatibility with Ztso (spec change in draft 3)
This patchset can also be found in this GitHub branch: https://github.com/cmuellner/linux/tree/ssdtso-v2
A QEMU implementation of DTSO can be found in this GitHub branch: https://github.com/cmuellner/qemu/tree/ssdtso-v2
Christoph Müllner (6): mm: Add dynamic memory consistency model switching uapi: prctl: Add new prctl call to set/get the memory consistency model RISC-V: Enable dynamic memory consistency model support with Ssdtso RISC-V: Implement prctl call to set/get the memory consistency model RISC-V: Expose Ssdtso via hwprobe API RISC-V: selftests: Add DTSO tests
Documentation/arch/riscv/hwprobe.rst | 3 + .../mm/dynamic-memory-consistency-model.rst | 86 ++++++++++++++++ Documentation/mm/index.rst | 1 + arch/Kconfig | 14 +++ arch/riscv/Kconfig | 11 +++ arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/dtso.h | 97 +++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/processor.h | 7 ++ arch/riscv/include/asm/switch_to.h | 3 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 3 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/dtso.c | 67 +++++++++++++ arch/riscv/kernel/sys_hwprobe.c | 2 + include/linux/sched.h | 5 + include/uapi/linux/prctl.h | 5 + kernel/sys.c | 12 +++ tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/dtso/.gitignore | 1 + tools/testing/selftests/riscv/dtso/Makefile | 11 +++ tools/testing/selftests/riscv/dtso/dtso.c | 82 ++++++++++++++++ 23 files changed, 416 insertions(+), 1 deletion(-) create mode 100644 Documentation/mm/dynamic-memory-consistency-model.rst create mode 100644 arch/riscv/include/asm/dtso.h create mode 100644 arch/riscv/kernel/dtso.c create mode 100644 tools/testing/selftests/riscv/dtso/.gitignore create mode 100644 tools/testing/selftests/riscv/dtso/Makefile create mode 100644 tools/testing/selftests/riscv/dtso/dtso.c
Some architectures have support to change the memory consistency model at run time. This patch adds a new field 'active_memory_consistency_model' to task_struct that allows architecture code to store the active model as a per-process property.
To avoid useless overhead, the mechanism needs to be explicitly enabled in the architecture's Kconfig.
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- .../mm/dynamic-memory-consistency-model.rst | 49 +++++++++++++++++++ Documentation/mm/index.rst | 1 + arch/Kconfig | 14 ++++++ include/linux/sched.h | 5 ++ 4 files changed, 69 insertions(+) create mode 100644 Documentation/mm/dynamic-memory-consistency-model.rst
diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Documentation/mm/dynamic-memory-consistency-model.rst new file mode 100644 index 000000000000..3117c3d82b2b --- /dev/null +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Dynamic memory consistency model switching +========================================== + +:Author: Christoph Müllner christoph.muellner@vrull.eu +:Date: 1 Feb 2024 + +This document gives an overview about dynamic memory consistency model +switching for user mode at run-time. + +Memory consistency models +========================= + +A memory consistency model is a set of guarantees a CPU architecture +provides about (re-)ordering memory accesses. Each architecture defines +its own model and set of rules within that, which are carefully specified. +The provided guarantees have consequences for the microarchitectures (e.g., +some memory consistency models allow reordering stores after loads) and +the software executed within this model (memory consistency models that +allow reordering memory accesses provide memory barrier instructions +to enforce additional guarantees when needed explicitly). + +Details about the architecture-independent memory consistency model abstraction +in the Linux kernel and the use of the different types of memory barriers +can be found here: + + Documentation/memory-barriers.txt + +Two models can be in a weaker/stronger relation. I.e., a consistency +model A is weaker/stronger than another model B if A provides a subset/superset +of the constraints that B provides. + +Some architectures define more than one memory consistency model. +On such architectures, switching the memory consistency model at run-time +to a stronger one is possible because software written for the weaker model is +compatible with the constraints of the stronger model. + +If two models are not in a weaker/stronger relation, switching between +them will violate the consistency assumptions that the software was +written under (i.e., causing subtle bugs that are very hard to debug). + +The following restrictions apply for switching the memory consistency model +at run-time: + +* Only switching from a weaker to a stronger model is safe. +* The stronger memory model affects all threads of a process, when running in user mode. +* Forked processes derive their active memory model from their parents. diff --git a/Documentation/mm/index.rst b/Documentation/mm/index.rst index 31d2ac306438..36d40502b421 100644 --- a/Documentation/mm/index.rst +++ b/Documentation/mm/index.rst @@ -43,6 +43,7 @@ above structured documentation, or deleted if it has served its purpose. arch_pgtable_helpers balance damon/index + dynamic-memory-consistency-model free_page_reporting hmm hwpoison diff --git a/arch/Kconfig b/arch/Kconfig index a5af0edd3eb8..89d4e27f9b80 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1479,6 +1479,20 @@ config ARCH_HAS_NONLEAF_PMD_YOUNG address translations. Page table walkers that clear the accessed bit may use this capability to reduce their search space.
+config ARCH_HAS_DYNAMIC_MEMORY_CONSISTENCY_MODEL + bool + help + An arch should select this symbol if it supports switching + the memory consistency model at run-time. + +config DYNAMIC_MEMORY_CONSISTENCY_MODEL + bool "Dynamic memory consistency model support" + depends on ARCH_HAS_DYNAMIC_MEMORY_CONSISTENCY_MODEL + default y + help + This option turns on the support to switch the memory consistency + model at runtime on a per-process-base. + source "kernel/gcov/Kconfig"
source "scripts/gcc-plugins/Kconfig" diff --git a/include/linux/sched.h b/include/linux/sched.h index ffe8f618ab86..5cbd3a3b80ab 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -979,6 +979,11 @@ struct task_struct { /* Canary value for the -fstack-protector GCC feature: */ unsigned long stack_canary; #endif + +#ifdef CONFIG_DYNAMIC_MEMORY_CONSISTENCY_MODEL + unsigned long memory_consistency_model; +#endif + /* * Pointers to the (original) parent process, youngest child, younger sibling, * older sibling, respectively. (p->father can be replaced with
This patch defines a prctl uAPI for switching the active memory consistency model of user-space processes.
The implementation follows the way other prctl calls are implemented by disabling them unless arch-specific code provides the relevant macros.
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- .../mm/dynamic-memory-consistency-model.rst | 27 +++++++++++++++++++ include/uapi/linux/prctl.h | 3 +++ kernel/sys.c | 12 +++++++++ 3 files changed, 42 insertions(+)
diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Documentation/mm/dynamic-memory-consistency-model.rst index 3117c3d82b2b..1fce855a1fad 100644 --- a/Documentation/mm/dynamic-memory-consistency-model.rst +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -47,3 +47,30 @@ at run-time: * Only switching from a weaker to a stronger model is safe. * The stronger memory model affects all threads of a process, when running in user mode. * Forked processes derive their active memory model from their parents. + +User API via prctl +================== + +Two prctl calls are defined to get/set the active memory consistency model: + +* prctl(PR_GET_MEMORY_CONSISTENCY_MODEL) + + Returns the active memory consistency model for the calling process/thread. + If the architecture does not support dynamic memory consistency models, + then -1 is returned, and errno is set to EINVAL. + +* prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, unsigned long new_model) + + Switches the memory consistency model for the calling process/thread + to the given model. If the architecture does not support dynamic + memory consistency models, or does not support the provided model, or + does not allow to switch to the proveided model then -1 is returned, + and errno is set to EINVAL. + +Supported memory consistency models +=================================== + +This section defines the memory consistency models which are supported +by the prctl interface. + +<none> diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..579662731eaa 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,7 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f
+#define PR_SET_MEMORY_CONSISTENCY_MODEL 71 +#define PR_GET_MEMORY_CONSISTENCY_MODEL 72 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index e219fcfa112d..a1b92a38f889 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,12 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef SET_MEMORY_CONSISTENCY_MODEL +# define SET_MEMORY_CONSISTENCY_MODEL(a) (-EINVAL) +#endif +#ifndef GET_MEMORY_CONSISTENCY_MODEL +# define GET_MEMORY_CONSISTENCY_MODEL() (-EINVAL) +#endif
/* * this is where the system-wide overflow UID and GID are defined, for @@ -2743,6 +2749,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error = RISCV_V_GET_CONTROL(); break; + case PR_SET_MEMORY_CONSISTENCY_MODEL: + error = SET_MEMORY_CONSISTENCY_MODEL(arg2); + break; + case PR_GET_MEMORY_CONSISTENCY_MODEL: + error = GET_MEMORY_CONSISTENCY_MODEL(); + break; default: error = -EINVAL; break;
This patch implements dynamic memory consistency switching on RISC-V using the Ssdtso ISA extension.
Ssdtso is a RISC-V ISA extension, which allows to switch the memory consistency model of less privileged modes from RVWMO to TSO at runtime. The active model is controlled by a DTSO bit in the {m,h,s}envcfg CSRs (per-hart state).
TSO is a stronger memory ordering than RVWMO, which means that executing software that was written for RVWMO can also run under TSO without causing memory consistency issues. Since RVWMO is the default model, switching to TSO is safe.
The patch introduces Ssdtso basic support: * enable dynamic memory consistency switching if Ssdtso support is enabled in the kernel config * define the relevant envcfg bits * add the relevant code to store/restore the DTSO state * register the the extension in hwcap/cpufeatures * extend task_struct to keep the state across context switches * add a Kconfig symbol to disable Ssdtso support
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- arch/riscv/Kconfig | 11 ++++ arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/dtso.h | 97 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/switch_to.h | 3 + arch/riscv/kernel/asm-offsets.c | 3 + arch/riscv/kernel/cpufeature.c | 1 + 7 files changed, 117 insertions(+) create mode 100644 arch/riscv/include/asm/dtso.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index bffbd869a068..1b26797e7cdd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,7 @@ config RISCV select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DEBUG_VM_PGTABLE select ARCH_HAS_DEBUG_WX + select ARCH_HAS_DYNAMIC_MEMORY_CONSISTENCY_MODEL if RISCV_ISA_SSDTSO select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE @@ -480,6 +481,16 @@ config RISCV_ISA_C
If you don't know what to do here, say Y.
+config RISCV_ISA_SSDTSO + bool "Ssdtso extension support for dynamic TSO memory ordering" + default y + help + Adds support to dynamically detect the presence of the Ssdtso + ISA-extension and allows user-space processes to activate/deactivate + the TSO memory ordering model at run-time. + + If you don't know what to do here, say Y. + config RISCV_ISA_SVNAPOT bool "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..83e5737d720d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -194,6 +194,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_DTSO (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/dtso.h b/arch/riscv/include/asm/dtso.h new file mode 100644 index 000000000000..25f9bb30884e --- /dev/null +++ b/arch/riscv/include/asm/dtso.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Christoph Muellner christoph.muellner@vrull.eu + */ + +#ifndef __ASM_RISCV_DTSO_H +#define __ASM_RISCV_DTSO_H + +#define RISCV_MEMORY_CONSISTENCY_MODEL_WMO 0 +#define RISCV_MEMORY_CONSISTENCY_MODEL_TSO 1 + +#ifdef CONFIG_RISCV_ISA_SSDTSO + +#include <linux/sched/task_stack.h> +#include <asm/cpufeature.h> +#include <asm/csr.h> + +static __always_inline bool has_dtso(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSDTSO); +} + +static __always_inline bool has_ztso(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZTSO); +} + +static inline bool dtso_is_enabled(void) +{ + if (has_dtso()) + return csr_read(CSR_SENVCFG) & ENVCFG_DTSO; + return 0; +} + +static inline void dtso_disable(void) +{ + if (has_dtso() && !has_ztso()) + csr_clear(CSR_SENVCFG, ENVCFG_DTSO); +} + +static inline void dtso_enable(void) +{ + if (has_dtso() && !has_ztso()) + csr_set(CSR_SENVCFG, ENVCFG_DTSO); +} + +static inline unsigned long get_memory_consistency_model( + struct task_struct *task) +{ + return task->memory_consistency_model; +} + +static inline void set_memory_consitency_model(struct task_struct *task, + unsigned long model) +{ + task->memory_consistency_model = model; +} + +static inline void dtso_restore(struct task_struct *task) +{ + unsigned long cur_model = get_memory_consistency_model(task); + + if (cur_model == RISCV_MEMORY_CONSISTENCY_MODEL_TSO) + dtso_enable(); + else + dtso_disable(); +} + +static inline void __switch_to_dtso(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + + /* + * We don't need to save the DTSO bit, because we don't expect it to + * change. So any mechanism that changes the DTSO bit, needs to take + * care to write to task->memory_consistency_model (and reschedule + * all threads of the process). + */ + + dtso_restore(next); +} + +#else /* ! CONFIG_RISCV_ISA_SSDTSO */ + +static __always_inline bool has_dtso(void) { return false; } +static __always_inline bool dtso_is_enabled(void) { return false; } +#define dtso_disable() do { } while (0) +#define dtso_enable() do { } while (0) +#define dtso_restore(task) do { } while (0) +#define __switch_to_dtso(prev, next) do { } while (0) + +#endif /* CONFIG_RISCV_ISA_SSDTSO */ + +#endif /* ! __ASM_RISCV_DTSO_H */ diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..88740f419d13 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,7 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SSDTSO 74
#define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..bedf7fe12c1d 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -9,6 +9,7 @@ #include <linux/jump_label.h> #include <linux/sched/task_stack.h> #include <asm/vector.h> +#include <asm/dtso.h> #include <asm/cpufeature.h> #include <asm/processor.h> #include <asm/ptrace.h> @@ -80,6 +81,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (has_dtso()) \ + __switch_to_dtso(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0)
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index a03129f40c46..b5dc39788c41 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -80,6 +80,9 @@ void asm_offsets(void) #ifdef CONFIG_STACKPROTECTOR OFFSET(TSK_STACK_CANARY, task_struct, stack_canary); #endif +#ifdef CONFIG_DYNAMIC_MEMORY_CONSISTENCY_MODEL + OFFSET(TASK_MEM_CONSISTENCY_MODEL, task_struct, memory_consistency_model); +#endif
DEFINE(PT_SIZE, sizeof(struct pt_regs)); OFFSET(PT_EPC, pt_regs, epc); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..b63d6b699238 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(ssdtso, RISCV_ISA_EXT_SSDTSO), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
We can use the PR_{S,G}ET_MEMORY_CONSISTENCY_MODEL prctl calls to change the memory consistency model at run-time if we have Ssdtso. This patch registers RISCV_WMO and RISCV_TSO as valid arguments for these prctl calls and implements the glue code to switch between these.
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- .../mm/dynamic-memory-consistency-model.rst | 12 +++- arch/riscv/include/asm/processor.h | 7 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/dtso.c | 67 +++++++++++++++++++ include/uapi/linux/prctl.h | 2 + 5 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kernel/dtso.c
diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Documentation/mm/dynamic-memory-consistency-model.rst index 1fce855a1fad..c8188c174e27 100644 --- a/Documentation/mm/dynamic-memory-consistency-model.rst +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -73,4 +73,14 @@ Supported memory consistency models This section defines the memory consistency models which are supported by the prctl interface.
-<none> +RISC-V +------ + +RISC-V uses RVWMO (RISC-V weak memory ordering) as default memory consistency +model. TSO (total store ordering) is another specified model and provides +additional ordering guarantees. Switching user-mode processes from RVWMO to TSO +is possible when the Ssdtso extension is available. + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO`: RISC-V weak memory ordering (default). + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO`: RISC-V total store ordering. diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index a8509cc31ab2..05e05fddc94d 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -184,6 +184,13 @@ extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
+#ifdef CONFIG_RISCV_ISA_SSDTSO +extern int dtso_set_memory_consistency_model(unsigned long arg); +extern int dtso_get_memory_consistency_model(void); +#define SET_MEMORY_CONSISTENCY_MODEL(arg) dtso_set_memory_consistency_model(arg) +#define GET_MEMORY_CONSISTENCY_MODEL() dtso_get_memory_consistency_model() +#endif /* CONIG_RISCV_ISA_SSDTSO */ + #endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f71910718053..85f7291da498 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o +obj-$(CONFIG_RISCV_ISA_SSDTSO) += dtso.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/dtso.c b/arch/riscv/kernel/dtso.c new file mode 100644 index 000000000000..591d5f9de0f5 --- /dev/null +++ b/arch/riscv/kernel/dtso.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024 Christoph Muellner christoph.muellner@vrull.eu + */ + +#include <linux/cpu.h> +#include <linux/smp.h> +#include <linux/prctl.h> + +#include <asm/cpu.h> +#include <asm/dtso.h> + +#include <trace/events/ipi.h> + +int dtso_set_memory_consistency_model(unsigned long arg) +{ + int cpu; + unsigned long cur_model = get_memory_consistency_model(current); + unsigned long new_model; + + switch (arg) { + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO: + new_model = RISCV_MEMORY_CONSISTENCY_MODEL_WMO; + break; + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO: + new_model = RISCV_MEMORY_CONSISTENCY_MODEL_TSO; + break; + default: + return -EINVAL; + } + + /* No change requested. */ + if (cur_model == new_model) + return 0; + + /* Enabling TSO only works if DTSO is available. */ + if (new_model == PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO && !has_dtso()) + return -EINVAL; + + /* Switching TSO->WMO is not allowed. */ + if (new_model == RISCV_MEMORY_CONSISTENCY_MODEL_WMO) + return -EINVAL; + + /* Set the new model in the task struct. */ + set_memory_consitency_model(current, new_model); + + /* + * We need to reschedule all threads of the current process. + * Let's do this by rescheduling all CPUs. + * This is stricter than necessary, but since this call is + * not expected to happen frequently the impact is low. + */ + for_each_cpu(cpu, cpu_online_mask) + smp_send_reschedule(cpu); + + return 0; +} + +int dtso_get_memory_consistency_model(void) +{ + unsigned long cur_model = get_memory_consistency_model(current); + + if (cur_model == RISCV_MEMORY_CONSISTENCY_MODEL_TSO) + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO; + + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO; +} diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 579662731eaa..20264bdc3092 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -308,5 +308,7 @@ struct prctl_mm_map {
#define PR_SET_MEMORY_CONSISTENCY_MODEL 71 #define PR_GET_MEMORY_CONSISTENCY_MODEL 72 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO 1 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO 2
#endif /* _LINUX_PRCTL_H */
This patch adds Ssdtso to the list of extensions which are announced to user-space using te hwprobe API.
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 2 ++ 3 files changed, 6 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index b2bcc9eed9aa..d881d56eba37 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,6 +188,9 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff")
+ * :c:macro:`RISCV_HWPROBE_EXT_SSDTSO`: The Ssdtso extension is supported, as + in version v1.0-draft3 of the corresponding extension. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9f2a8e3ff204..ee6e830abe4d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_SSDTSO (1ULL << 36) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index a7c56b41efd2..9024061e9193 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -132,6 +132,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZFHMIN); EXT_KEY(ZFA); } + + EXT_KEY(SSDTSO); #undef EXT_KEY }
This patch tests the dynamic memory consistency model prctl() behaviour on RISC-V. It does not depend on CONFIG_RISCV_ISA_SSDTSO or the availability of Ssdtso, but will test other aspects if these are not given.
Signed-off-by: Christoph Müllner christoph.muellner@vrull.eu --- tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/dtso/.gitignore | 1 + tools/testing/selftests/riscv/dtso/Makefile | 11 +++ tools/testing/selftests/riscv/dtso/dtso.c | 82 +++++++++++++++++++ 4 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/dtso/.gitignore create mode 100644 tools/testing/selftests/riscv/dtso/Makefile create mode 100644 tools/testing/selftests/riscv/dtso/dtso.c
diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile index 4a9ff515a3a0..1421c21841f9 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?= $(shell uname -m 2>/dev/null || echo not)
ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?= hwprobe vector mm +RISCV_SUBTARGETS ?= dtso hwprobe vector mm else RISCV_SUBTARGETS := endif diff --git a/tools/testing/selftests/riscv/dtso/.gitignore b/tools/testing/selftests/riscv/dtso/.gitignore new file mode 100644 index 000000000000..217d01679115 --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/.gitignore @@ -0,0 +1 @@ +dtso diff --git a/tools/testing/selftests/riscv/dtso/Makefile b/tools/testing/selftests/riscv/dtso/Makefile new file mode 100644 index 000000000000..a1ffbdd3da85 --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2023 VRULL + +CFLAGS += -I$(top_srcdir)/tools/include + +TEST_GEN_PROGS := dtso + +include ../../lib.mk + +$(OUTPUT)/dtso: dtso.c ../hwprobe/sys_hwprobe.S + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/dtso/dtso.c b/tools/testing/selftests/riscv/dtso/dtso.c new file mode 100644 index 000000000000..c8a7b25adefd --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/dtso.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* dtso - used for functional tests of memory consistency model switching + * at run-time. + * + * Copyright (c) 2023 Christoph Muellner christoph.muellner@vrull.eu + */ + +#include <sys/prctl.h> +#include <unistd.h> +#include <errno.h> + +#include "../hwprobe/hwprobe.h" +#include "../../kselftest_harness.h" + +/* + * We have the following cases: + * 1) DTSO support disabed in the kernel config: + * - Ssdtso is not detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL fails with EINVAL + * 2) DTSO support enabled and Ssdtso not available: + * - Ssdtso is not detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL works for WMO and fails for TSO with EINVAL: + * 3) DTSO support enabled and Ssdtso available + * - Ssdtso is detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL works for WMO and TSO + */ + +TEST(dtso) +{ + struct riscv_hwprobe pair; + int ret; + bool ssdtso_configured; + bool ssdtso_available; + + ret = prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + if (ret < 0) { + ASSERT_EQ(errno, EINVAL); + ssdtso_configured = false; + } else { + ASSERT_TRUE(ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO || + ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + ssdtso_configured = true; + } + + pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0; + ret = riscv_hwprobe(&pair, 1, 0, NULL, 0); + ASSERT_GE(ret, 0); + ASSERT_EQ(pair.key, RISCV_HWPROBE_KEY_IMA_EXT_0); + ssdtso_available = !!(pair.value & RISCV_HWPROBE_EXT_SSDTSO); + + if (ssdtso_configured) { + /* Read out current model. */ + ret = prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO || + ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + + if (ssdtso_available) { + /* Switch to TSO. */ + ret = prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, + PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + ASSERT_EQ(ret, 0); + ret = prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + + /* Try switching back to WMO (must fail). */ + ret = prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, + PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO); + ASSERT_LT(ret, 0); + ret = prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret == PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + } else { + /* Set the same model, that's currently active. */ + ret = prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, ret); + ASSERT_EQ(ret, 0); + } + } else { + ASSERT_EQ(ssdtso_available, false); + ksft_test_result_skip("Ssdtso not configured\n"); + } +} + +TEST_HARNESS_MAIN
linux-kselftest-mirror@lists.linaro.org
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Christoph Müllner