Tcwg-commits March 2020

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig updated (63f0b23 -> e3ba291)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 63f0b23 0: update: llvm-linux: all new e3ba291 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (63f0b23) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 216 +- 02-build_llvm/console.log | 12562 +++++++++++++++++------------------ 03-build_linux/console.log | 640 +- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 18 +- 06-update_baseline/console.log | 16 +- console.log | 13472 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13449 insertions(+), 13485 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (b3499f572d3 -> de6cd3e836e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project. from b3499f572d3 [ARM] Change VDUP type to i32 for MVE adds baa6f6a7828 Revert "[TableGen][GlobalISel] Account for HwMode in Regist [...] adds 180581cfcf5 [clang] Add support for consteval constructors adds 467c4902a10 [lldb] Enable now passing part of TestDataFormatterStdString.py adds 63778bc653a [llvm-readobj][llvm-readelf][test] - Add a test to check ho [...] adds 089cfe113da Improve step over performance adds fd7300f717c [Syntax] Test both the default and windows target platforms [...] adds 86b093d1a18 [llvm-readobj] Allow syms from all sections to match stack [...] adds a09ff56b5b5 [Tests] Regenerate some test checks; NFC adds c1efdbcbe0d [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds 9967352a034 Revert "[Syntax] Test both the default and windows target p [...] adds ce6c95aacae [InstCombine] Move test to instcombine; NFC adds fcba7c3534f [OPENMP50]Initial support for scan directive. adds 7f764fa18f6 [ValueTracking] Add some initial isKnownNonZero DemandedElt [...] adds a4edea29be2 Fix `-Wunused-variable` warning. NFC. adds ece6cf0fa56 [DSE,MSSA] Precommit additional tests for D73763. adds 7a85e3585ec [ARM,CDE] Implement GPR CDE intrinsics adds d22e6617125 [ARM,CDE] Implement CDE S and D-register intrinsics adds 969034b8603 [ARM,CDE] Implement CDE unpredicated Q-register intrinsics adds 6ae3eff8baa [ARM,CDE] Implement CDE vreinterpret intrinsics adds 6e34e71869a [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 adds f8352502a35 [scudo][standalone] Allow fallback to secondary if primary is full adds 53d6b156bbb AMDGPU: Add more tests for fshr adds a950e3beefd AMDGPU: Move towards deprecating alignbit intrinsic adds d168b777803 [DAGCombiner] Fix non-determinism problem related to argume [...] adds fc902cb6e2b [PowerPC][AIX][NFC] Add zero-sized by val params to cc test. adds 94061df6e5f [analyzer] StdLibraryFunctionsChecker: Add argument constraints adds eddede9d518 [Syntax] Test both the default and windows target platforms [...] adds 45a9945b9ea [ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family. adds 1adfa4c9916 [ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family. adds 34659de5fdd [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds ffcc076a2b2 [[Clang CallGraph]] CallGraph should still record calls to decls. adds ce5173c0e17 Use FinishThunk to finish musttail thunks adds 32fbea15485 [X86] Prevent (bitcast (broadcast_load)) combine from produ [...] adds 56122fcd641 [PowerPC][AIX][NFC] Extend the test coverage of ByVal args. adds edcfb47ff6d [DAGCombiner] Do not fold truncate(build_vector(..)) if it [...] adds ededa65d559 [analyzer] StdLibraryFunctionsChecker: Add NotNull Arg Constraint adds f59bb40e361 Attempt to fix failing build-bot with [-Werror,-Wcovered-sw [...] adds 942afe0cb2a [mlir/quant] fix a small typo in the quant utility adds 0b18b568e91 [lldb-vscode] Don't use SBLaunchInfo in request_attach adds 3205d1a8603 [InstCombine] Handle known shl nsw sign bit in SimplifyDemanded adds 5de4ba1770f Cleanup the plumbing for DILineInfoSpecifier. [NFC - Try 2] adds 18e8f27ad87 Add missing module map entry adds 462db62053f [mlir][AVX512] Start a primitive AVX512 dialect adds 636665331bb PR45181: Fix another invalid DIExpression combination adds fe5937cb33b [llc] Initialize TargetLoweringObjectFile for MIR input adds 7899fe9da8d [X86] Reland D71360 Clean up UseInitArray initialization fo [...] adds 06dea73307e [OPENMP50]Initial support for inclusive clause. adds 7efbd851adf [libc++] Add a new FILE_DEPENDENCIES parser adds 25294708f5e [libc] NFC - Move the round redirector from its own nested [...] adds 4716ebb823e [ADT] CoalescingBitVector: Avoid initial heap allocation, NFC adds a3fd1a1c744 [ADT] CoalescingBitVector: Add advanceToLowerBound iterator [...] adds a2459433551 [LiveDebugValues] Speed up collectIDsForRegs, NFC adds 7ec24448801 unittest: Work around build failure on MSVC builders adds 9b95929a26e [OPENMP50]Do not allow several scan directives in the same [...] adds 2b52e4e629e [InstCombine] Remove known bits constant folding adds be4e9db5799 [mlir][Linalg] NFC: Clean up for 0-D abstraction. adds 08a9147349e [mlir][LLVMIR] Fix fusion for rank-0 tensors adds fe5599eac6a [llvm-ar] Use target triple to deduce archive kind for bitc [...] adds 40fc80a0232 [mlir][AVX512] Hotfix - Fix CMake Doc generation dependence adds 6385c2ab8ff [AppleObjCRuntimeV2] Force lazily allocated class names to [...] adds 696ae6f7d8e [StopHook] Use wildcard matching. Pointed out by Jim Ingham. adds 417d69595f0 [InstSimplify] Reorder checks to be more efficient; NFC adds 079c6ddaf53 Correctly initialize the DW_AT_comp_dir attribute of Clang [...] adds 97f490d87b2 Don't set the isOptimized flag in module skeleton DICompileUnits. adds dc4259d5a38 [c++20] Further extend the set of comparisons broken by C++ [...] adds e708471395b [mlir][NFC] Cleanup AffineOps directory structure adds 576105c322b [lldb-vscode] stop read loop after termination adds 2dec82652e4 Create basic SBEnvironment class adds 1993f95f2b1 [ValueTracking][SVE] Fix getOffsetFromIndex for scalable vector. adds fc8a009bf39 Clean up and simplify after collision of c48442c and 19fccc [...] adds df4cc35efd0 [VE] Fix -Wunused-private-field after D72598 and -Wdeprecat [...] adds 43580a5c5af Allow remapping Clang module skeleton CU references with -f [...] adds f75f19c2374 [Clang][test] Add .i files for test discovery adds 0a42c9bfe4e Enable CUDA offloading on aarch64 host adds 479ee110615 [mlir] [VectorOps] Introduce vector.transpose adds e22fe98d059 [libc++] Make the %run substitution closer to how .pass.cpp [...] adds 6725c4836a5 Allow remapping the sysroot with -fdebug-prefix-map. adds 556b917fffc [clang-tidy] Merge common code between llvmlibc-restrict-sy [...] adds bde15de3cab Revert "Allow remapping the sysroot with -fdebug-prefix-map." adds ceae47143b1 Allow remapping the sysroot with -fdebug-prefix-map. adds 0feaf22c8a7 [libc++] Properly handle environment variables with '=' in them adds 6aef702ab63 [mlir][AVX512] Hotfix - Add cmake dependence on MLIRSideEffects adds aa1e0e01d89 [MLIR] Fix Xcode build due to incorrect library path adds 0e916bf9f5e Driver: Improve performance of getSDKName() adds 0a5fbf30937 Temporarily Revert "Create basic SBEnvironment class" adds 4f5af9d70dc [ValueTracking] Fix usage of DataLayout::getTypeStoreSize() adds 141e5890d81 [MLIR] Add an IfOp builder with results adds 298527587c7 [libomptarget][nfc] Disable amdgcn rtl build. The cmake log [...] adds 1ae737a7c6a [libc++] Temporarily disable an availability test that is broken adds fc7233d7744 Temporarily Revert "[X86] Reland D71360 Clean up UseInitArr [...] adds be10b7e43a3 Use values cached in ConstantExprs for expression evaluatio [...] adds d35a454170d [CodeGen] Emit destructor calls to destruct non-trivial C s [...] adds 09c8845adfd [lldb]/Tablegen] Use ElementType instead of DefaultValueUnsinged adds ced7617c385 PR45267: Don't reject pure-specifiers with escaped newlines [...] adds a299178ae77 [cmake] Fix -stripped for umbrella library install targets adds a8c22ba4162 [lldb-vscode] Add missing launchCommands entry in the package.json adds 4ec6ebabfc3 [lldb-vscode] Add inheritEnvironment option adds 34c0759f846 Create basic SBEnvironment class adds c85bf7cfa8b Revert "[lldb-vscode] Add inheritEnvironment option" adds e292cdfb338 Revert "[lldb-vscode] Add missing launchCommands entry in t [...] adds 7ece7c0faae Revert "Create basic SBEnvironment class" adds 85c30f3374d [X86] Reland D71360 Clean up UseInitArray initialization fo [...] adds de6cd3e836e [WebAssembly] Add SIMD integer abs builtins No new revisions were added by this update. Summary of changes: .../clang-tidy/llvmlibc/CMakeLists.txt | 1 + .../llvmlibc/RestrictSystemLibcHeadersCheck.cpp | 26 +- .../llvmlibc/RestrictSystemLibcHeadersCheck.h | 6 +- .../portability/RestrictSystemIncludesCheck.cpp | 36 - .../portability/RestrictSystemIncludesCheck.h | 43 +- clang-tools-extra/docs/clang-tidy/checks/list.rst | 2 +- .../llvmlibc-restrict-system-libc-headers.rst | 15 + .../checkers/Inputs/llvmlibc/system/math.h | 0 .../checkers/Inputs/llvmlibc/transitive.h | 1 - ...ibc-restrict-system-libc-headers-transitive.cpp | 8 - .../llvmlibc-restrict-system-libc-headers.cpp | 6 +- clang/CMakeLists.txt | 1 + clang/include/clang-c/Index.h | 6 +- clang/include/clang/AST/Expr.h | 3 + clang/include/clang/AST/OpenMPClause.h | 74 ++ clang/include/clang/AST/RecursiveASTVisitor.h | 10 + clang/include/clang/AST/StmtOpenMP.h | 57 ++ clang/include/clang/Analysis/CallGraph.h | 5 + clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 28 +- clang/include/clang/Basic/OpenMPKinds.def | 8 + clang/include/clang/Basic/StmtNodes.td | 1 + clang/include/clang/Basic/arm_cde.td | 159 +++- clang/include/clang/Basic/arm_mve.td | 66 +- clang/include/clang/Sema/Overload.h | 8 + clang/include/clang/Sema/Sema.h | 9 + clang/include/clang/Serialization/ASTBitCodes.h | 1 + .../clang/StaticAnalyzer/Checkers/Checkers.td | 7 + clang/lib/AST/Expr.cpp | 8 +- clang/lib/AST/ExprConstant.cpp | 9 +- clang/lib/AST/OpenMPClause.cpp | 28 + clang/lib/AST/StmtOpenMP.cpp | 21 + clang/lib/AST/StmtPrinter.cpp | 5 + clang/lib/AST/StmtProfile.cpp | 7 + clang/lib/Analysis/CallGraph.cpp | 6 +- clang/lib/Basic/OpenMPKinds.cpp | 15 + clang/lib/CodeGen/CGBuiltin.cpp | 9 + clang/lib/CodeGen/CGCall.cpp | 5 + clang/lib/CodeGen/CGCall.h | 33 +- clang/lib/CodeGen/CGClass.cpp | 4 +- clang/lib/CodeGen/CGDebugInfo.cpp | 18 +- clang/lib/CodeGen/CGExprAgg.cpp | 21 +- clang/lib/CodeGen/CGExprConstant.cpp | 4 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 5 + clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp | 4 + clang/lib/CodeGen/CGStmt.cpp | 3 + clang/lib/CodeGen/CGStmtOpenMP.cpp | 1 + clang/lib/CodeGen/CGVTables.cpp | 8 +- clang/lib/Driver/ToolChains/Darwin.cpp | 4 +- clang/lib/Parse/ParseDecl.cpp | 9 +- clang/lib/Parse/ParseDeclCXX.cpp | 2 +- clang/lib/Parse/ParseOpenMP.cpp | 13 +- clang/lib/Sema/SemaDecl.cpp | 3 + clang/lib/Sema/SemaDeclCXX.cpp | 14 +- clang/lib/Sema/SemaExceptionSpec.cpp | 1 + clang/lib/Sema/SemaExpr.cpp | 27 + clang/lib/Sema/SemaExprCXX.cpp | 3 + clang/lib/Sema/SemaInit.cpp | 14 +- clang/lib/Sema/SemaOpenMP.cpp | 105 ++- clang/lib/Sema/SemaOverload.cpp | 111 ++- clang/lib/Sema/TreeTransform.h | 54 +- clang/lib/Serialization/ASTReader.cpp | 13 + clang/lib/Serialization/ASTReaderStmt.cpp | 12 + clang/lib/Serialization/ASTWriter.cpp | 7 + clang/lib/Serialization/ASTWriterStmt.cpp | 7 + .../Checkers/StdLibraryFunctionsChecker.cpp | 218 +++++- clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 1 + clang/test/Analysis/analyzer-enabled-checkers.c | 1 + clang/test/Analysis/debug-CallGraph.cpp | 5 +- .../std-c-library-functions-arg-constraints.c | 87 +++ clang/test/Analysis/std-c-library-functions.c | 39 +- .../over.match.funcs/over.match.oper/p3-2a.cpp | 18 +- .../over.match.funcs/over.match.oper/p9-2a.cpp | 20 +- clang/test/CodeGen/arm-cde-gpr.c | 146 +++- clang/test/CodeGen/arm-cde-reinterpret.c | 78 ++ clang/test/CodeGen/arm-cde-vec.c | 104 +++ clang/test/CodeGen/arm-cde-vfp.c | 145 ++++ clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | 470 +++++++++++ clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | 832 +++++++++++++++++++- clang/test/CodeGen/builtins-wasm.c | 24 + clang/test/CodeGen/debug-prefix-map.c | 2 + clang/test/CodeGenCXX/ms-thunks-ehspec.cpp | 27 + clang/test/CodeGenCXX/thunks-ehspec.cpp | 29 + clang/test/CodeGenObjC/arc.m | 11 +- clang/test/CodeGenObjC/strong-in-c-struct.m | 79 ++ clang/test/Modules/ExtDebugInfo.m | 7 +- clang/test/Modules/debug-info-moduleimport.m | 27 +- clang/test/OpenMP/nesting_of_regions.cpp | 374 ++++++++- clang/test/OpenMP/scan_ast_print.cpp | 50 ++ clang/test/OpenMP/scan_messages.cpp | 164 ++++ clang/test/PCH/debug-info-pch-path.c | 4 +- clang/test/Parser/cxx-class.cpp | 4 +- clang/test/Sema/arm-cde-immediates.c | 135 +++- clang/test/SemaCXX/cxx2a-consteval.cpp | 144 +++- clang/test/lit.cfg.py | 2 +- clang/tools/libclang/CIndex.cpp | 10 + clang/tools/libclang/CXCursor.cpp | 3 + clang/unittests/Tooling/Syntax/TreeTest.cpp | 48 +- clang/utils/TableGen/MveEmitter.cpp | 45 +- compiler-rt/lib/scudo/standalone/combined.h | 21 +- .../lib/scudo/standalone/tests/combined_test.cpp | 31 +- libc/src/math/CMakeLists.txt | 15 +- libc/src/math/{round => }/round.cpp | 2 +- libc/src/math/{round => }/round.h | 0 libc/src/math/round/CMakeLists.txt | 14 - libc/src/math/{round => }/round_redirector.cpp | 0 .../fstreams/ifstream.cons/wchar_pointer.pass.cpp | 2 + .../ifstream.members/open_wchar_pointer.pass.cpp | 2 + .../libcxx/selftest/test.file_dependencies.sh.cpp | 13 +- .../charconv.to.chars/availability.fail.cpp | 3 + .../fstreams/filebuf.virtuals/seekoff.pass.cpp | 2 + .../fstreams/filebuf.virtuals/underflow.pass.cpp | 1 + .../fstreams/ifstream.assign/member_swap.pass.cpp | 2 + .../fstreams/ifstream.assign/move_assign.pass.cpp | 1 + .../ifstream.assign/nonmember_swap.pass.cpp | 2 + .../fstreams/ifstream.cons/move.pass.cpp | 1 + .../fstreams/ifstream.cons/path.pass.cpp | 1 + .../fstreams/ifstream.cons/pointer.pass.cpp | 2 + .../fstreams/ifstream.cons/string.pass.cpp | 2 + .../fstreams/ifstream.members/close.pass.cpp | 2 + .../fstreams/ifstream.members/open_path.pass.cpp | 1 + .../ifstream.members/open_pointer.pass.cpp | 2 + .../fstreams/ifstream.members/open_string.pass.cpp | 2 + .../fstreams/ifstream.members/rdbuf.pass.cpp | 2 + .../conversions.buffer/pbackfail.pass.cpp | 2 + .../conversions.buffer/underflow.pass.cpp | 2 + libcxx/utils/libcxx/test/config.py | 7 +- libcxx/utils/libcxx/test/format.py | 23 +- libcxx/utils/run.py | 45 +- lldb/include/lldb/Core/PropertiesBase.td | 6 + .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 34 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 2 +- lldb/source/Target/TargetProperties.td | 6 +- lldb/source/Target/ThreadPlanStepOverRange.cpp | 4 + .../libstdcpp/string/TestDataFormatterStdString.py | 3 +- .../tools/lldb-vscode/launch/TestVSCode_launch.py | 26 + .../test/Shell/ExecControl/StopHook/stop-hook.test | 4 +- lldb/tools/lldb-vscode/lldb-vscode.cpp | 5 +- lldb/utils/TableGen/LLDBPropertyDefEmitter.cpp | 15 +- llvm/CMakeLists.txt | 1 + llvm/include/llvm/ADT/CoalescingBitVector.h | 85 +- llvm/include/llvm/Analysis/ValueTracking.h | 25 + .../include/llvm/CodeGen/GlobalISel/RegisterBank.h | 13 +- .../llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 3 +- llvm/include/llvm/DebugInfo/DIContext.h | 8 +- llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h | 8 +- .../llvm/DebugInfo/Symbolize/SymbolizableModule.h | 5 +- llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h | 2 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 1 + llvm/include/llvm/IR/IntrinsicsARM.td | 92 ++- llvm/include/llvm/Support/TypeSize.h | 3 + llvm/include/llvm/module.modulemap | 1 + llvm/lib/Analysis/InstructionSimplify.cpp | 7 +- llvm/lib/Analysis/ValueTracking.cpp | 136 +++- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 27 +- llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp | 8 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 5 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 83 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 +- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 1 + llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 6 +- llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp | 2 - .../DebugInfo/Symbolize/SymbolizableObjectFile.cpp | 22 +- .../DebugInfo/Symbolize/SymbolizableObjectFile.h | 4 +- llvm/lib/DebugInfo/Symbolize/Symbolize.cpp | 8 +- .../lib/Target/AArch64/AArch64TargetObjectFile.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 10 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 + llvm/lib/Target/AMDGPU/SIInstructions.td | 1 - llvm/lib/Target/AMDGPU/VOP3Instructions.td | 2 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 106 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp | 78 +- llvm/lib/Target/ARM/ARMISelLowering.h | 16 +- llvm/lib/Target/ARM/ARMInstrCDE.td | 93 +++ llvm/lib/Target/ARM/ARMInstrMVE.td | 258 +++--- .../lib/Target/Hexagon/HexagonTargetObjectFile.cpp | 1 - llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp | 1 - llvm/lib/Target/Mips/MipsTargetObjectFile.cpp | 1 - llvm/lib/Target/PowerPC/PPCTargetObjectFile.cpp | 1 - llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 2 +- llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp | 1 - llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp | 1 - llvm/lib/Target/VE/VEFrameLowering.cpp | 6 +- llvm/lib/Target/VE/VEInstrInfo.cpp | 3 +- llvm/lib/Target/VE/VEInstrInfo.h | 1 - llvm/lib/Target/X86/X86ISelLowering.cpp | 29 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 12 +- llvm/lib/Target/X86/X86TargetObjectFile.cpp | 26 +- llvm/lib/Target/X86/X86TargetObjectFile.h | 24 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 24 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 14 + .../InstCombine/InstructionCombining.cpp | 22 +- .../Analysis/ValueTracking/knownnonzero-shift.ll | 6 +- .../CodeGen/AArch64/dag-combine-trunc-build-vec.ll | 48 ++ llvm/test/CodeGen/AMDGPU/bypass-div.ll | 36 +- llvm/test/CodeGen/AMDGPU/fshr.ll | 870 ++++++++++++++++++++- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 14 +- llvm/test/CodeGen/AMDGPU/srem64.ll | 14 +- llvm/test/CodeGen/AMDGPU/udiv64.ll | 12 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 10 +- llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 55 +- llvm/test/CodeGen/Thumb2/cde-gpr.ll | 189 +++++ llvm/test/CodeGen/Thumb2/cde-vec.ll | 114 +++ llvm/test/CodeGen/Thumb2/cde-vfp.ll | 198 +++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddv.ll | 416 ++++++++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vminvq.ll | 849 +++++++++++++++++++- llvm/test/CodeGen/X86/constructor.ll | 1 + llvm/test/CodeGen/X86/fdiv.ll | 24 + llvm/test/CodeGen/X86/init-priority.ll | 2 +- llvm/test/DebugInfo/X86/pr45181.ll | 306 ++++++++ .../MSSA/memset-unknown-sizes.ll | 71 ++ .../MSSA/multiblock-multipath.ll | 76 ++ .../MSSA/multiblock-overlap.ll | 112 +++ llvm/test/Transforms/GVN/PRE/volatile.ll | 143 ++-- .../InstCombine/X86/x86-vector-shifts.ll | 57 +- llvm/test/Transforms/InstCombine/assume.ll | 16 +- .../InstCombine}/known-signbit-shift.ll | 7 +- .../InstCombine/out-of-bounds-indexes.ll | 29 +- llvm/test/Transforms/InstCombine/phi-shifts.ll | 22 +- llvm/test/Transforms/InstSimplify/assume.ll | 6 +- llvm/test/Transforms/InstSimplify/compare.ll | 15 +- .../Transforms/InstSimplify/shift-knownbits.ll | 10 +- .../MemCpyOpt/store-to-memset-is-nonzero-type.ll | 73 ++ llvm/test/Transforms/MemCpyOpt/vscale-memset.ll | 115 +++ llvm/test/tools/llvm-ar/lto-kind-from-triple.test | 26 + .../test/tools/llvm-readobj/ELF/reloc-addends.test | 155 ++++ llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 73 +- llvm/tools/llc/llc.cpp | 3 + llvm/tools/llvm-ar/llvm-ar.cpp | 23 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 30 +- llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp | 5 +- llvm/unittests/ADT/CoalescingBitVectorTest.cpp | 76 +- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 7 +- llvm/utils/TableGen/RegisterBankEmitter.cpp | 64 +- mlir/cmake/modules/AddMLIR.cmake | 6 +- mlir/docs/Interfaces.md | 2 +- mlir/docs/Tutorials/Toy/Ch-5.md | 2 +- mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp | 4 +- mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp | 4 +- mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 2 +- mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp | 4 +- mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp | 2 +- .../Conversion/AVX512ToLLVM/ConvertAVX512ToLLVM.h | 29 + mlir/include/mlir/Dialect/AVX512/AVX512.td | 99 +++ mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h | 31 + mlir/include/mlir/Dialect/AVX512/CMakeLists.txt | 1 + .../mlir/Dialect/{Shape => Affine}/CMakeLists.txt | 0 .../Dialect/{AffineOps => Affine}/EDSC/Builders.h | 8 +- .../{AffineOps => Affine}/EDSC/Intrinsics.h | 6 +- .../Dialect/{AffineOps => Affine/IR}/AffineOps.h | 8 +- .../Dialect/{AffineOps => Affine/IR}/AffineOps.td | 8 +- .../{AffineOps => Affine/IR}/AffineOpsBase.td | 0 .../{AffineOps => Affine/IR}/AffineValueMap.h | 6 +- .../{AffineOps => Affine/IR}/CMakeLists.txt | 0 mlir/include/mlir/Dialect/Affine/Passes.h | 48 ++ mlir/include/mlir/Dialect/CMakeLists.txt | 3 +- mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt | 6 + mlir/include/mlir/Dialect/LLVMIR/LLVMAVX512.td | 52 ++ .../mlir/Dialect/LLVMIR/LLVMAVX512Dialect.h | 30 + mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 2 +- .../mlir/Dialect/Linalg/IR/LinalgStructuredOps.td | 2 +- .../Linalg/Transforms/LinalgTransformPatterns.td | 2 +- mlir/include/mlir/Dialect/LoopOps/LoopOps.td | 5 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 41 +- .../Dialect/{Vector => VectorOps}/VectorOps.td | 9 +- mlir/include/mlir/IR/OpImplementation.h | 5 +- mlir/include/mlir/InitAllDialects.h | 8 +- mlir/include/mlir/InitAllPasses.h | 6 + mlir/include/mlir/Transforms/Passes.h | 13 - mlir/lib/Analysis/AffineAnalysis.cpp | 4 +- mlir/lib/Analysis/AffineStructures.cpp | 4 +- mlir/lib/Analysis/CMakeLists.txt | 4 +- mlir/lib/Analysis/LoopAnalysis.cpp | 4 +- mlir/lib/Analysis/NestedMatcher.cpp | 2 +- mlir/lib/Analysis/SliceAnalysis.cpp | 2 +- mlir/lib/Analysis/Utils.cpp | 4 +- mlir/lib/Conversion/AVX512ToLLVM/CMakeLists.txt | 19 + .../AVX512ToLLVM/ConvertAVX512ToLLVM.cpp | 193 +++++ .../AffineToStandard/AffineToStandard.cpp | 2 +- .../lib/Conversion/AffineToStandard/CMakeLists.txt | 2 +- mlir/lib/Conversion/CMakeLists.txt | 1 + mlir/lib/Conversion/LoopsToGPU/CMakeLists.txt | 2 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp | 2 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp | 4 +- .../VectorToLoops/ConvertVectorToLoops.cpp | 2 +- mlir/lib/Dialect/AVX512/CMakeLists.txt | 15 + mlir/lib/Dialect/AVX512/IR/AVX512Dialect.cpp | 35 + mlir/lib/Dialect/Affine/CMakeLists.txt | 21 + .../{AffineOps => Affine}/EDSC/Builders.cpp | 2 +- .../{AffineOps => Affine/EDSC}/CMakeLists.txt | 8 +- .../Dialect/{AffineOps => Affine/IR}/AffineOps.cpp | 16 +- .../{AffineOps => Affine/IR}/AffineValueMap.cpp | 4 +- .../{AffineOps => Affine/IR}/CMakeLists.txt | 7 +- .../Transforms/AffineDataCopyGeneration.cpp | 4 +- .../Transforms/AffineLoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt | 21 + .../Transforms/SimplifyAffineStructures.cpp | 5 +- mlir/lib/Dialect/CMakeLists.txt | 3 +- mlir/lib/Dialect/LLVMIR/CMakeLists.txt | 20 + mlir/lib/Dialect/LLVMIR/IR/LLVMAVX512Dialect.cpp | 36 + mlir/lib/Dialect/Linalg/EDSC/Builders.cpp | 2 +- mlir/lib/Dialect/Linalg/EDSC/CMakeLists.txt | 2 +- mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt | 2 +- .../Dialect/Linalg/Transforms/LinalgToLoops.cpp | 105 ++- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 2 +- mlir/lib/Dialect/Linalg/Utils/CMakeLists.txt | 2 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 2 +- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 6 + mlir/lib/Dialect/LoopOps/Transforms/CMakeLists.txt | 2 +- .../Transforms/ParallelLoopSpecialization.cpp | 2 +- .../LoopOps/Transforms/ParallelLoopTiling.cpp | 2 +- mlir/lib/Dialect/Quant/Utils/UniformSupport.cpp | 4 +- mlir/lib/Dialect/Vector/CMakeLists.txt | 2 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 29 + mlir/lib/Dialect/Vector/VectorTransforms.cpp | 2 +- mlir/lib/Dialect/Vector/VectorUtils.cpp | 2 +- .../{Vector => VectorOps}/VectorTransforms.cpp | 182 ++--- .../Dialect/{Vector => VectorOps}/VectorUtils.cpp | 8 +- mlir/lib/IR/AffineMap.cpp | 3 +- mlir/lib/Target/CMakeLists.txt | 16 + mlir/lib/Target/LLVMIR/LLVMAVX512Intr.cpp | 51 ++ mlir/lib/Transforms/CMakeLists.txt | 5 +- mlir/lib/Transforms/LoopFusion.cpp | 2 +- mlir/lib/Transforms/LoopTiling.cpp | 2 +- mlir/lib/Transforms/LoopUnroll.cpp | 2 +- mlir/lib/Transforms/LoopUnrollAndJam.cpp | 2 +- mlir/lib/Transforms/MemRefDataFlowOpt.cpp | 2 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 2 +- mlir/lib/Transforms/Utils/CMakeLists.txt | 2 +- mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 2 +- mlir/lib/Transforms/Utils/LoopUtils.cpp | 2 +- mlir/lib/Transforms/Utils/Utils.cpp | 2 +- mlir/lib/Transforms/Vectorize.cpp | 2 +- .../Conversion/AVX512ToLLVM/convert-to-llvm.mlir | 17 + mlir/test/Dialect/AVX512/roundtrip.mlir | 21 + .../{AffineOps => Affine}/canonicalize.mlir | 0 mlir/test/Dialect/{AffineOps => Affine}/dma.mlir | 0 .../Dialect/{AffineOps => Affine}/inlining.mlir | 0 .../Dialect/{AffineOps => Affine}/invalid.mlir | 0 .../{AffineOps => Affine}/load-store-invalid.mlir | 0 .../Dialect/{AffineOps => Affine}/load-store.mlir | 0 .../memref-stride-calculation.mlir | 0 mlir/test/Dialect/{AffineOps => Affine}/ops.mlir | 0 mlir/test/Dialect/Linalg/fusion-tensor.mlir | 25 + mlir/test/Dialect/Vector/invalid.mlir | 35 + mlir/test/Dialect/Vector/ops.mlir | 12 + mlir/test/EDSC/CMakeLists.txt | 4 +- mlir/test/EDSC/builder-api-test.cpp | 4 +- mlir/test/Target/avx512.mlir | 31 + mlir/test/lib/Dialect/Affine/CMakeLists.txt | 14 + .../Affine}/TestAffineDataCopy.cpp | 2 +- mlir/test/lib/Dialect/CMakeLists.txt | 1 + mlir/test/lib/Transforms/CMakeLists.txt | 3 +- mlir/test/lib/Transforms/TestConstantFold.cpp | 2 +- mlir/test/lib/Transforms/TestLoopFusion.cpp | 2 +- mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp | 2 +- .../lib/Transforms/TestMemRefDependenceCheck.cpp | 2 +- .../lib/Transforms/TestParallelismDetection.cpp | 2 +- .../test/lib/Transforms/TestVectorizationUtils.cpp | 2 +- mlir/tools/mlir-opt/CMakeLists.txt | 1 + mlir/tools/mlir-translate/CMakeLists.txt | 2 + openmp/libomptarget/deviceRTLs/CMakeLists.txt | 1 - openmp/libomptarget/plugins/cuda/CMakeLists.txt | 8 +- 366 files changed, 10609 insertions(+), 1505 deletions(-) delete mode 100644 clang-tools-extra/test/clang-tidy/checkers/Inputs/llvmlibc/syst [...] delete mode 100644 clang-tools-extra/test/clang-tidy/checkers/Inputs/llvmlibc/tran [...] delete mode 100644 clang-tools-extra/test/clang-tidy/checkers/llvmlibc-restrict-sy [...] create mode 100644 clang/test/Analysis/std-c-library-functions-arg-constraints.c create mode 100644 clang/test/CodeGen/arm-cde-reinterpret.c create mode 100644 clang/test/CodeGen/arm-cde-vec.c create mode 100644 clang/test/CodeGen/arm-cde-vfp.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vaddv.c create mode 100644 clang/test/CodeGenCXX/ms-thunks-ehspec.cpp create mode 100644 clang/test/CodeGenCXX/thunks-ehspec.cpp create mode 100644 clang/test/OpenMP/scan_ast_print.cpp create mode 100644 clang/test/OpenMP/scan_messages.cpp rename libc/src/math/{round => }/round.cpp (94%) rename libc/src/math/{round => }/round.h (100%) delete mode 100644 libc/src/math/round/CMakeLists.txt copy libc/src/math/{round => }/round_redirector.cpp (100%) rename libc/src/math/round/round_redirector.cpp => libcxx/test/libcxx/selftest/tes [...] create mode 100644 llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-gpr.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-vec.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-vfp.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddv.ll create mode 100644 llvm/test/DebugInfo/X86/pr45181.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/memset-unknown-sizes.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-overlap.ll rename llvm/test/{Analysis/ValueTracking => Transforms/InstCombine}/known-signbit- [...] create mode 100644 llvm/test/Transforms/MemCpyOpt/store-to-memset-is-nonzero-type.ll create mode 100644 llvm/test/Transforms/MemCpyOpt/vscale-memset.ll create mode 100644 llvm/test/tools/llvm-ar/lto-kind-from-triple.test create mode 100644 llvm/test/tools/llvm-readobj/ELF/reloc-addends.test create mode 100644 mlir/include/mlir/Conversion/AVX512ToLLVM/ConvertAVX512ToLLVM.h create mode 100644 mlir/include/mlir/Dialect/AVX512/AVX512.td create mode 100644 mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h create mode 100644 mlir/include/mlir/Dialect/AVX512/CMakeLists.txt copy mlir/include/mlir/Dialect/{Shape => Affine}/CMakeLists.txt (100%) rename mlir/include/mlir/Dialect/{AffineOps => Affine}/EDSC/Builders.h (97%) rename mlir/include/mlir/Dialect/{AffineOps => Affine}/EDSC/Intrinsics.h (87%) rename mlir/include/mlir/Dialect/{AffineOps => Affine/IR}/AffineOps.h (99%) rename mlir/include/mlir/Dialect/{AffineOps => Affine/IR}/AffineOps.td (99%) rename mlir/include/mlir/Dialect/{AffineOps => Affine/IR}/AffineOpsBase.td (100%) rename mlir/include/mlir/Dialect/{AffineOps => Affine/IR}/AffineValueMap.h (96%) rename mlir/include/mlir/Dialect/{AffineOps => Affine/IR}/CMakeLists.txt (100%) create mode 100644 mlir/include/mlir/Dialect/Affine/Passes.h create mode 100644 mlir/include/mlir/Dialect/LLVMIR/LLVMAVX512.td create mode 100644 mlir/include/mlir/Dialect/LLVMIR/LLVMAVX512Dialect.h copy mlir/include/mlir/Dialect/{Vector => VectorOps}/VectorOps.td (99%) create mode 100644 mlir/lib/Conversion/AVX512ToLLVM/CMakeLists.txt create mode 100644 mlir/lib/Conversion/AVX512ToLLVM/ConvertAVX512ToLLVM.cpp create mode 100644 mlir/lib/Dialect/AVX512/CMakeLists.txt create mode 100644 mlir/lib/Dialect/AVX512/IR/AVX512Dialect.cpp create mode 100644 mlir/lib/Dialect/Affine/CMakeLists.txt rename mlir/lib/Dialect/{AffineOps => Affine}/EDSC/Builders.cpp (99%) copy mlir/lib/Dialect/{AffineOps => Affine/EDSC}/CMakeLists.txt (52%) rename mlir/lib/Dialect/{AffineOps => Affine/IR}/AffineOps.cpp (99%) rename mlir/lib/Dialect/{AffineOps => Affine/IR}/AffineValueMap.cpp (97%) rename mlir/lib/Dialect/{AffineOps => Affine/IR}/CMakeLists.txt (57%) rename mlir/lib/{ => Dialect/Affine}/Transforms/AffineDataCopyGeneration.cpp (99%) rename mlir/lib/{ => Dialect/Affine}/Transforms/AffineLoopInvariantCodeMotion.cpp (99%) create mode 100644 mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt rename mlir/lib/{ => Dialect/Affine}/Transforms/SimplifyAffineStructures.cpp (95%) create mode 100644 mlir/lib/Dialect/LLVMIR/IR/LLVMAVX512Dialect.cpp copy mlir/lib/Dialect/{Vector => VectorOps}/VectorTransforms.cpp (92%) copy mlir/lib/Dialect/{Vector => VectorOps}/VectorUtils.cpp (98%) create mode 100644 mlir/lib/Target/LLVMIR/LLVMAVX512Intr.cpp create mode 100644 mlir/test/Conversion/AVX512ToLLVM/convert-to-llvm.mlir create mode 100644 mlir/test/Dialect/AVX512/roundtrip.mlir rename mlir/test/Dialect/{AffineOps => Affine}/canonicalize.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/dma.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/inlining.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/invalid.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/load-store-invalid.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/load-store.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/memref-stride-calculation.mlir (100%) rename mlir/test/Dialect/{AffineOps => Affine}/ops.mlir (100%) create mode 100644 mlir/test/Target/avx512.mlir create mode 100644 mlir/test/lib/Dialect/Affine/CMakeLists.txt rename mlir/test/lib/{Transforms => Dialect/Affine}/TestAffineDataCopy.cpp (98%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (1b151e7 -> 7f6507c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/base-artifacts. discards 1b151e7 0: update: llvm-linux: all new 7f6507c 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1b151e7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12770 +++++++++++++++++------------------ 03-build_linux/console.log | 584 +- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 36 + console.log | 13624 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13662 insertions(+), 13594 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (93556fb211fa -> 14cfdbd39e31)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/linux. from 93556fb211fa Linux 4.19.111 adds e01975190d7b perf/amd/uncore: Replace manual sampling check with CAP_NO [...] adds 6811f1727af0 mmc: sdhci-omap: Add platform specific reset callback adds 971d17255721 mmc: sdhci-omap: Workaround errata regarding SDR104/HS200 [...] adds 625d0b132e8a mmc: host: Fix Kconfig warnings on keystone_defconfig adds e8faa2c49b86 ACPI: watchdog: Allow disabling WDAT at boot adds 2ca4fec1d0f0 HID: apple: Add support for recent firmware on Magic Keyboards adds 70056047a678 HID: i2c-hid: add Trekstor Surfbook E11B to descriptor override adds 81aebc37d223 cfg80211: check reg_rule for NULL in handle_channel_custom() adds 8343dffacc1b scsi: libfc: free response frame from GPN_ID adds 90d77cff14fe net: usb: qmi_wwan: restore mtu min/max values after raw_i [...] adds a17fcd59a2c8 net: ks8851-ml: Fix IRQ handling and locking adds ebd1b09e8112 mac80211: rx: avoid RCU list traversal under mutex adds 797479da0ae9 signal: avoid double atomic counter increments for user ac [...] adds 851346e59122 slip: not call free_netdev before rtnl_unlock in slip_open adds e78ae0038ee8 hinic: fix a irq affinity bug adds 6bd688f39430 hinic: fix a bug of setting hw_ioctxt adds 71ae5b691490 net: rmnet: fix NULL pointer dereference in rmnet_newlink() adds be0453582577 net: rmnet: fix NULL pointer dereference in rmnet_changelink() adds 5cd211aa255f net: rmnet: fix suspicious RCU usage adds 7111ec0927f1 net: rmnet: remove rcu_read_lock in rmnet_force_unassociat [...] adds 48c5bfbbcec1 net: rmnet: do not allow to change mux id if mux id is duplicated adds 799781649bb5 net: rmnet: use upper/lower device infrastructure adds 8cf81bf8ec15 net: rmnet: fix bridge mode bugs adds 5043d35d3738 net: rmnet: fix packet forwarding in rmnet bridge mode adds 04a244c8e61f sfc: fix timestamp reconstruction at 16-bit rollover points adds b0caab0e619e jbd2: fix data races at struct journal_head adds dd5a14630d81 wimax: i2400: fix memory leak adds dfb827019bcc wimax: i2400: Fix memory leak in i2400m_op_rfkill_sw_toggle adds 3f909e15839c mmc: sdhci-omap: Don't finish_mrq() on a command error dur [...] adds 6bdf6513f330 mmc: sdhci-omap: Fix Tuning procedure for temperatures < -20C adds b600c5a14eb9 driver core: Remove the link if there is no driver with AUTO flag adds 1c89b531db42 driver core: Fix adding device links to probing suppliers adds 1f5102cb6bc9 driver core: Make driver core own stateful device links adds 822e87b74f1e driver core: Add device link flag DL_FLAG_AUTOPROBE_CONSUMER adds 53a895ff19bd driver core: Remove device link creation limitation adds cda3bca05e2c driver core: Fix creation of device links with PM-runtime flags adds bc97a345d975 net: qrtr: fix len of skb_put_padto in qrtr_node_enqueue adds 8cf58ea4abd3 ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional() adds c1a9559a24b0 ARM: 8958/1: rename missed uaccess .fixup section adds 30f6cae72265 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 705d1b54a70a HID: google: add moonball USB id adds a44324b0bdca efi: Fix debugobjects warning on 'efi_rts_work' adds b4176d3b1a82 ipv4: ensure rcu_read_lock() in cipso_v4_error() adds 14cfdbd39e31 Linux 4.19.112 No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Documentation/driver-api/device_link.rst | 63 +++-- Makefile | 2 +- arch/arm/kernel/vdso.c | 2 + arch/arm/lib/copy_from_user.S | 2 +- arch/x86/events/amd/uncore.c | 14 +- drivers/acpi/acpi_watchdog.c | 12 +- drivers/base/core.c | 293 +++++++++++++++------ drivers/base/dd.c | 2 +- drivers/base/power/runtime.c | 4 +- drivers/firmware/efi/runtime-wrappers.c | 2 +- drivers/hid/hid-apple.c | 3 +- drivers/hid/hid-google-hammer.c | 2 + drivers/hid/hid-ids.h | 1 + drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 + drivers/mmc/host/Kconfig | 2 + drivers/mmc/host/sdhci-omap.c | 148 ++++++++++- drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 2 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_rx.c | 5 +- drivers/net/ethernet/micrel/ks8851_mll.c | 14 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 186 +++++++------ drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h | 3 +- .../net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 7 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 8 - drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h | 1 - drivers/net/ethernet/sfc/ptp.c | 38 ++- drivers/net/slip/slip.c | 3 + drivers/net/usb/qmi_wwan.c | 3 + drivers/net/wimax/i2400m/op-rfkill.c | 1 + drivers/scsi/libfc/fc_disc.c | 2 + fs/jbd2/transaction.c | 8 +- include/linux/device.h | 7 +- kernel/signal.c | 23 +- mm/slub.c | 9 + net/ipv4/cipso_ipv4.c | 7 +- net/mac80211/rx.c | 2 +- net/qrtr/qrtr.c | 2 +- net/wireless/reg.c | 2 +- 41 files changed, 645 insertions(+), 255 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (4119cd693d2 -> 497498c878d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/gcc. from 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 1553 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/cgraph.c | 64 +- gcc/cgraph.h | 17 +- gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000.c | 8 + gcc/cp/ChangeLog | 10 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 13 + gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/types.cc | 48 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 615 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + 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+ .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + 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.../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + 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.../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (c3a1714ce7 -> d9fb0d7136)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/binutils-gdb. from c3a1714ce7 plugin: Use LDPT_ADD_SYMBOLS_V2 to get symbol type adds 3d98c46092 plugin: Don't invoke LTO-wrapper adds 5844b4657a Fix compile time warnings about the possibility of using uni [...] adds c7da12c72c Add support for NetBSD threads in ppc-nbsd-nat.c adds 0d832e7f5e Add support for the xdef and xref pseudo-ops to the Z80 assembler. adds 0dd7b8f788 [gdb/testsuite] Fix timeouts in gdb.threads/step-over-*.exp adds 4a90f06205 Add support for NetBSD threads in hppa-nbsd-nat.c adds 9faa006d11 Inherit ppc_nbsd_nat_target from nbsd_nat_target adds 70304be939 Fix Ada val_print removal regression adds 1773be9ea2 Fix column alignment in "maint info line-table" adds f67210ff1c Avoid stringop-truncation errors adds f7d4f0b1b9 Fix assert in c-exp.y adds 1ff700c202 Update the return type of gdb_ptrace to be more flexible adds c884cc4619 gdb: remove HAVE_DECL_PTRACE adds c623cc9089 [gdb/testsuite] Fix gdb.threads/omp-par-scope.exp XPASS adds fe26d3a34a Make dwarf2_evaluate_property parameter const adds d9fb0d7136 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 26 ++ bfd/config.in | 6 - bfd/configure | 10 - bfd/configure.ac | 6 - bfd/plugin.c | 453 +-------------------- bfd/plugin.h | 5 +- bfd/version.h | 2 +- binutils/ChangeLog | 14 + binutils/ar.c | 2 +- binutils/nm.c | 2 +- binutils/readelf.c | 34 +- gas/ChangeLog | 6 + gas/config/tc-z80.c | 2 + gas/doc/c-z80.texi | 83 ++-- gdb/ChangeLog | 64 +++ gdb/ada-tasks.c | 3 +- gdb/ada-valprint.c | 99 ++--- gdb/amd64-bsd-nat.c | 2 +- gdb/c-exp.y | 2 +- gdb/config.in | 4 - gdb/configure | 20 - gdb/dwarf2/loc.c | 4 +- gdb/dwarf2/loc.h | 2 +- gdb/hppa-nbsd-nat.c | 14 +- gdb/i386-bsd-nat.c | 2 +- gdb/linux-tdep.c | 4 +- gdb/nat/gdb_ptrace.h | 8 - gdb/ppc-nbsd-nat.c | 17 +- gdb/ptrace.m4 | 6 +- gdb/sparc-nat.c | 2 +- gdb/symmisc.c | 29 +- gdb/testsuite/ChangeLog | 15 + .../gdb.ada/{interface.exp => sub_variant.exp} | 17 +- .../global_pack.ads => sub_variant/subv.adb} | 34 +- gdb/testsuite/gdb.dwarf2/dw2-ranges-base.exp | 6 +- gdb/testsuite/gdb.threads/omp-par-scope.exp | 4 +- .../gdb.threads/step-over-lands-on-breakpoint.exp | 5 +- .../gdb.threads/step-over-trips-on-watchpoint.exp | 5 +- gdb/testsuite/lib/gdb.exp | 24 ++ gdb/x86-bsd-nat.c | 2 +- gdbserver/ChangeLog | 5 + gdbserver/config.in | 4 - gdbserver/configure | 20 - gdbsupport/ChangeLog | 5 + gdbsupport/config.in | 4 - gdbsupport/configure | 20 - ld/ChangeLog | 5 + ld/testsuite/ld-plugin/lto.exp | 15 +- 48 files changed, 408 insertions(+), 715 deletions(-) copy gdb/testsuite/gdb.ada/{interface.exp => sub_variant.exp} (63%) copy gdb/testsuite/gdb.ada/{info_auto_lang/global_pack.ads => sub_variant/subv.adb} (51%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (21756ca -> a003813)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 21756ca 0: update: binutils-gcc-linux: boot new a003813 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (21756ca) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 122 +- 02-prepare_abe/console.log | 258 +- 03-build_abe-binutils/console.log | 11642 +++++++------- 04-build_abe-stage1/console.log | 15765 +++++++++--------- 05-build_linux/console.log | 2848 ++-- 06-boot_linux/console.log | 404 +- 07-check_regression/console.log | 4 +- 08-update_baseline/console.log | 6 +- console.log | 31053 ++++++++++++++++++------------------ jenkins/manifest.sh | 16 +- regressions.txt | 2 +- 11 files changed, 31061 insertions(+), 31059 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[newlib] branch topic/serial_io updated (2e8dab58f -> 74cfbbae8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch topic/serial_io in repository newlib. from 2e8dab58f Cygwin: serial: revamp overlapped IO in read and select new 33afbcf65 Cygwin: serial: select: fix previous revamp patch new 74cfbbae8 Cygwin: serial: avoid overrun of vtime The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/fhandler.h | 1 + winsup/cygwin/fhandler_serial.cc | 8 ++++---- winsup/cygwin/select.cc | 12 ++++++++---- 3 files changed, 13 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (257edc6db943 -> 585e0cc08069)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/linux. from 257edc6db943 Linux 5.4.26 adds 536942bf70b5 netfilter: hashlimit: do not use indirect calls during gc adds f6fccb0a0e59 netfilter: xt_hashlimit: unregister proc file before relea [...] adds f3c478104a9a drm/amdgpu: Fix TLB invalidation request when using semaphore adds 20eed7692749 ACPI: watchdog: Allow disabling WDAT at boot adds 65b44497414b HID: apple: Add support for recent firmware on Magic Keyboards adds 87bd74b77531 ACPI: watchdog: Set default timeout in probe adds 190e929e6cba HID: i2c-hid: add Trekstor Surfbook E11B to descriptor override adds 1bc271dd397d HID: hid-bigbenff: fix general protection fault caused by [...] adds ccb747d805d3 HID: hid-bigbenff: call hid_hw_stop() in case of error adds dd0d2d6ab6a2 HID: hid-bigbenff: fix race condition for scheduled work d [...] adds c35aa36fec91 selftests/rseq: Fix out-of-tree compilation adds a6f7e69cfafd tracing: Fix number printing bug in print_synth_event() adds 079e9ad79410 cfg80211: check reg_rule for NULL in handle_channel_custom() adds 6c663120ecdb scsi: libfc: free response frame from GPN_ID adds d939f3389f9b net: usb: qmi_wwan: restore mtu min/max values after raw_i [...] adds 5d92d834aa27 net: ks8851-ml: Fix IRQ handling and locking adds a342bb7b9902 mac80211: rx: avoid RCU list traversal under mutex adds 0c050d655475 net: ll_temac: Fix race condition causing TX hang adds 6e3b69543b5e net: ll_temac: Add more error handling of dma_map_single() calls adds c2cffaea4fde net: ll_temac: Fix RX buffer descriptor handling on GFP_AT [...] adds 74886a6d9de8 net: ll_temac: Handle DMA halt condition caused by buffer [...] adds 74c77d6a4ea9 blk-mq: insert passthrough request into hctx->dispatch directly adds bbf3acbb8a77 drm/amdgpu: fix memory leak during TDR test(v2) adds fd1f29f2a824 kbuild: add dtbs_check to PHONY adds df8e98b00941 kbuild: add dt_binding_check to PHONY in a correct place adds d1984c92f072 signal: avoid double atomic counter increments for user ac [...] adds 4d6ee3123d65 slip: not call free_netdev before rtnl_unlock in slip_open adds 1c7dde0a9bfc net: phy: mscc: fix firmware paths adds 65340b196811 hinic: fix a irq affinity bug adds e6f52d5ce172 hinic: fix a bug of setting hw_ioctxt adds cfc7f5fe5c61 hinic: fix a bug of rss configuration adds 006cd2426a05 net: rmnet: fix NULL pointer dereference in rmnet_newlink() adds 8a027eee62f7 net: rmnet: fix NULL pointer dereference in rmnet_changelink() adds 002b4bd9b51d net: rmnet: fix suspicious RCU usage adds 5ce5e95d72f1 net: rmnet: remove rcu_read_lock in rmnet_force_unassociat [...] adds 835bbd892683 net: rmnet: do not allow to change mux id if mux id is duplicated adds 8eccc6d06ea1 net: rmnet: use upper/lower device infrastructure adds 34c550ebb219 net: rmnet: fix bridge mode bugs adds e2b8b042c98b net: rmnet: fix packet forwarding in rmnet bridge mode adds 99746e92fa4c sfc: fix timestamp reconstruction at 16-bit rollover points adds dbce8292217a jbd2: fix data races at struct journal_head adds 235fb892d846 blk-mq: insert flush request to the front of dispatch queue adds 881876bee657 net: qrtr: fix len of skb_put_padto in qrtr_node_enqueue adds 1a9e78628d44 ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional() adds 47b6d269dbbd ARM: 8958/1: rename missed uaccess .fixup section adds ae119b7e1247 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 5d961582ea88 HID: google: add moonball USB id adds 1dc67950e2d1 HID: add ALWAYS_POLL quirk to lenovo pixart mouse adds 81e0dac3780a ARM: 8961/2: Fix Kbuild issue caused by per-task stack pro [...] adds 20ba40d262b0 ipv4: ensure rcu_read_lock() in cipso_v4_error() adds 585e0cc08069 Linux 5.4.27 No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Makefile | 5 +- arch/arm/Makefile | 4 +- arch/arm/boot/compressed/Makefile | 4 +- arch/arm/kernel/vdso.c | 2 + arch/arm/lib/copy_from_user.S | 2 +- block/blk-flush.c | 2 +- block/blk-mq-sched.c | 44 ++++- block/blk-mq.c | 18 +- block/blk-mq.h | 3 +- drivers/acpi/acpi_watchdog.c | 12 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +- drivers/hid/hid-apple.c | 3 +- drivers/hid/hid-bigbenff.c | 31 ++- drivers/hid/hid-google-hammer.c | 2 + drivers/hid/hid-ids.h | 2 + drivers/hid/hid-quirks.c | 1 + drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 2 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_main.c | 3 +- drivers/net/ethernet/huawei/hinic/hinic_rx.c | 5 +- drivers/net/ethernet/micrel/ks8851_mll.c | 14 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 186 +++++++++--------- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h | 3 +- .../net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 7 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 8 - drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h | 1 - drivers/net/ethernet/sfc/ptp.c | 38 +++- drivers/net/ethernet/xilinx/ll_temac.h | 4 + drivers/net/ethernet/xilinx/ll_temac_main.c | 209 +++++++++++++++++---- drivers/net/phy/mscc.c | 4 +- drivers/net/slip/slip.c | 3 + drivers/net/usb/qmi_wwan.c | 3 + drivers/scsi/libfc/fc_disc.c | 2 + drivers/watchdog/wdat_wdt.c | 23 +++ fs/jbd2/transaction.c | 8 +- kernel/signal.c | 23 ++- kernel/trace/trace_events_hist.c | 32 +++- mm/slub.c | 9 + net/ipv4/cipso_ipv4.c | 7 +- net/mac80211/rx.c | 2 +- net/netfilter/xt_hashlimit.c | 36 +--- net/qrtr/qrtr.c | 2 +- net/wireless/reg.c | 2 +- tools/testing/selftests/rseq/Makefile | 2 +- 50 files changed, 560 insertions(+), 247 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (4a18f168f47 -> 497498c878d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/gcc. from 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. new 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. new 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 1565 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/cgraph.c | 64 +- gcc/cgraph.h | 17 +- gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000.c | 8 + gcc/cp/ChangeLog | 10 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 13 + gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/types.cc | 48 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 620 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 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+ .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + 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.../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 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+ .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 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100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create 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Tcwg-commits March 2020