Tcwg-commits March 2020

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11017 discussions

[gcc] branch master updated (f9355dee93f -> 0dad5b33687)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. new 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 129 +++++ gcc/config/arm/arm-builtins.c | 90 ++++ gcc/config/arm/arm_mve.h | 449 +++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 564 +++++++++++---------- gcc/config/arm/mve.md | 187 ++++++- gcc/testsuite/ChangeLog | 39 ++ .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../intrinsics/{vctp16q_m.c => vbicq_m_n_s16.c} | 14 +- .../intrinsics/{vctp64q_m.c => vbicq_m_n_s32.c} | 14 +- .../intrinsics/{vctp16q_m.c => vbicq_m_n_u16.c} | 14 +- .../intrinsics/{vctp16q_m.c => vbicq_m_n_u32.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 23 + .../{vmovnbq_s16.c => vqrshrnbq_n_s16.c} | 8 +- .../{vmovnbq_s32.c => vqrshrnbq_n_s32.c} | 8 +- .../{vmovnbq_u16.c => vqrshrnbq_n_u16.c} | 8 +- .../{vmovnbq_u32.c => vqrshrnbq_n_u32.c} | 8 +- .../{vqmovunbq_s16.c => vqrshrunbq_n_s16.c} | 8 +- .../{vqmovunbq_s32.c => vqrshrunbq_n_s32.c} | 8 +- .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + 40 files changed, 1753 insertions(+), 347 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vbicq_m_n_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp64q_m.c => vbicq_m_n_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vbicq_m_n_u16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vbicq_m_n_u32.c} (57%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vqrshrnbq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vqrshrnbq_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vqrshrnbq_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vqrshrnbq_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s16.c => vqrshrunbq_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s32.c => vqrshrunbq_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (33203b4c27d -> f9355dee93f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. new f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 488 +++ gcc/config/arm/arm_mve.h | 3279 ++++++++++++++++---- gcc/config/arm/arm_mve_builtins.def | 468 +-- gcc/config/arm/mve.md | 1008 +++++- gcc/testsuite/ChangeLog | 150 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vaddq_n_f16.c} | 8 +- .../intrinsics/{vsubq_n_f32.c => vaddq_n_f32.c} | 8 +- .../intrinsics/{vcvtq_n_f16_s16.c => vandq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vandq_f32.c} | 12 +- .../intrinsics/{vcvtq_n_f16_s16.c => vbicq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vbicq_f32.c} | 12 +- .../intrinsics/{vmvnq_n_s16.c => vbicq_n_s16.c} | 6 +- .../intrinsics/{vmvnq_n_s32.c => vbicq_n_s32.c} | 6 +- .../intrinsics/{vdupq_n_u16.c => vbicq_n_u16.c} | 6 +- .../intrinsics/{vdupq_n_u32.c => vbicq_n_u32.c} | 6 +- .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpeqq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpeqq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpgeq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpgeq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpgtq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpgtq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpleq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpleq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpltq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpltq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpneq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpneq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../intrinsics/{vabsq_f16.c => vcvtbq_f16_f32.c} | 6 +- .../intrinsics/{vabsq_f16.c => vcvttq_f16_f32.c} | 6 +- .../intrinsics/{vcvtq_n_f16_s16.c => veorq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => veorq_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../intrinsics/{vabdq_s16.c => vmlaldavq_s16.c} | 12 +- .../intrinsics/{vcmpeqq_s32.c => vmlaldavq_s32.c} | 12 +- .../intrinsics/{vbicq_u16.c => vmlaldavq_u16.c} | 12 +- .../intrinsics/{vabdq_u32.c => vmlaldavq_u32.c} | 12 +- .../{vcaddq_rot90_s16.c => vmlaldavxq_s16.c} | 12 +- .../{vcaddq_rot90_s32.c => vmlaldavxq_s32.c} | 12 +- .../intrinsics/{vcmpeqq_s16.c => vmlsldavq_s16.c} | 12 +- .../intrinsics/{vcmpeqq_s32.c => vmlsldavq_s32.c} | 12 +- .../{vcaddq_rot90_s16.c => vmlsldavxq_s16.c} | 12 +- .../{vcaddq_rot90_s32.c => vmlsldavxq_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 22 + .../{vmullbq_int_u16.c => vmullbq_poly_p16.c} | 8 +- .../{vmullbq_int_u8.c => vmullbq_poly_p8.c} | 8 +- .../{vmullbq_int_u16.c => vmulltq_poly_p16.c} | 8 +- .../{vmullbq_int_u8.c => vmulltq_poly_p8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vmulq_n_f16.c} | 8 +- .../intrinsics/{vsubq_n_f32.c => vmulq_n_f32.c} | 8 +- .../intrinsics/{vcvtq_n_f16_s16.c => vornq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vornq_f32.c} | 12 +- .../intrinsics/{vcvtq_n_f16_s16.c => vorrq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vorrq_f32.c} | 12 +- .../intrinsics/{vmvnq_n_s16.c => vorrq_n_s16.c} | 6 +- .../intrinsics/{vmvnq_n_s32.c => vorrq_n_s32.c} | 6 +- .../intrinsics/{vdupq_n_u16.c => vorrq_n_u16.c} | 6 +- .../intrinsics/{vdupq_n_u32.c => vorrq_n_u32.c} | 6 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 2 +- .../{vaddq_n_s16.c => vqdmullbq_n_s16.c} | 12 +- .../{vbrsrq_n_s32.c => vqdmullbq_n_s32.c} | 12 +- .../{vmullbq_int_s16.c => vqdmullbq_s16.c} | 8 +- .../{vmullbq_int_s32.c => vqdmullbq_s32.c} | 8 +- .../{vaddq_n_s16.c => vqdmulltq_n_s16.c} | 12 +- .../{vbrsrq_n_s32.c => vqdmulltq_n_s32.c} | 12 +- .../{vmullbq_int_s16.c => vqdmulltq_s16.c} | 8 +- .../{vmullbq_int_s32.c => vqdmulltq_s32.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 2 +- .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 2 +- .../{vcaddq_rot270_s32.c => vrmlaldavhq_s32.c} | 12 +- .../intrinsics/{vabdq_u32.c => vrmlaldavhq_u32.c} | 12 +- .../{vcaddq_rot270_s32.c => vrmlaldavhxq_s32.c} | 12 +- .../{vcaddq_rot270_s32.c => vrmlsldavhq_s32.c} | 12 +- .../intrinsics/{vabdq_s32.c => vrmlsldavhxq_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 2 +- .../intrinsics/{vrev64q_s16.c => vshllbq_n_s16.c} | 12 +- .../intrinsics/{vmovltq_s8.c => vshllbq_n_s8.c} | 8 +- .../intrinsics/{vmovltq_u16.c => vshllbq_n_u16.c} | 8 +- .../intrinsics/{vmovltq_u8.c => vshllbq_n_u8.c} | 8 +- .../intrinsics/{vrev64q_s16.c => vshlltq_n_s16.c} | 12 +- .../intrinsics/{vmovltq_s8.c => vshlltq_n_s8.c} | 8 +- .../intrinsics/{vmovltq_u16.c => vshlltq_n_u16.c} | 8 +- .../intrinsics/{vmovltq_u8.c => vshlltq_n_u8.c} | 8 +- .../mve/intrinsics/{vsubq_n_f16.c => vsubq_f16.c} | 6 +- .../mve/intrinsics/{vsubq_n_f32.c => vsubq_f32.c} | 6 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 3 +- 205 files changed, 6531 insertions(+), 1258 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vaddq_n_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vaddq_n_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vandq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vandq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vbicq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vbicq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s16.c => vbicq_n_s16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s32.c => vbicq_n_s32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u16.c => vbicq_n_u16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u32.c => vbicq_n_u32.c} (66%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpeqq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpeqq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpgeq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpgeq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpgtq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpgtq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpleq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpleq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpltq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpltq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpneq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpneq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_f16.c => vcvtbq_f16_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_f16.c => vcvttq_f16_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => veorq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => veorq_f32.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_s16.c => vmlaldavq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s32.c => vmlaldavq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_u16.c => vmlaldavq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vmlaldavq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s16.c => vmlaldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s32.c => vmlaldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s16.c => vmlsldavq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s32.c => vmlsldavq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s16.c => vmlsldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s32.c => vmlsldavxq [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u16.c => vmullbq_pol [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u8.c => vmullbq_poly [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u16.c => vmulltq_pol [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u8.c => vmulltq_poly [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vmulq_n_f16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vmulq_n_f32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vornq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vornq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vorrq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vorrq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s16.c => vorrq_n_s16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s32.c => vorrq_n_s32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u16.c => vorrq_n_u16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u32.c => vorrq_n_u32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s16.c => vqdmullbq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_s32.c => vqdmullbq_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s16.c => vqdmullbq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s32.c => vqdmullbq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s16.c => vqdmulltq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_s32.c => vqdmulltq_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s16.c => vqdmulltq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s32.c => vqdmulltq_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlaldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vrmlaldavhq_u32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlaldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlsldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_s32.c => vrmlsldavhxq_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vshllbq_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_s8.c => vshllbq_n_s8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u16.c => vshllbq_n_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u8.c => vshllbq_n_u8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vshlltq_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_s8.c => vshlltq_n_s8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u16.c => vshlltq_n_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u8.c => vshlltq_n_u8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vsubq_f16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vsubq_f32.c} (77%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig updated (39930d67fff -> 135744ce689)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig in repository toolchain/ci/llvm-project. from 39930d67fff Add new website to release notes. adds 9e0bd5ec03c [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 135744ce689 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 ++++-- clang/lib/Parse/ParseDecl.cpp | 6 ++++++ clang/lib/Parse/ParseTemplate.cpp | 3 ++- clang/lib/Sema/SemaTemplate.cpp | 13 ++++++++----- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +++-- clang/test/SemaTemplate/instantiate-requires-expr.cpp | 13 +++++++++++++ clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp | 1 + 9 files changed, 39 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig updated (332a04de4 -> 1d84dd894)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 332a04de4 10: update: llvm-linux: 17560 new 1d84dd894 10: update: llvm-linux: 17560 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (332a04de4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-build_llvm/console.log | 12580 ++++++++++++------------- 03-build_linux/console.log | 6436 +++++++------ 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 38 +- console.log | 19134 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- regressions.txt | 20 +- 8 files changed, 19146 insertions(+), 19150 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[binutils-gdb] branch master updated (98097623244 -> a225c9a8692)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 98097623244 Inherit sh_nbsd_nat_target from nbsd_nat_target new a225c9a8692 Add support for NetBSD threads in sh-nbsd-nat.c The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 6 ++++++ gdb/sh-nbsd-nat.c | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (d71dba7b611 -> 33203b4c27d)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. new 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 868 +++++ gcc/config/arm/arm_mve.h | 3657 +++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 120 + gcc/config/arm/constraints.md | 14 +- gcc/config/arm/mve.md | 1205 ++++++- gcc/config/arm/predicates.md | 8 + gcc/testsuite/ChangeLog | 365 ++ .../mve/intrinsics/{vshlq_s16.c => vabdq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vabdq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vabdq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vabdq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vabdq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vabdq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 22 + .../mve/intrinsics/{vclsq_s8.c => vaddq_n_s8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 22 + .../mve/intrinsics/{vclzq_u8.c => vaddq_n_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 22 + .../intrinsics/{vaddlvq_p_s32.c => vaddvq_p_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 22 + .../intrinsics/{vaddlvq_p_u32.c => vaddvq_p_u32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vandq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vandq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vandq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vandq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vandq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vandq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vbicq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vbicq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vbicq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vbicq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vbicq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vbicq_u8.c} | 12 +- .../intrinsics/{vbrsrq_n_f16.c => vbrsrq_n_s16.c} | 14 +- .../intrinsics/{vbrsrq_n_f32.c => vbrsrq_n_s32.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 22 + .../intrinsics/{vbrsrq_n_f16.c => vbrsrq_n_u16.c} | 14 +- .../intrinsics/{vbrsrq_n_f32.c => vbrsrq_n_u32.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 22 + .../{vshlq_s16.c => vcaddq_rot270_s16.c} | 8 +- .../{vshlq_s32.c => vcaddq_rot270_s32.c} | 8 +- .../intrinsics/{vshlq_s8.c => vcaddq_rot270_s8.c} | 8 +- .../{vcmpneq_u16.c => vcaddq_rot270_u16.c} | 12 +- .../{vcmpneq_u32.c => vcaddq_rot270_u32.c} | 12 +- .../{vcmpneq_u8.c => vcaddq_rot270_u8.c} | 12 +- .../intrinsics/{vshlq_s16.c => vcaddq_rot90_s16.c} | 8 +- .../intrinsics/{vshlq_s32.c => vcaddq_rot90_s32.c} | 8 +- .../intrinsics/{vshlq_s8.c => vcaddq_rot90_s8.c} | 8 +- .../{vcmpneq_u16.c => vcaddq_rot90_u16.c} | 12 +- .../{vcmpneq_u32.c => vcaddq_rot90_u32.c} | 12 +- .../intrinsics/{vcmpneq_u8.c => vcaddq_rot90_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 22 + .../mve/intrinsics/{vctp32q.c => vcmpcsq_n_u8.c} | 12 +- .../intrinsics/{vcmpneq_u16.c => vcmpcsq_u16.c} | 8 +- .../intrinsics/{vcmpneq_u32.c => vcmpcsq_u32.c} | 8 +- .../mve/intrinsics/{vcmpneq_u8.c => vcmpcsq_u8.c} | 8 +- .../intrinsics/{vcmpneq_s16.c => vcmpeqq_n_s16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpeqq_n_s32.c} | 8 +- .../intrinsics/{vcmpneq_s8.c => vcmpeqq_n_s8.c} | 8 +- .../intrinsics/{vcmpneq_s16.c => vcmpeqq_n_u16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpeqq_n_u32.c} | 8 +- .../intrinsics/{vcmpneq_s8.c => vcmpeqq_n_u8.c} | 8 +- .../intrinsics/{vcmpneq_s16.c => vcmpeqq_s16.c} | 4 +- .../intrinsics/{vcmpneq_s32.c => vcmpeqq_s32.c} | 4 +- .../mve/intrinsics/{vcmpneq_s8.c => vcmpeqq_s8.c} | 4 +- .../intrinsics/{vcmpneq_u16.c => vcmpeqq_u16.c} | 4 +- .../intrinsics/{vcmpneq_u32.c => vcmpeqq_u32.c} | 4 +- .../mve/intrinsics/{vcmpneq_u8.c => vcmpeqq_u8.c} | 4 +- .../mve/intrinsics/{vctp32q.c => vcmpgeq_n_s16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpgeq_n_s32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpgeq_n_s8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vcmpgeq_s16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpgeq_s32.c} | 8 +- .../mve/intrinsics/{vcmpneq_s8.c => vcmpgeq_s8.c} | 8 +- .../mve/intrinsics/{vctp32q.c => vcmpgtq_n_s16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpgtq_n_s32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpgtq_n_s8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vcmpgtq_s16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpgtq_s32.c} | 8 +- .../mve/intrinsics/{vcmpneq_s8.c => vcmpgtq_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 22 + .../mve/intrinsics/{vctp32q.c => vcmphiq_n_u8.c} | 12 +- .../intrinsics/{vcmpneq_u16.c => vcmphiq_u16.c} | 8 +- .../intrinsics/{vcmpneq_u32.c => vcmphiq_u32.c} | 8 +- .../mve/intrinsics/{vcmpneq_u8.c => vcmphiq_u8.c} | 8 +- .../mve/intrinsics/{vctp32q.c => vcmpleq_n_s16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpleq_n_s32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpleq_n_s8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vcmpleq_s16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpleq_s32.c} | 8 +- .../mve/intrinsics/{vcmpneq_s8.c => vcmpleq_s8.c} | 8 +- .../mve/intrinsics/{vctp32q.c => vcmpltq_n_s16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpltq_n_s32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vcmpltq_n_s8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vcmpltq_s16.c} | 8 +- .../intrinsics/{vcmpneq_s32.c => vcmpltq_s32.c} | 8 +- .../mve/intrinsics/{vcmpneq_s8.c => vcmpltq_s8.c} | 8 +- .../intrinsics/{vcmpneq_s16.c => vcmpneq_n_s16.c} | 6 +- .../intrinsics/{vcmpneq_s32.c => vcmpneq_n_s32.c} | 6 +- .../intrinsics/{vcmpneq_s8.c => vcmpneq_n_s8.c} | 6 +- .../intrinsics/{vcmpneq_s16.c => vcmpneq_n_u16.c} | 6 +- .../intrinsics/{vcmpneq_s32.c => vcmpneq_n_u32.c} | 6 +- .../intrinsics/{vcmpneq_s8.c => vcmpneq_n_u8.c} | 6 +- .../mve/intrinsics/{vshlq_s16.c => veorq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => veorq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => veorq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => veorq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => veorq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => veorq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vhaddq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vhaddq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vhaddq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vhaddq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vhaddq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vhaddq_u8.c} | 12 +- .../{vshlq_s16.c => vhcaddq_rot270_s16.c} | 8 +- .../{vshlq_s32.c => vhcaddq_rot270_s32.c} | 8 +- .../intrinsics/{vshlq_s8.c => vhcaddq_rot270_s8.c} | 8 +- .../{vshlq_s16.c => vhcaddq_rot90_s16.c} | 8 +- .../{vshlq_s32.c => vhcaddq_rot90_s32.c} | 8 +- .../intrinsics/{vshlq_s8.c => vhcaddq_rot90_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vhsubq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vhsubq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vhsubq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vhsubq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vhsubq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vhsubq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_u16.c => vmaxaq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vmaxaq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_u8.c => vmaxaq_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vmaxq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vmaxq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vmaxq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vmaxq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vmaxq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vmaxq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 22 + .../mve/intrinsics/{vshlq_u16.c => vminaq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vminaq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_u8.c => vminaq_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vminq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vminq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vminq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vminq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vminq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vminq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vmladavq_s16.c} | 12 +- .../mve/intrinsics/{vshlq_s32.c => vmladavq_s32.c} | 12 +- .../mve/intrinsics/{vshlq_s8.c => vmladavq_s8.c} | 12 +- .../intrinsics/{vcmpneq_u16.c => vmladavq_u16.c} | 12 +- .../intrinsics/{vcmpneq_u32.c => vmladavq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vmladavq_u8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vmladavxq_s16.c} | 12 +- .../intrinsics/{vcmpneq_s32.c => vmladavxq_s32.c} | 12 +- .../intrinsics/{vcmpneq_s8.c => vmladavxq_s8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vmlsdavq_s16.c} | 12 +- .../mve/intrinsics/{vshlq_s32.c => vmlsdavq_s32.c} | 12 +- .../mve/intrinsics/{vshlq_s8.c => vmlsdavq_s8.c} | 12 +- .../intrinsics/{vcmpneq_s16.c => vmlsdavxq_s16.c} | 12 +- .../intrinsics/{vcmpneq_s32.c => vmlsdavxq_s32.c} | 12 +- .../intrinsics/{vcmpneq_s8.c => vmlsdavxq_s8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vmulhq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vmulhq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vmulhq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vmulhq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vmulhq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vmulhq_u8.c} | 12 +- .../{vcmpneq_s16.c => vmullbq_int_s16.c} | 12 +- .../{vcmpneq_s32.c => vmullbq_int_s32.c} | 12 +- .../intrinsics/{vcmpneq_s8.c => vmullbq_int_s8.c} | 12 +- .../{vcmpneq_u16.c => vmullbq_int_u16.c} | 12 +- .../{vcmpneq_u32.c => vmullbq_int_u32.c} | 12 +- .../intrinsics/{vcmpneq_u8.c => vmullbq_int_u8.c} | 12 +- .../{vcmpneq_s16.c => vmulltq_int_s16.c} | 12 +- .../{vcmpneq_s32.c => vmulltq_int_s32.c} | 12 +- .../intrinsics/{vcmpneq_s8.c => vmulltq_int_s8.c} | 12 +- .../{vcmpneq_u16.c => vmulltq_int_u16.c} | 12 +- .../{vcmpneq_u32.c => vmulltq_int_u32.c} | 12 +- .../intrinsics/{vcmpneq_u8.c => vmulltq_int_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 22 + .../mve/intrinsics/{vclsq_s8.c => vmulq_n_s8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vmulq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vmulq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vmulq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vmulq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vmulq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vmulq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vornq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vornq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vornq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vornq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vornq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vornq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vorrq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vorrq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vorrq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vorrq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vorrq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vorrq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vqaddq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vqaddq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vqaddq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vqaddq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vqaddq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vqaddq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vqdmulhq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vqdmulhq_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vqdmulhq_s8.c} | 8 +- .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 22 + .../intrinsics/{vshlq_s16.c => vqrdmulhq_s16.c} | 8 +- .../intrinsics/{vshlq_s32.c => vqrdmulhq_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vqrdmulhq_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vqrshlq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vqrshlq_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vqrshlq_s8.c} | 8 +- .../mve/intrinsics/{vshlq_u16.c => vqrshlq_u16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vqrshlq_u32.c} | 8 +- .../mve/intrinsics/{vshlq_u8.c => vqrshlq_u8.c} | 8 +- .../intrinsics/{vrev64q_s16.c => vqshlq_n_s16.c} | 8 +- .../intrinsics/{vshrq_n_s32.c => vqshlq_n_s32.c} | 8 +- .../mve/intrinsics/{vclsq_s8.c => vqshlq_n_s8.c} | 8 +- .../mve/intrinsics/{vmvnq_u16.c => vqshlq_n_u16.c} | 8 +- .../mve/intrinsics/{vclzq_u32.c => vqshlq_n_u32.c} | 8 +- .../mve/intrinsics/{vmvnq_u8.c => vqshlq_n_u8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vqshlq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vqshlq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vqshlq_s8.c} | 8 +- .../mve/intrinsics/{vshlq_u16.c => vqshlq_u16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vqshlq_u32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_u8.c => vqshlq_u8.c} | 8 +- .../intrinsics/{vrev64q_s16.c => vqshluq_n_s16.c} | 12 +- .../intrinsics/{vqnegq_s32.c => vqshluq_n_s32.c} | 12 +- .../mve/intrinsics/{vclsq_s8.c => vqshluq_n_s8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vqsubq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vqsubq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vqsubq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vqsubq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vqsubq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vqsubq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vrhaddq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vrhaddq_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vrhaddq_s8.c} | 8 +- .../intrinsics/{vcmpneq_u16.c => vrhaddq_u16.c} | 12 +- .../intrinsics/{vcmpneq_u32.c => vrhaddq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vrhaddq_u8.c} | 12 +- .../mve/intrinsics/{vshlq_s16.c => vrmulhq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vrmulhq_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vrmulhq_s8.c} | 8 +- .../intrinsics/{vcmpneq_u16.c => vrmulhq_u16.c} | 12 +- .../intrinsics/{vcmpneq_u32.c => vrmulhq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vrmulhq_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vrshlq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vrshlq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vrshlq_s8.c} | 8 +- .../mve/intrinsics/{vshlq_u16.c => vrshlq_u16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vrshlq_u32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_u8.c => vrshlq_u8.c} | 8 +- .../intrinsics/{vrev64q_s16.c => vrshrq_n_s16.c} | 8 +- .../intrinsics/{vshrq_n_s32.c => vrshrq_n_s32.c} | 8 +- .../mve/intrinsics/{vclsq_s8.c => vrshrq_n_s8.c} | 8 +- .../mve/intrinsics/{vmvnq_u16.c => vrshrq_n_u16.c} | 8 +- .../mve/intrinsics/{vclzq_u32.c => vrshrq_n_u32.c} | 8 +- .../mve/intrinsics/{vmvnq_u8.c => vrshrq_n_u8.c} | 8 +- .../mve/intrinsics/{vshlq_s16.c => vshlq_n_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vshlq_n_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vshlq_n_s8.c} | 8 +- .../mve/intrinsics/{vshlq_u16.c => vshlq_n_u16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vshlq_n_u32.c} | 8 +- .../mve/intrinsics/{vshlq_u8.c => vshlq_n_u8.c} | 8 +- .../mve/intrinsics/{vshlq_s16.c => vshlq_r_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vshlq_r_s32.c} | 8 +- .../mve/intrinsics/{vshlq_s8.c => vshlq_r_s8.c} | 8 +- .../mve/intrinsics/{vshlq_u16.c => vshlq_r_u16.c} | 8 +- .../mve/intrinsics/{vshlq_u32.c => vshlq_r_u32.c} | 8 +- .../mve/intrinsics/{vshlq_u8.c => vshlq_r_u8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 22 + .../mve/intrinsics/{vclsq_s8.c => vsubq_n_s8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 22 + .../mve/intrinsics/{vshlq_s16.c => vsubq_s16.c} | 8 +- .../mve/intrinsics/{vshlq_s32.c => vsubq_s32.c} | 8 +- .../arm/mve/intrinsics/{vshlq_s8.c => vsubq_s8.c} | 8 +- .../mve/intrinsics/{vcmpneq_u16.c => vsubq_u16.c} | 12 +- .../mve/intrinsics/{vcmpneq_u32.c => vsubq_u32.c} | 12 +- .../mve/intrinsics/{vcmpneq_u8.c => vsubq_u8.c} | 12 +- 367 files changed, 9609 insertions(+), 1268 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vabdq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vabdq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vabdq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vabdq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vabdq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vabdq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vaddq_n_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u8.c => vaddq_n_u8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddlvq_p_s32.c => vaddvq_p_s32. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddlvq_p_u32.c => vaddvq_p_u32. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vandq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vandq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vandq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vandq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vandq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vandq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vbicq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vbicq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vbicq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vbicq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vbicq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vbicq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_f16.c => vbrsrq_n_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_f32.c => vbrsrq_n_s32.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_f16.c => vbrsrq_n_u16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_f32.c => vbrsrq_n_u32.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vcaddq_rot270_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vcaddq_rot270_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vcaddq_rot270_s8.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vcaddq_rot270_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vcaddq_rot270_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vcaddq_rot270_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vcaddq_rot90_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vcaddq_rot90_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vcaddq_rot90_s8.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vcaddq_rot90_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vcaddq_rot90_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vcaddq_rot90_u8. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpcsq_n_u8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vcmpcsq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vcmpcsq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vcmpcsq_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpeqq_n_s16.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpeqq_n_s32.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpeqq_n_s8.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpeqq_n_u16.c} (72%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpeqq_n_u32.c} (72%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpeqq_n_u8.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpeqq_s16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpeqq_s32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpeqq_s8.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vcmpeqq_u16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vcmpeqq_u32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vcmpeqq_u8.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgeq_n_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgeq_n_s32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgeq_n_s8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpgeq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpgeq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpgeq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgtq_n_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgtq_n_s32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpgtq_n_s8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpgtq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpgtq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpgtq_s8.c} (64%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmphiq_n_u8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vcmphiq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vcmphiq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vcmphiq_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpleq_n_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpleq_n_s32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpleq_n_s8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpleq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpleq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpleq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpltq_n_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpltq_n_s32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vcmpltq_n_s8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpltq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpltq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpltq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpneq_n_s16.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpneq_n_s32.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpneq_n_s8.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vcmpneq_n_u16.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vcmpneq_n_u32.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vcmpneq_n_u8.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => veorq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => veorq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => veorq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => veorq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => veorq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => veorq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vhaddq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vhaddq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vhaddq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vhaddq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vhaddq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vhaddq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vhcaddq_rot270_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vhcaddq_rot270_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vhcaddq_rot270_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vhcaddq_rot90_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vhcaddq_rot90_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vhcaddq_rot90_s8.c} (61%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vhsubq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vhsubq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vhsubq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vhsubq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vhsubq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vhsubq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vmaxaq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vmaxaq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vmaxaq_s8.c} (64%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vmaxq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vmaxq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vmaxq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmaxq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmaxq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmaxq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vminaq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vminaq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vminaq_s8.c} (64%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vminq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vminq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vminq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vminq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vminq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vminq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vmladavq_s16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vmladavq_s32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vmladavq_s8.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmladavq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmladavq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmladavq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vmladavxq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vmladavxq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vmladavxq_s8.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vmlsdavq_s16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vmlsdavq_s32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vmlsdavq_s8.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vmlsdavxq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vmlsdavxq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vmlsdavxq_s8.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vmulhq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vmulhq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vmulhq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmulhq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmulhq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmulhq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vmullbq_int_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vmullbq_int_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vmullbq_int_s8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmullbq_int_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmullbq_int_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmullbq_int_u8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s16.c => vmulltq_int_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s32.c => vmulltq_int_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_s8.c => vmulltq_int_s8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmulltq_int_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmulltq_int_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmulltq_int_u8.c} (57%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vmulq_n_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vmulq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vmulq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vmulq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vmulq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vmulq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vmulq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vornq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vornq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vornq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vornq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vornq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vornq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vorrq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vorrq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vorrq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vorrq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vorrq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vorrq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqaddq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqaddq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqaddq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vqaddq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vqaddq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vqaddq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqdmulhq_s16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqdmulhq_s32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqdmulhq_s8.c} (62%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqrdmulhq_s16.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqrdmulhq_s32.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqrdmulhq_s8.c} (62%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqrshlq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqrshlq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqrshlq_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vqrshlq_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vqrshlq_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vqrshlq_u8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vqshlq_n_s16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshrq_n_s32.c => vqshlq_n_s32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vqshlq_n_s8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_u16.c => vqshlq_n_u16.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u32.c => vqshlq_n_u32.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_u8.c => vqshlq_n_u8.c} (61%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqshlq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqshlq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqshlq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vqshlq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vqshlq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vqshlq_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vqshluq_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqnegq_s32.c => vqshluq_n_s32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vqshluq_n_s8.c} (55%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vqsubq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vqsubq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vqsubq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vqsubq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vqsubq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vqsubq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vrhaddq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vrhaddq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vrhaddq_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vrhaddq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vrhaddq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vrhaddq_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vrmulhq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vrmulhq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vrmulhq_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vrmulhq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vrmulhq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vrmulhq_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vrshlq_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vrshlq_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vrshlq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vrshlq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vrshlq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vrshlq_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vrshrq_n_s16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshrq_n_s32.c => vrshrq_n_s32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vrshrq_n_s8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_u16.c => vrshrq_n_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u32.c => vrshrq_n_u32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_u8.c => vrshrq_n_u8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vshlq_n_s16.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vshlq_n_s32.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vshlq_n_s8.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vshlq_n_u16.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vshlq_n_u32.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vshlq_n_u8.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vshlq_r_s16.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vshlq_r_s32.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vshlq_r_s8.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u16.c => vshlq_r_u16.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u32.c => vshlq_r_u32.c} (73%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_u8.c => vshlq_r_u8.c} (73%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_s8.c => vsubq_n_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s16.c => vsubq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s32.c => vsubq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_s8.c => vsubq_s8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u16.c => vsubq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u32.c => vsubq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_u8.c => vsubq_u8.c} (59%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[binutils-gdb] branch master updated (946ffddcae7 -> 98097623244)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 946ffddcae7 Automatic date update in version.in new 98097623244 Inherit sh_nbsd_nat_target from nbsd_nat_target The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 7 +++++++ gdb/sh-nbsd-nat.c | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (f166a8cdf48 -> d71dba7b611)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. new d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 47 ++++++ gcc/config/arm/arm-builtins.c | 18 +++ gcc/config/arm/arm_mve.h | 160 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 8 +- gcc/config/arm/mve.md | 56 +++++++- gcc/testsuite/ChangeLog | 19 +++ .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 22 +++ .../arm/mve/intrinsics/{vctp16q.c => vcmpneq_s8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 22 +++ 20 files changed, 596 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q.c => vcmpneq_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allmodconfig updated (39930d67fff -> 135744ce689)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allmodconfig in repository toolchain/ci/llvm-project. from 39930d67fff Add new website to release notes. adds 9e0bd5ec03c [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 135744ce689 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 ++++-- clang/lib/Parse/ParseDecl.cpp | 6 ++++++ clang/lib/Parse/ParseTemplate.cpp | 3 ++- clang/lib/Sema/SemaTemplate.cpp | 13 ++++++++----- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +++-- clang/test/SemaTemplate/instantiate-requires-expr.cpp | 13 +++++++++++++ clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp | 1 + 9 files changed, 39 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allmodconfig updated (ce7712c43 -> bf3d9bffd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards ce7712c43 0: update: llvm-linux: all new bf3d9bffd 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ce7712c43) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-build_llvm/console.log | 12658 ++++++++-------- 03-build_linux/console.log | 16608 +++++++++++---------- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 12 +- console.log | 29448 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 29440 insertions(+), 29464 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

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