On Thu, 17 Jan 2019 at 18:34, Mathieu Poirier mathieu.poirier@linaro.org wrote:
On Wed, Jan 09, 2019 at 10:54:40PM +0000, Mike Leach wrote:
Add in test device tree definitions for qcom DB410 platform, and ARM Juno platform.
Signed-off-by: Mike Leach mike.leach@linaro.org
arch/arm64/boot/dts/arm/juno-base.dtsi | 76 ++++++++++++++++ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 9 ++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 101 +++++++++++++++++++++- 3 files changed, 183 insertions(+), 3 deletions(-)
This needs to be split in two different patches, one for Juno and another one for MSM since they will be picked up by two different maintainers.
OK, will do.
Mike
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index ed774ee8f659..8c8037cac5bd 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -132,6 +132,15 @@ }; };
cti@20020000 { /* sys_cti_0 */
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x20020000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>;
@@ -220,6 +229,16 @@ }; };
cti@20110000 { /* sys_cti_1 */
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x20110000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
cpu_debug0: cpu-debug@22010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x22010000 0x0 0x1000>;
@@ -229,6 +248,15 @@ power-domains = <&scpi_devpd 0>; };
cti@22020000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x22020000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm0: etm@22040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x22040000 0 0x1000>;
@@ -289,6 +317,15 @@ power-domains = <&scpi_devpd 0>; };
cti@22120000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x22120000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm1: etm@22140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x22140000 0 0x1000>;
@@ -314,6 +351,16 @@ power-domains = <&scpi_devpd 0>; };
cti@23020000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x23020000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm2: etm@23040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23040000 0 0x1000>;
@@ -386,6 +433,15 @@ power-domains = <&scpi_devpd 0>; };
cti@23120000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x23120000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm3: etm@23140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23140000 0 0x1000>;
@@ -411,6 +467,16 @@ power-domains = <&scpi_devpd 0>; };
cti@23220000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x23220000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm4: etm@23240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23240000 0 0x1000>;
@@ -436,6 +502,16 @@ power-domains = <&scpi_devpd 0>; };
cti@23320000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x23320000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm5: etm@23340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x23340000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index cf285152deab..bb62134f612a 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -82,4 +82,13 @@
}; };
cti@20160000 { /* sys_cti_2 */
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x20160000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a1..169060609e00 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -18,6 +18,9 @@ #include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8916";
compatible = "qcom,msm8916";
interrupt-parent = <&intc>; #address-cells = <2>;
@@ -1150,7 +1153,6 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk";
out-ports { #address-cells = <1>; #size-cells = <0>;
@@ -1296,7 +1298,7 @@ cpu = <&CPU3>; };
etm@85c000 {
etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>;
@@ -1314,7 +1316,7 @@ }; };
etm@85d000 {
etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>;
@@ -1368,6 +1370,99 @@ }; };
/* System CTIs */
/* CTI 0 - TMC connections */
cti@810000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x810000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
};
/* CTI 1 - TPIU connections */
cti@811000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x811000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
};
/* CTIs 2-11 - no information - not instantiated */
/* Core CTIs; CTIs 12-15 */
/* CTI - CPU-0 */
cti@858000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x858000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
trig-conns@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
arm,trig-in-sigs = <0 1 2 3>;
arm,trig-out-sigs = <4 5 6 7>;
arm,cs-dev-assoc = <&etm0>;
};
trig-conns@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
cpu = <&CPU0>;
arm,trig-out-sigs=<0 1 2 3>;
arm,trig-in-sigs=<4 5 6 7>;
};
};
/* CTI - CPU-1 */
cti@859000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x859000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
arm,cti-v8-arch;
cpu = <&CPU1>;
arm,cs-dev-assoc = <&etm1>;
};
/* CTI - CPU-2 */
cti@85a000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x85a000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
arm,cti-ctm-id = <1>;
trig-conns@0 {
arm,trig-out-sigs=<0 1 2 3>;
arm,trig-in-sigs=<4 5 6 7>;
arm,trig-conn-name = "test_conn_name";
};
};
/* CTI - CPU-3 */
cti@85b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x85b000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
};
venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;
-- 2.19.1
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