CoreSight July 2022

coresight@lists.linaro.org

10 participants
16 discussions

[PATCH v3] coresight: etm4x: add CPU hotplug support for probing

by Tamas Zsoldos

etm4x devices cannot be successfully probed when their CPU is offline. For example, when booting with maxcpus=n, ETM probing will fail on CPUs >n, and the probing won't be reattempted once the CPUs come online. This will leave those CPUs unable to make use of ETM. This change adds a mechanism to delay the probing if the corresponding CPU is offline, and to try it again when the CPU comes online. Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> --- Changes since v2: * Fix tear down issue (thanks to Suzuki). --- .../coresight/coresight-etm4x-core.c | 153 +++++++++++++----- 1 file changed, 113 insertions(+), 40 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..71ab1d6e72dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,13 @@ static enum cpuhp_state hp_online; struct etm4_init_arg { unsigned int pid; - struct etmv4_drvdata *drvdata; + struct device *dev; struct csdev_access *csa; }; +static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); +static int etm4_probe_cpu(unsigned int cpu); + /* * Check if TRCSSPCICRn(i) is implemented for a given instance. * @@ -1071,7 +1074,7 @@ static void etm4_init_arch_data(void *info) struct csdev_access *csa; int i; - drvdata = init_arg->drvdata; + drvdata = dev_get_drvdata(init_arg->dev); csa = init_arg->csa; /* @@ -1514,7 +1517,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) static int etm4_online_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) coresight_enable(etmdrvdata[cpu]->csdev); @@ -1890,48 +1893,20 @@ static void etm4_pm_clear(void) } } -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) { int ret; struct coresight_platform_data *pdata = NULL; - struct etmv4_drvdata *drvdata; + struct device *dev = init_arg->dev; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct coresight_desc desc = { 0 }; - struct etm4_init_arg init_arg = { 0 }; u8 major, minor; char *type_name; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) - pm_save_enable = coresight_loses_context_with_cpu(dev) ? - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; - - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { - drvdata->save_state = devm_kmalloc(dev, - sizeof(struct etmv4_save_state), GFP_KERNEL); - if (!drvdata->save_state) - return -ENOMEM; - } - - drvdata->base = base; - - spin_lock_init(&drvdata->spinlock); - - drvdata->cpu = coresight_get_cpu(dev); - if (drvdata->cpu < 0) - return drvdata->cpu; - - init_arg.drvdata = drvdata; - init_arg.csa = &desc.access; - init_arg.pid = etm_pid; + return -EINVAL; - if (smp_call_function_single(drvdata->cpu, - etm4_init_arch_data, &init_arg, 1)) - dev_err(dev, "ETM arch init failed\n"); + desc.access = *init_arg->csa; if (!drvdata->arch) return -EINVAL; @@ -2002,6 +1977,68 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return 0; } +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +{ + struct etmv4_drvdata *drvdata; + struct csdev_access access = { 0 }; + struct etm4_init_arg init_arg = { 0 }; + struct etm4_init_arg *delayed; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) + pm_save_enable = coresight_loses_context_with_cpu(dev) ? + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; + + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { + drvdata->save_state = devm_kmalloc(dev, + sizeof(struct etmv4_save_state), GFP_KERNEL); + if (!drvdata->save_state) + return -ENOMEM; + } + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + + init_arg.dev = dev; + init_arg.csa = &access; + init_arg.pid = etm_pid; + + /* + * Serialize against CPUHP callbacks to avoid race condition + * between the smp call and saving the delayed probe. + */ + cpus_read_lock(); + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, &init_arg, 1)) { + /* The CPU was offline, try again once it comes online. */ + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); + if (!delayed) { + cpus_read_unlock(); + return -ENOMEM; + } + + *delayed = init_arg; + + per_cpu(delayed_probe, drvdata->cpu) = delayed; + + cpus_read_unlock(); + return 0; + } + cpus_read_unlock(); + + return etm4_add_coresight_dev(&init_arg); +} + static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -2040,6 +2077,35 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) return ret; } +static int etm4_probe_cpu(unsigned int cpu) +{ + int ret; + struct etm4_init_arg init_arg; + struct csdev_access access = { 0 }; + struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); + + if (!iap) + return 0; + + init_arg = *iap; + devm_kfree(init_arg.dev, iap); + *this_cpu_ptr(&delayed_probe) = NULL; + + ret = pm_runtime_resume_and_get(init_arg.dev); + if (ret < 0) { + dev_err(init_arg.dev, "Failed to get PM runtime!\n"); + return 0; + } + + init_arg.csa = &access; + etm4_init_arch_data(&init_arg); + + etm4_add_coresight_dev(&init_arg); + + pm_runtime_put(init_arg.dev); + return 0; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -2054,16 +2120,20 @@ static void clear_etmdrvdata(void *info) int cpu = *(int *)info; etmdrvdata[cpu] = NULL; + per_cpu(delayed_probe, cpu) = NULL; } static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) { - etm_perf_symlink(drvdata->csdev, false); + bool fully_registered; /* * Taking hotplug lock here to avoid racing between etm4_remove_dev() * and CPU hotplug call backs. */ cpus_read_lock(); + + fully_registered = (etmdrvdata[drvdata->cpu] == drvdata); + /* * The readers for etmdrvdata[] are CPU hotplug call backs * and PM notification call backs. Change etmdrvdata[i] on @@ -2071,12 +2141,15 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) * inside one call back function. */ if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) - etmdrvdata[drvdata->cpu] = NULL; + clear_etmdrvdata(&drvdata->cpu); cpus_read_unlock(); - cscfg_unregister_csdev(drvdata->csdev); - coresight_unregister(drvdata->csdev); + if (fully_registered) { + etm_perf_symlink(drvdata->csdev, false); + cscfg_unregister_csdev(drvdata->csdev); + coresight_unregister(drvdata->csdev); + } return 0; } -- 2.17.1

1 year, 5 months

[PATCH v2 00/13] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on hardware enable, and freed on hardware disable. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks backward compatibility for perf record and perf report. Because the method for generating the AUXTRACE_INFO meta data has changed, using an older perf record will result in metadata that does not match the trace IDs used in the recorded trace data. This mismatch will cause subsequent decode to fail. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are no longer present in the metadata. This will mean older versions of perf report cannot decode the file. Applies to coresight/next [c06475910b52] Tested on DB410c Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: trace-id: update CoreSight core to use Trace ID API coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove unused legacy source Trace ID ops coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +--- .../hwtracing/coresight/coresight-etm-perf.c | 17 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 85 +++--- .../coresight/coresight-etm3x-sysfs.c | 28 +- .../coresight/coresight-etm4x-core.c | 65 ++++- .../coresight/coresight-etm4x-sysfs.c | 32 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +--- .../hwtracing/coresight/coresight-trace-id.c | 263 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 65 +++++ include/linux/coresight-pmu.h | 31 ++- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 31 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 + tools/perf/util/cs-etm.c | 220 +++++++++++++-- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 784 insertions(+), 207 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

1 year, 8 months

[PATCH v5 00/14] A patch series improving data quality of perf test for CoreSight

by carsten.haitzler＠foss.arm.com

From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (Rasterman) (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 160 ++++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- tools/perf/Documentation/arm-coresight.txt | 5 + tools/perf/Makefile.perf | 18 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 24 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 29 files changed, 1105 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

1 year, 8 months

A patch series improving data quality of perf test for CoreSight

by carsten.haitzler＠foss.arm.com

This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com>

1 year, 8 months

[PATCH v12 0/9] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series: "[v2,00/13] coresight: Add new API to allocate trace source ID values" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220704081149.… Changes from V11: 1. Clear bits for atid before setting them and relese atid when tpda remove. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Mao Jinlong (9): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add coresight components arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 111 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++ MAINTAINERS | 2 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 671 ++++++++++++++++++ drivers/hwtracing/coresight/Kconfig | 23 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 208 ++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 + drivers/hwtracing/coresight/coresight-tpdm.c | 259 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 ++ include/linux/coresight.h | 1 + 13 files changed, 1510 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

1 year, 8 months

Re: [-next] Lockdep warnings

by Leo Yan

On Tue, Jul 26, 2022 at 01:50:06PM +0100, Mark Rutland wrote: > On Tue, Jul 26, 2022 at 01:40:40PM +0100, Mark Rutland wrote: > > [Adding Peter; I suspect this is due to the cpuidle rework] > > Looking again I see the cpuidle rework isn't in next, so evidently not... > > Sorry for the noise! I'd like to loop in Mike.L and CoreSight ML for CTI PM callbacks. Please see below a comment for CTI spinlock usage. > > I'll go give next a spin in a VM, but I suspect I might need real HW to see > > this due to the way PSCI idle states work. > > > > Mark. > > > > On Tue, Jul 26, 2022 at 11:41:34AM +0100, Sudeep Holla wrote: > > > I was seeing the below lockdep warnings on my arm64 Juno development > > > platform almost 2 weeks back with -next. I wanted to check for similar > > > reports before post and forgot. > > > > > > --->8 > > > > > > DEBUG_LOCKS_WARN_ON(lockdep_hardirqs_enabled()) > > > hardirqs last enabled at (46157): cpuidle_enter_state+0x174/0x2b4 > > > WARNING: CPU: 5 PID: 0 at kernel/locking/lockdep.c:5506 check_flags+0x90/0x1e8 > > > hardirqs last disabled at (46158): el1_interrupt+0x2c/0xc8 > > > Modules linked in: > > > softirqs last enabled at (46154): __do_softirq+0x2c0/0x388 > > > softirqs last disabled at (46139): __irq_exit_rcu+0x118/0x18c > > > CPU: 5 PID: 0 Comm: swapper/5 Not tainted 5.19.0-rc6-next-20220714 #9 > > > pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) > > > pc : check_flags+0x90/0x1e8 > > > lr : check_flags+0x90/0x1e8 > > > Call trace: > > > check_flags+0x90/0x1e8 > > > lock_is_held_type+0x80/0x164 > > > rcu_read_lock_sched_held+0x40/0x7c > > > trace_rcu_dyntick+0x5c/0x140 > > > ct_kernel_enter+0x78/0xd4 > > > ct_idle_exit+0x1c/0x44 > > > cpu_idle_poll+0x74/0xb8 > > > do_idle+0x90/0x2c4 > > > cpu_startup_entry+0x30/0x34 > > > secondary_start_kernel+0x130/0x144 > > > __secondary_switched+0xb0/0xb4 > > > irq event stamp: 64229 > > > hardirqs last enabled at (64229): cpu_idle_poll+0x40/0xb8 > > > hardirqs last disabled at (64228): do_idle+0xbc/0x2c4 > > > softirqs last enabled at (64190): __do_softirq+0x2c0/0x388 > > > softirqs last disabled at (64185): __irq_exit_rcu+0x118/0x18c > > > ---[ end trace 0000000000000000 ]--- > > > possible reason: unannotated irqs-off. > > > irq event stamp: 64229 > > > hardirqs last enabled at (64229): cpu_idle_poll+0x40/0xb8 > > > hardirqs last disabled at (64228): do_idle+0xbc/0x2c4 > > > softirqs last enabled at (64190): __do_softirq+0x2c0/0x388 > > > softirqs last disabled at (64185): __irq_exit_rcu+0x118/0x18c > > > > > > ---- > > > > > > However I don't see the above warning with the latest -next. When I tried > > > yesterday's -next now, I see a different warning. Not sure if they are > > > related. I haven't tried to bisect. > > > > > > --->8 > > > ============================= > > > [ BUG: Invalid wait context ] > > > 5.19.0-rc8-next-20220725 #38 Not tainted > > > ----------------------------- > > > swapper/0/0 is trying to lock: > > > (&drvdata->spinlock){....}-{3:3}, at: cti_cpu_pm_notify+0x54/0x114 > > > other info that might help us debug this: > > > context-{5:5} > > > 1 lock held by swapper/0/0: > > > #0: (cpu_pm_notifier.lock){....}-{2:2}, at: cpu_pm_enter+0x2c/0x80 > > > stack backtrace: > > > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.19.0-rc8-next-20220725-00004-g599e6691ed8c #38 > > > Call trace: > > > dump_backtrace+0xe8/0x108 > > > show_stack+0x18/0x4c > > > dump_stack_lvl+0x90/0xc8 > > > dump_stack+0x18/0x54 > > > __lock_acquire+0xa70/0x32d0 > > > lock_acquire+0x160/0x308 > > > _raw_spin_lock+0x60/0xa0 > > > cti_cpu_pm_notify+0x54/0x114 > > > raw_notifier_call_chain_robust+0x50/0xd4 > > > cpu_pm_enter+0x48/0x80 > > > psci_enter_idle_state+0x34/0x74 > > > cpuidle_enter_state+0x120/0x2a8 > > > cpuidle_enter+0x38/0x50 > > > do_idle+0x1e8/0x2b8 > > > cpu_startup_entry+0x24/0x28 > > > kernel_init+0x0/0x1a0 > > > start_kernel+0x0/0x470 > > > start_kernel+0x34c/0x470 > > > __primary_switched+0xbc/0xc4 If we look into for this callback, we can see the lock sequence is: cti_cpu_pm_notify() `> cpu_pm_notify_robust(): `> raw_spin_lock_irqsave(cpu_pm_notifier.lock, flag) -> a raw spinlock `> cti_cpu_pm_notify() `> spin_lock(&drvdata->spinlock) -> a normal spinlock A raw spinlock is not a sleepable lock, and normal spinlock can be a sleepable lock (e.g. it can be a mutex after enabled PREEMPT_RT). One solution is we can change to a raw spinlock in CTI driver, so this can dismiss the lockdep warning. Actually, I am a bit suspect if it's really necessary to use spinlock in CTI PM callbacks, the reason is in CPU's idle flow, it will run into idle thread context and disable the local IRQ, which means it likely has no race condition with thread context and interrupt handler, so we can remove the locking in PM callbacks. Mike, could you check for this? Thanks! Leo

1 year, 9 months

[PATCH v1 0/4] coresight: Reduce duplicated sysfs accessors

by James Clark

The intent of this change is to reduce the large number identical of functions created by macros for sysfs accessors. It's possible to re-use the same function but pass in the register to access as an argument. This reduces the size of the coresight modules folder by 244KB. The first two patches are refactors to simplify and remove some dead code, and the second two are the changes to use a shared function. Testing ======= No changes in any of the outputs: cat /sys/bus/coresight/devices/*/mgmt/* > before.txt cat /sys/bus/coresight/devices/*/mgmt/* > after.txt diff before.txt after.txt With the following modules loaded: ls /sys/bus/coresight/devices/ etm0 etm2 funnel0 funnel2 replicator0 tmc_etf0 tmc_etf2 tpiu0 etm1 etm3 funnel1 funnel3 stm0 tmc_etf1 tmc_etr0 James Clark (4): coresight: Remove unused function parameter coresight: Simplify sysfs accessors by using csdev_access abstraction coresight: Re-use same function for similar sysfs register accessors coresight: cti-sysfs: Re-use same functions for similar sysfs register accessors drivers/hwtracing/coresight/coresight-catu.c | 27 +-- drivers/hwtracing/coresight/coresight-core.c | 14 ++ .../hwtracing/coresight/coresight-cti-sysfs.c | 213 +++++++----------- drivers/hwtracing/coresight/coresight-etb10.c | 28 +-- .../coresight/coresight-etm3x-sysfs.c | 34 +-- drivers/hwtracing/coresight/coresight-priv.h | 48 ++-- .../coresight/coresight-replicator.c | 10 +- drivers/hwtracing/coresight/coresight-stm.c | 40 +--- .../hwtracing/coresight/coresight-tmc-core.c | 48 ++-- include/linux/coresight.h | 18 ++ 10 files changed, 196 insertions(+), 284 deletions(-) -- 2.28.0

1 year, 9 months

Re: [PATCH] coresight: trbe: fix Kconfig "its" grammar

by Mathieu Poirier

Hi Randy - I'll pick this up for the next cycle. Thanks, Mathieu On Thu, 14 Jul 2022 at 19:59, Randy Dunlap <rdunlap(a)infradead.org> wrote: > > Use the possessive "its" instead of the contraction "it's" > where appropriate. > > Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> > Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-arm-kernel(a)lists.infradead.org > --- > drivers/hwtracing/coresight/Kconfig | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -193,10 +193,10 @@ config CORESIGHT_TRBE > depends on ARM64 && CORESIGHT_SOURCE_ETM4X > help > This driver provides support for percpu Trace Buffer Extension (TRBE). > - TRBE always needs to be used along with it's corresponding percpu ETE > + TRBE always needs to be used along with its corresponding percpu ETE > component. ETE generates trace data which is then captured with TRBE. > Unlike traditional sink devices, TRBE is a CPU feature accessible via > - system registers. But it's explicit dependency with trace unit (ETE) > + system registers. But its explicit dependency with trace unit (ETE) > requires it to be plugged in as a coresight sink device. > > To compile this driver as a module, choose M here: the module will be

1 year, 9 months

[GIT PULL] CoreSight changes for v5.20

by Suzuki K Poulose

Hi Greg, Please find the CoreSight updates for v5.20 below. Kindly consider pulling. Thanks Suzuki The following changes since commit a111daf0c53ae91e71fd2bfe7497862d14132e3e: Linux 5.19-rc3 (2022-06-19 15:06:47 -0500) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.20 for you to fetch changes up to 4d45bc82df667ad9e9cb8361830e54fc1264e993: coresight: etm4x: avoid build failure with unrolled loops (2022-07-11 09:22:35 +0100) ---------------------------------------------------------------- CoreSight self-hosted tracing changes for v5.20. - Fixes LOCKDEP warnings on module unload with configfs - Conversion of DT bindings to DT schema - Branch broadcast support for perf cs_etm - Etm4x driver fixes for build failures with Clang and unrolled loops Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Bagas Sanjaya (1): Documentation: coresight: Escape coresight bindings file wildcard James Clark (4): coresight: Add config flag to enable branch broadcast Documentation: coresight: Turn numbered subsections into real subsections Documentation: coresight: Link config options to existing documentation Documentation: coresight: Expand branch broadcast documentation Mike Leach (2): coresight: configfs: Fix unload of configurations on module exit coresight: syscfg: Update load and unload operations Nick Desaulniers (1): coresight: etm4x: avoid build failure with unrolled loops Rob Herring (3): dt-bindings: arm: Rename Coresight filenames to match compatible dt-bindings: arm: Convert CoreSight bindings to DT schema dt-bindings: arm: Convert CoreSight CPU debug to DT schema Suzuki K Poulose (1): coresight: Clear the connection field properly .../bindings/arm/arm,coresight-catu.yaml | 101 ++++++ .../bindings/arm/arm,coresight-cpu-debug.yaml | 81 +++++ .../{coresight-cti.yaml => arm,coresight-cti.yaml} | 5 +- .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 126 +++++++ .../arm/arm,coresight-dynamic-replicator.yaml | 126 +++++++ .../bindings/arm/arm,coresight-etb10.yaml | 92 +++++ .../devicetree/bindings/arm/arm,coresight-etm.yaml | 156 ++++++++ .../bindings/arm/arm,coresight-static-funnel.yaml | 90 +++++ .../arm/arm,coresight-static-replicator.yaml | 91 +++++ .../devicetree/bindings/arm/arm,coresight-stm.yaml | 101 ++++++ .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 131 +++++++ .../bindings/arm/arm,coresight-tpiu.yaml | 91 +++++ ...{ete.yaml => arm,embedded-trace-extension.yaml} | 3 +- .../{trbe.yaml => arm,trace-buffer-extension.yaml} | 2 +- .../bindings/arm/coresight-cpu-debug.txt | 49 --- .../devicetree/bindings/arm/coresight.txt | 402 --------------------- .../trace/coresight/coresight-etm4x-reference.rst | 17 +- Documentation/trace/coresight/coresight.rst | 58 ++- MAINTAINERS | 8 +- drivers/hwtracing/coresight/coresight-config.h | 2 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-etm-perf.c | 2 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 + drivers/hwtracing/coresight/coresight-etm4x.h | 3 +- drivers/hwtracing/coresight/coresight-syscfg.c | 299 ++++++++++++--- drivers/hwtracing/coresight/coresight-syscfg.h | 13 + include/linux/coresight-pmu.h | 2 + 27 files changed, 1542 insertions(+), 524 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml rename Documentation/devicetree/bindings/arm/{coresight-cti.yaml => arm,coresight-cti.yaml} (98%) create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml rename Documentation/devicetree/bindings/arm/{ete.yaml => arm,embedded-trace-extension.yaml} (95%) rename Documentation/devicetree/bindings/arm/{trbe.yaml => arm,trace-buffer-extension.yaml} (94%) delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

1 year, 9 months

[PATCH v2] coresight: etm4x: add CPU hotplug support for probing

by Tamas Zsoldos

etm4x devices cannot be successfully probed when their CPU is offline. For example, when booting with maxcpus=n, ETM probing will fail on CPUs >n, and the probing won't be reattempted once the CPUs come online. This will leave those CPUs unable to make use of ETM. This change adds a mechanism to delay the probing if the corresponding CPU is offline, and to try it again when the CPU comes online. Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> --- Changes from v1 (all suggested by Suzuki): 1. Expanded commit message. 2. The delayed probe now uses etm4_init_arg. 3. Reuses etm4_online_cpu() instead of installing own cpuhp callback. 4. Changed guard condition in etm4_remove_dev(). --- .../coresight/coresight-etm4x-core.c | 153 +++++++++++++----- 1 file changed, 113 insertions(+), 40 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..c39d9055b22c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,13 @@ static enum cpuhp_state hp_online; struct etm4_init_arg { unsigned int pid; - struct etmv4_drvdata *drvdata; + struct device *dev; struct csdev_access *csa; }; +static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); +static int etm4_probe_cpu(unsigned int cpu); + /* * Check if TRCSSPCICRn(i) is implemented for a given instance. * @@ -1071,7 +1074,7 @@ static void etm4_init_arch_data(void *info) struct csdev_access *csa; int i; - drvdata = init_arg->drvdata; + drvdata = dev_get_drvdata(init_arg->dev); csa = init_arg->csa; /* @@ -1514,7 +1517,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) static int etm4_online_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) coresight_enable(etmdrvdata[cpu]->csdev); @@ -1890,48 +1893,20 @@ static void etm4_pm_clear(void) } } -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) { int ret; struct coresight_platform_data *pdata = NULL; - struct etmv4_drvdata *drvdata; + struct device *dev = init_arg->dev; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct coresight_desc desc = { 0 }; - struct etm4_init_arg init_arg = { 0 }; u8 major, minor; char *type_name; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) - pm_save_enable = coresight_loses_context_with_cpu(dev) ? - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; - - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { - drvdata->save_state = devm_kmalloc(dev, - sizeof(struct etmv4_save_state), GFP_KERNEL); - if (!drvdata->save_state) - return -ENOMEM; - } - - drvdata->base = base; - - spin_lock_init(&drvdata->spinlock); - - drvdata->cpu = coresight_get_cpu(dev); - if (drvdata->cpu < 0) - return drvdata->cpu; - - init_arg.drvdata = drvdata; - init_arg.csa = &desc.access; - init_arg.pid = etm_pid; + return -EINVAL; - if (smp_call_function_single(drvdata->cpu, - etm4_init_arch_data, &init_arg, 1)) - dev_err(dev, "ETM arch init failed\n"); + desc.access = *init_arg->csa; if (!drvdata->arch) return -EINVAL; @@ -2002,6 +1977,68 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return 0; } +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +{ + struct etmv4_drvdata *drvdata; + struct csdev_access access = { 0 }; + struct etm4_init_arg init_arg = { 0 }; + struct etm4_init_arg *delayed; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) + pm_save_enable = coresight_loses_context_with_cpu(dev) ? + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; + + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { + drvdata->save_state = devm_kmalloc(dev, + sizeof(struct etmv4_save_state), GFP_KERNEL); + if (!drvdata->save_state) + return -ENOMEM; + } + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + + init_arg.dev = dev; + init_arg.csa = &access; + init_arg.pid = etm_pid; + + /* + * Serialize against CPUHP callbacks to avoid race condition + * between the smp call and saving the delayed probe. + */ + cpus_read_lock(); + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, &init_arg, 1)) { + /* The CPU was offline, try again once it comes online. */ + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); + if (!delayed) { + cpus_read_unlock(); + return -ENOMEM; + } + + *delayed = init_arg; + + per_cpu(delayed_probe, drvdata->cpu) = delayed; + + cpus_read_unlock(); + return 0; + } + cpus_read_unlock(); + + return etm4_add_coresight_dev(&init_arg); +} + static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -2040,6 +2077,35 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) return ret; } +static int etm4_probe_cpu(unsigned int cpu) +{ + int ret; + struct etm4_init_arg init_arg; + struct csdev_access access = { 0 }; + struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); + + if (!iap) + return 0; + + init_arg = *iap; + devm_kfree(init_arg.dev, iap); + *this_cpu_ptr(&delayed_probe) = NULL; + + ret = pm_runtime_resume_and_get(init_arg.dev); + if (ret < 0) { + dev_err(init_arg.dev, "Failed to get PM runtime!\n"); + return 0; + } + + init_arg.csa = &access; + etm4_init_arch_data(&init_arg); + + etm4_add_coresight_dev(&init_arg); + + pm_runtime_put(init_arg.dev); + return 0; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -2054,16 +2120,20 @@ static void clear_etmdrvdata(void *info) int cpu = *(int *)info; etmdrvdata[cpu] = NULL; + per_cpu(delayed_probe, cpu) = NULL; } static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) { - etm_perf_symlink(drvdata->csdev, false); + bool had_delayed_probe; /* * Taking hotplug lock here to avoid racing between etm4_remove_dev() * and CPU hotplug call backs. */ cpus_read_lock(); + + had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu); + /* * The readers for etmdrvdata[] are CPU hotplug call backs * and PM notification call backs. Change etmdrvdata[i] on @@ -2071,12 +2141,15 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) * inside one call back function. */ if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) - etmdrvdata[drvdata->cpu] = NULL; + clear_etmdrvdata(&drvdata->cpu); cpus_read_unlock(); - cscfg_unregister_csdev(drvdata->csdev); - coresight_unregister(drvdata->csdev); + if (!had_delayed_probe) { + etm_perf_symlink(drvdata->csdev, false); + cscfg_unregister_csdev(drvdata->csdev); + coresight_unregister(drvdata->csdev); + } return 0; } -- 2.17.1

1 year, 9 months

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight July 2022