CoreSight August 2021

coresight@lists.linaro.org

11 participants
27 discussions

[PATCH v5 0/9] perf: Refine barriers for AUX ring buffer

by Leo Yan

This patch series is to refine the memory barriers for AUX ring buffer. Patches 01 ~ 04 to address the barriers usage in the kernel. The first patch is to make clear comment for how to use the barriers between the data store and aux_head store, this asks the driver to make sure the data is visible. Patches 02 ~ 04 is to refine the drivers for barriers after the data store. Patch 05 is to use WRITE_ONCE() for updating aux_tail. Patches 06 ~ 09 is to drop the legacy __sync functions, and polish for duplicate code and cleanup the build and feature test after SYNC_COMPARE_AND_SWAP is not used. For easier review and more clear patch organization, comparing against to the previous patch series, the patches for support compat mode for AUX trace have been left out and will be sent out as a separate patch set. This patch set have been tested on Arm64 Juno platform. Changes from v4: - Refined comment for CoreSight ETR/ETF drivers (Suzuki/Peter); - Changed to use compiler barrier for BTS (mentioned by Peter, but have not received response from Intel developer); - Refined the coding style for patch 07 (Adrian). Changes from v3: - Removed the inapprocate paragraph in the commit log for patch "perf auxtrace: Drop legacy __sync functions" (Adrian); - Added new patch to remove feature-sync-compare-and-swap test (Adrian); - Th patch for "perf auxtrace: Use WRITE_ONCE() for updating aux_tail", is a standlone and simple change, so moved it ahead in the patch set for better ordering; - Minor improvement for commit logs in the last two patches. Changes from v2: - Removed auxtrace_mmap__read_snapshot_head(), which has the duplicated code with auxtrace_mmap__read_head(); - Cleanuped the build for HAVE_SYNC_COMPARE_AND_SWAP_SUPPORT (Adrian); - Added global variable "kernel_is_64_bit" (Adrian); - Added compat variants compat_auxtrace_mmap__{read_head|write_tail} (Adrian). Leo Yan (9): perf/ring_buffer: Add comment for barriers on AUX ring buffer coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering perf/x86: Add compiler barrier after updating BTS perf auxtrace: Use WRITE_ONCE() for updating aux_tail perf auxtrace: Drop legacy __sync functions perf auxtrace: Remove auxtrace_mmap__read_snapshot_head() perf: Cleanup for HAVE_SYNC_COMPARE_AND_SWAP_SUPPORT tools: Remove feature-sync-compare-and-swap feature detection arch/x86/events/intel/bts.c | 6 ++++ .../hwtracing/coresight/coresight-tmc-etf.c | 5 +++ .../hwtracing/coresight/coresight-tmc-etr.c | 8 +++++ kernel/events/ring_buffer.c | 9 ++++++ tools/build/Makefile.feature | 1 - tools/build/feature/Makefile | 4 --- tools/build/feature/test-all.c | 4 --- .../feature/test-sync-compare-and-swap.c | 15 --------- tools/perf/Makefile.config | 4 --- tools/perf/util/auxtrace.c | 18 +++-------- tools/perf/util/auxtrace.h | 31 +------------------ 11 files changed, 34 insertions(+), 71 deletions(-) delete mode 100644 tools/build/feature/test-sync-compare-and-swap.c -- 2.25.1

2 years, 7 months

[PATCH 0/2] coresight: ultrasoc: Add support for System Memory Buffer device

by Qi Liu

This patchset add support for SMB(System Memory Buffer) device, SMB obtains CPU instructions from Coresight ETM device and stores these messages in system memory. SMB is developed by Ultrasoc technology, which is acquired by Siemens, and we still use "Ultrasoc" to name document and driver. Change since RFC: - Move ultrasoc driver to drivers/hwtracing/coresight. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): Documentation: tracing: Documentation for ultrasoc SMB drivers coresight: ultrasoc: Add System Memory Buffer driver .../trace/coresight/ultrasoc-trace.rst | 193 +++++ MAINTAINERS | 7 + drivers/hwtracing/coresight/Kconfig | 3 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/ultrasoc/Kconfig | 12 + drivers/hwtracing/coresight/ultrasoc/Makefile | 6 + .../coresight/ultrasoc/ultrasoc-smb.c | 722 ++++++++++++++++++ .../coresight/ultrasoc/ultrasoc-smb.h | 142 ++++ 8 files changed, 1087 insertions(+) create mode 100644 Documentation/trace/coresight/ultrasoc-trace.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc/Kconfig create mode 100644 drivers/hwtracing/coresight/ultrasoc/Makefile create mode 100644 drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.h -- 2.17.1

2 years, 7 months

[PATCH 00/10] arm64: Self-hosted trace related erratum workarouds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #2119858 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 The series applies on the self-hosted/trbe fixes posted here [0]. A tree containing both the series is available here [1]. [0] https://lkml.kernel.org/r/20210723124456.3828769-1-suzuki.poulose@arm.com [1] git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v1 Suzuki K Poulose (10): coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: Add erratum detection for TRBE overwrite in FILL mode coresight: trbe: Workaround TRBE errat overwrite in FILL mode arm64: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures Documentation/arm64/silicon-errata.rst | 8 + arch/arm64/Kconfig | 70 ++++++ arch/arm64/include/asm/barrier.h | 17 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 44 ++++ arch/arm64/tools/cpucaps | 2 + drivers/hwtracing/coresight/coresight-trbe.c | 227 ++++++++++++++++--- 7 files changed, 341 insertions(+), 31 deletions(-) -- 2.24.1

2 years, 7 months

[PATCH v2] coresight: syscfg: fix compiler warnings

by Jian Cai

This fixes warnings with -Wimplicit-function-declaration, e.g. drivers/hwtracing/coresight/coresight-syscfg.c:455:15: error: implicit declaration of function 'kzalloc' [-Werror, -Wimplicit-function-declaration] csdev_item = kzalloc(sizeof(struct cscfg_registered_csdev), GFP_KERNEL); Fixes: 85e2414c518a ("coresight: syscfg: Initial coresight system configuration") Reviewed-by: Guenter Roeck <linux(a)roeck-us.net> Signed-off-by: Jian Cai <jiancai(a)google.com> --- Changes v1 -> v2: Format the commit message and add Fixes and Reviewed-by tag. drivers/hwtracing/coresight/coresight-syscfg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index fc0760f55c53..43054568430f 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -5,6 +5,7 @@ */ #include <linux/platform_device.h> +#include <linux/slab.h> #include "coresight-config.h" #include "coresight-etm-perf.h" -- 2.33.0.259.gc128427fd7-goog

2 years, 7 months

[PATCH v2 0/9] Support ETE decoding

by James Clark

Changes since v1: * Re-implement with a new magic number instead of piggybacking on ETMv4 * Improve comments and function name around cs_etm_decoder__get_etmv4_arch_ver() * Add a warning for unrecognised magic numbers * Split typo fix into new commit * Add Leo's reviewed-by tags * Create a new struct for ETE config (cs_ete_trace_params) instead of re-using ETMv4 config Applies to perf/core f3c33cbd922 Also available at https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-ete-v2 James Clark (9): perf cs-etm: Refactor initialisation of decoder params. perf cs-etm: Initialise architecture based on TRCIDR1 perf cs-etm: Refactor out ETMv4 header saving perf cs-etm: Save TRCDEVARCH register perf cs-etm: Fix typo perf cs-etm: Update OpenCSD decoder for ETE perf cs-etm: Create ETE decoder perf cs-etm: Print the decoder name perf cs-etm: Show a warning for an unknown magic number tools/build/feature/test-libopencsd.c | 4 +- tools/perf/arch/arm/util/cs-etm.c | 97 ++++++++---- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 148 ++++++++---------- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 13 ++ tools/perf/util/cs-etm.c | 43 ++++- tools/perf/util/cs-etm.h | 10 ++ 6 files changed, 200 insertions(+), 115 deletions(-) -- 2.28.0

2 years, 7 months

[PATCH] tools: perf: Report collisions in AUX records

by Suzuki K Poulose

Just like the other flags in the AUX records, report a summary of the Collisions if there were any. Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Arnaldo Carvalho de Melo <acme(a)kernel.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: linux-perf-users(a)vger.kernel.org Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- tools/perf/util/events_stats.h | 1 + tools/perf/util/session.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/tools/perf/util/events_stats.h b/tools/perf/util/events_stats.h index 3480bafd414b..1b0006092265 100644 --- a/tools/perf/util/events_stats.h +++ b/tools/perf/util/events_stats.h @@ -30,6 +30,7 @@ struct events_stats { u64 total_lost_samples; u64 total_aux_lost; u64 total_aux_partial; + u64 total_aux_collision; u64 total_invalid_chains; u32 nr_events[PERF_RECORD_HEADER_MAX]; u32 nr_lost_warned; diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 51f727402912..59b6c3fe0d01 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1540,6 +1540,8 @@ static int machines__deliver_event(struct machines *machines, evlist->stats.total_aux_lost += 1; if (event->aux.flags & PERF_AUX_FLAG_PARTIAL) evlist->stats.total_aux_partial += 1; + if (event->aux.flags & PERF_AUX_FLAG_COLLISION) + evlist->stats.total_aux_collision += 1; } return tool->aux(tool, event, sample, machine); case PERF_RECORD_ITRACE_START: @@ -1895,6 +1897,13 @@ static void perf_session__warn_about_errors(const struct perf_session *session) ""); } + if (session->tool->aux == perf_event__process_aux && + stats->total_aux_collision != 0) { + ui__warning("AUX data detected collision %" PRIu64 " times out of %u!\n\n", + stats->total_aux_collision, + stats->nr_events[PERF_RECORD_AUX]); + } + if (stats->nr_unknown_events != 0) { ui__warning("Found %u unknown events!\n\n" "Is this an older tool processing a perf.data " -- 2.24.1

2 years, 7 months

Re: [PATCHv2 4/4] coresight: Add ETR-PERF polling.

by Mathieu Poirier

On Tue, Jul 13, 2021 at 02:15:32PM +0200, Daniel Kiss wrote: > ETR might fill up the buffer sooner than an event makes perf to trigger > the synchronisation especially in system wide trace. Polling runs > periodically to sync the ETR buffer. Period is configurable via sysfs, > disabled by default. > > Signed-off-by: Daniel Kiss <daniel.kiss(a)arm.com> > Signed-off-by: Branislav Rankov <Branislav.Rankov(a)arm.com> > Tested-by: Denis Nikitin <denik(a)chromium.org> > --- > .../testing/sysfs-bus-coresight-devices-tmc | 8 + > drivers/hwtracing/coresight/Kconfig | 12 + > drivers/hwtracing/coresight/Makefile | 1 + > .../hwtracing/coresight/coresight-etm-perf.c | 8 + > .../coresight/coresight-etr-perf-polling.c | 275 ++++++++++++++++++ > .../coresight/coresight-etr-perf-polling.h | 38 +++ > .../hwtracing/coresight/coresight-tmc-core.c | 4 + > .../hwtracing/coresight/coresight-tmc-etr.c | 13 + > 8 files changed, 359 insertions(+) > create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.c > create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.h > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > index 6aa527296c710..3b411e8a6f417 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > @@ -91,3 +91,11 @@ Contact: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS > mode. Writable only for TMC-ETR configurations. The value > should be aligned to the kernel pagesize. > + > +What: /sys/bus/coresight/devices/<memory_map>.tmc/polling/period > +Date: July 2021 > +KernelVersion: 5.14 > +Contact: Daniel Kiss <daniel.kiss(a)arm.com> > +Description: (RW) Time in milliseconds when the TMC-ETR is synced. > + Default value is 0, means the feature is disabled. > + Writable only for TMC-ETR configurations. > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index 84530fd80998c..4e91fb98849f4 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -44,6 +44,18 @@ config CORESIGHT_LINK_AND_SINK_TMC > To compile this driver as a module, choose M here: the > module will be called coresight-tmc. > > + > +config CORESIGHT_ETR_PERF_POLL > + bool "Coresight ETR Perf Polling" > + > + depends on CORESIGHT_LINK_AND_SINK_TMC > + help > + Enable the support for software periodic synchronization of the ETR buffer. > + ETR might fill up the buffer sooner than an event makes perf to trigger > + the synchronization especially in system wide trace. Polling runs > + periodically to sync the ETR buffer. Period is configurable via sysfs, > + disabled by default. > + > config CORESIGHT_CATU > tristate "Coresight Address Translation Unit (CATU) driver" > depends on CORESIGHT_LINK_AND_SINK_TMC > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index d60816509755c..6baac328eea87 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -5,6 +5,7 @@ > obj-$(CONFIG_CORESIGHT) += coresight.o > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ > coresight-sysfs.o > +coresight-$(CONFIG_CORESIGHT_ETR_PERF_POLL) += coresight-etr-perf-polling.o > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > coresight-tmc-etr.o > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index a3f4c07f5bf8b..3095840a567c4 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -19,6 +19,7 @@ > #include <linux/workqueue.h> > > #include "coresight-etm-perf.h" > +#include "coresight-etr-perf-polling.h" > #include "coresight-priv.h" > > static struct pmu etm_pmu; > @@ -438,6 +439,8 @@ static void etm_event_start(struct perf_event *event, int flags) > /* Tell the perf core the event is alive */ > event->hw.state = 0; > > + etr_perf_polling_event_start(event, event_data, handle); > + > /* Finally enable the tracer */ > if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) > goto fail_disable_path; > @@ -497,6 +500,8 @@ static void etm_event_stop(struct perf_event *event, int mode) > if (!sink) > return; > > + etr_perf_polling_event_stop(event, event_data); > + > /* stop tracer */ > source_ops(csdev)->disable(csdev, event); > > @@ -741,6 +746,8 @@ int __init etm_perf_init(void) > etm_pmu.addr_filters_validate = etm_addr_filters_validate; > etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; > > + etr_perf_polling_init(); The problem here is that a function specific to an ETR is inserted in code that should be generic. So if we want to do the same for ETB, ETF and any kind of sink that's out there, we'd have to duplicate code and it would quickly get messy. What is needed is a generic solution. Moreover what is proposed here is centered on sinks, while the entire coresight framework is centered on sources. The polling function, although specific to sinks, should emanate from and be driven by the generic code that handles sources. There should also be a single event responsible for doing the polling rather than all of them as it is the case in this patchset. In per-thread mode where a single thread is traced it isn't a problem. In CPU-wide scenarios the first event should do the polling. There will be a gap between the time that event stops and all the other events in the trace session stop but that is a limitation we will have to live with. That leaves us with per-thread sessions where child threads are spun off. You will have to look into how events are handle in that case. Suzuki has done work in that area and might remember a few things. There are other design problems with this set that I won't get into since it needs a refactoring anyway. Regards, Mathieu > + > ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); > if (ret == 0) > etm_perf_up = true; > @@ -750,5 +757,6 @@ int __init etm_perf_init(void) > > void __exit etm_perf_exit(void) > { > + etr_perf_polling_exit(); > perf_pmu_unregister(&etm_pmu); > } > diff --git a/drivers/hwtracing/coresight/coresight-etr-perf-polling.c b/drivers/hwtracing/coresight/coresight-etr-perf-polling.c > new file mode 100644 > index 0000000000000..87e6bc42a62de > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-etr-perf-polling.c > @@ -0,0 +1,275 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright(C) 2021 Arm Limited. All rights reserved. > + * Author: Daniel Kiss <daniel.kiss(a)arm.com> > + */ > + > +#include <linux/coresight.h> > +#include <linux/coresight-pmu.h> > +#include <linux/cpumask.h> > +#include <linux/device.h> > +#include <linux/init.h> > +#include <linux/list.h> > +#include <linux/percpu-defs.h> > +#include <linux/perf_event.h> > +#include <linux/slab.h> > +#include <linux/stringhash.h> > +#include <linux/types.h> > +#include <linux/workqueue.h> > + > +#include "coresight-etr-perf-polling.h" > +#include "coresight-priv.h" > +#include "coresight-tmc.h" > + > +struct polling_event_list { > + struct perf_event *perf_event; > + struct etm_event_data *etm_event_data; > + struct perf_output_handle *ctx_handle; > + void (*tmc_etr_reset_hw)(struct tmc_drvdata *data); > + struct list_head list; > +}; > + > +struct polling { > + int cpu; > + struct polling_event_list *polled_event; > + struct delayed_work delayed_work; > +}; > + > +static atomic_t period; > +static spinlock_t spinlock_re; > +static struct list_head registered_events; > + > +static DEFINE_PER_CPU(struct polling, polling); > + > +static ssize_t period_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + int temp; > + > + temp = atomic_read(&period); > + return sprintf(buf, "%i\n", temp); > +} > + > +static ssize_t period_store(struct device *dev, struct device_attribute *attr, > + const char *buf, size_t count) > +{ > + int temp = 0; > + > + if (!kstrtoint(buf, 10, &temp) && (temp >= 0)) > + atomic_set(&period, temp); > + return count; > +} > + > +static DEVICE_ATTR_RW(period); > + > +static struct attribute *coresight_tmc_polling_attrs[] = { > + &dev_attr_period.attr, > + NULL, > +}; > +const struct attribute_group coresight_tmc_polling_group = { > + .attrs = coresight_tmc_polling_attrs, > + .name = "polling", > +}; > +EXPORT_SYMBOL_GPL(coresight_tmc_polling_group); > + > +static inline void polling_sched_worker(struct polling *p) > +{ > + int tickrate = atomic_read(&period); > + > + if (tickrate > 0) > + schedule_delayed_work_on(p->cpu, &p->delayed_work, > + msecs_to_jiffies(tickrate)); > +} > + > +static inline bool is_etr_related(struct etm_event_data *etm_event_data, int cpu) > +{ > + struct list_head *path; > + struct coresight_device *sink; > + struct tmc_drvdata *drvdata; > + > + path = etm_event_cpu_path(etm_event_data, cpu); > + if (WARN_ON(!path)) > + return false; > + sink = coresight_get_sink(path); > + if (WARN_ON(!sink)) > + return false; > + drvdata = dev_get_drvdata(sink->dev.parent); > + if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) > + return false; > + return true; > +} > + > +/* > + * Adds the event to the polled events list. > + */ > +void etr_perf_polling_event_start(struct perf_event *event, > + struct etm_event_data *etm_event_data, > + struct perf_output_handle *ctx_handle) > +{ > + int cpu = smp_processor_id(); > + struct polling *p = per_cpu_ptr(&polling, cpu); > + struct polling_event_list *element, *tmp; > + > + if (!is_etr_related(etm_event_data, cpu)) > + return; > + > + spin_lock(&spinlock_re); > + list_for_each_entry_safe(element, tmp, &registered_events, list) { > + if (element->ctx_handle == ctx_handle) { > + element->perf_event = event; > + element->etm_event_data = etm_event_data; > + spin_unlock(&spinlock_re); > + p->polled_event = element; > + polling_sched_worker(p); > + return; > + } > + } > + spin_unlock(&spinlock_re); > +} > + > +/* > + * Removes the event from the to be polled events list. > + */ > +void etr_perf_polling_event_stop(struct perf_event *event, > + struct etm_event_data *etm_event_data) > +{ > + int cpu = smp_processor_id(); > + struct polling *p = per_cpu_ptr(&polling, cpu); > + > + if (!is_etr_related(etm_event_data, cpu)) > + return; > + > + if (p->polled_event) { > + struct polling_event_list *element = p->polled_event; > + > + if (element->perf_event == event) { > + p->polled_event = NULL; > + element->perf_event = NULL; > + element->etm_event_data = NULL; > + cancel_delayed_work(&p->delayed_work); > + return; > + } > + } > +} > + > +/* > + * The polling worker is a workqueue job which is periodically > + * woken up to update the perf aux buffer from the etr shrink. > + */ > +static void etr_perf_polling_worker(struct work_struct *work) > +{ > + unsigned long flags; > + struct list_head *path; > + struct coresight_device *sink; > + int size; > + int cpu = smp_processor_id(); > + struct polling *p = per_cpu_ptr(&polling, cpu); > + > + if (!atomic_read(&period)) > + return; > + > + if (!p->polled_event) > + return; > + /* > + * Scheduling would do the same from the perf hooks, > + * this should be done in one go. > + */ > + local_irq_save(flags); > + > + polling_sched_worker(p); > + > + path = etm_event_cpu_path(p->polled_event->etm_event_data, cpu); > + sink = coresight_get_sink(path); > + size = sink_ops(sink)->update_buffer( > + sink, p->polled_event->ctx_handle, > + p->polled_event->etm_event_data->snk_config); > + > + /* > + * Restart the trace. > + */ > + if (p->polled_event->tmc_etr_reset_hw) > + p->polled_event->tmc_etr_reset_hw(dev_get_drvdata(sink->dev.parent)); > + > + WARN_ON(size < 0); > + if (size > 0) { > + struct etm_event_data *new_event_data; > + > + perf_aux_output_end(p->polled_event->ctx_handle, size); > + new_event_data = perf_aux_output_begin( > + p->polled_event->ctx_handle, > + p->polled_event->perf_event); > + if (WARN_ON(new_event_data == NULL)) { > + local_irq_restore(flags); > + return; > + } > + > + p->polled_event->etm_event_data = new_event_data; > + WARN_ON(new_event_data->snk_config != > + p->polled_event->etm_event_data->snk_config); > + } > + > + local_irq_restore(flags); > +} > + > +void etr_perf_polling_handle_register(struct perf_output_handle *handle, > + void (*tmc_etr_reset_hw)(struct tmc_drvdata *drvdata)) > +{ > + struct polling_event_list *element; > + > + element = kmalloc(sizeof(*element), GFP_ATOMIC); > + if (WARN_ON(!element)) > + return; > + memset(element, 0, sizeof(*element)); > + element->ctx_handle = handle; > + element->tmc_etr_reset_hw = tmc_etr_reset_hw; > + spin_lock(&spinlock_re); > + list_add(&element->list, &registered_events); > + spin_unlock(&spinlock_re); > +} > +EXPORT_SYMBOL_GPL(etr_perf_polling_handle_register); > + > +void etr_perf_polling_handle_deregister(struct perf_output_handle *handle) > +{ > + struct polling_event_list *element, *tmp; > + > + spin_lock(&spinlock_re); > + list_for_each_entry_safe(element, tmp, &registered_events, list) { > + if (element->ctx_handle == handle) { > + list_del(&element->list); > + spin_unlock(&spinlock_re); > + kfree(element); > + return; > + } > + } > + spin_unlock(&spinlock_re); > +} > +EXPORT_SYMBOL_GPL(etr_perf_polling_handle_deregister); > + > +void etr_perf_polling_init(void) > +{ > + int cpu; > + > + spin_lock_init(&spinlock_re); > + INIT_LIST_HEAD(&registered_events); > + atomic_set(&period, 0); > + for_each_possible_cpu(cpu) { > + struct polling *p = per_cpu_ptr(&polling, cpu); > + > + p->cpu = cpu; > + p->polled_event = NULL; > + INIT_DELAYED_WORK(&p->delayed_work, etr_perf_polling_worker); > + } > +} > + > +void etr_perf_polling_exit(void) > +{ > + int cpu; > + > + for_each_possible_cpu(cpu) { > + struct polling *p = per_cpu_ptr(&polling, cpu); > + > + cancel_delayed_work_sync(&p->delayed_work); > + WARN_ON(p->polled_event); > + } > + WARN_ON(!list_empty(&registered_events)); > +} > diff --git a/drivers/hwtracing/coresight/coresight-etr-perf-polling.h b/drivers/hwtracing/coresight/coresight-etr-perf-polling.h > new file mode 100644 > index 0000000000000..d47b4424594e6 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-etr-perf-polling.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright(C) 2021 Arm Limited. All rights reserved. > + * Author: Daniel Kiss <daniel.kiss(a)arm.com> > + */ > + > +#ifndef _CORESIGHT_ETM_PERF_POLLING_H > +#define _CORESIGHT_ETM_PERF_POLLING_H > + > +#include <linux/coresight.h> > +#include <linux/perf_event.h> > +#include "coresight-etm-perf.h" > +#include "coresight-tmc.h" > + > +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL > +void etr_perf_polling_init(void); > +void etr_perf_polling_exit(void); > +void etr_perf_polling_handle_register(struct perf_output_handle *handle, > + void (*tmc_etr_reset_hw)(struct tmc_drvdata *drvdata)); > +void etr_perf_polling_handle_deregister(struct perf_output_handle *handle); > +void etr_perf_polling_event_start(struct perf_event *event, > + struct etm_event_data *etm_event_data, > + struct perf_output_handle *ctx_handle); > +void etr_perf_polling_event_stop(struct perf_event *event, > + struct etm_event_data *etm_event_data); > + > +extern const struct attribute_group coresight_tmc_polling_group; > + > +#else /* !CONFIG_CORESIGHT_ETR_PERF_POLL */ > +#define etr_perf_polling_init() > +#define etr_perf_polling_exit() > +#define etr_perf_polling_handle_register(...) > +#define etr_perf_polling_handle_deregister(...) > +#define etr_perf_polling_event_start(...) > +#define etr_perf_polling_event_stop(...) > +#endif > + > +#endif > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 74c6323d4d6ab..dbcdba162bd38 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -26,6 +26,7 @@ > > #include "coresight-priv.h" > #include "coresight-tmc.h" > +#include "coresight-etr-perf-polling.h" > > DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > @@ -365,6 +366,9 @@ static const struct attribute_group coresight_tmc_mgmt_group = { > static const struct attribute_group *coresight_tmc_groups[] = { > &coresight_tmc_group, > &coresight_tmc_mgmt_group, > +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL > + &coresight_tmc_polling_group, > +#endif > NULL, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 55c9b5fd9f832..67cd4bdcda71b 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -16,6 +16,7 @@ > #include <linux/vmalloc.h> > #include "coresight-catu.h" > #include "coresight-etm-perf.h" > +#include "coresight-etr-perf-polling.h" > #include "coresight-priv.h" > #include "coresight-tmc.h" > > @@ -1137,6 +1138,16 @@ void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) > drvdata->etr_buf = NULL; > } > > +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL > + > +static void tmc_etr_reset_hw(struct tmc_drvdata *drvdata) > +{ > + __tmc_etr_disable_hw(drvdata); > + __tmc_etr_enable_hw(drvdata); > +} > + > +#endif > + > static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) > { > int ret = 0; > @@ -1620,6 +1631,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) > drvdata->mode = CS_MODE_PERF; > drvdata->perf_buf = etr_perf->etr_buf; > drvdata->perf_handle = handle; > + etr_perf_polling_handle_register(handle, tmc_etr_reset_hw); > atomic_inc(csdev->refcnt); > } > > @@ -1667,6 +1679,7 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) > drvdata->mode = CS_MODE_DISABLED; > /* Reset perf specific data */ > drvdata->perf_buf = NULL; > + etr_perf_polling_handle_deregister(drvdata->perf_handle); > drvdata->perf_handle = NULL; > > spin_unlock_irqrestore(&drvdata->spinlock, flags); > -- > 2.25.1 >

2 years, 7 months

Re: [PATCH 0/2] Add Coresight support for RB5 board

by Mathieu Poirier

Hi Tao, On Thu, 19 Aug 2021 at 03:29, Tao Zhang <quic_taozha(a)quicinc.com> wrote: > > This series adds Coresight support for SM8250 Soc on RB5 board. > It is composed of two elements. > a) Add ETM PID for Kryo-5XX. > b) Add coresight support to DTS for RB5. > > This series applies to coresight/next > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git > > Tao Zhang (2): > coresight: etm4x: Add ETM PID for Kryo-5XX > arm64: dts: qcom: sm8250: Add Coresight support > > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 442 +++++++++++++++++- > .../coresight/coresight-etm4x-core.c | 1 + > 2 files changed, 439 insertions(+), 4 deletions(-) > I have added your work to my patchset queue. On the other hand I have a lot of patches to review these days and as such won't be able to look at it for 4 to 5 weeks. Thanks, Mathieu > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >

2 years, 7 months

Enabling support in coresight for Panic - Kdump

by Linu Cherian

Hi Leo, We are interested in adding support in Coresight driver to collect trace data at the time of kernel panic. Would like to know the current status of this patch series you posted some time back [1]. If no one is working on this, we would like to revive and resubmit this. Appreciate your guidance on this. Also please discard the earlier duplicate emails which i have send to you by mistake. Thanks. 1. https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1652258.html.

2 years, 7 months

[PATCH v2 0/2] perf: Support compat mode for AUX ring buffer

by Leo Yan

This patch set is to address the comments in the patch set v1 [1] and updates the patches. Changes from v1: - Added Adrian's review tag for patch 01; - Refined comment in patch 01 (James); - Added James' review and test tag for patch 02. [1] https://lore.kernel.org/patchwork/cover/1473936/ Leo Yan (2): perf auxtrace: Add compat_auxtrace_mmap__{read_head|write_tail} perf auxtrace arm: Support compat_auxtrace_mmap__{read_head|write_tail} tools/perf/arch/arm/util/auxtrace.c | 32 +++++++++++ tools/perf/util/auxtrace.c | 88 +++++++++++++++++++++++++++-- tools/perf/util/auxtrace.h | 22 +++++++- 3 files changed, 135 insertions(+), 7 deletions(-) -- 2.25.1

2 years, 7 months

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CoreSight August 2021