CoreSight September 2017

coresight@lists.linaro.org

13 participants
17 discussions

by marekzmyslowski

Hello Mathieu, Thank for the config file. It works. I was able to build the OpenCSD kernel (form the perf-opencsd-master branch) and install on the USB (I used the ArchLinuxARM-aarch64-latest.tar.gz). I also built the perf tool (make -C tools/perf). Everything is booting but the perf has some issues: [root@alarm home]# ./perf record -vvv -e cs_etm/(a)20070000.etr/u --per-thread uname map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir Problems setting modules path maps, continuing anyway... ------------------------------------------------------------ perf_event_attr: type 8 size 112 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 enable_on_exec 1 sample_id_all 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 4 ------------------------------------------------------------ perf_event_attr: type 1 size 112 config 0x9 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 mmap 1 comm 1 enable_on_exec 1 task 1 sample_id_all 1 mmap2 1 comm_exec 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 5 mmap size 528384B AUX area mmap length 4194304 perf event ring buffer mmapped per thread failed to mmap AUX area failed to mmap with 12 (Cannot allocate memory) I fixed the "map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir" issue by adding appropriate symbolic link but I still have an issue with the mmap. Any idea what can be wrong here (below limits that I have on my Juno)? [root@alarm ~]# ulimit -a core file size (blocks, -c) unlimited data seg size (kbytes, -d) unlimited scheduling priority (-e) 0 file size (blocks, -f) unlimited pending signals (-i) 31798 max locked memory (kbytes, -l) 64 max memory size (kbytes, -m) unlimited open files (-n) 1024 pipe size (512 bytes, -p) 8 POSIX message queues (bytes, -q) 819200 real-time priority (-r) 0 stack size (kbytes, -s) 8192 cpu time (seconds, -t) unlimited max user processes (-u) 31798 virtual memory (kbytes, -v) unlimited file locks (-x) unlimited [root@alarm ~]# Regards Marek W dniu 2017-08-18 16:54:42 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 18 August 2017 at 04:22, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mathieu, > > > > I've decided that currently I don't need Android. The Linux is enough. > > That is probably a better place to start. > > > However I have another issue. I've downloaded the perf-opencsd-master branch. I run the config with the ARCH=arm64 and CROSS_COMPLIE=aarch64-linux-gnu- and added support for Versatile board. Then I compiled kernel - everything was OK. Next I built the USB using the following instruction: > > https://archlinuxarm.org/platforms/armv8/arm/juno (it works fine. The linux boot on the Juno). > > Next I copied the Image file and juno.dtb into the USB but it doesn't boot. It hangs here: > > > > initrd: address 0x0 > > initrd: length 0x0 > > PEI 1132 ms > > DXE 1695 ms > > BDS 368934875444 ms > > BDS 368934873448 ms > > BDS 1535 ms > > Total Time = 368934871781 ms > > > > linux: address 0x80080000 > > linux: length 0x1150200 > > fdt: address 0x9FE00000 > > fdt: length 0x5F54 > > > > Any idea what I'm doing wrong? Any help will be appreciated (I'm so close to have Juno + CoreSight + perf :) ) > > I can't help you with booting the board itself. The best I can do is > advise to use u-boot instead of UEFI and give you my kernel .config > file (attached). For the rest there is plenty of documentation out > there. > > > > > Regards > > Marek > > > > W dniu 2017-08-16 23:08:04 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > >> Hello Marek, > >> > >> Please CC the CoreSight mailing list when asking questions as someone > >> else may also be able to answer. > >> > >> First and foremost I advise using the official CoreSight kernel found > >> on the openCSD site [1] rather than my personal branch [2] - you > >> never know what you'll get with the latter. > >> > >> That being said the CoreSight kernel on the openCSD site is not an > >> Android kernel - it is simply a mainline kernel supplemented with > >> patches that haven't made their way to mainline yet. You will have to > >> either add the android patches to the CoreSight kernel or the other > >> way around (CoreSight patches on android kernel). > >> > >> Android user space is also different and does not include the > >> perf-tools. You will have to add them manually along with the > >> dependencies they require. I haven't gone through that process and as > >> such can't advise more on that portion. > >> > >> Get back to me with your questions if the above isn't sufficient. > >> > >> Best regards, > >> Mathieu > >> > >> [1]. https://github.com/Linaro/OpenCSD/tree/perf-opencsd-master > >> [2]. https://git.linaro.org/people/mathieu.poirier/coresight.git/ > >> > >> On 16 August 2017 at 14:32, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hello Mathieu, > >> > > >> > I'm sorry for bothering but I think you may be person that can help me. I'm trying to install and run Android on Juno Board r0. I tested Android 17.05 from Linaro and it works. Now I'm trying to have a perf using Coresight but I'm little confused. Do I need to build Android from Linaro and the kernel from here https://git.linaro.org/people/mathieu.poirier/coresight.git/ or here https://github.com/Linaro/OpenCSD/tree/perf-opencsd-4.12. > >> > Any help with this will be appreciated :) > >> > > >> > Regards > >> > Marek Zmysłowski > >> > > > > > > >

5 years, 11 months

[PATCH v2 00/23] Add support for CoreSight trace decoding

by Tor Jeremiassen

Hi, This patchset adds support for user space decoding of CoreSight traces [1] of the ARM architecture. Kernel support for configuring CoreSight tracers and collect the hardware trace data in the auxtrace section of the perf.data file is already integrated [2]. The user space implementation mirrors to a large degree that of the Intel Processor Trace (PT) [3] implementation, except that the decoder library itself is separate from the perf tool sources, and is built and maintained as a separate open source project [4]. Instead, this patch set includes the necessary code and build settings to interfaces to the decoder library. This approach was chosen as the decoder library has uses outside the perf toolset and on non-linux platforms. The decoder library interface code in this patch set only supports ETMv4 trace decoding, though the library itself supports a broader range. Future patches will add support for more versions of the ARM ETM trace encoding. The trace decoder library used with this patch set is the most recent version with tag v0.7.3 This patch set, instead of being based on commits in my private branch, has been applied to a new copy of the perf-opencsd-master branch of [4] and pushed to [5] with the same perf-opencsd-master branch name. Changes since last revision: Given this is the second time it is sent out to the new audience on coresight(a)lists.linaro.org, I am resetting the version number to 2 to avoid confusion with previous mailings with a more restricted audience. Two additional commits have been added to the patches in this patch set to be fully compatible with the most recent version of the decoder library. The previous patch set assumed an older version. [1] https://lwn.net/Articles/626463 [2] https://github.com/torvalds/linux/tree/master/drivers/hwtracing/coresight [3] https://lwn.net/Articles/648154 [4] https://github.com/Linaro/OpenCSD [5] https://github.com/tor-jeremiassen/OpenCSD Tor Jeremiassen (23): perf tools: Add initial hooks for decoding coresight traces perf tools: Add processing of coresight metadata perf tools: Add coresight trace decoder library interface perf tools: Add data block processing function perf tools: Add channel context item to track packet sources perf tools: Add etmv4i packet printing capability perf tools: Add decoder new and free perf tools: Add trace packet print for dump_trace option perf tools: Add code to process the auxtrace perf event perf tools: Add function to read data from dsos perf tools: Add mapping from cpu to cs_etm_queue perf tools: Add functions to allocate and free queues perf tools: Add functions to setup and initialize queues perf tools: Add functions to allocate and free queues perf tools: Add function to get trace data from aux buffer perf tools: Add function to run the trace decoder and process samples perf tools: Add functions to process queues and run the trace decoder perf tools: Add perf event processing perf tools: Add processing of queues when events are flushed perf tools: Add synth_events and supporting functions perf tools: Add function to clear the decoder packet buffer perf tools: Add functions for full etmv4i packet decode MAINTAINERS: Adding entry for CoreSight trace decoding MAINTAINERS | 3 +- tools/perf/Makefile.config | 26 + tools/perf/util/Build | 6 + tools/perf/util/auxtrace.c | 2 + tools/perf/util/cs-etm-decoder/Build | 2 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 581 +++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 138 +++ tools/perf/util/cs-etm.c | 1180 +++++++++++++++++++++++ tools/perf/util/cs-etm.h | 50 + 9 files changed, 1987 insertions(+), 1 deletion(-) create mode 100644 tools/perf/util/cs-etm-decoder/Build create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.h create mode 100644 tools/perf/util/cs-etm.c -- 2.7.4

6 years, 4 months

Question for openCSD - open soruce Coresight Trace Decode

by 임영재

6 years, 6 months

New perf-opencsd repo on gitHub

by Mathieu Poirier

Good day all, As discussed in the meeting yesterday I have started a new gitHub repository [1] to host the perf-opencsd kernel. Right now it has all the same kernel branches as found on the openCSD repository. I have also added a small wiki that gives people a little bit of information on the repository itself. Note that the openCSD repository hasn't been modified yet and that *everything* in the perf-opencsd is currently considered experimental. I am sharing this early to give people a chance to comment on the structure, naming and whatever they want to see modified. Regards, Mathieu [1]. https://github.com/Linaro/perf-opencsd

6 years, 7 months

[PATCH 1/2] perf inject: correct recording of branch address and destination

by Sebastian Pop

ARM ETM traces contain packets of executed instructions. The addresses recorded in the trace correspond to the beginning and one instruction past the end of the block of executed instructions. In order to record the address and destination of executed branches, keep track of two packets: the jump occurs from the last executed instruction of the previous packet to the address of the first instruction in the current packet. Signed-off-by: Sebastian Pop <s.pop(a)samsung.com> Signed-off-by: Brian Rzycki <b.rzycki(a)samsung.com> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 ++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 91 +++++++++++++++++-------- 3 files changed, 75 insertions(+), 29 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index b4cbf4c..6164bfe 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -143,6 +143,18 @@ static int cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_buffer[et].sample_type = sample_type; decoder->packet_buffer[et].start_addr = elem->st_addr; decoder->packet_buffer[et].end_addr = elem->en_addr; + switch (elem->last_i_type) { + case OCSD_INSTR_BR: + case OCSD_INSTR_BR_INDIRECT: + decoder->packet_buffer[et].last_instruction_is_branch = true; + break; + case OCSD_INSTR_OTHER: + case OCSD_INSTR_ISB: + case OCSD_INSTR_DSB_DMB: + default: + decoder->packet_buffer[et].last_instruction_is_branch = false; + break; + } decoder->packet_buffer[et].exc = false; decoder->packet_buffer[et].exc_ret = false; decoder->packet_buffer[et].cpu = *((int*)inode->priv); diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index d15a288..4fd5a9b 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -49,6 +49,7 @@ struct cs_etm_packet { enum cs_etm_sample_type sample_type; uint64_t start_addr; uint64_t end_addr; + bool last_instruction_is_branch; bool exc; bool exc_ret; int cpu; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 8270203..c99b728 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -104,6 +104,10 @@ struct cs_etm_queue { * inserted. */ size_t last_branch_pos; + /* + * A pointer to the last and current decoded packets. + */ + struct cs_etm_packet *prev_packet, *packet; }; static int cs_etm__get_trace(struct cs_etm_buffer *buff, struct cs_etm_queue *etmq); @@ -226,6 +230,8 @@ static void cs_etm__free_queue(void *priv) zfree(&etmq->event_buf); zfree(&etmq->last_branch); zfree(&etmq->last_branch_rb); + zfree(&etmq->prev_packet); + zfree(&etmq->packet); zfree(&etmq->chain); free(etmq); } @@ -392,6 +398,7 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, if (etm->synth_opts.last_branch) { size_t sz = sizeof(struct branch_stack); + size_t szp = sizeof(struct cs_etm_packet); sz += etm->synth_opts.last_branch_sz * sizeof(struct branch_entry); @@ -401,6 +408,12 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, etmq->last_branch_rb = zalloc(sz); if (!etmq->last_branch_rb) goto out_free; + etmq->prev_packet = zalloc(szp); + if (!etmq->prev_packet) + goto out_free; + etmq->packet = zalloc(szp); + if (!etmq->packet) + goto out_free; } etmq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); @@ -451,6 +464,8 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, zfree(&etmq->event_buf); zfree(&etmq->last_branch); zfree(&etmq->last_branch_rb); + zfree(&etmq->prev_packet); + zfree(&etmq->packet); zfree(&etmq->chain); free(etmq); return NULL; @@ -594,8 +609,7 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq) etmq->last_branch_rb->nr = 0; } -static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, - struct cs_etm_packet *packet) +static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq) { struct branch_stack *bs = etmq->last_branch_rb; struct branch_entry *be; @@ -611,10 +625,16 @@ static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, etmq->last_branch_pos -= 1; - be = &bs->entries[etmq->last_branch_pos]; - be->from = packet->start_addr; - be->to = packet->end_addr; - /* No support for mispredict */ + be = &bs->entries[etmq->last_branch_pos]; + + /* + * The FROM address needs to be the instruction before the end of the + * packet at END_ADDR: substract from END_ADDR the size of the last + * instruction: 4 bytes. + */ + be->from = etmq->prev_packet->end_addr - 4; + be->to = etmq->packet->start_addr; + /* No support for mispredict. */ be->flags.mispred = 0; be->flags.predicted = 1; @@ -721,13 +741,13 @@ static struct cs_etm_cache_entry *cs_etm__cache_lookup(struct dso *dso, } #endif -static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, - struct cs_etm_packet *packet) +static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq) { int ret = 0; struct cs_etm_auxtrace *etm = etmq->etm; union perf_event *event = etmq->event_buf; struct perf_sample sample = {.ip = 0,}; + struct cs_etm_packet *packet = etmq->packet; uint64_t start_addr = packet->start_addr; uint64_t end_addr = packet->end_addr; @@ -941,17 +961,18 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, static int cs_etm__sample(struct cs_etm_queue *etmq, int *cpu) { - //const struct cs_etm_state *state = etmq->state; - struct cs_etm_packet packet; - //struct cs_etm_auxtrace *etm = etmq->etm; - int err; + struct cs_etm_auxtrace *etm = etmq->etm; + struct cs_etm_packet *tmp; + int err = cs_etm_decoder__get_packet(etmq->decoder, etmq->packet); - err = cs_etm_decoder__get_packet(etmq->decoder,&packet); - // if there is no sample, it returns err = -1, no real error + /* + * If there is no sample, it returns err = -1, no real error. + */ if (err) return err; - if (etmq->etm->synth_opts.last_branch) { - *cpu = packet.cpu; + + if (etm->synth_opts.last_branch) { + *cpu = etmq->packet->cpu; /* * FIXME: as the trace sampling does not work for now, (for @@ -961,17 +982,30 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, int *cpu) * should be rewritten as "if reached sampling period". */ if (etmq->last_branch_rb->nr == - etmq->etm->synth_opts.last_branch_sz) { - err = cs_etm__synth_instruction_sample(etmq, &packet); + etm->synth_opts.last_branch_sz) { + err = cs_etm__synth_instruction_sample(etmq); if (err) return err; } - cs_etm__update_last_branch_rb(etmq, &packet); - } else if (packet.sample_type & CS_ETM_RANGE) { - err = cs_etm__synth_instruction_sample(etmq,&packet); - if (err) - return err; - } + /* + * Record a branch when the last instruction in PREV_PACKET is a + * branch. + */ + if (etmq->prev_packet->last_instruction_is_branch) + cs_etm__update_last_branch_rb(etmq); + + /* + * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for + * the next incoming packet. + */ + tmp = etmq->packet; + etmq->packet = etmq->prev_packet; + etmq->prev_packet = tmp; + } else if (etmq->packet->sample_type & CS_ETM_RANGE) { + err = cs_etm__synth_instruction_sample(etmq); + if (err) + return err; + } return 0; } @@ -1016,15 +1050,14 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq, u64 *timestamp) * buffer at the end of the trace. */ if (etmq->etm->synth_opts.last_branch) { - struct cs_etm_packet packet; struct branch_stack *bs = etmq->last_branch_rb; struct branch_entry *be = &bs->entries[etmq->last_branch_pos]; - packet.cpu = cpu; - packet.start_addr = be->from; - packet.end_addr = be->to; + etmq->packet->cpu = cpu; + etmq->packet->start_addr = be->to; + etmq->packet->end_addr = be->to + 4; - err = cs_etm__synth_instruction_sample(etmq, &packet); + err = cs_etm__synth_instruction_sample(etmq); if (err) return err; } -- 2.7.4

6 years, 7 months

[PATCH v7 00/22] Add support for CoreSight trace decoding

by Tor Jeremiassen

Hi, This patchset adds support for user space decoding of CoreSight traces [1] of the ARM architecture. Kernel support for configuring CoreSight tracers and collect the hardware trace data in the auxtrace section of the perf.data file is already integrated [2]. The user space implementation mirrors to a large degree that of the Intel Processor Trace (PT) [3] implementation, except that the decoder library itself is separate from the perf tool sources, and is built and maintained as a separate open source project [4]. Instead, this patch set includes the necessary code and build settings to interfaces to the decoder library, as well as a "stub" or "null" library for the case when the perf tool is built without the library. The decoder library interface code in this patch set only supports ETMv4 trace decoding, though the library itself supports a broader range. Future patches will add support for more versions of the ARM ETM trace encoding. Changes from v2: Changed patch sequence to enable packet dump (-D or --dump-raw-trace option) first. Then build up to full packet decode. Also added functions to the trace decoder library interface as they are referenced by the functions in the main coresight processing file and combined them in those patches. Changes from v3: Introduced functions in cs-etm-decoder.c at the same time they are referenced in cs-etm.c, and not waiting until the very end to change the build script to compile the full decoder library interface. Changes from v4: Removed function to directly read vmlinux file text section, instead relying on perf dso access functions. Changes from v5: Refactored cs-etm-decoder-stub.c so that the different parts are introduced when the corresponding parts in cs-etm-decoder.c are added. Changed error returns in cs-etm-decoder.c to use enums as opposed to literals. Changed handling of how memory access function is added to decoder library. Now, instead of adding for each MMAP2 entry and the kernel only one entry is added for the entire address space. The functionality is equivalent to the previous, except the code is simpler. Changes from v6: Removed stub library, instead replaced by conditionally using a static inline function in cs-etm.h when the decoder library is not available. Tor Jeremiassen (22): perf tools: Add initial hooks for decoding coresight traces perf tools: Add processing of coresight metadata perf tools: Add coresight trace decoder library interface perf tools: Add data block processing function perf tools: Add etmv4i packet printing capability perf tools: Add decoder new and free perf tools: Add trace packet print for dump_trace option perf tools: Add code to process the auxtrace perf event perf tools: Add function to read data from dsos perf tools: Add mapping from cpu to cs_etm_queue perf tools: Add functions to allocate and free queues perf tools: Add functions to setup and initialize queues perf tools: Add functions to allocate and free queues perf tools: Add function to get trace data from aux buffer perf tools: Add function to run the trace decoder and process samples perf tools: Add functions to process queues and run the trace decoder perf tools: Add perf event processing perf tools: Add processing of queues when events are flushed perf tools: Add synth_events and supporting functions perf tools: Add function to clear the decoder packet buffer perf tools: Add functions for full etmv4i packet decode MAINTAINERS: Adding entry for CoreSight trace decoding MAINTAINERS | 3 +- tools/perf/Makefile.config | 26 + tools/perf/util/Build | 6 + tools/perf/util/auxtrace.c | 2 + tools/perf/util/cs-etm-decoder/Build | 2 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 526 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 133 +++ tools/perf/util/cs-etm.c | 1179 +++++++++++++++++++++++ tools/perf/util/cs-etm.h | 50 + 9 files changed, 1926 insertions(+), 1 deletion(-) create mode 100644 tools/perf/util/cs-etm-decoder/Build create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.h create mode 100644 tools/perf/util/cs-etm.c -- 2.7.4

6 years, 7 months

[PATCH 0/2] perf tools: floating autoFDO patches

by Mathieu Poirier

These two patches generated a fair amount of discussion on the mailing list when they were sent and as such I didn't apply them. But from what I understand people use them when doing autoFDO testing. They may not be perfect but at least provide a base for discussion and further improvement. My intention is to add them to the perf-opencsd-master branch for the 4.14 cycle. If anyone is categorically against it please get back to me with convincing arguments. Best regards, Mathieu Sebastian Pop (2): perf inject: correct recording of branch address and destination perf inject: record branches in chronological order tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 136 ++++++++++++++---------- 3 files changed, 95 insertions(+), 54 deletions(-) -- 2.7.4

6 years, 7 months

Re: Re: Re: OpenCSD + DragonBoard 410c

by marekzmyslowski

Great. Thank you. Regards Marek W dniu 2017-09-14 23:45:51 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 14 September 2017 at 15:24, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mike, > > > > Thank you. I will try to use it. One more question if I may. Where do you get userdata/rootfs - for example something like this > https://github.com/96boards/documentation/blob/master/ConsumerEdition/Drago… > ? > > > I'm not sure about what you need here... The user space I run can be > found here [1] but it seems you've already found that page... > > Mathieu > > [1]. https://96boards.org/documentation/ConsumerEdition/DragonBoard-410c/Downloa… > > > > > > > Regards > > Marek > > > > W dniu 2017-09-14 18:13:26 użytkownik Mike Leach <mike.leach(a)linaro.org> napisał: > >> Hi, > >> > >> I've attached the .config I am using to debug coresight drivers on > >> DB410c - used to build the opencsd-perf-4.13 kernel tree in the > >> OpenCSD github project. > >> The .dtb to use is apq8016-sbc.dtb > >> > >> Regards > >> > >> Mike > >> > >> On 14 September 2017 at 09:31, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hi, > >> > > >> > I'm trying to build kernel for the DragonBoard 410c to use the CoreSight. What config should I used (default for the qcom) and what dtb file is related to that board? > >> > > >> > Regards > >> > Marek > >> > _______________________________________________ > >> > CoreSight mailing list > >> > CoreSight(a)lists.linaro.org > >> > https://lists.linaro.org/mailman/listinfo/coresight > >> > >> > >> > >> -- > >> Mike Leach > >> Principal Engineer, ARM Ltd. > >> Blackburn Design Centre. UK > >> > > > > > > > > _______________________________________________ > > CoreSight mailing list > > CoreSight(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/coresight >

6 years, 7 months

Re: Re: OpenCSD + DragonBoard 410c

by marekzmyslowski

Hello Mike, Thank you. I will try to use it. One more question if I may. Where do you get userdata/rootfs - for example something like this https://github.com/96boards/documentation/blob/master/ConsumerEdition/Drago… ? Regards Marek W dniu 2017-09-14 18:13:26 użytkownik Mike Leach <mike.leach(a)linaro.org> napisał: > Hi, > > I've attached the .config I am using to debug coresight drivers on > DB410c - used to build the opencsd-perf-4.13 kernel tree in the > OpenCSD github project. > The .dtb to use is apq8016-sbc.dtb > > Regards > > Mike > > On 14 September 2017 at 09:31, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hi, > > > > I'm trying to build kernel for the DragonBoard 410c to use the CoreSight. What config should I used (default for the qcom) and what dtb file is related to that board? > > > > Regards > > Marek > > _______________________________________________ > > CoreSight mailing list > > CoreSight(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/coresight > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Blackburn Design Centre. UK >

6 years, 7 months

OpenCSD + DragonBoard 410c

by marekzmyslowski

Hi, I'm trying to build kernel for the DragonBoard 410c to use the CoreSight. What config should I used (default for the qcom) and what dtb file is related to that board? Regards Marek

6 years, 7 months

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CoreSight September 2017