== Progress ==
* GCC upstream validation:
- reported a couple of regressions
* GCC
- MVE/vectorization: committed patches for vcmp, waiting for
feedback on the remaining patches for vld2/vst2, vld4/st4
- started work on vaddv support
- committed a few testsuite improvement patches
- committed patch for PR 42579
* Misc
- looking at gdb issue with register names in target description
== Next ==
* MVE auto-vectorization/intrinsics improvements
* GCC/cortex-M testing improvements & fixes
* GDB/cortex-M
Short week (2.5 days off)
== Progress ==
* GCC upstream validation:
- discussing update of the list of configs
* GCC
- MVE/vectorization: committing cleanup patches for vcmp, waiting for
feedback on the remaining patches for vcmp, vld2/vst2, vld4/st4
* Misc
- scripts patch reviews
- looking at gdb issue with register names in target description
== Next ==
* MVE auto-vectorization/intrinsics improvements
* GCC/cortex-M testing improvements & fixes
* GDB/cortex-M
Progress:
* UM-2 [QEMU upstream maintainership]
+ Code review:
- Managed to review all of RTH's 82-patch SVE2 patchset...
+ Misc bugs:
- fixed some errors in modelling of SRAM in AN547 board
- fixed a bug in GICv3 EOI (EL3 should be able to handle
Group 1 NS IRQs)
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Implemented multiply-add-long-dual-accumulate insns
(VMLALDAV, VMLSLDAV, VRMLALDAVH, VRMLSLDAVH)
Progress meter: 40/210 (19%)
-- PMM
VirtIO Initiative ([STR-9])
===========================
- did some investigation on getting [Gunyah hypervisor] up and running
- debugging xl domU launch under QEMU
- got reverse debugging working on virtio ;-)
[STR-9] <https://projects.linaro.org/browse/STR-9>
[Gunyah hypervisor] <https://github.com/quic/gunyah-hypervisor>
QEMU Upstream Work ([UM-2])
===========================
- reviewed a large chunk of rth's FloatParts opus Message-Id:
<20210508014802.892561-1-richard.henderson(a)linaro.org>
- posted [PATCH v3 00/31] testing/next pre-PR (hexagon, tricore, misc)
Message-Id: <20210512102051.12134-1-alex.bennee(a)linaro.org>
[UM-2] <https://projects.linaro.org/browse/UM-2>
[testing/next branch]
<https://github.com/stsquad/qemu/tree/testing/next>
Other
=====
[Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro
Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com>
Completed Reviews [1/1]
=======================
[PATCH 00/72] Convert floatx80 and float128 to FloatParts
Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org>
Absences
========
- Bank Holiday on Monday
Current Review Queue
====================
TODO [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
Message-Id: <20210429234201.125565-1-shashi.mallela(a)linaro.org>
===========================================================================================================================
TODO [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS
Message-Id: <20210505030443.25310-1-rebecca(a)nuviainc.com>
====================================================================================================================================
TODO [PATCH v6 00/82] target/arm: Implement SVE2
Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org>
===================================================================================================================
TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels'
Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com>
===================================================================================================================================================
--
Alex Bennée
Hi Richard,
Your patch a076632e274abe344ca7648b7c7f299273d4cbe0 appears to have broken bootstrap-O3 for 32-bit armhf. Do you have an AArch32-capable machine to reproduce/investigate this on? Let me know if not, and I'll make a proper bug report with a testcase.
ICE:
00:33:32 In function ‘syscall.forkExec’:
00:33:32 go1: error: address taken, but ADDRESSABLE bit not set
00:33:32 PHI argument
00:33:32 &go..C479;
00:33:32 for PHI node
00:33:32 err$__object_78 = PHI <err$__object_76(58), &go..C479(59)>
00:33:32 during GIMPLE pass: fre
00:33:32 go1: internal compiler error: verify_ssa failed
00:33:32 0x9c18d7 verify_ssa(bool, bool)
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/tree-ssa.c:1214
00:33:32 0x6f8d5b execute_function_todo
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2049
00:33:32 0x6f9abf do_per_function
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:1687
00:33:32 0x6f9abf execute_todo
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2096
00:33:32 Please submit a full bug report,
00:33:32 with preprocessed source if appropriate.
00:33:32 Please include the complete backtrace with any bug report.
00:33:32 See <https://gcc.gnu.org/bugs/> for instructions.
00:33:32 Makefile:3001: recipe for target 'syscall.lo' failed
Full build log: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
> On May 11, 2021, at 8:15 AM, tcwg-jira (Jira) <projects(a)linaro.org> wrote:
>
> There is 1 comment.
>
>
> GNU Toolchain / <Mail Attachment.png> GNU-692 IN PROGRESS
> Regressions from tcwg_binutils/tcwg_cross/tcwg_gnu CI
>
> View issue · Add comment
>
> 1 comment
>
> tcwg-jira on 11/May/21 5:04 AM
>
> Successfully identified regression in gcc in CI configuration tcwg_gnu/gnu-master-arm-bootstrap_O3. So far, this commit has regressed CI configurations:
> • tcwg_gnu/gnu-master-arm-bootstrap_O3
> Culprit:
> <cut>
> commit a076632e274abe344ca7648b7c7f299273d4cbe0
> Author: Richard Biener <rguenther(a)suse.de>
> Date: Fri May 7 09:51:18 2021 +0200
> middle-end/100464 - avoid spurious TREE_ADDRESSABLE in folding debug stmts
> canonicalize_constructor_val was setting TREE_ADDRESSABLE on bases
> of ADDR_EXPRs but that's futile when we're dealing with CTOR values
> in debug stmts. This rips out the code which was added for Java
> and should have been an assertion when we didn't have debug stmts.
> To not regress g++.dg/tree-ssa/array-temp1.C we have to adjust the
> testcase to not look for a no longer applied invalid optimization.
> 2021-05-10 Richard Biener <rguenther(a)suse.de>
> PR middle-end/100464
> PR c++/100468
> gcc/
> • gimple-fold.c (canonicalize_constructor_val): Do not set
> TREE_ADDRESSABLE.
> gcc/cp/
> • call.c (set_up_extended_ref_temp): Mark the temporary
> addressable if the TARGET_EXPR was.
> gcc/testsuite/
> • gcc.dg/pr100464.c: New testcase.
> • g++.dg/tree-ssa/array-temp1.C: Adjust.
> </cut>
> Details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
> Even more details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
>
>
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== This Week ==
* GCC
- PR97903 (missed lowering to vtst): Committed fix to trunk,
- PR66791: Submitted patch to replace vtst* (a, b) by (a & b) != 0 in
arm_neon.h.
- Committed fix for build failure in trunk.
* Validation
- vect metric: Pushed all pending patches.
== Next Week ==
- PR66791: Continue working on more intrinsics
- Validation: Monitor vect metric
== Progress ==
* GCC upstream validation:
- Reported a few regressions
- discussing update of the list of configs
- tried qemu-6.0, issue with hwasan testing on aarch64
* GCC
- MVE/vectorization: waiting for feedback on patches for vcmp,
vld2/vst2, vld4/st4
* Misc
- scripts patch reviews
- looking at gdb issue with register names in target description
== Next ==
* MVE auto-vectorization/intrinsics improvements
* GCC/cortex-M testing improvements & fixes
Progress (short week, 2 days):
* UM-2 [QEMU upstream maintainership]
- sent some small patches: fixing Coverity issues; converting a
few users of a legacy API to the new function
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
- Implemented more insns: VMUL, VSTRB/H/W, VMAX, VMIN,
VABD, VHADD, VHSUB, VMULL, VRMULH. Progress meter: 36/210 (17%)
-- PMM
