Progress:
* qemu maintenance
** sent arm-devs and target-arm pullreqs now we're in softfreeze
* VIRT-4
** received Arndale board, confirmed it works (took several
hours mostly due to bonkers power switch design)
** VIRT-49
*** making progress; updated card with a list of sub-subtasks
Plans:
* keep pushing on with VIRT-49
* finish config of arndale board, test running KVM on it
* book travel/hotel for Connect Dublin
* office move Fri 26/Mon 29
-- PMM
All,
http://cbuild.validation.linaro.org/helpers/recent was reporting an Internal
Server Error earlier today, and after looking at the logs the resultant
cause was because the gcc-4.8+svn198079 Lava job
(https://validation.linaro.org/lava-server/scheduler/job/52224) decided that
it was an a9 (as opposed to a9hf) job and that it didn't no which version of
Ubuntu it was running on.
The caused the logs to be put in
http://cbuild.validation.linaro.org/build/gcc-4.8+svn198079/logs/armv7l--cb…
The tcwg-web app then fell over because it couldn't pass the
armv7l--cbuild-panda-es06-cortexa9r1 name.
I fixed the issue by manually renaming the build log directory to:
http://cbuild.validation.linaro.org/build/gcc-4.8+svn198079/logs/armv7l-pre…
And once the cron job which scans the builds had run everything now works.
Actions:
1. Paul - do you mind taking a look at the build and seeing what went wrong
- my initial cursory glance makes me believe its the board having heat
issues causing random things to happen.
2. Paul & Matt - Looking at the code (and from something else Michael said
to me last week) I think having hostnames with '-' characters in them will
confuse the cbuild interface. I propose changing cbuild to do a s/-/_/g on
all the hostname it reads as a workaround. I don't plan on changing actual
hostnames of boards. Paul is this going to cause a problem for you in Lava?
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
Hi,
Some time ago I had some problems linking my project libraries for
Android using the Linaro toolchain 4.7.1 which I reported to the
list:
http://lists.linaro.org/pipermail/linaro-toolchain/2012-June/002631.html
I ended up using the 4.6.x version of the compiler because
I could not find a fix and I did not get any hints from
the mailing list.
Now I need to really switch to 4.7(for better C++11 support)
but I'm pretty much having the same issue with the 4.7.3 version:
E.g.
System/Logging/DroidLogger.cpp.o: requires unsupported dynamic reloc
R_ARM_REL32; recompile with -fPIC
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error:
/home/marius/Development/ToolChains/Android/experimental_ndk/sources/cxx-stl/gnu-libstdc++/4.7.3/libs/armeabi-v7a/libsupc++.a(eh_globals.o):
requires unsupported dynamic reloc R_ARM_REL32; recompile with -fPIC
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error: hidden symbol '__dso_handle' is not defined locally
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error: hidden symbol '__dso_handle' is not defined locally
I'm using it with the Android NDK version r8e.
I have downloaded the prebuilt binaries:
android-toolchain 4.7 (ICS, JB) <http://www.linaro.org/downloads/> 4.7-2013.03
13.03
(Linaro GCC 4.7-2013.03) 4.7.3 20130226 (prerelease)
Does anyone have any hints on how to overcome the above mentioned problem?
--
Marius Cetateanu | Software Engineer
T +32 2 888 42 60
F +32 2 647 48 55
E mce(a)softkinetic.com
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Boulevard de la Plaine 15, 1050, B-Brussels, Belgium
Registration No: RPM/RPR Brussels 0811 784 189
Our e-mail communication disclaimers & liability are available at:
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Hi Matt,
This week I found an error in LLVM that can only be reproduced on ARM
hardware, if the GCC that compiles it specifies --mcpu=cortex-a15. The
error is a segfault on one of the tests compiled by that Clang/LLVM. As you
can see, it's not something trivial that we'd expect people to do easily.
My question is: How do we tackle this type of bug?
One option is to do all the debugging and interface with the original patch
author until we fix the problem. This works well for simple bugs, but in
this case I'm not sure it will work.
Another option was to have a board on Linaro's DMZ with no access to
anything else internally, so that people could log in and debug the problem
in situ.
This board would have to be setup just for the debugging with a random
password given only to the author of the patch and cleaned up right after
the bug is fixed (to avoid external abuse).
We could use the same board for LLVM, GCC, GDB, etc. but it should be easy
to re-flash it to a minimum system, so that we don't spend too much time
setting it up.
Does anyone have a better idea?
cheers,
--renato
Hi,
Feel free to point me at a newer toolchain. Was building the SNU
OpenCL SDK native on my chromebook running ubuntu raring when I hit
the following:
make: Entering directory `/home/tgall/opencl/SNU/src/runtime/build/cpu'
arm-linux-gnueabihf-g++ -fsigned-char -march=armv7-a -mfloat-abi=hard
-mfpu=neon -ftree-vectorize -ftree-vectorizer-verbose=0 -fsigned-char
-fPIC -DDEF_INCLUDE_ARM -g -c -o smoothstep.o
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common/smoothstep.c
-I/home/tgall/opencl/SNU/inc
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/async
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/atomic
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/conversion
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/geometric
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/integer
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/math
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/reinterpreting
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/relational
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/vector -O0 -g
In file included from
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/cl_cpu_ops.h:47:0,
from
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common/smoothstep.c:34:
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/type/cl_ops_floatn.h:
In function 'float2 operator-(float, float2)':
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/type/cl_ops_floatn.h:114:1:
internal compiler error: output_operand: invalid operand for code 'P'
Please submit a full bug report,
with preprocessed source if appropriate.
See <file:///usr/share/doc/gcc-4.7/README.Bugs> for instructions.
Preprocessed source stored into /tmp/cciluYVq.out file, please attach
this to your bugreport.
Traceback (most recent call last):
File "/usr/share/apport/gcc_ice_hook", line 34, in <module>
pr.write(open(apport.fileutils.make_report_path(pr), 'w'))
File "/usr/lib/python2.7/dist-packages/problem_report.py", line 254, in write
self._assert_bin_mode(file)
File "/usr/lib/python2.7/dist-packages/problem_report.py", line 632,
in _assert_bin_mode
assert (type(file) == BytesIO or 'b' in file.mode), 'file stream
must be in binary mode'
AssertionError: file stream must be in binary mode
make: *** [smoothstep.o] Error 1
tgall@miranda:~/opencl/SNU$ arm-linux-gnueabihf-g++ --version
arm-linux-gnueabihf-g++ (Ubuntu/Linaro 4.7.2-23ubuntu2) 4.7.3
I've attached the preprocessed source as well.
FWIW, I don't hit this when building with -O3. In this case I was
compiling for debug.
Thanks!
--
Regards,
Tom
"Where's the kaboom!? There was supposed to be an earth-shattering
kaboom!" Marvin Martian
Tech Lead, Graphics Working Group | Linaro.org │ Open source software
for ARM SoCs
w) tom.gall att linaro.org
h) tom_gall att mac.com
== Progress ==
* Disable-peeling:
- some benchmarking jobs ran, thanks to the new boards in cbuild.
- Spawned other jobs for reference
* Libsanitizer:
- Built native GCC on snowball to understand the isatty() behaviour
compared to qemu.
* Neon intrinsics codegen:
- resumed looking at the vuzp crc example from Steve Capper.
* Neon intrinsics codegen:
- added fp16 support (works with RVCT, GCC does not support it yet)
* Internal support
== Next ==
* Disable-peeling: analyze results when available.
* Revert-coalesce-vars: idem.
* Libsanitizer: analyze isatty() on board
* Neon intrinsics: continue with vuzp example.
One day off this week.
== Issues ==
* None
== Progress ==
* Linaro GCC 4.8, 4.7 and 4. 2013.04 released (with CL and MG)
* Boehm-gc AArch64 support backport in GCC:
- support committed.
* Libunwind AArch64 support:
- Resumed ongoing work.
== Plan ==
* Libunwind AArch64 support:
- Fix and submit upstream
== Progress ==
* Started investigating dwarf test suite failures on ARM.
* Created a new comparison between arm native gdb and arm remote gdb.
* More investigation of test cases to figure out causes of test cases that
are not run or unsupported.
* Experimentation with screens on gateway to speed up remote debugging,
didnt work.
* 1:1 with Matt.
* Took a day off on Friday 12th April 2013 for car checkup in workshop.
* Received Invitation letter from Arwen on Friday which means now visa
application only needs hotel booking information.
*** Still No blue-print available to log work in JIRA.
== Plan ==
* Setup arm gdb to debug itself and debug dwarf problems on arm.
* Fill up the arm native vs arm remote comparison sheet.
* Submit Ireland visa application after receiving invitation letter and
hotel booking details.
* Setup screens for remote testing using toolchain cbuild infrastructure.
== Progress ==
* gc sections tests
Completed upstream of g-c section patches after updating review comments.
Closed the card associated with the work.
http://cards.linaro.org/browse/TCWG-27
* gprof support work for Aarch64
Read gprof internal documents from sourceware.org.
Working on GCC side to support gprof for Aarch64.
Misc
------
11-4-2013 was a local holiday.
== Plan ==
* Continue gprof support work for Aarch64
* Attend internal team meetings on 16 and 17th.
== Summary ==
- http://cards.linaro.org/browse/TCWG-14
Coremark ARM mode gives about 2% performance improvement with about 1%
code size reduction. Thumb2 mode however has performance regression even
though code size reduces about 0.6%. Performance regression here is like
what we are seeing in EPILOGUE_UESES
changes(http://cards.linaro.org/browse/TCWG-13). Spawned spec in CBUILD
to see the impact with spec2000.
- http://cards.linaro.org/browse/TCWG-13
Thumb2 mode performance regression is due to the percentage of time
spent in core_state_transition. Looks like an alignment issue; same asm
is generated for this function with the patch. Investigating it.
== Plan ==
- Plan to resolve http://cards.linaro.org/browse/TCWG-13 this week.
- Get spec2000 results for http://cards.linaro.org/browse/TCWG-14 to
decide on the next step