Progress:
* UM-2 [QEMU upstream maintainership]
- sent patch fixing some regexes in our documentation
- patch review and queueing up an arm pull request
- Investigated the mps3-an536 Cortex-R52 FPGA image to see
what work would be required to implement a QEMU model of it,
wrote a draft of a jira epic issue for this
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
* Implemented and tested the memcpy/memmove insns CPY*
* Got the whole patchseries into good enough shape to send out
for review
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Resumed working on new approach to support changing SVE vector length
in remote debugging. I was able to use DWARF location expressions in
the target description to express the SVE vector register sizes in
terms of the VG register. Also adapted the regcache to support
variable-length registers, and removed the VQ value from the target
description and from aarch64_gdbarch_tdep, making GDB use one target
description regardless of the vector length size. Still ironing out
some bugs, and haven't tackled gdbserver yet.
--
Thiago
Just FYI.
This test is just bogus and fixing it might be simple as using -fsanitize=undefined to check at runtime there is no undefined behavior being hit.
In this case even if we do the comparison in `signed` and do the negate in `unsigned` types. we can still remove the negate in this case since we know the only value that will be still negative in that branch is LONG_MIN. So my patch just simplifies the inner comparison to that instead of `a < 0` and then be able to remove the neg.
Someone else will have to fix the testcase since it is a testcase issue ...
________________________________________
From: ci_notify(a)linaro.org <ci_notify(a)linaro.org>
Sent: Friday, September 1, 2023 3:07 PM
To: Andrew Pinski
Subject: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions
External Email
----------------------------------------------------------------------
Dear contributor, our automatic CI has detected problems related to your patch(es).
Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list.
In CI config tcwg_gcc_check/master-aarch64 after:
| 2 patches in gcc
| Patchwork URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.sourceware.o…
| 504821491ff VR-VALUES: Rewrite test_for_singularity using range_op_handler
| f6d1540c3e0 VR-VALUES: Rename op0/op1 to op1/op2 for test_for_singularity
| ... applied on top of baseline commit:
| b0d75f7d3bb libstdc++: Fix debug-mode tests for constexpr algorithms
FAIL: 1 regressions
regressions.sum:
=== gcc tests ===
Running gcc:gcc.target/aarch64/aarch64.exp ...
FAIL: gcc.target/aarch64/vnegd_s64.c scan-assembler-times neg\\tx[0-9]+, x[0-9]+ 1
=== Results Summary ===
-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:
Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- code review:
+ RTH's linux-user ESR signal frame patchset
+ iMX6/7 cleanup patchset
+ some other minor bits and pieces
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
* SETG* instructions (memset + MTE tag setting) implemented and
given some basic testing
-- PMM
Hi Jan,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I am having some trouble to reproduce it outside
our CI environment, but it has been hitting this issues consistently
and it does seems related to your patch.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_pr…
Hi Richard,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that for
test_copy_lane_f32, test_copy_lane_s32, test_copy_lane_u32, gcc
is now generating zip1 instead of a ins; which does not seem
fully correct.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/91…
Hello,
# TCWG CI
- GCC regression GNU-884: Prathamesh confirmed that the new generated
code is better so I posted a patch adjusting the testcase.
- GCC regression GNU-885: Confirmed that the problem is still present in
trunk as of commit 829c0c06fe7b from yesterday, so opened bugzilla
111125 and copied the patch author. He fixed the regression.
- Posted Gerrit review request to increase timeout for GDB check jobs to
accommodate longer times for Armv8l builds.
# GDB Upstream
- Reviewed v4 of Luis' patch series adding SME support to GDB and
gdbserver.
--
Thiago
Hi Andrew,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that the
expected 18 for aarch64 is now 17:
$ grep "Jumps threaded" a-ssa-dom-thread-7.c.197t.thread2
Jumps threaded: 17
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_native_check_gcc--master-aarch64-build/5…
Hi Richard,
Your patch below ICEs on aarch64-linux-gnu. Should reproduce easily on native or cross aarch64-linux-gnu build.
Let me know if you need any assistance in reproducing this.
Thanks,
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 24, 2023, at 22:03, ci_notify(a)linaro.org wrote:
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it. If you have any questions, please
> follow up on linaro-toolchain(a)lists.linaro.org mailing list.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | commit a1558e9ad856938f165f838733955b331ebbec09
> | Author: Richard Biener <rguenther(a)suse.de>
> | Date: Wed Aug 23 14:28:26 2023 +0200
> |
> | tree-optimization/111115 - SLP of masked stores
> |
> | The following adds the capability to do SLP on .MASK_STORE, I do not
> | plan to add interleaving support.
> |
> | PR tree-optimization/111115
> | ... 21 lines of the commit log omitted.
>
> FAIL: 6 regressions
>
> regressions.sum:
> === gcc tests ===
>
> Running gcc:gcc.target/aarch64/sve/aarch64-sve.exp ...
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (internal compiler error: in get_group_load_store_type, at tree-vect-stmts.cc:2121)
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (test for excess errors)
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2b\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2d\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2h\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2w\\t.z[0-9]
>
> ... and 1 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/artifact…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/856/artifact…
>
> Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/…
>
> Full commit : https://github.com/gcc-mirror/gcc/commit/a1558e9ad856938f165f838733955b331e…
>
> Latest bug report status : https://linaro.atlassian.net/browse/GNU-893
>
> List of configurations that regressed due to this commit :
> * tcwg_gcc_check
> ** master-aarch64
> *** FAIL: 6 regressions
> *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/