linaro-toolchain

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4 participants
5631 discussions

by Richard Henderson

Hi guys. I just realized that today's meeting will be right in the middle of dinner plans. I'll organize better next week. Anyway, here's my status: - Fourth SME patch set -- parts merged, and some bugs fixed. - Base/arm-compat portion of semihosting rewrite now upstream. Target-specific bits for m68k, mips, nios2, xtensa outstanding. - Almost done with FEAT_HAFDBS (hardware access/dirty updates). Big changes to ptw.c to make that work: 50+ patches. The reorg should make FEAT_RME easier though. r~

3 years, 2 months

[ACTIVITY] Report for weeks #24 and #25

by Thiago Jung Bauermann

Hello, I just noticed that I didn't send a report for week #24. Sorry about that. For that reason, this report covers two weeks. # Linaro CI's GDB testsuite results * Submitted upstream patch fixing gdb_compile regexp to account for our GNATMAKE_FOR_TARGET value containing spaces. This should solve the Ada test failures in our CI. * Fixed the Abe shell script to correctly set auto-load-safe-path so that GDB can load libthread_db.so.1. Unfortunately the CI detected a problem with using the generated manifest to reproduce the toolchain build, so I'm back to the drawing board on this one. * Sent a Gerrit change request for the Abe script updating it to use release 12's branch and tag for GDB and gdbserver, and another one removing a workaround for a build problem fixed in GDB 9. * Sent a Gerrit change request for tcwg-dev-build.sh fixing a couple of issues I found when using it to build and test GDB. # [GNU-767] Support changing SVE vector length in remote debugging * Analysed and fixed a couple more regressions in my branch. # Misc * Attended a few online sessions from Linaro San Francisco Get Together. * Sent Gerrit change request updating the TCWG script that generates our SSH known_hosts file to include the Ed25519 host keys, which are now preferred in Ubuntu 22.04. * Was out one day due to “Corpus Christi” public holiday. -- Thiago

3 years, 2 months

[weekly][linaro] report week ending 24 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - First week back after holiday: lots of catchup - Good progress with the code review queue, including getting rid of a few things that had been lurking in it for too long, and another pass through the latest SME series - KVM Forum programme committee work -- PMM

3 years, 2 months

[ACTIVITY] Report for week #23

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Debugged and fixed a few issues in my code where gdbserver was having trouble with setting the target description for new threads. Also fixed regressions in a couple more testcases. # Linaro CI's GDB testsuite results * Luis commented on IRC that the GDB testsuite results from the Linaro CI seemed a bit high with about 540 failures, so I set out to investigate. The two biggest sources of failures are: 1. Ada tests were failing because they can't build their test executables. This is expected because we don't have the Ada compiler in the CI, but normally these testcases would just bail out as unsupported. Found out that there was a regex in the GDB testsuite that was (IMHO) too strict for our particular setup and fixed it. 2. All CTF tests are failing. The compiler in the CI seems to be building test executables with CTF debug info, so we do seem to have a problem there. The CI's GDB is also not loading libthread_db.so because of a GDB security setting, so I fixed that as well and expect some more tests to pass now. I still haven't submitted my fixes for 1. to upstream and for the libthread_db.so.1 issue to our CI scripts because I'm still working with jenkins-scripts and Abe to reproduce the CI environment to verify the fixes. -- Thiago

3 years, 3 months

[ACTIVITY] report week ending 10 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - This week was almost entirely code review and similar upstream tasks - managed to review all the preliminary parts of the SME patchset - reviewed several other refactoring series from rth - reviewed a big PS/2 keyboard emulation refactoring patchset - prep for KVM Forum program committee session * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - FEAT_RASv1p1 and FEAT_DoubleFault now upstream -- PMM

3 years, 3 months

[ACTIVITY] Report for week #22

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Debugged and fixed issues in my code where gdbserver was in some cases trying to read inferior registers before aarch64_target was fully initialised, and also while the inferior thread was running. This improved reliability but there are still some testsuite regressions to look into. # Sourceware bug 28561 - [gdb/testsuite] Error due to not reading \r\n at end of mi prompt * Posted comment to the bug report summarising my current results. * Tried to reproduce the bug using the upstream v5.3 kernel (since I was able to see it with openSUSE Leap's v5.3 kernel), but failed. Still trying to understand what that implies. -- Thiago

3 years, 3 months

[TCWG CI] Regression caused by gcc: rs6000: Harden mma_init_builtins

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: rs6000: Harden mma_init_builtins: commit 6278065af07634278ba30029d92a82b089969baa Author: Peter Bergner <bergner(a)linux.ibm.com> rs6000: Harden mma_init_builtins Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:03:13 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:03:14 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 31574 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allmodconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-6278065af07634278ba30029d92a82b089969baa cd investigate-gcc-6278065af07634278ba30029d92a82b089969baa # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 6278065af07634278ba30029d92a82b089969baa ../artifacts/test.sh # Reproduce last_good build git checkout --detach a5b5c7c2840ebb0aaa0d0f1e090fb2fc6942196d ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 6278065af07634278ba30029d92a82b089969baa Author: Peter Bergner <bergner(a)linux.ibm.com> Date: Wed Jul 7 11:39:34 2021 -0500 rs6000: Harden mma_init_builtins The previous MMA patch added some fragile code to initialize its new built-ins. This patch hardens the initialization. 2021-07-07 Peter Bergner <bergner(a)linux.ibm.com> gcc/ * config/rs6000/rs6000-call.c (mma_init_builtins): Use VSX_BUILTIN_LXVP and VSX_BUILTIN_STXVP. --- gcc/config/rs6000/rs6000-call.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 6115e3b34d9..904e104c058 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -14293,7 +14293,8 @@ mma_init_builtins (void) /* Some MMA built-ins that are expanded into gimple are converted into internal MMA built-ins that are expanded into rtl. The internal built-in follows immediately after this built-in. */ - if (d[1].icode != CODE_FOR_nothing) + if (d->code != VSX_BUILTIN_LXVP + && d->code != VSX_BUILTIN_STXVP) { op[nopnds++] = void_type_node; icode = d[1].icode; </cut>

3 years, 3 months

[ACTIVITY] report week ending 31 May

by Peter Maydell

Progress (covers two half-weeks): * UM-2 [QEMU upstream maintainership] - investigating a reported bug with semihosting syscalls over gdbstub - reviewed a massive series from RTH refactoring our SVE code in preparation for handling SME * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - looking at exactly what FEAT_RASv1p1 and FEAT_DoubleFault require of a minimal RAS implementation like QEMU's - sent a patch implementing FEAT_RASv1p1 (a no-op for QEMU) - sent a patch implementing FEAT_DoubleFault (turns out to be simpler than I initially feared it might be) -- PMM

3 years, 3 months

[TCWG CI] Regression caused by gcc: rs6000: MMA test case ICEs using -O3 [PR99842]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: rs6000: MMA test case ICEs using -O3 [PR99842]: commit df4e0359dad239854af0ea9eacb8e7e3719557d0 Author: Peter Bergner <bergner(a)linux.ibm.com> rs6000: MMA test case ICEs using -O3 [PR99842] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:00:57 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:00:57 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:00:57 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:00:59 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 21071 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allyesconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-df4e0359dad239854af0ea9eacb8e7e3719557d0 cd investigate-gcc-df4e0359dad239854af0ea9eacb8e7e3719557d0 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach df4e0359dad239854af0ea9eacb8e7e3719557d0 ../artifacts/test.sh # Reproduce last_good build git checkout --detach e21e93407202e62a10c372595076c593c561bb11 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit df4e0359dad239854af0ea9eacb8e7e3719557d0 Author: Peter Bergner <bergner(a)linux.ibm.com> Date: Sun May 30 22:45:55 2021 -0500 rs6000: MMA test case ICEs using -O3 [PR99842] The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The lxv and lxvp instructions have indexed forms (lxvx and lxvpx), so the simple solution is to just allow indexed addresses in the predicate. 2021-05-30 Peter Bergner <bergner(a)linux.ibm.com> gcc/ PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New. --- gcc/config/rs6000/predicates.md | 3 +- gcc/testsuite/g++.target/powerpc/pr99842.C | 188 +++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index e21bc745f72..121cbf14810 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1172,7 +1172,8 @@ (match_test "(mode == V16QImode && (vsx_register_operand (op, mode) || (MEM_P (op) - && quad_address_p (XEXP (op, 0), mode, false))))")) + && (indexed_or_indirect_address (XEXP (op, 0), mode) + || quad_address_p (XEXP (op, 0), mode, false)))))")) ;; Return 1 if this operand is valid for an MMA disassemble insn. (define_predicate "mma_disassemble_output_operand" diff --git a/gcc/testsuite/g++.target/powerpc/pr99842.C b/gcc/testsuite/g++.target/powerpc/pr99842.C new file mode 100644 index 00000000000..922450e2c21 --- /dev/null +++ b/gcc/testsuite/g++.target/powerpc/pr99842.C @@ -0,0 +1,188 @@ +/* PR target/99842 */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power10 -Wno-return-type" } */ + +/* Verify we do not ICE on the following noisy creduced test case. */ + +enum { a, b, c, d }; +template <typename> struct e; +template <typename g, typename h, typename k> struct e<g(h, k)> { + typedef h f; +}; +template <typename> struct ac; +template <typename ab> struct ac<const ab> : ac<ab> {}; +template <typename> struct l; +template <typename, int, int m, int = 0, int = a, int = m> class n; +template <typename> class o; +template <typename, typename, typename> class ag; +template <typename, typename, int = c> class af; +template <typename> struct ad; +template <typename ab> struct an { + typedef n<typename ab ::ah, ac<ab>::ai, ac<ab>::aj> f; +}; +template <typename al> struct am { typedef o<al> f; }; +template <typename al, typename = typename ac<al>::ao, + typename = typename ac<al>::av> +struct ak; +template <typename al, typename ao> struct ak<al, ao, int> { + typedef typename am<al>::f f; +}; +template <typename, typename, typename> struct aq; +template <typename ar, typename as> struct aq<ar, ar, as> { typedef ar at; }; +template <typename ap> ap bf(const typename ad<ap>::f *); +template <typename ap, int> ap aw(typename ad<ap>::f *ax) { return bf<ap>(ax); } +typedef __attribute__((altivec(vector__))) double au; +template <> struct ad<au> { typedef double f; }; +template <> au bf(const double *ax) { return __builtin_vec_vsx_ld(0, ax); } +template <typename> struct az {}; +template <typename al> class o : public l<al> { +public: + typedef typename ac<al>::ah ah; + template <typename ay> al &operator+=(const o<ay> &); +}; +template <typename> struct l {}; +template <typename ba, typename bb, int bd> struct ac<af<ba, bb, bd>> { + typedef typename ba::ah ah; + enum { ai, aj }; +}; +template <typename, typename, int bd> +class af + : public ak< + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>, bd>, + int, int>::f {}; +template <typename, typename, typename> struct be; +template <typename bj, typename bg, typename g> void bi(bj, bg bm, g) { + typename an<bg>::f bk(bm); +} +template <typename bj, typename bg, typename g> void bl(bj, bg bm, g bp) { + be<bj, bg, g>::bn(a, bm, bp); +} +template <typename, typename, typename, typename> struct bo; +class bs { +public: + bs(double *, int); + double &operator()(int, int) { return bq[br]; } + template <typename bw, int> bw bt(int i, int j) { + double &bu = operator()(i, j); + return aw<bw, b>(&bu); + } + double *bq; + int br; +}; +class ca : public bs { +public: + ca(double *by, int bz) : bs(by, bz) {} +}; +template <typename al> class ce : public am<al>::f { +protected: + template <typename ay> void cb(l<ay>) { + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>> + cc; + bl(0, cc, az<typename ay::ah>()); + } + template <typename> void ch(long); + template <typename ay> void ch(l<ay> cf) { cb(cf); } +}; +template <typename cg, int aa, int m, int cl, int ci, int cj> +struct ac<n<cg, aa, m, cl, ci, cj>> { + typedef cg ah; + typedef int av; +}; +template <typename cg, int, int m, int, int, int> +class n : public ce<n<cg, m, c>> { +public: + template <typename ab> n(ab p) { n::template ch<ab>(p); } +}; +template <typename bc, typename ba, typename bb> struct ac<ag<bc, ba, bb>> { + typedef ba ao; + typedef typename e<bc(typename ba::ah, typename bb::ah)>::f ah; + typedef typename aq<typename ac<ba>::av, typename ac<bb>::av, bc>::at av; +}; +template <typename> class cm; +template <typename, typename r, typename cs> +class ag + : public cm<typename aq<typename ac<r>::av, typename ac<cs>::av, int>::at> { +}; +template <typename> +class cm : public ak<ag<int, n<double, 1, 1>, n<double, 1, 1>>>::f {}; +template <typename al> +template <typename ay> +al &o<al>::operator+=(const o<ay> &) { + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>> + co; + bi(0, co, int()); +} +enum { cp }; +template <int> struct cq; +template <typename> struct cr { + enum { q }; + enum { ae = cq<q>::at }; +}; +template <> struct cq<cp> { + enum { at = d }; +}; +struct t { + template <typename ba, typename bb, typename s> static void bn(ba, bb, s) { + typedef typename bb::ah x; + x u; + bo<long, ca, x, ca>::bn(0, 0, ca(0, 0), ca(&u, 1), 0, 0, 0); + } +}; +template <typename, typename bb, int = cr<bb>::ae> struct cu; +template <typename cd, typename ba, typename bb, int ct, typename ah> +struct be<cd, af<ba, bb, ct>, az<ah>> { + static void bn(cd, af<ba, bb> bm, az<ah>) { + ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>> da; + cu<ba, bb>::cv(c, da, bm); + } +}; +template <typename al> struct cw { + template <typename bj> + static void + cv(bj, ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3> bx) { + double alpha; + ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>> bh; + al::cx(c, bh, bx, alpha); + } +}; +template <typename ba, typename bb> struct cu<ba, bb, d> : cw<cu<ba, bb>> { + template <typename s> static void cx(s, ba, bb bx, typename af<ba, bb>::ah) { + ba cz; + t::bn(cz, bx, c); + } +}; +template <typename dj, typename, bool> +void db(__vector_quad *, __vector_pair &, dj); +template <typename, typename, typename, typename, typename, typename, int> +void dc(ca alhs) { + typedef au dj; + typedef au dd; + ca bh(alhs); + enum { de }; + __vector_quad df, dg; + int j; + dd v; + __vector_pair dh; + __builtin_mma_assemble_pair( + &dh, (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j), + (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j)); + db<dj, dd, true>(&df, dh, v); + __vector_pair di; + __builtin_mma_assemble_pair( + &di, (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j), + (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j)); + db<dj, dd, true>(&dg, di, v); +} +template <typename bv, typename w, typename cy> struct bo<bv, w, double, cy> { + static void bn(bv, bv, w bh, cy, double, bv, double) { + dc<bv, double, w, double, cy, double, d>(bh); + } +}; +void dm() { + n<double, 1, 1> dk(1), y(0); + y += dk; +} </cut>

3 years, 3 months

[ACTIVITY] Report for week #21

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Found out that one issue I was having with gdbserver was caused by an incompatibility it has with zsh (sourceware bug 26116). * Fixed a gdbserver crash in my code where a register set was NULL in the target description. * Now working on an issue where the target description says SVE isn't supported, but the regsets information says they are. This is caused by my code sometimes moving the first ptrace call to get the inferior registers to a time before it is properly stopped. # Sourceware bug 28561 - [gdb/testsuite] Error due to not reading \r\n at end of mi prompt * Set up a few containers and KVM guests to attempt to reproduce this bug on different environments. Reproduced it successfully on an openSUSE Leap 15.3 guest, as well as Ubuntu 20.04 and 22.04 containers in said guest. I wasn't able to reproduce on Ubuntu 20.04 nor 22.04 guests. Suspecting it's a kernel issue where the fix was backported to the Ubuntu kernels. -- Thiago

3 years, 3 months

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