QEMU Tooling ([VIRT-252])
=========================
Extend gdbstub for SVE ([VIRT-281])
- posted [PATCH v4 00/21] gdbstub refactor and SVE support (+check-tcg
tweaks) Message-Id: <20191220120438.16114-1-alex.bennee(a)linaro.org>
[VIRT-281] <https://projects.linaro.org/browse/VIRT-281>
GSoC Mentoring Afermath ([VIRT-348])
- started working on re-base of [TCG code quality tracking]
- bit of a re-factor rethink required
[TCG code quality tracking]
<https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10>
Upstream Work ([VIRT-109])
==========================
- posted [PULL 00/25] testing and logging updates Message-Id:
<20191219104934.866-1-alex.bennee(a)linaro.org>
- posted [PATCH v1 0/4] semihosting read console support Message-Id:
<20191218180029.6744-1-alex.bennee(a)linaro.org>
- posted [PATCH v2 0/5] semihosting read console support Message-Id:
<20191220132246.6759-1-alex.bennee(a)linaro.org>
[VIRT-109] <https://projects.linaro.org/browse/VIRT-109>
Completed Reviews [4/4]
=======================
{PATCH} Semihost SYS_READC implementation (v6)
Message-Id: <20191104204230.12249-1-keithp(a)keithp.com>
- CLOSING NOTE [2019-12-18 Wed 19:39]
Found some issues with deadlocks, fixed and sent my own series
including this patch.
Added: <2019-12-06 Fri>
[PATCH] docker: gtester is no longer used
Message-Id: <1576632611-55032-1-git-send-email-pbonzini(a)redhat.com>
- CLOSING NOTE [2019-12-20 Fri 12:20]
Queued to my tree
Added: <2019-12-18 Wed>
{Qemu-devel} {RFC PATCH} Implement qemu_thread_yield for posix, use it in mttcg to handle EXCP_YIELD
Message-Id: <20190717054655.14104-1-npiggin(a)gmail.com>
- CLOSING NOTE [2019-12-20 Fri 13:11]
Replied.
[PATCH v2 00/28] cputlb: Remove support for MMU_MODE*_SUFFIX
Message-Id: <20191216221158.29572-1-richard.henderson(a)linaro.org>
Absences
========
- Christmas and New Year holidays
Current Review Queue
====================
* [RFC PATCH 00/13] hw/timer/allwinner: Make it reusable
Message-Id: <20191219185127.24388-1-f4bug(a)amsat.org>
Added: <2019-12-19 Thu>
* [PATCH v2 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef
Message-Id: <20191218172009.8868-1-philmd(a)redhat.com>
Added: <2019-12-18 Wed>
* [RFC PATCH v3 000/132] Proof of concept for Meson integration
Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com>
Added: <2019-12-12 Thu>
* {PATCH 0/2} tests/acceptance: Add boot vmlinux test
Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com>
Added: <2019-12-06 Fri>
--
Alex Bennée
Progress (covers two weeks; lost half of last week to the cold that's
been going around the office here):
* VIRT-65 [QEMU upstream maintainership]
- code review
+ RTH's ARMv8.2-UAO patchset
+ RTH's ARMv8.1-PAN patchset
+ had a look at Huawei SDEI patchset; there are some things I don't
like about the approach but I don't currently have any better ideas :-(
Sent an email to the list to see if others have any suggestions.
+ Andrew Jones' patchset to pause the virtual timer when VM is paused
+ Some smmuv3 emulation fixes from Amazon
+ Support for emulating generic timers that run at platform-dependent
frequency (rather than insisting they always run at 62.5MHz)
- release work
+ herded a handful of key bugfixes into rc5; got rc5 and
then the final release out of the door
+ got new s390 box into the set of machines we test QEMU on
(IBM want to turn off the old one at the end of the year)
+ a couple of arm pull requests now 5.0 is open for new contributions
thanks
-- PMM
== Progress ==
* LLVM 9.0.1
- Had trouble with our TK1 machine
- Trying to build rc3 on one of the buildbots
- AArch64 rc3 looks fine
* Morello
- Got lldb-server working on android and it seems to behave fine
- Working on getting the lldb test-suite to work in remote mode with the
morello android simulator
- Running into all sorts of issues with it
== Plan ==
* More of the same
* Out of office: 25-26 December, 1-7 January
One cannot use objcopy --target=efi-app-aarch64 because it appears
that PE/COFF targets are not enabled for aarch64.
Making UEFI & Windows on Snapdragon work harder.
Given that Windows 10 is fully supported on aarch64, I assume it does
have PE/COFF.
Can someone please fix bfd to provide PE targets on aarch64?
--
Regards,
Dimitri.
== Progress ==
* GCC:
- -mpure-code on v6m: committed.
- investigated potential problem with -mno-unaligned-access. It was a
wrong-user-code case, but maybe it would be desirable to implement an
option like llvm's -arm-assume-misaligned-load-store
* BFD Linker:
- GNU-629: non-contiguous memory support: Now able to detect cases
where input sections change size during the linker iterations and when
linker-created stubs would cause overflows.
* GCC upstream validation:
- reported/checked a few issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* Holidays: Dec 23rd-Jan 2nd
There’s been an ongoing failure on the clang-cmake-armv8-selfhost
builder for the last day or so; see e.g.:
http://lab.llvm.org:8011/builders/clang-cmake-armv7-selfhost/builds/2827/
This list is recorded as the contact information for that builder.
It is apparently crashing in a tblgen backend that I just added:
```
Stack dump:
0. Program arguments:
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/stage1/bin/clang-tblgen
-gen-clang-type-writer -I
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include
-I
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include/clang/AST
-I
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/llvm/include
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include/clang/AST/TypeProperties.td
--write-if-changed -o
/home/buildslave/buildslave/clang-cmake-armv7-selfhost/stage1/tools/clang/include/clang/AST/AbstractTypeWriter.inc
Segmentation fault (core dumped)
```
I would like to fix this, but I have no ability to reproduce it, and the
crash information in the log is quite minimal. Is there a way I can get
a shell on a system that can reproduce this, or at the very least get a
line number for where exactly it is crashing?
John.
The Arm GNU Toolchain for the A-profile Architecture
=====================================================
We are pleased to announce the Arm release of the pre-built GNU cross-toolchain
for the A-profile cores: GCC 9.2-2019.12.
Further information about the GNU Arm toolchain and the release packages is
available at Arm Developer site
https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
Features
========
* Based on GCC 9.2 (See https://gcc.gnu.org/gcc-9/changes.html for details).
Supported targets
=================
* On Windows(x86_64):
- AArch64 (bare-metal and Linux)
- AArch32 (bare-metal and Linux hard-float)
* On Linux(x86_64):
- AArch64 (bare-metal, Linux and Linux big-endian)
- AArch32 (bare-metal and Linux hard-float)
* On Linux(AArch64)
- AArch64 (bare-metal)
- AArch32 (bare-metal and Linux hard-float)
Changes since Arm release GCC 8.3-2019.03
=========================================
* Additional AArch64 hosted cross-toolchains for AArch64 (bare-metal) and
AArch32 (bare-metal and Linux hard-float)
* Additional Windows hosted cross-toolchains for AArch64 (Linux) and
AArch32 (Linux hard-float)
* Retired Linux(x86_64) toolchain for AArch64 (big-endian bare-metal) and
AArch32 (Linux soft-float)
* Changed toolchain naming convention to match standard target triplet
naming convention, with vendor name being none.
For example, arm-eabi is now arm-none-eabi.
* Fixed the Windows toolchain convention to correctly include mingw-w64
instead of mingw32
Host Requirements
==================
* x86-64 Linux: Ubuntu 16.04 LTS or later, or RHEL 7 or later
* AArch64 Linux: Ubuntu 18.04 LTS or later, or RHEL 8
* x86 Windows: Windows 10
Package Versions
=================
* GCC 9.2.1
* glibc 2.30
* binutils 2.33.1
* GDB 8.3.0
* libexpat 2.2.5
* Linux Kernel v4.20.13
* libgmp 4.3.2
* libisl 0.15
* libmpfr 3.1.6
* libmpc 1.0.3
* libiconv 1.15
Contact Arm
===========
For any questions, please use the Arm Communities forums at:
https://community.arm.com/tools/
Please report any bugs via the Linaro Bugzilla at:
https://bugs.linaro.org/
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
* One day off
o LLVM:
* Couple of failures with the bots
* Machine Outliner:
- Completed testcases
- Validation before re-submission
o Misc
* Various meetings and discussions.
[VIRT-327 # Richard's upstream QEMU work ]
Following up on the feedback from last week on VHE and PAN, posted a patch set
eliminating MMU_MODE*_SUFFIX, and the current limit of NB_MMU_IDX <= 12 that
went with that.
Some patch review.
r~
== Progress ==
* GCC:
- -mpure-code on v6m: waiting for approval, pinged again.
* BFD Linker:
- GNU-629: non-contiguous memory support: Looking at how to handle the
case where input sections change size during the linker iterations.
* GCC upstream validation:
- reported/checked a few issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* GCC: pure-code/v6m, handle feedback
* Binutils: GNU-629: support non-contiguous memory regions in linker
== Future ==
Holidays: Dec 23rd-Jan 2nd
Morello:
- Updated clang driver to use lld with --image-base rather than a linker script.
- LLD changes merged.
- Fixed up a few problems spotted by CI and a test on the examples.
- Thoughts on code sequences for an experimental descriptor based ABI.
LLD:
- Committed changes to fix branch patch and thunks interaction in
instrumented Chromium build
- Discussion about deploying BTI in large programs like Chromium with
pre-compiled objects and lots of assembler files.
Planned absences
On holiday for the rest of the decade. First day back in the office 6th January
QEMU Tooling ([VIRT-252])
=========================
Extend gdbstub for SVE ([VIRT-281])
- worked on [v3 rebase]
- added a new test case and discovered a bug in upstream gdbserver
- raised [GNU-647] to track it
[v3 rebase] https://github.com/stsquad/qemu/tree/sve-registers-v3
[GNU-647] https://projects.linaro.org/browse/GNU-647
QEMU ARMv8.1 VHE ([VIRT_263])
=============================
- bunch of review and testing of rth's v4 series
[VIRT_263] https://projects.linaro.org/browse/VIRT-263
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v2 0/6} linux-user mmap debug cleanup Message-Id:
<20191206110354.GA775461(a)stefanha-x1.localdomain>
Completed Reviews [8/8]
=======================
{PATCH 0/3} iotests: Check for the possibility to create large files
Message-Id: <20191202101631.10003-1-thuth(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 10:14]
Preparatory for the multiarch Travis tests.
Added: <2019-12-02 Mon>
{PATCH v2 0/2} Run tcg tests with tci on Travis
Message-Id: <20191128153525.2646-1-thuth(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 10:21]
will take v3 with --disable-kvm and sparc tweaks
Added: <2019-11-28 Thu>
{PATCH 0/2} flush CPU TB cache in breakpoint_invalidate
Message-Id: <20191127220602.10827-1-jcmvbkbc(a)gmail.com>
- CLOSING NOTE [2019-12-03 Tue 11:20]
Needs a slightly neater solution than always flushing everything.
Added: <2019-11-28 Thu>
{PATCH 0/1} tests/vm: Allow to set path to qemu-img
Message-Id: <20191114134246.12073-1-wainersm(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 11:37]
Queued to my tree
Added: <2019-11-14 Thu>
{PATCH 0/4} docker: Update Travis-CI image to run acceptance tests
Message-Id: <20190818231827.27573-1-philmd(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 16:03]
Will wait for next iteration.
{PATCH 0/4} python/qemu: New accel module and improvements
Message-Id: <20191115180829.10275-1-wainersm(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 17:00]
All looks good. I assume will be merged with another series that
uses the new features.
Added: <2019-11-28 Thu>
{PATCH v7 0/8} Acceptance test: Add "boot_linux" acceptance test
Message-Id: <20191104151323.9883-1-crosa(a)redhat.com>
- CLOSING NOTE [2019-12-03 Tue 19:20]
Broken for me with load_module failure
Added: <2019-11-04 Mon>
{PATCH v4 00/40} target/arm: Implement ARMv8.1-VHE
Message-Id: <20191203022937.1474-1-richard.henderson(a)linaro.org>
- CLOSING NOTE [2019-12-06 Fri 18:35]
Reviewed about half the patch set, will do the remainder on v5 once
Peter's comments are addressed.
Added: <2019-12-03 Tue>
Current Review Queue
====================
* {PATCH} Semihost SYS_READC implementation (v6)
Message-Id: <20191104204230.12249-1-keithp(a)keithp.com>
Added: <2019-12-06 Fri>
* {PATCH 0/2} tests/acceptance: Add boot vmlinux test
Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com>
Added: <2019-12-06 Fri>
* {RFC PATCH 00/10} hw/avr: Introduce the Arduino board
Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org>
Added: <2019-11-28 Thu>
* {RFC 0/3} tests/vhost-user-fs-test: add vhost-user-fs test case
Message-Id: <20191025100152.6638-1-stefanha(a)redhat.com>
Added: <2019-10-25 Fri>
--
Alex Bennée
Morello:
- Static linking patches committed to merge branch.
- Dynamic linking patches up for review.
- Agreed definition of what LLD for stage-1 looks like.
- Discussions on what linker and ABI work is likely to be needed for stage-2.
Linaro:
Some LLD thunk/patch generation problems
https://bugs.llvm.org/show_bug.cgi?id=44071 for a gigantic build of
Chromium > 260 Mb .text section on AArch64. Diagnosed problems but
will need to fix next week.
Some support for ClangBuiltLinux with respect to some integrated
assembler compatibility with GNU as.
Buildbot duty.
Pretty quiet, attempted to reproduce some timeouts seen on the LNT
generate cmake. 3 minutes on an lightly loaded machine, exceeding 20
minutes in some cases on the heavily loaded buildbot host. Seems to
have resolved itself with the latest container update.
- Some changes to BTI for the Android team. All committed upstream.
-- Adding PT_GNU_PROPERTY support.
-- Increasing alignment of .note.gnu.property section to 8.
Holiday
- On holiday from Monday 16th to 3rd January inclusive. Back in office
January 6th.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review (have had a go at cutting down the backlog; down to
six patchsets in my queue...):
+ reviewed the 'clock framework API' patchset; this is
looking good, the only major question to sort out is what
the right internal representation for the clock frq/period is
+ Paolo's series to add kernel-doc support to our Sphinx
setup (which is a mashup of something I hacked together
ages ago and more recent work from him)
+ RAS memory error support for KVM guests (mostly
reviewing the easy bits and noting that others have
provided code review comments on the rest)
+ reviewed RTH's MemTag emulation series
+ reviewed the bits of RTH's VHE series that Alex hadn't got to
+ tested an arm/acpi patchset from Huawei from March
which had unfortunately fallen through the cracks.
It failed 'make check' so they'll need to fix and resubmit :-(
- release work:
+ we needed an rc4
+ and it looks like we'll need an rc5 for one last important
bugfix; I'm hoping we can do an rc and then actual release
a few days later, though
thanks
-- PMM
== Progress ==
* GCC:
- -mpure-code on v6m: waiting for approval, pinged again.
* BFD Linker:
- GNU-629: non-contiguous memory support: received some feedback.
Looking at how to handle the case where input sections change size
during the linker iterations.
* GCC upstream validation:
- reported/checked a few issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* GCC: pure-code/v6m, handle feedback
* Binutils: GNU-629: support non-contiguous memory regions in linker
== Progress ==
* LLVM 9.0.1
- Trying to bisect the arm failures
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Finished with the unexpected failures
- There are still some unexpected passes, but Omair has agreed to
look into them
* Morello
- Managed to build android and lldb-server, currently trying to see
if I can get them to work together
hi,I started implementing GDB process record and replay with ARM CoreSight as described in the rfc published early this year. Current implementation of coresight tracing in Perf is based on the sysfs interface, by accessing /sys/bus/event_source/devices/cs_etm ... file. GDB implementation of bts and ipt is based on the syscall "sys_perf_event_open".it would be nice to use the similar mechanism for realizing similar functionalities. therefore I would like to know if linux kernel (with coresight deivers) is exposing coresight drivers through the syscall sys_perf_event_open and if this is the case how shall I configure the perf_event_attr to use it.
thanks Zied Guermazi
# Progress #
o Upstream GDB
* ARM sim build failure with -fno-common
- Sent a patch to gdb-patches. Going through rounds of reviews.
* Patch reviewing and answering community questions.
o GDB
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Spent some more time with this in the hopes of understanding the
various failure modes. Still not clear if the kernel is doing the right
thing. It may be hard to adjust things on GDB's side, but i have a
couple patches solving some of the problems.
o Misc
* Updated personal information in the HR system.
# Plan #
o Upstream GDB
* Get approval for the fix to -fno-common build issues with ARM sim.
o GDB
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Engage with kernel folks for better understanding of signal
delivery scheme. Polish current fixes and submit for review.
o LLVM:
* Machine Outliner:
- Disabled asm statements.
- Added Helium LD/ST instructions support
- Adding testcases
o Misc
* Various meetings and discussions.
7 working days, then Thanksgiving.
[VIRT-262 # ARMv8.1-PAN Privileged Access Never]
Finished, still need to post.
[VIRT-273 # ARMv8.2-ATS1E1, AT S1E1R and AT S1E1W instruction variants ]
Finished, still need to post.
[VIRT-276 # ARMv8.2-UAO, PSTATE override of Unprivileged Load/Store ]
Finished, still need to post.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
FIXED! Welsh sprint with AJB; found and fixed two bugs.
Final bug causing guest kernel crash while booting fixed
upstream by Marc Zyngier vs ptrauth.
Will do some more thorough testing during rc4 and post
once the development phase opens up again.
[VIRT-327 # Richard's upstream QEMU work ]
Review of target/hexagon skeleton.
Review of arm dcpop patch set for beata.
Fixed a couple of arm translator bug for clyon.
Some investigation into a reported hppa-linux-user bug.
While I can reproduce locally, so far I have not tracked
down anything that I can prove is a translation bug.
r~
QEMU Tooling ([VIRT-252])
=========================
Extend gdbstub for SVE ([VIRT-281])
- worked on [v2 rebase addressing comments]
- posted {PATCH v2 00/14} gdbstub refactor and SVE support Message-Id:
<20191130084602.10818-1-alex.bennee(a)linaro.org>
[VIRT-281] https://projects.linaro.org/browse/VIRT-281
[working prototype]
https://github.com/stsquad/qemu/tree/gdbstub/sve-registers
[v2 rebase addressing comments]
https://github.com/stsquad/qemu/tree/gdbstub/sve-registers-v2
QEMU ARMv8.1 VHE ([VIRT_263])
=============================
- inaugural Welsh code sprint with rth
- found some new bugs, squashed some old bugs
- together with recent upstream fixes SUCCESS!
- can now boot a guest from a VHE enabled kernel :-)
[VIRT_263] https://projects.linaro.org/browse/VIRT-263
Upstream Work ([VIRT-109])
==========================
- posted {PULL for 4.2 0/3} a few vm-test fixes Message-Id:
<20191126120339.18059-1-alex.bennee(a)linaro.org>
- there are still niggling netbsd failures
- posted {PATCH for 4.2?} .travis.yml: drop xcode9.4 from build matrix
Message-Id: <20191127132430.3681-1-alex.bennee(a)linaro.org>
- investigation into [ARM HPC compiler triggered linux-user bug]
- may be 64k page related as couldn't reproduce on Ubuntu
- posted {PATCH v1 0/5} linux-user mmap debug cleanup Message-Id:
<20191128194603.24818-1-alex.bennee(a)linaro.org>
[ARM HPC compiler triggered linux-user bug]
https://bugs.launchpad.net/qemu/+bug/1853826
Other Activities
================
- published [QEMU Summit and KVM Forum trip report]
[QEMU Summit and KVM Forum trip report]
https://collaborate.linaro.org/display/CR/20191030+QEMU+Summit+and+KVM+Foru…
Absences
========
- 2nd Dec Holiday
Current Review Queue
====================
* {PATCH 0/4} python/qemu: New accel module and improvements
Message-Id: <20191115180829.10275-1-wainersm(a)redhat.com>
Added: <2019-11-28 Thu>
* {PATCH v2 0/2} Run tcg tests with tci on Travis
Message-Id: <20191128153525.2646-1-thuth(a)redhat.com>
Added: <2019-11-28 Thu>
* {PATCH 0/2} flush CPU TB cache in breakpoint_invalidate
Message-Id: <20191127220602.10827-1-jcmvbkbc(a)gmail.com>
Added: <2019-11-28 Thu>
* {RFC PATCH 00/10} hw/avr: Introduce the Arduino board
Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org>
Added: <2019-11-28 Thu>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ finally got back to the reset-refactoring patchset
and gave review on v5 of that. This is very nearly ready.
+ reviewed and got into 4.2 rc3 some patches from Marc Z
fixing some missing emulation/bugs that newer Linux
guest kernels trip over
+ rc3 out of the door; we will need an rc4, though
- more time consumed by office-move
thanks
-- PMM
[Morello]
Rebase of LLD against September CUCL update complete
- Painful due to LLD changing address layout (every test expected
value shifted), and a naming convention change.
- No functional changes needed to patch.
- Submitted static linking patches for review. Will send the dynamic
ones after all static linking has been merged.
Wrote up notes of Linaro Tech-leads Morello Q&A.
Misc:
Upstream LLD reviews
== Progress ==
* Out of office on Thursday
* LLVM 9.0.1
- Uploaded ARM & AArch64 binaries for rc1
- ARM: opened 2 bug reports (asan and cfi tests failing)
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Opened a few more bug reports
- Got one nasty failure that I want to look into a bit more before
committing a patch XFAIL-ing everything so far
* Morello
- Got a VM working, built the toolchain, currently trying to build android
- Setting up all sorts of gerrit accounts and other minutiae
== Plan ==
* More of the same
Hi!
I've attempted to study the implementation of memcpy for 32-bit Arm cores in
Glibc (which is also found in arm-optimized-routines and first appeared in
Linaro's cortex-strings project), and I came across a peculiar snippet:
#ifdef USE_VFP
/* Magic dust alert! Force VFP on Cortex-A9. Experiments show
that the FP pipeline is much better at streaming loads and
stores. This is outside the critical loop. */
vmov.f32 s0, s0
#endif
This seems to imply that this NOP-like instruction affects CPU state and makes
the vldr/vstr instructions that follow use different datapaths that they might
otherwise? Can anyone shed more light on this, please?
I was able to trace history of this code back to revision 100 in cortex-strings
repository, where it appeared as part of a large rewrite by Will Newton:
https://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/rev…
The entire memcpy.S file in Arm optimized-routines repo can be found here:
https://github.com/ARM-software/optimized-routines/blob/master/string/arm/m…
Thanks!
Alexander
Hi Arnd,
I took a look on the stack usage issue in the kernel snippet you provided [1],
and as you have noted the most impact indeed come from -ftree-ch optimization.
It is enabled in all optimization levels besides -Os (since besides possible
increasing the stack usage it also might increase code side).
I am still fulling grasping what free-ch optimization does, but my understanding
so far is it tries to reorganize the loop for later loop optimization phases.
More specifically, what it ends up doing on the specific snippet is create extra
stack variables for the internal membber access in the inner loop (which in its
turns increase stack usage).
This is also why adding the compiler barrier inhibits the optimization, since it
prevents the ftree-ch to optimize the internal loop reorganization and it is
passed as is to later optimizations phases.
It is also a generic pass that affects all architecture, albeit the resulting
stack will depend on later passes. With GCC 9.2.1 I see the resulting stack
usage using -fstack-usage along with -O2:
arm 632
aarch64 448
powerpc 912
powerpc64le 560
s390 600
s390x 632
i386 1376
x86_64 784
Also, -fconserve-stack does not really help with this pass since ftree-ch does
not check the flag usage. The fconserve-stack currently only seems to effect
the inliner by setting both large-stack-frame and large-stack-frame-growth to
some conservative values.
The straightforward change I am checking is just to disable tree-ch optimization
if fconserve-stack is also enabled:
diff --git a/gcc/tree-ssa-loop-ch.c b/gcc/tree-ssa-loop-ch.c
index b894a7e0918..b14dd66257c 100644
--- a/gcc/tree-ssa-loop-ch.c
+++ b/gcc/tree-ssa-loop-ch.c
@@ -291,7 +291,8 @@ public:
{}
/* opt_pass methods: */
- virtual bool gate (function *) { return flag_tree_ch != 0; }
+ virtual bool gate (function *) { return flag_tree_ch != 0
+ && flag_conserve_stack == 0; }
/* Initialize and finalize loop structures, copying headers inbetween. */
virtual unsigned int execute (function *);
On powerpc64le with gcc master:
$ /home/azanella/gcc/gcc-git-build/gcc/xgcc -B /home/azanella/gcc/gcc-git-build/gcc -O2 ../stack_usage.c -c -fstack-usage && cat stack_usage.su
../stack_usage.c:157:6:mlx5e_grp_sw_update_stats 496 static
$ /home/azanella/gcc/gcc-git-build/gcc/xgcc -B /home/azanella/gcc/gcc-git-build/gcc -O2 ../stack_usage.c -c -fstack-usage -fconserve-stack && cat stack_usage.su
../stack_usage.c:157:6:mlx5e_grp_sw_update_stats 176 static
The reference for minimal stack usage is with -Os:
$ /home/azanella/gcc/gcc-git-build/gcc/xgcc -B /home/azanella/gcc/gcc-git-build/gcc -Os ../stack_usage.c -c -fstack-usage && cat stack_usage.su
../stack_usage.c:157:6:mlx5e_grp_sw_update_stats 32 static
I will try to check if also enable the same test for -fgcse and -free-ter
do make sense.
[1] https://godbolt.org/z/WKa-Bd
# Progress #
o Upstream GDB
* Make remote packet length in debugging output adjustable (as
opposed to fix to 512 bytes).
* Investigated ARM sim build issues with the GCC default moving to
-fno-common.
o GDB:
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- No progress yet. Waiting for Kernel feedback.
* [RESOLVED] GNU-645 - gdbserver is not using SVE register
descriptions properly
- Pushed a fix upstream.
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- On hold for now.
o Friday off
# Plan #
o Upstream GDB
* Fox -fno-common build issues with ARM sim.
o GDB
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Continue working on a fix.
== This Week ==
* GCC
- PR92554: Spent some time triaging the issue, but gave up after
Richard posted better fix.
- PR89007: Addressing upstream suggestions.
- PR92608: Committed fix to trunk.
- GNU-583: Looking thru Kugan's patch and upstream discussion.
* Validation
- Submitted patch to add --gcc_patch_file option to abe.
- Submitted patch to remove --interactive from abe.
== Next Week ==
- Continue ongoing tasks
== Progress ==
* GCC:
- -mpure-code on v6m: sent an updated patch, waiting for approval.
* BFD Linker:
- non-contiguous memory support: partial prototype working on the
use-case, but causes regressions.
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* GCC: pure-code/v6m, handle feedback
* Binutils: support non-contiguous memory regions in linker
QEMU Tooling ([VIRT-252])
=========================
Extend gdbstub for SVE ([VIRT-281])
- worked on [v2 rebase addressing comments]
[VIRT-281] https://projects.linaro.org/browse/VIRT-281
[v2 rebase addressing comments]
https://github.com/stsquad/qemu/tree/gdbstub/sve-registers-v2
Upstream Work ([VIRT-109])
==========================
- general poking around and stress testing on the run up to release
- documented some outstanding issues [on the planning page]
- posted {PULL for rc3 0/5} a few doc and testing tweaks Message-Id:
<20191120105801.2735-1-alex.bennee(a)linaro.org>
- posted {PATCH for 4.2 v1 0/3} some tests/vm fixes Message-Id:
<20191122112231.18431-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[on the planning page] https://wiki.qemu.org/Planning/4.2
Other Activities
================
- finalising [draft of KVM Forum conference report]
- will publish on Monday once Beata adds the last note
[draft of KVM Forum conference report]
https://collaborate.linaro.org/pages/resumedraft.action?draftId=128647720
Completed Reviews [3/3]
=======================
{PATCH v2 0/6} Make the qemu_logfile handle thread safe.
Message-Id: <20191115131040.2834-1-robert.foley(a)linaro.org>
- CLOSING NOTE [2019-11-22 Fri 17:15]
Ad of v3 this is ready to go, just awaiting the tree to open again
Added: <2019-11-15 Fri>
{PATCH v3 0/6} Make the qemu_logfile handle thread safe.
Message-Id: <20191118211528.3221-1-robert.foley(a)linaro.org>
{PATCH 0/6} Enable Travis builds on arm64, ppc64le and s390x
Message-Id: <20191119170822.45649-1-thuth(a)redhat.com>
Current Review Queue
====================
* {PATCH 0/1} tests/vm: Allow to set path to qemu-img
Message-Id: <20191114134246.12073-1-wainersm(a)redhat.com>
Added: <2019-11-14 Thu>
* {PATCH v7 0/8} Acceptance test: Add "boot_linux" acceptance test
Message-Id: <20191104151323.9883-1-crosa(a)redhat.com>
Added: <2019-11-04 Mon>
* {RFC 0/3} tests/vhost-user-fs-test: add vhost-user-fs test case
Message-Id: <20191025100152.6638-1-stefanha(a)redhat.com>
Added: <2019-10-25 Fri>
* {PATCH v5 00/22} target/arm: Implement ARMv8.5-MemTag, system mode
Message-Id: <20191011134744.2477-1-richard.henderson(a)linaro.org>
Added: <2019-10-11 Fri>
--
Alex Bennée
[Morello]
- LLD finished pre-review refactoring and splitting up into reviewable chunks
- Implemented range-extension and interworking thunks to test
interaction with aligning .text to comply with Cheri Concentrate
- Answered some questions from Linaro tech-leads about Morello
Plans
- Rebase once CUCL merge has been completed and submit for review.
Planned Absences:
Christmas Holiday 16th December - 3rd January inclusive
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ Marc-Andre's series trying to get rid of QOM pointer properties
+ various minor bits for rc2
- unsuccessfully tried to work out why one of QEMU's test
cases asserts on BSD hosts only
- some time consumed by office-move
thanks
-- PMM
== Progress ==
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Opened 4 bug reports
- One of them got a lot of attention so I was asked to upload more
logs/try various things
- Still have a couple of test failures to look into
* Morello
- First contact with the team
- Started looking at the internal docs
- Trying to build the existing toolchain
== Plan ==
* Figure out the current state of LLDB for Morello and what needs to be done
* Continue triaging LLDB failures
Dear Linaro,
Dear Linaro I'm using arm cortex A53 (mt6735 [part number]). But I do not know which tool-chain I have to use. I found your website https://www.linaro.org/downloads/ on internet. and my guess is aarch64-linux-gnu. can you please guide me through selecting a proper tool-chain.
Regards,
Saeed Djamali
# Progress #
o Upstream GDB
* More patch reviewing and answering questions.
o GDB:
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Managed to track this down all the way to the aarch64
single-stepping infrastructure in the kernel. Created reproduction steps
and sent an e-mail to linux-arm-kernel
- Also noticed a difference in the order in which SIGCHLD's are
delivered between x86_64 and aarch64. This confused GDB, which expects
the ordering it sees on x86_64. Working on a fix.
* Tweaked QEMU setup a little for SVE testing
* GNU-645 - gdbserver is not using SVE register descriptions properly
- Tracked down why gdbserver is not sending SVE register data back
to GDB. Working on a fix.
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- On hold for now.
# Plan #
o GDB
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Continue working on a fix.
* GNU-645 - gdbserver is not using SVE register descriptions properly
- Continue working on a fix.
[VIRT-262 # ARMv8.1-PAN Privileged Access Never]
Started, based on VHE patch set due to mmu_idx reorg therein.
Needs some minor re-work to handle Secure EL1.
[VIRT-273 # ARMv8.2-ATS1E1, AT S1E1R and AT S1E1W instruction variants ]
Started.
[VIRT-327 # Richard's upstream QEMU work ]
Some soft-freeze bug fixing of stuff that I broke this cycle.
Some patch review.
[Kernel]
Posted v7 of the ARMv8.5-RNG patch set. There's some significant
mis-communication going on between me and Mark Rutland; I have no
idea what he wants at this point...
[GCC]
Committed the base asm-flags patch set. Posted a follow-up
to un-break thumb1, and add tests for it.
r~
== This Week ==
* GCC
- PR89007: Posted patch upstream.
- GNU-583: Worked with Kugan, to reproduce LTO failure and verified
his patch fixes it.
- Bug 5479: Investigated with Maxim, most likely a glibc issue.
* Validation:
- Posted abe patch to add --gcc_patch_file option.
== Next Week ==
- Continue ongoing tasks.
Monday off
== Progress ==
* GCC:
- -mpure-code on v6m: answered questions about my patch. Almost OK
* Linker:
- started looking at implementing non-contiguous memory support
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* GCC: pure-code/v6m, handle feedback
* Binutils: support non-contiguous memory regions in linker
[Morello]
- Dynamic linking implementation complete and tests written based on
GNU ld output.
- Good progress on refactoring the work prior to breaking it down into
reviewable chunks. Have got a good idea of what I'd like the
implementation to look like.
TODO:
- Finish refactoring patches.
- Rebase into reviewable patches.
- Document the design decisions.
- Test on more than just the examples in the toolchain.
- Rebase on top of latest CUCL drop when merge is finished.
[Other]
LLVM-MC upstream review for the Linux Kernel.
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- feature now merged in 4.2
- closed out a bunch of related JIRA cards
- API version now merged and this card is closed
Extend gdbstub for SVE ([VIRT-281])
- posted {RFC PATCH 00/11} gdbstub re-factor and SVE support
Message-Id: <20191115173000.21891-1-alex.bennee(a)linaro.org>
[VIRT-281] https://projects.linaro.org/browse/VIRT-281
[working prototype]
https://github.com/stsquad/qemu/tree/gdbstub/sve-registers
Upstream Work ([VIRT-109])
==========================
- posted {PULL 0/8} testing and tcg plugin api ver Message-Id:
<CAFEAcA_9AwoTE9zaKbiF6DkpN+O8LaEKGOct-m5S3yvFBHGK1g(a)mail.gmail.com>
- posted {PATCH for 4.2-rc2 v1 0/5} misc doc and testing fixes
Message-Id: <20191113115952.775-1-alex.bennee(a)linaro.org>
- posted {RFC PATCH} scripts/tap-driver: report "slow" tests (HACK)
Message-Id: <20191113142101.30280-1-alex.bennee(a)linaro.org>
Other Activities
================
- wrote [draft of KVM Forum conference report]
[draft of KVM Forum conference report]
https://collaborate.linaro.org/pages/resumedraft.action?draftId=128647720
Completed Reviews [5/5]
=======================
{PATCH 0/2} replace sysconf(_SC_PAGESIZE) with qemu_real_host_page_size
Message-Id: <20191015031350.4345-2-richardw.yang(a)linux.intel.com>
{PATCH v2 0/4} arm/aspeed: Watchdog and SDRAM fixes
Message-Id: <20191113005201.19005-1-joel(a)jms.id.au>
{kvm-unit-test PATCH 0/5} Improvements for the Travis CI
Message-Id: <20191113112649.14322-6-thuth(a)redhat.com>
{PATCH} target/arm: Clean up arm_cpu_vq_map_next_smaller asserts
Message-Id: <20191115131623.322-1-richard.henderson(a)linaro.org>
{PATCH v1 0/5} Make the qemu_logfile handle thread safe.
Message-Id: <20191112150105.2498-1-robert.foley(a)linaro.org>
Current Review Queue
====================
* {PATCH v2 0/6} Make the qemu_logfile handle thread safe.
Message-Id: <20191115131040.2834-1-robert.foley(a)linaro.org>
Added: <2019-11-15 Fri>
* {PATCH 0/1} tests/vm: Allow to set path to qemu-img
Message-Id: <20191114134246.12073-1-wainersm(a)redhat.com>
Added: <2019-11-14 Thu>
* {PATCH v7 0/8} Acceptance test: Add "boot_linux" acceptance test
Message-Id: <20191104151323.9883-1-crosa(a)redhat.com>
Added: <2019-11-04 Mon>
* {RFC 0/3} tests/vhost-user-fs-test: add vhost-user-fs test case
Message-Id: <20191025100152.6638-1-stefanha(a)redhat.com>
Added: <2019-10-25 Fri>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
- wrote up first draft of requirements for the better CI setup for
testing pull request merge builds
(https://wiki.qemu.org/Requirements/GatingCI)
- wrote up version of the QEMU Summit minutes that includes enough
context to make sense to people who weren't present; plan to
send to qemu-devel next Friday
- got 4.2 rc1 out of the door; this release seems to be pleasantly
quiet for a change.
thanks
-- PMM
== Progress ==
* Committed SVE-related fix for InstCombine
* Started triaging check-lldb failures on AArch64 [LLVM-512]
- Committed a trivial fix for one of the tests
- Still looking into the other failures
* Received and setup laptop for Morello work
- Awaiting further instructions
== Plan ==
* Start working on Morello
* Keep triaging check-lldb failures
* If time permits, look into SVE asserts some more
# Progress #
o Annual Review
* Concluded
o Upstream GDB
* Patch reviews on gerrit and answering questions.
* Fixed PR25124 - [ARM] regression: thumb-bx-pc.exp
(https://sourceware.org/bugzilla/show_bug.cgi?id=25124)
* Investigated an odd failure in gdb.base/step-over-syscall.exp and
ended up finding some odd stepping behavior that may or may not be
kernel related. Still investigating under GNU-644
(https://projects.linaro.org/browse/GNU-644)
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- On hold for now. It would be nice to be able to use a NOP instead
of a dummy label + jump.
* Setup QEMU for running SVE bits and reproduced some SVE hiccups in
gdbserver that Alex mentioned.
* Misc discussions about SVE and the GDB implementation in general.
# Plan #
o Upstream GDB
* More patch reviewing and answering questions.
o GDB:
* GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures
- Continue investigating
* Tweak QEMU setup a little for SVE testing
== Progress ==
* GCC:
- -mpure-code on v6m: no feedback yet
* Linker:
- started looking at implementing non-contiguous memory support
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* GCC: pure-code/v6m, handle feedback
* Binutils: support non-contiguous memory regions in linker
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Reworked the timer redirection. Now the EL2 and EL0 redirection
is unified, which is a bit easier to understand. Still no joy
working out where the unwanted interrupt is coming from. As far
as I can tell everything is plumbed correctly...
I'll shelve this until PMM is not swamped with release work.
It must wait for 5.0 for merging anyway.
[VIRT-327 # Richard's upstream QEMU work ]
Assorted patch review.
[Kernel]
Posted two more rounds of ARMv8.5-RNG for review. Seems I'd
misunderstood one of Mark's previous suggestions, and Ard changed
his mind about how RNDR vs RNDRRS should be used in the context
of the shared resource across host*CORES + virt*VCPUS.
[GCC]
Posted an implementation of asm-flag-output for AArch32+AArch64.
I should have done this years ago. There are two potential users
within the kernel, and one is access_ok() which has thousands
of uses. (Oh, and RNG, which has like 3 uses. :-P)
Reviewed some arm simd patches that caught my eye.
r~
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- feature now merged in 4.2
- closed out a bunch of related JIRA cards
- posted {PATCH} tcg plugins: expose an API version concept
Message-Id: <20191104131836.12566-1-alex.bennee(a)linaro.org>
- requested by Peter before hardfreeze
Extend gdbstub for SVE ([VIRT-281])
- got a [working prototype]
- probably need a little core gdbstub re-factor before posting RFC
[VIRT-281] https://projects.linaro.org/browse/VIRT-281
[working prototype]
https://github.com/stsquad/qemu/tree/gdbstub/sve-registers
Upstream Work ([VIRT-109])
==========================
- posted {PULL v3 00/15} testing updates Message-Id:
<20191025193709.28783-1-alex.bennee(a)linaro.org>
- had to drop NetBSD autobuild (again)
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[branch]
https://github.com/stsquad/qemu/tree/testing/docker-multiarch-refactor
[testing/next] https://github.com/stsquad/qemu/tree/testing/next
Other Activities
================
- Presented at KVM Forum
- went down well, made a number of contacts who are interested
- A bunch of discussion on Hexagon
- More detailed write-up to follow
Completed Reviews [4/4]
=======================
{PATCH 0/5} travis.yml improvements: Update libraries, build with arm64
Message-Id: <20191009170701.14756-1-thuth(a)redhat.com>
- CLOSING NOTE [2019-10-18 Fri 19:04]
Pulled some bits into testing/next
Added: <2019-10-09 Wed>
{PATCH} Semihost SYS_READC implementation (v4)
Message-Id: <20191024224622.12371-1-keithp(a)keithp.com>
{PATCH v2 0/4} target/arm: Support for Data Cache Clean up to PoP
Message-Id: <CADSWDztHetgmbUOp4WyRAkR0daAG6kkwhUTcyKWiCTWHQ1XB=w(a)mail.gmail.com>
{PATCH 0/4} Make the qemu_logfile handle thread safe.
Message-Id: <20191107142613.2379-1-robert.foley(a)linaro.org>
Absences
========
- KVM Forum Oct 29th-Nov 1st
Current Review Queue
====================
* {PATCH v7 0/8} Acceptance test: Add "boot_linux" acceptance test
Message-Id: <20191104151323.9883-1-crosa(a)redhat.com>
Added: <2019-11-04 Mon>
* {RFC 0/3} tests/vhost-user-fs-test: add vhost-user-fs test case
Message-Id: <20191025100152.6638-1-stefanha(a)redhat.com>
Added: <2019-10-25 Fri>
* {PATCH v5 00/22} target/arm: Implement ARMv8.5-MemTag, system mode
Message-Id: <20191011134744.2477-1-richard.henderson(a)linaro.org>
Added: <2019-10-11 Fri>
* {PATCH v4 0/9} target/arm/kvm: enable SVE in guests
Message-Id: <20190924113105.19076-1-drjones(a)redhat.com>
Added: <2019-09-24 Tue>
--
Alex Bennée
Morello
- Started to document the LLD implementation.
- Implemented CHERI concentrate alignment for the important sections.
- Dynamic linking is feature complete, but not finished yet, still Todo:
-- More test cases for the various different combinations.
-- Refactor to clean up the implementation.
-- Rebase all the patches to remove the false starts.
-- Update the documentation I've just started as it is already out of date.
-- Not looked at ifunc or TLS yet.
llvm-mc
Some review on MC patch to allow limited symbolic computation when
evaluating .if
Progress / KVM Forum trip report:
* As usual, we held the QEMU Summit at the same time as the forum;
this is an hour-or-two invitation only meeting of the top 20 or
so maintainers/submaintainers, discussing process and other project
issues. A proper summary/writeup of the minutes will be posted to
qemu-devel later, but IMHO this year the most interesting topics were:
- Spreading the load of managing pull request merges; currently
I do this with the aid of some hand-hacked scripts. To be able
to spread this work among more people we need to replace that
with a more maintained and standardized CI/testing setup. RedHat
have agreed to provide some people to work on at least the initial
setup part of this, and we got some consensus that the approach to
take was to use Gitlab with some custom 'runners' to handle the
'build/test on aarch64/ppc/s390x/etc' parts.
- We talked about the project's general stance on 'plugin' interfaces;
which can be controversial both because they commit us to maintaining
a stable API/ABI and because they have the potential to be used to
work around the GPL (eg proprietary device models). We plan to
write up some guidelines here (mostly just writing down the
existing consensus).
- We also talked (again) about our handling of security issues and
CVEs. My impression is that there are some parts of this that
people aren't hugely happy with but that nobody has the time/effort to
try to improve things (eg better documentation/tracking of issues,
more prompt upstream point releases with security fixes), so things
are likely to stay about as they are now.
* Interesting talks (videos are being uploaded to:
https://www.youtube.com/channel/UCRCSQmAOh7yzgheq-emy1xA ):
- 'The Hype Around the RISC-V Hypervisor' : the RISC-V architecture's
hypervisor extension isn't completely finalized yet, but it's far
enough advanced that KVM support and also QEMU emulation of it have
been written. An amusing sign of the architecture's academic
underpinnings is that this first version doesn't have any hardware
acceleration of the interrupt controller, but does have full
nested-virtualization support.
- 'ZERO: Next Generation Virtualization Platform for Huawei Cloud':
Huawei describe hardware for a cloud environment which offloads
as much as possible of the hypervisor work to custom I/O cards
and a custom silicon cloud-control device, in a general approach
that's probably familiar to anybody who watched the Amazon Nitro
presentation from the other year.
- 'What's Going On? Taking Advantage of TCG's Total System Awareness':
Alex Bennée's talk on the introspection plugin work we've been doing
in Linaro (and which will be in QEMU 4.2).
- 'Playing Lego with Virtualization Components':
description of the Rust 'rust-vmm' set of libraries intended to
provide useful building blocks for putting together virtual machine
managers (like Firecracker, crosvm). Basically similar content to
a presentation they did for Cambridge University earlier this year,
but this talk's been recorded so is good if you weren't in the audience
the first time around.
* And as always the in-person networking is valuable:
- Oracle have a "split device emulation into separate processes" idea
that's alarmingly invasive of the source code, but Stefan came up
with an approach that might let them do what they need without making
the source code harder to work with for the rest of us.
- Met the RedHat person who's going to do the CI-for-pullreqs work
(see QEMU Summit item earlier) : getting this unstalled was probably
the most useful concrete outcome of the conference
- Finally met Aurelien Jarno (a longstanding hobbyist contributor
to QEMU who usually can't attend these conferences)
* While at the conference Drew and I managed to finally get the
SVE support for KVM guests into master (the last hurdle was an awkward
test failure on the aarch32-compat-on-aarch64-kernel setup I happen
to use as one of my build test environments; we don't care about whether
KVM really works in this setup but we need 'make check' to not fail)
* Also managed to fit in some wrangling of pull requests; the timing
of the 4.2 release unfortunately put softfreeze on the Tuesday
before the conference and rc0 on the Tuesday afterwards; rc0
ended up being postponed a couple of days as a consequence.
thanks
-- PMM
Linaro
- On buildbot monitoring duty, relatively quiet week with just a
couple of fairly simple to diagnose problems to report.
Morello
- Dynamic linking progressing albeit slowly.
-- Trying to work out the requirements from existing documents and
implementation.
-- Have some simple cases doing mostly the right thing and have
written some tests.
-- Will need to rewrite to move calculations earlier in the link-step.
-- Morello is quite different from Cheri in this regard so I have had
to diverge much more from the implementation.
Tree:
https://github.com/rth7680/qemu.git tgt-arm-vhe-5
Testcase:
qemu-test:~rth/linux/initramfs-min.cpio.gz
The host kernel could be anything, but I've been using
the same Image.gz that is inside the cpio archive.
./aarch64-softmmu/qemu-system-aarch64 -m 4G \
-M virt,virtualization=on,gic-version=max -cpu max \
-kernel Image.gz -initrd initramfs-min.cpio.gz
At the shell prompt, ./test will run a guest kernel with kvm.
As momentarily discussed with PMM in the hallway:
As soon as the guest kernel enables interrupts,
arch_timer_starting_cpu
enable_percpu_irq
irq_percpu_enable
gic_unmask_irq
-- Incorrect exception delivery.
the GTIMER_PHYS interrupt is delivered to EL2 (seems to be ok), the host kernel
does something (haven't dug into what exactly, bug presumably setting bits that
are supposed to pass the virq to the guest), and immediately another interrupt
is delivered to EL2. Repeat.
Whether this is incorrect routing of the virq interrupt, or incorrect
masking/acking of the hard irq interrupt at EL2, I do not yet know.
PMM: I don't know the answer to either (a) or (b) as asked on hangouts. I
think (b) is correct, but I can't be sure. I'm trying to understand how (a) is
supposed to work now. In particular, I can't find any code that sets
HCR_EL2.{VI,VF}, only tests them.
r~
# Progress #
o Ramp up
* Concluded.
o Annual Review
* Attended discussions.
o Upstream GDB
* Patch reviews on gerrit.
* Answered questions.
* The state of ARM/AArch64 GDB upstream seems to be reasonable, with
a few failures here and there. Numerous failures on problematic racy
tests (gdb.threads).
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Spent some more time on this and improve the patch further,
covering most problematic cases for "for", "while" and "do/while" loops.
* Read some documentation on setting up Fast Models for testing MVE
(Helium).
* Inspected various aspects of ARM support in GDB, like SVE, PAC and
ACLE.
# Plan #
o Annual Review
* Conclude.
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Discuss with gcc@ a bit more about my proposed solution.
* Attempt to setup system QEMU and/or Fast Model for testing ACLE SVE
and, maybe, MVE.
== Progress ==
* Out of office 1 day
* Buildbot monitoring
- Moved the buildbots to pull from github
* Trying to setup a build environment on ex40-01
- Gave up on the tcwg-sq-01/2 boards because they seemed too unstable
* Still no access to Morello docs
* Playing with lldb python scripting
- Got a script that intercepts all calls to
VectorType::getNumElements that don't come from a getElementCount
(since that likely means that they won't be preserving the 'scalable'
property)
- This should help figure out problems spotted by the fuzzer
- Likely needs a bit more refining
== Plan ==
* More of the same
* Out of office on Friday (1 November)
== Progress ==
* GCC:
- -mpure-code on v6m: no feedback yet
* FDPIC/GDB
- problems with the board I used, it hangs shortly after or during
boot. None of the workaround/fixes suggested to me worked. Having an
stm32 qemu config would help.
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
- sent 2 small qemu patches (fix vmrs support for m-profile, and add cortex-m7)
- confirmed that gcc LTO profiled bootstrap works on arm with recent
trunk, although it takes ages. Will need to try on a more powerful
board
== Next ==
* Holidays next week, back Nov 4th
* FDPIC: resume work on GDB: check the various qemu forks with stm32
board support.
Add FDPIC configuration in the GCC trunk validation.
* GCC: pure-code/v6m, handle feedback
* Binutils: support non-contiguous memory regions in linker
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ lots of wrangling of patches and pulls since I'm away
next week and it's also going to be softfreeze
+ preparation for KVM Forum next week
thanks
-- PMM
Progress:
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Updates for user-only.
Merge bug fixes from eugeni.stepanov(a)gmail.com.
[VIRT-349 # QEMU SVE2 Supprt ]
Convert neon pmul helpers to a form that will be usable for sve2.
[VIRT-327 # Richard's upstream QEMU work ]
Pull for tcg-next.
Review plugins v5.
Update for capstone submodule.
Started reviewing multi-phase reset v5.
[Kernel]
Hacked up a patch for ARMv8.5-RNG.
r~
# Progress #
o Ramp up
* Credentials, machine access and LDAP updates done.
o Qualcomm Landing Team sunsetting
* Returned Qualcomm's Laptop.
o Upstream GDB
* Ramping up on reviews.
* Gathering data on the current state of GDB on ARM.
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Came up with a little hack/proof-of-concept to get this fixed.
Though ugly, it seems fixing this in the front-end may make more sense,
as the information i need (source line) is easily accessible in there.
- Discussion ongoing with gcc@. GDB clearly needs the compiler to
provide more information.
* Created JIRA cards for all known pending ARM tasks for GDB, based
on Alan's and Joey's input. TODO-ed all of them for the time being.
# Plan #
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Continue pursuing a fix.
* Prioritize GDB JIRA cards and start work on them.
[Morello]
- Got static linking support to the point that I can successfully link
with LLD the coremark, dhrystone and EEMBC from the arran-toolchain.
Not got any outstanding failures to investigate.
- Altered LLD so a linker script is no longer necessary for newlib.
- Started the process of rebasing and adding tests for all the
fixes/hacks I needed to make to the linker work.
- Aligned the base and limit of capabilities according to the incoming
CHERI concentrate scheme. Interesting question of what should a linker
do when alignment requirements on the base and limit cross section
boundaries, and what are the responsibilities for an object producer
when creating a section when the length of the capability is known at
compile time.
Planned absences:
Holiday Thursday, Friday (24th, 25th October)
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ finishing off the ptimer API transition work
+ review of rth's "speed up calculation of tbflags" patchset
+ put together and sent an arm pullreq
* VIRT-350 [Update Arm KVM support in QEMU]
+ the patchset for hotpluggable RAM support is now upstream
thanks
-- PMM
== Progress ==
* GCC:
- Work on -mpure-code on v6m. Patches sent for upstream review.
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* FDPIC: resume work on GDB
* GCC: pure-code/v6m
* Binutils: support non-contiguous memory regions in linker
== Progress ==
* clang-tidy workshop (and associated prep)
- I think this went really well, we got good feedback from some of
the participants
* Trying to setup a build environment on tcwg-sq-02.tcwglab
- Mostly so I can deploy the SVE fuzzer there, but maybe for other things too
- All the compilers that I've tried so far are ICE-ing at some point
or another while building llvm
- Still looking into it but I'm starting to suspect there's
something fishy about this board
* Still no access to Morello docs
* Read a bit more about LLDB
* Finished annual review
== Plan ==
* Maybe THIS time I'll get access to the Morello docs next week
* If not, more SVE fuzzer
* One day off
o LLVM:
* Buildbots babysitting:
- Various breakage on the bots and in the kernel build
* Machine Outliner:
- preparing upstream submission
o Misc
* Various meetings and discussions.
== Progress ==
* GCC:
- Work on -mpure-code on v6m
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
- watched a couple of GNU Cauldron presentations
== Next ==
* FDPIC: resume work on GDB
* GCC: pure-code/v6m
* Binutils: support non-contiguous memory regions in linker
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Still need to think of more test cases...
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v5 of the system-only patch set,
with testing help from Alex.
[VIRT-327 # Richard's upstream QEMU work ]
Catching up on patch review
- arm semihosting
- tcg profiler
- ptimer transactions
- s390 mvcl interrupt
- started on v2 of dave martin's bti kernel patch set.
Posted v6 of my arm hflags patch set.
r~
== Progress ==
* Support Morello fat pointers in LLDB [LLVM-597]
- Read an intro to Cheri (research project that Morello is based on)
- Read more LLDB docs
* Started writing annual review
* Setup VM for a clang-tidy workshop that I'm co-organizing as part of
the Stockholm LLVM socials
== Plan ==
* Hopefully will get access to Morello docs next week so I can start actual work
* Rebase and play more with the SVE IR fuzzer [LLVM-586]
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Lots of work with Alex trying to produce a reduced test case.
We are now unit testing entry and exit from EL0 (EL2&0),
EL1 and EL0-in-EL1 (EL1&0).
Next would be to test the various memory access faults.
[VIRT-327 # Richard's upstream QEMU work ]
Patch review for SVE in KVM, S390 interrupt handling during MVCL.
r~
Short week (2 days off)
== Progress ==
* GCC:
- looked at what's needed to enable -mexecute-only on v6m
* GCC upstream validation:
- reported a couple of issues.
* misc:
- infra fixes / troubleshooting / reviews
- catching up after Connect (internal debrief, ...)
- started looking at GNU Cauldron presentations
== Next ==
* FDPIC: resume work on GDB
* GCC: execute-only/v6m
* Binutils: support non-contiguous memory regions in linker
Slightly overlong this time as it covers pre&post connect weeks.
QEMU Tooling ([VIRT-252])
=========================
[VIRT-252] https://projects.linaro.org/browse/VIRT-252
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
QEMU plugin support ([VIRT-280])
- sporadic work on the [v5 branch]
- posted {PATCH v6 0/6} semihosting cleanups (plus minor tests/tcg
tweak) Message-Id: <20190913151845.12582-1-alex.bennee(a)linaro.org>
- now merged - delta down a little ;-)
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
[v5 branch] https://github.com/stsquad/qemu/tree/plugins/plugins-v5
GSoC Mentoring Afermath ([VIRT-348])
- more work preparing [subset for final list review]
- stats, CONFIG_PROFILER and perf integration
- dropped coverset and dot diagram as a bit too rough
- however should form a good basis going forward
[VIRT-348] https://projects.linaro.org/browse/VIRT-384
[subset for final list review]
https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf
ARMv8.1 VHE Extensions ([VIRT-263])
===================================
- worked with rth to get a minimal testcase
- very messy [wip branch]
[VIRT-263] https://projects.linaro.org/browse/VIRT-263
[wip branch] https://github.com/rth7680/qemu/tree/test-vhe
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v3 00/33} testing/next (docker,tcg, alpha ;-)
Message-Id: <20190924210106.27117-1-alex.bennee(a)linaro.org>
- posted {RFC PATCH} configure: deprecate 32 bit build hosts
Message-Id: <20190925233013.6449-1-alex.bennee(a)linaro.org> mostly to
stimulate discussion of our modest proposal
- posted {PULL 00/28} testing updates (docker,podman,tcg,alpha)
Message-Id: <20190926183553.13895-1-alex.bennee(a)linaro.org>
- posted {PATCH} accel/kvm: ensure ret always set Message-Id:
<20191002102212.6100-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other Activities
================
- More Connect travel administrava (airport transfer booked now)
- Connect itself
- many interesting talks
- discussions with bemi w.r.t migration and command line opts
- discussions with rth w.r.t 64/32, VHE and PR process
- discussions with FutureWei w.r.t scaling QEMU emulation
- KVM Forum administrava
Completed Reviews [2/2]
=======================
{PATCH} configure: Remove s390 (31-bit mode) from the list of supported CPUs
Message-Id: <20190928190334.6897-1-thuth(a)redhat.com>
{PATCH v2} s390x/tcg: MVCL: Exit to main loop if requested
Message-Id: <20191002082636.7739-1-david(a)redhat.com>
Absences
========
- KVM Forum Oct 29th-Nov 1st
Current Review Queue
====================
* {PATCH v2 00/15} target/arm: Implement semihosting v2.0
Message-Id: <20190916141544.17540-1-peter.maydell(a)linaro.org>
Added: <2019-10-03 Thu>
* {PATCH 00/19} hw/arm/raspi: Improve Raspberry Pi 2/3 reliability
Message-Id: <20190926173428.10713-1-f4bug(a)amsat.org>
Added: <2019-09-27 Fri>
* {PATCH RFC} docker: automatic dependencies for dockerfiles
Message-Id: <20190920001823.23279-1-jsnow(a)redhat.com>
Added: <2019-09-24 Tue>
* {PATCH v4 0/9} target/arm/kvm: enable SVE in guests
Message-Id: <20190924113105.19076-1-drjones(a)redhat.com>
Added: <2019-09-24 Tue>
--
Alex Bennée
On buildbot duty
- Several buildbot failures to investigate along with one linux kernel
regression
- Didn't manage to get the libcxx buildbot failures resolved on time.
I think the community are still trying to fix it (Script needs to be
Python2/Python3
Started work on LLD support for Morello
- Getting familiar with the toolchain
- First target is sufficient support to statically link the Howdy
"hello world" equivalent.
- Made the first couple of local patches to implement the easiest set
of static relocations.
Some upstream LLD patch review.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ investigated the cause of a hang when using single-threaded TCG
+ sent RFC patchset proposing a rework of the ptimer API/implementation
which will fix LP:1777777. Unfortunately we'll need to update all
the devices using ptimers. I started in on that process of conversion,
which turns out to be a little more awkward than I had expected;
I ran into at least one corner case I hadn't thought about.
thanks
-- PMM
== Progress ==
* Out of office on Monday
* Catching up after Connect
* Minor buildbot fix
* IR SVE Reviews [LLVM-545]
- Another round on the size queries patch
* SVE IR fuzzer [LLVM-586]
- Waiting for the size queries patch to get merged so I can give it a spin
* Support Arran fat pointers in LLDB [LLVM-597]
- Built lldb
- Looked a bit through the docs
== Plan ==
* Play more with lldb, read more docs
* A bit of globalisel maintenance
o LLVM:
* Buildbots babysitting:
- Troubleshot ARMv8 selfhosted bots issue
* Machine Outliner:
- Experiment outlining with -mexecute-only
- Tried to find a testcase which exhibits issues with unwinding
without much success.
o Misc
* Various meetings and discussions.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ identified cause of LP:1844597 and sent patch fixing it (we broke
direct-booting kernels when the emulated system has an AArch32 EL3)
+ tracked down the cause of LP:1777777 to a race condition that's
inherent to the current design of QEMU's 'ptimer' countdown timers;
fixing this will require us to rethink when we call the callback
when a ptimer hits 0. Posted some ideas to mailing list, for feedback
on whether I missed a better way to rework them.
+ usual upstream maintainer stuff; managed one way or another to
get a few of the most obstinately sticky patchsets off my to-review list
thanks
-- PMM
== Progress ==
* GCC:
- FDPIC: Whole series now committed. Reverted one patch (aiming at
cortex-M, caused problems in ARM mode, investigating)
* GCC upstream validation:
- reported a couple of issues. Helped with testing.
- getting ready to add cortex-m33 validation with qemu
* Binutils:
- Non-contiguous memory regions support in the BFD linker: not started yet.
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
Linaro Connect San Diego
== Progress ==
* Out of office on Friday
* Use newer perf for benchmarking [TCWG-1512]
- Switched benchmarking to use bionic containers, with perf 4.18.0;
seems to work
* Investigate running benchmarks in containers [TCWG-1513]
- Done
* Uploaded LLVM 9.0.0-rc5 and rc6
* SVE IR fuzzer [LLVM-586]
- Unblocked my work on this, need to give it a serious spin
== Plan ==
* Buildbot babysitting this week
* LLVM-586
* Try to build LLDB
[VIRT-327 # Richard's upstream QEMU work ]
Convert notdirty and rom handling to cputlb; lots of cleanup around
that area. Version 3 is the first version that worked; two previous
RFCs took quite a bit of effort to work out why they didn't work.
[GCC]
Committed the lse out-of-line patch set.
Posted patches for two follow-on bugs affecting aarch64-elf.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ sent v2 of the semihosting v2 API implementation patchset
+ sent patch to fix a Makefile bug I introduced that broke in-tree builds
+ code review etc
thanks
-- PMM
[VIRT-327 # Richard's upstream QEMU work ]
Posted v2 of fixing tlb bswap.
Fixed a regression in arm SMLAL*
Reviewed v2 of risc-v vector extension (ugh).
Created pull for Sven's target/hppa fixes.
[GNU Cauldron]
* Project Ranger: New extensible representation for value ranges.
* Lightning talks, a new gdbserver.
- too short to have enough details to be useful.
- incomplete enough that no demo possible.
- maybe look back at this when it's more developed.
* Register allocation BOF
* ARM BOF
- MTE is alive! In that there are now RFC patches for glibc and gcc.
It's probably time to revive my MTE patch set, at least for system mode.
I spent quite a long time talking with Richard Earnshaw about the
current state of affairs. I'm hoping that we can get the kernel folk
to agree on some fundamentals of the userland ABI, even perhaps before
the final support is in the kernel, so that we can implement the
linux-user side, which would probably be most helpful for glibc+gcc work.
* GCC Steering Committee
* Rethinking GCC development process + continuous testing
* Truly interprocedural IPA-SRA
* Lightning talks,
- EmBench
- Combined elimination for -Os.
* RISC-V BOF
r~
o LLVM:
* Buildbots babysitting:
- Reported a kernel build issue after clang handling of
-march/-mfpu and crypto option was changed.
* Machine Outliner:
- Disabling Thumb1 outlining until we find a better way to handle tailcalls
- Working on Connect slides
o Misc
* Various meetings and discussions.
== Progress ==
* GCC:
- FDPIC: Committed the whole series, expect for one testsuite patch,
pending final review.
* GCC upstream validation:
- reported a couple of issues. Helped with testing.
- getting ready to add cortex-m33 validation with qemu
* Binutils:
- Non-contiguous memory regions support in the BFD linker: not started yet.
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
- binutils/linker support for non-contiguous memory regions
- FDPIC: work on gdb
- GCC upstream validation: Add a config for cortex-m33 (v8-m)
LLVM-579 Implement -fix-cortex-a8 in LLD. Keeping up with review
comments, I think this is getting close now.
Connect slides moving forwards. Now have 2 out of 3 presenters done.
Rest of the week taken up by investigations and LLD reviews.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ implemented and sent patchset for semihosting v2 API
+ target-arm pullreq, patch review, etc
+ got the QEMU Summit invite list finalised and sent invites
+ some internal meetings
thanks
-- PMM
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Finally merged, after a few more iterations and testing!
- Doesn't work for AArch32 yet but I think I have a fix
* Use newer perf for benchmarking [TCWG-1512]
- Tried 4.15.0-62 generic on the TK1, doesn't seem to work; investigating
* SVE IR fuzzer [LLVM-586]
- Didn't get to work much on it
* Uploaded LLVM 9.0.0-rc4
== Plan ==
* Fix AArch32 benchmarking
* TCWG-1512 and LLVM-586
o LLVM:
* Buildbots babysitting
* Machine Outliner:
- Experiments on Zephyr exposed some issues w/r to unwinding and
relocation overflow, working on these.
o Misc
* Various meetings and discussions.
Hi guys. Due to unfortunate baggage handling, I don't have my laptop and
won't be able to log in Monday. I should be back online Tuesday, all going
well.
r~
Progress:
+ usual upstream maintainership stuff
+ notably, finished review of RTH's decodetree conversion patchset,
got it into master
+ started on implementing semihosting v2 API (the most interesting
new feature of which is support for AArch32 binaries exiting with
a specified exit status)
thanks
-- PMM
== Progress ==
* GCC:
- FDPIC: almost OK. Found minor issues with testcases
* GCC upstream validation:
- reported a couple of issues. Helped with testing.
- getting ready to add cortex-m33 validation with qemu
* Binutils:
- Non-contiguous memory regions support in the BFD linker: not started yet.
* misc:
- infra fixes / troubleshooting / reviews
- a bit of Jira
== Next ==
GCC:
- commit FDPIC patches after final validation
- binutils/linker support for non-contiguous memory regions
- GCC upstream validation: Add a config for cortex-m33 (v8-m)