- linaro-toolchain - lists.linaro.org

[ACTIVITY] week ending 29 Mar 2020

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] Posted the first incremental patch set for review, as requested by Qualcomm. [VIRT-327 # Richard's upstream QEMU work ] Patch review, much of it 5.0 related, but also v6 of the riscv vector patch set. Revise the PIE and linkage patch set. r~

6 years, 1 month

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[ACTIVITY] 23-27 March 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of failures/regressions * GCC: - comparing testsuite results for cortex-m3 and cortex-m33 with cortex-a9 to check what cortex-M problem there are. Fixed a few testcases. Managed to use qemu-system-arm to run cortex-m33 code with CMSE features. (Thanks to Peter Maydell for the help!) * misc: - infra fixes / troubleshooting / reviews == Next == * FDPIC GDB * GCC/cortex-M

6 years, 1 month

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[ACTIVITY] report week ending 27 Mar

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - Softfreeze this week, so a lot of pull request handling, and one last small arm pullreq to put together and send out - Our Coverity Scan setup was broken (the person who usually does the builds updated his machine to a newer Fedora which broke the tool). I pulled up an old patchset I had from a year ago which scripts things so you can do a build-and-upload automatically via Docker so that we're not dependent on one person for this. This took longer than I expected as there were a bunch of things that needed fixing both in the scripting and in bits of the codebase that the tools warned about. Patch series sent. - When we did get a Coverity run through, it reported 112 new issues; spent some time going through and triaging them (lots of false positives but also lots of real bugs) and submitting patches for some of them. * VIRT-364 [QEMU support for ARMv8.1-M extensions] - sketched out the work required and created some 'story' level cards to go under the epic. Still open questions: + should we model Cortex-M55 or a more generic 'max' CPU? + what board model do we want to use? + does LITE have any guest code using v8.1M features for testing? Random notes: * my new desk chair and standing desk arrived this week (the latter still needs assembling...) so I am gradually improving the rough edges of my WFH setup. thanks -- PMM

6 years, 1 month

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[ACTIVITY] week ending Mar. 29 2020

by Alex Bennée

VirtIO Related Work ([VIRT-366]) ================================ - posted [RFC PATCH 0/8] some tweaks to the document build process Message-Id: <20200327103803.10460-1-alex.bennee(a)linaro.org> [VIRT-366] <https://projects.linaro.org/browse/VIRT-366> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 for 5.0 00/11] testing/next Message-Id: <20200323161514.23952-1-alex.bennee(a)linaro.org> - posted [PULL for 5.0-rc1 00/11] testing updates (+ one mttcg change) Message-Id: <20200325151543.32478-1-alex.bennee(a)linaro.org> - needed [PATCH] qemu/atomic.h: add #ifdef guards for stdatomic.h Message-Id: <20200326170121.13045-1-alex.bennee(a)linaro.org> - posted [PATCH for 5.0 v1 0/7] A selection of sanitiser fixes Message-Id: <20200327094945.23768-2-alex.bennee(a)linaro.org> - posted [PULL v2 for 5.0 00/12] testing updates (+ one mttcg change) Message-Id: <20200327181320.23329-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [3/3] ======================= [PATCH-for-5.0 v2 0/4] tests/docker: Fixes for 5.0 Message-Id: <20200322120104.21267-1-philmd(a)redhat.com> - CLOSING NOTE [2020-03-23 Mon 10:00] Simple enough Added: <2020-03-22 Sun> [PATCH] qemu-user: fix build with LLVM lld 10 Message-Id: <20200327140839.GB28583@Air-de-Roger> [virtio-dev] [PATCH v3] Add virtio SCMI device specification Message-Id: <87blonas8y.fsf(a)linaro.org> Absences ======== - Splitting time between work and home-schooling Current Review Queue ==================== * [PATCH v4 00/10] tests/vm: Add support for aarch64 VMs Message-Id: <20200312142728.12285-1-robert.foley(a)linaro.org> Added: <2020-03-27 Fri> * [PATCH v8 00/74] per-CPU locks Message-Id: <20200326193156.4322-1-robert.foley(a)linaro.org> Added: <2020-03-27 Fri> * [virtio-dev] [RFC PATCH] virtio-iommu: Add PAGE_SIZE_MASK property Message-Id: <20200323133831.2110014-1-jean-philippe(a)linaro.org> Added: <2020-03-27 Fri> * [virtio-dev] [PATCH v2 00/10] virtio-mem: paravirtualized memory Message-Id: <20200311171422.10484-1-david(a)redhat.com> Added: <2020-03-27 Fri> -- Alex Bennée

6 years, 1 month

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[ACTIVITY] 23 - 27 March 2020

by Diana Picus

== Progress == * Out of office 1 day * More Morello - Patch set for the 'disassemble' command in review - Working on the final part of the capability formatting == Plan == * More Morello

6 years, 1 month

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[ACTIVITY] week ending 22 Mar 2020

by Richard Henderson

Progress: [VIRT-349 # QEMU SVE2 Support ] 10 of N insn groups implemented. Annoyingly, there doesn't seem to be a summary of new insns, so confirming that all of the insns have been implemented. [VIRT-327 # Richard's upstream QEMU work ] Patch review. Mostly Phil's arm --disable-tcg set. Cleanup for some of the new Coverity reports. Flush tcg patch queue. [GCC] Two revisions improving TImode comparisons for aarch64 (PR94174). https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542447.html [Kernel] Follow-up on a discussion a few weeks ago re __range_ok. The gcc cmpti patch set is in support of that, but I also found a much better solution for constant sized checks. http://lists.infradead.org/pipermail/linux-arm-kernel/2020-March/719754.html r~

6 years, 1 month

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[ACTIVITY] week ending Mar. 22 2020

by Alex Bennée

VirtIO Related Work ([VIRT-366]) ================================ - Whole bunch of scoping work on tasks for this cycle - Briefed the TSC Strategic Meeting on work plan - Feedback on Friday call seemed positive, hopefully will get the votes [VIRT-366] <https://projects.linaro.org/browse/VIRT-366> QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - posted [PATCH v1 00/28 for 5.0] testing and gdbstub Message-Id: <20200316172155.971-1-alex.bennee(a)linaro.org> - now merged and parent cards closed out including <https://projects.linaro.org/browse/VIRT-26> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 0/5] testing updates (docker and acceptance CI tweaks) Message-Id: <20200309202318.3481-1-alex.bennee(a)linaro.org> - spent a fair time fighting with check-acceptance tests weirdness - fielded questions from potential students for GSoC cache modelling project - more time tracking down "check-acceptance" issues - posted [RFC PATCH for 5.0] configure: disable MTTCG for MIPS guests Message-Id: <20200320114522.16273-1-alex.bennee(a)linaro.org> Completed Reviews [2/2] ======================= [PATCH v10 0/3] Acceptance test: Add "boot_linux" acceptance test Message-Id: <20200317141654.29355-3-crosa(a)redhat.com> [PATCH 0/5] QEMU Gating CI Message-Id: <20200312193616.438922-5-crosa(a)redhat.com> Absences ======== - Splitting time between work and home-schooling Current Review Queue ==================== * [PATCH 0/2] thread: add lock guard macros Message-Id: <20200311123624.277221-1-stefanha(a)redhat.com> Added: <2020-03-11 Wed> * [PATCH v8 0/9] qemu-binfmt-conf.sh Message-Id: <20200307170251.GA7@dd5f6ec33fb0> Added: <2020-03-08 Sun> * [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com> Added: <2020-02-14 Fri> * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> -- Alex Bennée

6 years, 1 month

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[ACTIVITY] 16-20 March 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: minor follow-ups * GCC upstream validation: - reported a couple of failures/regressions - PR90378 working on reproducing a non-functional code problem with spec2006 on arm with LTO and -Os. Looks like a stack corruption issue * GCC: - comparing testsuite results for cortex-m3 and cortex-m33 with cortex-a9 to check what cortex-M problem there are. * misc: - infra fixes / troubleshooting / reviews == Next == * spec2006 / LTO / Os / aarch32 * FDPIC GDB * GCC/cortex-M

6 years, 1 month

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[ACTIVITY] report week ending Mar 20

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - Softfreeze this week, so a lot of pull request handling, and one last small arm pullreq to put together and send out - Our Coverity Scan setup was broken (the person who usually does the builds updated his machine to a newer Fedora which broke the tool). I pulled up an old patchset I had from a year ago which scripts things so you can do a build-and-upload automatically via Docker so that we're not dependent on one person for this. This took longer than I expected as there were a bunch of things that needed fixing both in the scripting and in bits of the codebase that the tools warned about. Patch series sent. - When we did get a Coverity run through, it reported 112 new issues; spent some time going through and triaging them (lots of false positives but also lots of real bugs) thanks -- PMM

6 years, 1 month

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[ACTIVITY]

by Diana Picus

== Progress == * Out of office 1 day * More Morello ('disassemble' command) == Plan == * More Morello * Will probably be out of office more with toddler

6 years, 1 month

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GDB bad in gcc-linaro-7.5.0-2019.12-i686-mingw32_arm-linux-gnueabihf ?

by Steve Kledtke

Howdy, 1st post on this list. I just tried the windows binaries found on the latest-7 release site, namely of: gcc-linaro-7.5.0-2019.12-i686-mingw32_arm-linux-gnueabihf When I go into the bin folder and enter: .\arm-linux-gnueabihf-gdb.exe --version It outputs nothing, just returns. The version I used prior, 7.3.1, still works as supposed. Notable is that from 7.3.1 to 7.5.0, the gdb.exe size grew from ~96MB to ~128MB. I re-downloaded the whole tar again and replaced the bin folder, no change. I can actually *build* a C++ project with those binaries, though, and the output executable works. Only GDB seems to be affected so far.

6 years, 1 month

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[ACTIVITY] 2 weeks ending 15 May 2020

by Richard Henderson

[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Reorg sve load/stores w/probe_access_flags. Posted v6, now including support for sve. [VIRT-327 # Richard's upstream QEMU work ] Posted v3 of tbi cleanups. Updated a forgotten patch vs sve fmla/fcmla. Oodles of patch review. r~

6 years, 1 month

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[ACTIVITY] week ending Mar. 15 2020

by Alex Bennée

VirtIO Related Work ([VIRT-366]) ================================ - posted [PATCH] tools/virtiofsd: add support for --socket-group Message-Id: <20200312104142.21259-1-alex.bennee(a)linaro.org> - continued discussion on approaches on virtio-dev list Message-Id: <874kv15o4q.fsf(a)linaro.org> - email threads with Qualcomm Message-Id: <CAHFG_=WY8duYm7xNTNo=iGZKqD12gt9ps05pyc1qmbUDcLM0Bw(a)mail.gmail.com> to drill down on their requirements - two long HOs with Qualcomm and Google to further discuss work - I feel like there a few tasks forming which I will try an clean-up the breakdown on the initiate for next week. [VIRT-366] <https://projects.linaro.org/browse/VIRT-366> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 0/5] testing updates (docker and acceptance CI tweaks) Message-Id: <20200309202318.3481-1-alex.bennee(a)linaro.org> - spent a fair time fighting with check-acceptance tests weirdness - had an initial look at [PATCH 0/5] QEMU Gating CI Message-Id: <20200312193616.438922-1-crosa(a)redhat.com> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [6/6] ======================= [PATCH v7 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Message-Id: <20200310213203.18730-1-nieklinnenbank(a)gmail.com> [PATCH v16 00/10] VIRTIO-IOMMU device Message-Id: <20200214132745.23392-11-eric.auger(a)redhat.com> - CLOSING NOTE [2020-03-11 Wed 17:18] Already merged upstream Added: <2020-03-03 Tue> {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com> - CLOSING NOTE [2020-03-12 Thu 09:58] Not plumbed into the testing infrastructure so a bit of a code dump. Added: <2020-02-13 Thu> [PATCH v3 02/10] tests/vm: Add configuration to basevm.py Message-Id: <20200310182536.11137-3-robert.foley(a)linaro.org> [PATCH 0/4] tests/vm: minor install tweaks, update netbsd & freebsd Message-Id: <20200310083218.26355-1-kraxel(a)redhat.com> [PATCH 0/5] docs/system: Split target-arm.rst Message-Id: <20200309215818.2021-3-peter.maydell(a)linaro.org> Absences ======== - None Current Review Queue ==================== * [PATCH 0/2] thread: add lock guard macros Message-Id: <20200311123624.277221-1-stefanha(a)redhat.com> Added: <2020-03-11 Wed> * [PATCH v8 0/9] qemu-binfmt-conf.sh Message-Id: <20200307170251.GA7@dd5f6ec33fb0> Added: <2020-03-08 Sun> * [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com> Added: <2020-02-14 Fri> * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> -- Alex Bennée

6 years, 2 months

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[ACTIVITY] report week ending 13 Mar

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - More documentation cleanup (splitting the Arm boards section up into one page per board) - Various patch review - Put together last large pull request before softfreeze hits next week - Fixed the Windows installer generation, which I broke in the process of moving the HTML docs around - Fixed read buffer overrun in i82596 device model spotted by coverity - Fixed a user-experience papercut that's been bothering me for years: for arm you needed to specify '-M virt' to avoid an error even if all you wanted was the '-cpu help' or '-device help' output. * VIRT-241 [QEMU ISA Support for A-profile] - Jira gardening: split out the optional parts of each architectural tick sub-epic, and added the new 8.6 tasks thanks -- PMM

6 years, 2 months

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[ACTIVITY] 9-13 March 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: patch accepted and committed * GCC upstream validation: - reported a couple of failures/regressions - PR90378 working on reproducing a non-functional code problem with spec2006 on arm with LTO and -Os * misc: - infra fixes / troubleshooting / reviews == Next == * spec2006 / LTO / Os / aarch32 * FDPIC GDB

6 years, 2 months

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[ACTIVITY] 9 - 13 March 2020

by Diana Picus

== Progress == * Out of office 1 day * More Morello (updating for new capability encoding, disassembling correctly) == Plan == * More Morello

6 years, 2 months

1
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Linaro tool chain version for ARMv9

by Chun-Chia Hsu (許峻嘉)

Hi Sir, I have some questions for tool chain: 1. Can the latest version “linaro-gcc/7.5” support ARMv9 new ISA? 2. If not, when will the new release version can support? Thanks a lot. Chun-Chia

6 years, 2 months

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[ACTIVITY] week ending Mar. 8 2020

by Alex Bennée

VirtIO Related Work ([VIRT-366]) ================================ - Followed up with ARM on the roll of Hafnium and secure partitioning with VirtIO - Continued working through various requirements for the work - raised [VIRT-373] to describe some potentially common work on handling userspace backends - started discussion on approaches on virtio-dev list Message-Id: <874kv15o4q.fsf(a)linaro.org> - posted [RFC PATCH] tools/virtiofsd: add support for --socket-group Message-Id: <20200304185025.19853-1-alex.bennee(a)linaro.org> [VIRT-366] <https://projects.linaro.org/browse/VIRT-366> [VIRT-373] <https://projects.linaro.org/browse/VIRT-373> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 00/10] testing/next updates (tweaks and re-greening) Message-Id: <20200302181907.32110-1-alex.bennee(a)linaro.org> - posted [PULL 0/9] testing updates (tests/vm and acceptance tweaks) Message-Id: <20200304100154.14822-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [3/3] ======================= [PATCH v3 00/33] Convert qemu-doc to rST Message-Id: <20200228153619.9906-1-peter.maydell(a)linaro.org> [PATCH v5 00/50] Initial support for multi-process qemu Message-Id: <cover.1582576372.git.jag.raman(a)oracle.com> - CLOSING NOTE [2020-03-02 Mon 18:20] Initial pass, mostly checking wasn't CI broken, which it was. Added: <2020-02-28 Fri> [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Message-Id: <20200301215029.15196-1-nieklinnenbank(a)gmail.com> Absences ======== - None Current Review Queue ==================== * [PATCH v16 00/10] VIRTIO-IOMMU device Message-Id: <20200214132745.23392-11-eric.auger(a)redhat.com> Added: <2020-03-03 Tue> * [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com> Added: <2020-02-14 Fri> * {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com> Added: <2020-02-13 Thu> * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> -- Alex Bennée

6 years, 2 months

1
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[ACTIVITY] report week ending 6 Mar

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - found and fixed some bugs in our "hflags caching" for M-profile which caused spurious assertions in some corner cases - got the rST conversion patchset through review and into master - sent some followup cleanup patches that remove some texinfo related bits of code we no longer need - patch review: + rth's final respin of the "honour more HCR_EL2 traps" series + patchset fixing some memory leaks of timer objects + patchset for cubieboard model to error out rather than ignoring some bogus user command line options * VIRT-241 [QEMU ISA Support for A-profile] + Wrote an implementation of v8.2-TTS2UXN; investigating how best to test it thanks -- PMM

6 years, 2 months

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[ACTIVITY] 2 - 6 March 2020

by Diana Picus

== Progress == * Out of office 2 days * More Morello (updating for new capability encoding) == Plan == * More Morello

6 years, 2 months

1
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[ACTIVITY] week ending 1 Mar 2020

by Richard Henderson

[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Lots of work, including an arch update. The system-mode patch set is much changed, but still not quite ready. [VIRT-349 # QEMU SVE2 Supprt ] [VIRT-327 # Richard's upstream QEMU work ] TBI fixes, 2 rounds. HCR fixes, 2 rounds. TCG patch queue flushed. Some patch review. r~

6 years, 2 months

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gdb: instructions and functions recording on ARM processors using CoreSight ETM

by Zied Guermazi

Good afternoon, I would like to announce the breakthrough in extending gdb with non intrusive instructions and functions tracing on ARM processors using Coresight ETM traces, as described in previous mails. the source code is made public in the git repository https://github.com/gzied/binutils-gdb/ in the branch gdb_arm_coresight. this implementation was compiled and tested on an STM32MP1 (ARMv7 Architecture) board running "Linux arm 5.3.10-armv7-lpae-x15" distribution where the device tree was modified to declare CoreSight components. to build the software >checkout the software from the branch gdb_arm_coresight > cd .. >mkdir build >cd build > ../binutils-gdb/configure --with-arm-cs >make after a successful build gdb will be available in the folder build/gdb to run the software build the software you would like to debug with debugging info (-g flag) >gcc -g software.c -o software start debugging your software >gdb software set a breakpoint at main (gdb) b main (gdb) run set a breakpoint in a location after the code you would like to trace (gdb) b my_function set your etm sink, sinks can be found by listing the folder /sys/bus/event_source/devices/cs_etm/sinks/. use a sink that is capable of storing the traces on chip (etf, etb ...) (gdb) set record btrace etm sink tmc_etf0 start recording etm traces (gdb) record btrace etm continue the execution of the program (gdb) c wait until the breakpoint is hit, analyse and display the traces - on assembly level (gdb) record instruction-history - on c level (gdb) record function-call-history /ilc you can increase the number of instructions displayed by using (gdb) set record instruction-history-size size (gdb) set record function-call-history-size size the work is still in an early stage and needs to be improved, extended and stabilized. your feedback and contributions are welcome Kind Regards Zied Guermazi

6 years, 2 months

3
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[ACTIVITY] week ending Mar. 1 2020

by Alex Bennée

VirtIO Related Work ([VIRT-366]) ================================ - had a couple of HOs and internal threads to flesh out understanding for VirtIO work - queried VIRTIO adoption in other hypervisors Message-Id: <87mu93vwy2.fsf(a)linaro.org> to help understanding - need a meeting with QC/NXP to discuss their requirements and why they need certain devices in VirtIO - a lot of the Android focus seems to be on isolating various secure workloads - avoiding needing secure but un-trusted code at elevated privileges with access to main OS - suspect the breakdown in the card needs re-arranging [VIRT-366] <https://projects.linaro.org/browse/VIRT-366> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id: <20200130113223.31046-10-alex.bennee(a)linaro.org> - posted [PULL 00/19] testing and plugin updates Message-Id: <20200226073929.28237-1-alex.bennee(a)linaro.org> - did some debugging/diagnosis for recent slowdown of ARM emulation in master Message-Id: <CAPan3Wq-MVwcJQELP8n+g33CR7tsiGXQ698gA177nd2my9hWCw(a)mail.gmail.com> - posted [PATCH v1 0/4] Fix codegen translation cache size Message-Id: <20200226181020.19592-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [3/3] ======================= [PATCH v16 00/10] VIRTIO-IOMMU device Message-Id: <20200214132745.23392-1-eric.auger(a)redhat.com> - CLOSING NOTE [2020-02-26 Wed 15:37] It's in an in-flight PR now, will play with it once it lands. Added: <2020-02-14 Fri> [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns Message-Id: <20200225143923.22297-1-peter.maydell(a)linaro.org> [PATCH v3 0/3] Fix number of priority bits for arm boards Message-Id: <1582537164-764-1-git-send-email-sai.pavan.boddu(a)xilinx.com> - CLOSING NOTE [2020-02-28 Fri 17:22] Have been pulled into target-arm next but didn't fix the kvm-unit-test failures with priority masking as I had hopped they would. Added: <2020-02-25 Tue> Absences ======== - None Current Review Queue ==================== * [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com> Added: <2020-02-14 Fri> * {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com> Added: <2020-02-13 Thu> * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> -- Alex Bennée

6 years, 2 months

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[ACTIVITY] report week ending 28 Feb

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - Got confused by QEMU aborting in the PMU code on a GICv3-only host, which turns out to be because our error handling for "no GICv2 support" was broken. Sent a patch. - Another push towards getting texi-to-rST conversion done: + Converted a few more simple texi doc files to rST + Took up a patchset Paolo did for more automated conversion, and sorted out the parts it didn't deal with, to get it to a point where it could delete almost all of the texinfo sources. Sent a big patchset to the list for review. - patch review: + Gumstix cleanup patchset + rth's series to honour more HCR_EL2 traps + add a few missing devices to integratorcp + get the number of implemented priority bits in GICv2 right * VIRT-241 [QEMU ISA Support for A-profile] - Implemented the v8.3-RCPC, v8.4-RCPC and v8.3-CCIDX extensions, and sent patches to the list thanks -- PMM

6 years, 2 months

1
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[ACTIVITY] 24-28 February 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: posted updated v5 * GCC: * GCC-9: continued work for validation of -mpure-code on v6m. Fix committed to trunk and backported to gcc-9 * GCC upstream validation: - reported a couple of failures/regressions - working on reproducing a non-functional code problem with spec2006 on arm with LTO and -Os * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * spec2006 / LTO / Os / aarch32 * FDPIC GDB

6 years, 2 months

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[ACTIVITY] 24 - 28 February 2020

by Diana Picus

== Progress == * More Morello (updating for new capability encoding) == Plan == * More Morello * Tiny bit GlobalISel

6 years, 2 months

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[ACTIVITY] week ending 23 Feb 2020

by Richard Henderson

Four day week. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Lots of work here. Noticed that our TBI handling is wrong for system mode, such that the FAR_ELx register gets the wrong contents. Noticed that SVE isn't handling TBI at all, much less being prepared for MTE. Noticed that even AdvSIMD would not quite produce the correct results for LD*/ST* (multiple structures). Rearranging the actual MTE check from the ground up. Found an odd case with DC_ZVA that threw a wrench into that planning. [VIRT-327 # Richard's upstream QEMU work ] Honor more HCR_EL2 trap bits. HPPA patch queue flushed. Patch review for ppc "hardfloat" patch. Patch review for memory_region_allocate_system_memory. r~

6 years, 2 months

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[ACTIVITY] report week ending 21 Feb

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - Sent out a patchset creating a 'tools' manual and moving some docs into it that were previously in the 'interop' manual - more code review this week than last week - pushed out another arm pullreq * VIRT-241 [QEMU ISA Support for A-profile] - several patches implementing features landed in master, so I was able to close out some of the subtasks here thanks -- PMM

6 years, 2 months

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[ACTIVITY] 17-21 February 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: handling feedback received * GCC: * GCC-9: continued work for validation of -mpure-code on v6m. All new failures reported with cortex-m0 + -mpure-code are to be expected (mainly testcases forcing options incompatible with -mpure-code) * GCC upstream validation: - reported a couple of failures/regressions - looked at a problem with LTO profiled bootstrap failing on aarch32 with gcc-8. Could not reproduce with current trunk - working on reproducing a non-functional code problem with spec2006 on arm with LTO and -Os * misc: - infra fixes / troubleshooting / reviews - looked at a problem reported about addr2line and kernel symbols. Needs more analysis == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m * spec2006 / LTO / Os / aarch32 * FDPIC GDB

6 years, 2 months

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[ACTIVITY] 17 - 21 February 2020

by Diana Picus

== Progress == * More Morello (updating for new capability encoding) * Tiny amount of GlobalISel arm32 maintenance (not committed yet) == Plan == * More Morello

6 years, 2 months

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Re: progress in btrace with etm in gdb

by Mathieu Poirier

Same comment applies with regards to mailing lists. On Mon, 17 Feb 2020 at 10:16, zied guermazi <guermazi_zied(a)yahoo.com> wrote: > > Hi Mike, hi Matthieu, > > I was too rapid to press the send button, sorry for the inconvienience. > and yes, it works. I published the source code in github (https://github.com/gzied/binutils-gdb/tree/gdb_arm_coresight) ,as well as a mail in linaro mailing list (https://lists.linaro.org/pipermail/coresight/2020-February/003676.html). Unfortunately you didn't publish your work in "PATCH" format and as such it can't be reviewed. > Eventhough there is still an effort needed to stabilize it for armv7, and test it for armv8, I consider this as a breakthough that we can build on the top of it. > I will be visiting Embedded world exhibition between 25th and 27th of February in Nuremberg, Germany. are you planning to be there too. I am looking forwards to meet you there if possible to discuss possibilities of further development and integration in the main stream. I won't be in Nuremberg next week and I'm pretty sure Mike won't be there either. Other people on the lists might be around and interested in meeting with you. Mike and I will be attending Linaro Connect in Budapest between the 23rd and 27th of March. The Linaro toolchain group will also be there so it might be the perfect opportunity to sit down for an hour or so and have a chat. A good day to you, Mathieu > > Kind Regards > Zied Guermazi > > > > > > On Monday, February 17, 2020, 06:08:26 PM GMT+1, zied guermazi <guermazi_zied(a)yahoo.com> wrote: > > > Hi Mike, hi Matthieu > it works! > > > > On Monday, December 16, 2019, 11:20:20 PM GMT+1, zied guermazi <guermazi_zied(a)yahoo.com> wrote: > > > hi Mike, hi Mathieu > last few weeks I was able to spend some time on implementing this feature, and I want to share the status with you and get your recommendation on organizational and technical level. > so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7). > I would like to push this on git, first for review and second for integration and creating traction . Do you think it is ok to push it in this status (feature partially achieved) ? is linaro gdb git the correct one? who is the maintainer of this part of gdb? I do not have an ARMv8 platform to test. who can support here? > > during the implementation few technical question raised: > - etm tracing collection requires selecting a trace sink. and I have two alternatives: either extending the "record btrace etm" command (used to start tracing) with a sink as an argument or extending the command "set record btrace" (general configuration of tracing) with etm sink sub-command? (I have hard-coded it currently to be able to progress) > - currently I am hardcoding the path "/sys/bus/event_source/devices/cs_etm/" as the default etm source, is this guaranteed to be unique? can we have a system with many etm sources enumerated in the sysfs. > > for parsing the traces I will need some configuration parameters like the content of registers ETMCR, ETMIDR, ETMCCER, ETMTRACEIDR. if my understanding of the implementation of perf is correct, it is collecting them from the sysfs files located in /sys/bus/event_source/devices/cs_etm/cpu0/mgmt/. which are global for the system. my question is what will happen if two process are requesting tracing at the same time? how to differentiate between traces going to one session from the second one? is it possible to get the parameters of a given session by some kind of ioctl request to the file descriptor we get out of sys_perf_open call? > > I will publish those queries in the linaro coresight and gdb forums, I wanted first to align with you especially on the organizational issues, before going to a bigger round. > > Thanks for your support > Zied Guermazi > >

6 years, 2 months

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Failure to find kernel symbols

by Leo Yan

Hi all, I'd like to report a bug for toolchain related with arm64. When I work on perf tool and found some kernel symbols are failed to be parsed based on kernel address. This issue can be simplized with the command addr2line: $ aarch64-none-linux-gnu-addr2line -e vmlinux ffff800010e11bb4 :? $ aarch64-none-linux-gnu-addr2line -e vmlinux ffff800010259700 :? I tried two toolchains, one in on X86 and another is on Arm64 native, both have the same result. The toolchain versions are: addr2line on Juno-r2 board: root@debian:~/coresight_test# addr2line -v GNU addr2line (GNU Binutils for Debian) 2.31.1 Copyright (C) 2018 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) any later version. This program has absolutely no warranty. addr2line on x86: $ aarch64-none-linux-gnu-addr2line -v GNU addr2line (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209 Copyright (C) 2019 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) any later version. This program has absolutely no warranty. If use the objdump, these two addresses are belongs to the functions as below. The vmlinux has been uploaded into: http://people.linaro.org/~leo.yan/opencsd_juno/perf_decoder_analysis_202002… Sorry if this is not the right place to report this issue and appreciate to let me know the right way to report this. ffff800010e11900 <_raw_spin_lock_irqsave>: ffff800010e11900: d503201f nop ffff800010e11904: d503201f nop ffff800010e11908: a9be7bfd stp x29, x30, [sp,#-32]! ffff800010e1190c: aa0003e3 mov x3, x0 ffff800010e11910: 910003fd mov x29, sp ffff800010e11914: f9000bf3 str x19, [sp,#16] ffff800010e11918: d53b4233 mrs x19, daif ffff800010e1191c: 12190260 and w0, w19, #0x80 ffff800010e11920: 34000340 cbz w0, ffff800010e11988 <_raw_spin_lock_irqsave+0x88> ffff800010e11924: d5384101 mrs x1, sp_el0 ffff800010e11928: b9401020 ldr w0, [x1,#16] ffff800010e1192c: 11000400 add w0, w0, #0x1 ffff800010e11930: b9001020 str w0, [x1,#16] ffff800010e11934: 1400000d b ffff800010e11968 <_raw_spin_lock_irqsave+0x68> ffff800010e11938: 1400000c b ffff800010e11968 <_raw_spin_lock_irqsave+0x68> ffff800010e1193c: 52800001 mov w1, #0x0 // #0 ffff800010e11940: aa0303e0 mov x0, x3 ffff800010e11944: 52800022 mov w2, #0x1 // #1 ffff800010e11948: 2a0103e4 mov w4, w1 ffff800010e1194c: 88e47c62 casa w4, w2, [x3] ffff800010e11950: 2a0403e0 mov w0, w4 ffff800010e11954: 35000120 cbnz w0, ffff800010e11978 <_raw_spin_lock_irqsave+0x78> ffff800010e11958: aa1303e0 mov x0, x19 ffff800010e1195c: f9400bf3 ldr x19, [sp,#16] ffff800010e11960: a8c27bfd ldp x29, x30, [sp],#32 ffff800010e11964: d65f03c0 ret ffff800010e11968: d2800001 mov x1, #0x0 // #0 ffff800010e1196c: 52800022 mov w2, #0x1 // #1 ffff800010e11970: 1400008b b ffff800010e11b9c <_raw_spin_lock_irqsave+0x29c> ffff800010e11974: 34ffff20 cbz w0, ffff800010e11958 <_raw_spin_lock_irqsave+0x58> ffff800010e11978: 2a0003e1 mov w1, w0 ffff800010e1197c: aa0303e0 mov x0, x3 ffff800010e11980: 97cd0524 bl ffff800010152e10 <queued_spin_lock_slowpath> ffff800010e11984: 17fffff5 b ffff800010e11958 <_raw_spin_lock_irqsave+0x58> ffff800010e11988: d2800c00 mov x0, #0x60 // #96 ffff800010e1198c: d50342df msr daifset, #0x2 ffff800010e11990: 17ffffe5 b ffff800010e11924 <_raw_spin_lock_irqsave+0x24> ffff800010e11994: f9800011 prfm pstl1strm, [x0] ffff800010e11998: 885f7c02 ldxr w2, [x0] ffff800010e1199c: 4b010042 sub w2, w2, w1 ffff800010e119a0: 8803fc02 stlxr w3, w2, [x0] ffff800010e119a4: 35ffffa3 cbnz w3, ffff800010e11998 <_raw_spin_lock_irqsave+0x98> ffff800010e119a8: 17fffd70 b ffff800010e10f68 <_raw_read_unlock+0x50> ffff800010e119ac: f9800071 prfm pstl1strm, [x3] ffff800010e119b0: 885ffc60 ldaxr w0, [x3] ffff800010e119b4: 4a010004 eor w4, w0, w1 ffff800010e119b8: 35000064 cbnz w4, ffff800010e119c4 <_raw_spin_lock_irqsave+0xc4> ffff800010e119bc: 88047c62 stxr w4, w2, [x3] ffff800010e119c0: 35ffff84 cbnz w4, ffff800010e119b0 <_raw_spin_lock_irqsave+0xb0> ffff800010e119c4: 17fffd90 b ffff800010e11004 <_raw_write_lock_irqsave+0x74> ffff800010e119c8: f9800011 prfm pstl1strm, [x0] ffff800010e119cc: 885f7c03 ldxr w3, [x0] ffff800010e119d0: 4b020063 sub w3, w3, w2 ffff800010e119d4: 8804fc03 stlxr w4, w3, [x0] ffff800010e119d8: 35ffffa4 cbnz w4, ffff800010e119cc <_raw_spin_lock_irqsave+0xcc> ffff800010e119dc: 17fffd9e b ffff800010e11054 <_raw_read_unlock_irqrestore+0x34> ffff800010e119e0: f9800071 prfm pstl1strm, [x3] ffff800010e119e4: 885ffc61 ldaxr w1, [x3] ffff800010e119e8: 4a000024 eor w4, w1, w0 ffff800010e119ec: 35000064 cbnz w4, ffff800010e119f8 <_raw_spin_lock_irqsave+0xf8> ffff800010e119f0: 88047c62 stxr w4, w2, [x3] ffff800010e119f4: 35ffff84 cbnz w4, ffff800010e119e4 <_raw_spin_lock_irqsave+0xe4> ffff800010e119f8: 17fffdc6 b ffff800010e11110 <_raw_spin_trylock+0x88> ffff800010e119fc: f9800011 prfm pstl1strm, [x0] ffff800010e11a00: 885ffc01 ldaxr w1, [x0] ffff800010e11a04: 11080021 add w1, w1, #0x200 ffff800010e11a08: 88027c01 stxr w2, w1, [x0] ffff800010e11a0c: 35ffffa2 cbnz w2, ffff800010e11a00 <_raw_spin_lock_irqsave+0x100> ffff800010e11a10: 17fffde9 b ffff800010e111b4 <_raw_read_trylock+0x84> ffff800010e11a14: f9800011 prfm pstl1strm, [x0] ffff800010e11a18: 885f7c02 ldxr w2, [x0] ffff800010e11a1c: 4b010042 sub w2, w2, w1 ffff800010e11a20: 88037c02 stxr w3, w2, [x0] ffff800010e11a24: 35ffffa3 cbnz w3, ffff800010e11a18 <_raw_spin_lock_irqsave+0x118> ffff800010e11a28: 17fffdef b ffff800010e111e4 <_raw_read_trylock+0xb4> ffff800010e11a2c: f9800071 prfm pstl1strm, [x3] ffff800010e11a30: 885ffc61 ldaxr w1, [x3] ffff800010e11a34: 4a000024 eor w4, w1, w0 ffff800010e11a38: 35000064 cbnz w4, ffff800010e11a44 <_raw_spin_lock_irqsave+0x144> ffff800010e11a3c: 88047c62 stxr w4, w2, [x3] ffff800010e11a40: 35ffff84 cbnz w4, ffff800010e11a30 <_raw_spin_lock_irqsave+0x130> ffff800010e11a44: 17fffe0b b ffff800010e11270 <_raw_write_trylock+0x88> ffff800010e11a48: f9800071 prfm pstl1strm, [x3] ffff800010e11a4c: 885ffc60 ldaxr w0, [x3] ffff800010e11a50: 4a010004 eor w4, w0, w1 ffff800010e11a54: 35000064 cbnz w4, ffff800010e11a60 <_raw_spin_lock_irqsave+0x160> ffff800010e11a58: 88047c62 stxr w4, w2, [x3] ffff800010e11a5c: 35ffff84 cbnz w4, ffff800010e11a4c <_raw_spin_lock_irqsave+0x14c> ffff800010e11a60: 17fffe2c b ffff800010e11310 <_raw_spin_trylock_bh+0x80> ffff800010e11a64: f9800011 prfm pstl1strm, [x0] ffff800010e11a68: 885f7c02 ldxr w2, [x0] ffff800010e11a6c: 4b010042 sub w2, w2, w1 ffff800010e11a70: 8803fc02 stlxr w3, w2, [x0] ffff800010e11a74: 35ffffa3 cbnz w3, ffff800010e11a68 <_raw_spin_lock_irqsave+0x168> ffff800010e11a78: 17fffe39 b ffff800010e1135c <_raw_read_unlock_bh+0x44> ffff800010e11a7c: f9800011 prfm pstl1strm, [x0] ffff800010e11a80: 885ffc01 ldaxr w1, [x0] ffff800010e11a84: 11080021 add w1, w1, #0x200 ffff800010e11a88: 88027c01 stxr w2, w1, [x0] ffff800010e11a8c: 35ffffa2 cbnz w2, ffff800010e11a80 <_raw_spin_lock_irqsave+0x180> ffff800010e11a90: 17fffe4a b ffff800010e113b8 <_raw_read_lock+0x48> ffff800010e11a94: f9800071 prfm pstl1strm, [x3] ffff800010e11a98: 885ffc60 ldaxr w0, [x3] ffff800010e11a9c: 4a010004 eor w4, w0, w1 ffff800010e11aa0: 35000064 cbnz w4, ffff800010e11aac <_raw_spin_lock_irqsave+0x1ac> ffff800010e11aa4: 88047c62 stxr w4, w2, [x3] ffff800010e11aa8: 35ffff84 cbnz w4, ffff800010e11a98 <_raw_spin_lock_irqsave+0x198> ffff800010e11aac: 17fffe5d b ffff800010e11420 <_raw_write_lock_bh+0x58> ffff800010e11ab0: f9800011 prfm pstl1strm, [x0] ffff800010e11ab4: 885ffc01 ldaxr w1, [x0] ffff800010e11ab8: 11080021 add w1, w1, #0x200 ffff800010e11abc: 88027c01 stxr w2, w1, [x0] ffff800010e11ac0: 35ffffa2 cbnz w2, ffff800010e11ab4 <_raw_spin_lock_irqsave+0x1b4> ffff800010e11ac4: 17fffe6d b ffff800010e11478 <_raw_read_lock_bh+0x48> ffff800010e11ac8: f9800071 prfm pstl1strm, [x3] ffff800010e11acc: 885ffc60 ldaxr w0, [x3] ffff800010e11ad0: 4a010004 eor w4, w0, w1 ffff800010e11ad4: 35000064 cbnz w4, ffff800010e11ae0 <_raw_spin_lock_irqsave+0x1e0> ffff800010e11ad8: 88047c62 stxr w4, w2, [x3] ffff800010e11adc: 35ffff84 cbnz w4, ffff800010e11acc <_raw_spin_lock_irqsave+0x1cc> ffff800010e11ae0: 17fffe80 b ffff800010e114e0 <_raw_write_lock+0x58> ffff800010e11ae4: f9800071 prfm pstl1strm, [x3] ffff800010e11ae8: 885ffc60 ldaxr w0, [x3] ffff800010e11aec: 4a010004 eor w4, w0, w1 ffff800010e11af0: 35000064 cbnz w4, ffff800010e11afc <_raw_spin_lock_irqsave+0x1fc> ffff800010e11af4: 88047c62 stxr w4, w2, [x3] ffff800010e11af8: 35ffff84 cbnz w4, ffff800010e11ae8 <_raw_spin_lock_irqsave+0x1e8> ffff800010e11afc: 17fffe93 b ffff800010e11548 <_raw_spin_lock_bh+0x58> ffff800010e11b00: f9800071 prfm pstl1strm, [x3] ffff800010e11b04: 885ffc60 ldaxr w0, [x3] ffff800010e11b08: 4a010004 eor w4, w0, w1 ffff800010e11b0c: 35000064 cbnz w4, ffff800010e11b18 <_raw_spin_lock_irqsave+0x218> ffff800010e11b10: 88047c62 stxr w4, w2, [x3] ffff800010e11b14: 35ffff84 cbnz w4, ffff800010e11b04 <_raw_spin_lock_irqsave+0x204> ffff800010e11b18: 17fffea8 b ffff800010e115b8 <_raw_spin_lock+0x58> ffff800010e11b1c: f9800011 prfm pstl1strm, [x0] ffff800010e11b20: 885f7c02 ldxr w2, [x0] ffff800010e11b24: 4b010042 sub w2, w2, w1 ffff800010e11b28: 8803fc02 stlxr w3, w2, [x0] ffff800010e11b2c: 35ffffa3 cbnz w3, ffff800010e11b20 <_raw_spin_lock_irqsave+0x220> ffff800010e11b30: 17fffef1 b ffff800010e116f4 <_raw_read_unlock_irq+0x34> ffff800010e11b34: f9800011 prfm pstl1strm, [x0] ffff800010e11b38: 885ffc01 ldaxr w1, [x0] ffff800010e11b3c: 11080021 add w1, w1, #0x200 ffff800010e11b40: 88027c01 stxr w2, w1, [x0] ffff800010e11b44: 35ffffa2 cbnz w2, ffff800010e11b38 <_raw_spin_lock_irqsave+0x238> ffff800010e11b48: 17ffff0e b ffff800010e11780 <_raw_read_lock_irq+0x50> ffff800010e11b4c: f9800071 prfm pstl1strm, [x3] ffff800010e11b50: 885ffc60 ldaxr w0, [x3] ffff800010e11b54: 4a010004 eor w4, w0, w1 ffff800010e11b58: 35000064 cbnz w4, ffff800010e11b64 <_raw_spin_lock_irqsave+0x264> ffff800010e11b5c: 88047c62 stxr w4, w2, [x3] ffff800010e11b60: 35ffff84 cbnz w4, ffff800010e11b50 <_raw_spin_lock_irqsave+0x250> ffff800010e11b64: 17ffff24 b ffff800010e117f4 <_raw_write_lock_irq+0x64> ffff800010e11b68: f9800071 prfm pstl1strm, [x3] ffff800010e11b6c: 885ffc60 ldaxr w0, [x3] ffff800010e11b70: 4a010004 eor w4, w0, w1 ffff800010e11b74: 35000064 cbnz w4, ffff800010e11b80 <_raw_spin_lock_irqsave+0x280> ffff800010e11b78: 88047c62 stxr w4, w2, [x3] ffff800010e11b7c: 35ffff84 cbnz w4, ffff800010e11b6c <_raw_spin_lock_irqsave+0x26c> ffff800010e11b80: 17ffff3b b ffff800010e1186c <_raw_spin_lock_irq+0x64> ffff800010e11b84: f9800011 prfm pstl1strm, [x0] ffff800010e11b88: 885ffc01 ldaxr w1, [x0] ffff800010e11b8c: 11080021 add w1, w1, #0x200 ffff800010e11b90: 88027c01 stxr w2, w1, [x0] ffff800010e11b94: 35ffffa2 cbnz w2, ffff800010e11b88 <_raw_spin_lock_irqsave+0x288> ffff800010e11b98: 17ffff50 b ffff800010e118d8 <_raw_read_lock_irqsave+0x58> ffff800010e11b9c: f9800071 prfm pstl1strm, [x3] ffff800010e11ba0: 885ffc60 ldaxr w0, [x3] ffff800010e11ba4: 4a010004 eor w4, w0, w1 ffff800010e11ba8: 35000064 cbnz w4, ffff800010e11bb4 <_raw_spin_lock_irqsave+0x2b4> ffff800010e11bac: 88047c62 stxr w4, w2, [x3] ffff800010e11bb0: 35ffff84 cbnz w4, ffff800010e11ba0 <_raw_spin_lock_irqsave+0x2a0> ffff800010e11bb4: 17ffff70 b ffff800010e11974 <_raw_spin_lock_irqsave+0x74> ffff8000102591f0 <perf_event_exit_cpu>: ffff8000102591f0: a9bf7bfd stp x29, x30, [sp,#-16]! ffff8000102591f4: 910003fd mov x29, sp ffff8000102591f8: 97ffdbf4 bl ffff8000102501c8 <perf_event_exit_cpu_context> ffff8000102591fc: 52800000 mov w0, #0x0 // #0 ffff800010259200: a8c17bfd ldp x29, x30, [sp],#16 ffff800010259204: d65f03c0 ret ffff800010259208: f9800031 prfm pstl1strm, [x1] ffff80001025920c: c85f7c20 ldxr x0, [x1] ffff800010259210: b27b0000 orr x0, x0, #0x20 ffff800010259214: c8037c20 stxr w3, x0, [x1] ffff800010259218: 35ffffa3 cbnz w3, ffff80001025920c <perf_event_exit_cpu+0x1c> ffff80001025921c: 17ffc8b9 b ffff80001024b500 <set_fs+0x48> [SNIP] ffff8000102596e0: 17fff669 b ffff800010257084 <perf_prepare_sample+0x5b4> ffff8000102596e4: f9800091 prfm pstl1strm, [x4] ffff8000102596e8: c85f7c80 ldxr x0, [x4] ffff8000102596ec: ca030001 eor x1, x0, x3 ffff8000102596f0: b5000081 cbnz x1, ffff800010259700 <perf_event_exit_cpu+0x510> ffff8000102596f4: c801fc82 stlxr w1, x2, [x4] ffff8000102596f8: 35ffff81 cbnz w1, ffff8000102596e8 <perf_event_exit_cpu+0x4f8> ffff8000102596fc: d5033bbf dmb ish ffff800010259700: 17fffa30 b ffff800010257fc0 <perf_swevent_set_period+0x60> ffff800010259704: f98000d1 prfm pstl1strm, [x6] Thanks, Leo

6 years, 2 months

1
0
0 0

Re: progress in btrace with etm in gdb

by Mathieu Poirier

i Hi Zied, As requested before, always add the CS mailing list when interacting with us. There is a fair amount of people on there that would surely be interested in this work. I also CC'd the linaro-toolchain group since some of the content below is related to what they do. On Mon, 17 Feb 2020 at 10:08, zied guermazi <guermazi_zied(a)yahoo.com> wrote: > > Hi Mike, hi Matthieu > it works! > > > > On Monday, December 16, 2019, 11:20:20 PM GMT+1, zied guermazi <guermazi_zied(a)yahoo.com> wrote: > > > hi Mike, hi Mathieu > last few weeks I was able to spend some time on implementing this feature, and I want to share the status with you and get your recommendation on organizational and technical level. > so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7). > I would like to push this on git, first for review and second for integration and creating traction . Do you think it is ok to push it in this status (feature partially achieved) ? is linaro gdb git the correct one? who is the maintainer of this part of gdb? I do not have an ARMv8 platform to test. who can support here? I will address your questions one by one: Q: Do you think it is ok to push it in this status (feature partially achieved) ? A: That depends on how advanced things are. If it is stable (i.e it does something) and can be used as a starting point for other people to work on, then there is probably value in publishing your work. Q: is linaro gdb git the correct one? A: I see from your other email that you've already published your work. Q: who is the maintainer of this part of gdb? A: I'm sure the GDB project has documentation and a well defined process that would identify who you should submit your code to. Q: I do not have an ARMv8 platform to test. who can support here? A: No doubt you'd get a lot more interest if you were working on V8. I suggest purchasing a dragonboard 410c - they are super cheap, well supported and one of our CS reference platforms. I think we talked about that before... > > during the implementation few technical question raised: > - etm tracing collection requires selecting a trace sink. and I have two alternatives: either extending the "record btrace etm" command (used to start tracing) with a sink as an argument or extending the command "set record btrace" (general configuration of tracing) with etm sink sub-command? (I have hard-coded it currently to be able to progress) I would assume this "set record btrace" command has an effect on the current session only. If so I would go for the latter option. > - currently I am hardcoding the path "/sys/bus/event_source/devices/cs_etm/" as the default etm source, is this guaranteed to be unique? can we have a system with many etm sources enumerated in the sysfs. > I am very confused by this question. Yes, the path "/sys/bus/event_source/devices/cs_etm/" is guaranteed to be unique but it is by no means a "default source". Is is simply a directory used by the perf tools to have more details on the CS specifics for the running platform. Nowadays it is fair to assume there is one ETM perf CPU, all enumerated under sysfs. Also keep in mind that processes are being moved around by the scheduler and as such, a specific source can't be hard coded. > for parsing the traces I will need some configuration parameters like the content of registers ETMCR, ETMIDR, ETMCCER, ETMTRACEIDR. if my understanding of the implementation of perf is correct, it is collecting them from the sysfs files located in /sys/bus/event_source/devices/cs_etm/cpu0/mgmt/. which are global for the system. my question is what will happen if two process are requesting tracing at the same time? how to differentiate between traces going to one session from the second one? is it possible to get the parameters of a given session by some kind of ioctl request to the file descriptor we get out of sys_perf_open call? Configuration of the tracers does indeed need to be considered. At this time we assume all the tracers in an implementation are similar, hence using ".../cpu0/mgmt". The information gathered from there is related to the static configuration of the tracers. Per session dynamic configuration is collected from the perf tools command line and communicated to the perf infrastructure for later interpretation by the decoding code when instantiating a decoder from the openCSD library. Since the current framework handles only N:1 source/sink configuration, there can only be one trace session using a sink. There is currently no way to extract trace session configuration other than the user space perf tools mechanic. > > I will publish those queries in the linaro coresight and gdb forums, I wanted first to align with you especially on the organizational issues, before going to a bigger round. > > Thanks for your support > Zied Guermazi > >

6 years, 2 months

1
0
0 0

[ACTIVITY] 10 - 14 February 2020

by Diana Picus

== Progress == * More Morello (updating for new capability encoding) * Went to the embassy to get my passport * Read a couple ARM policy refreshers... == Plan == * More Morello

6 years, 2 months

1
0
0 0

[ACTIVITY] week ending 16 Feb 2020

by Richard Henderson

[VIRT-262 # ARMv8.1-PAN ] [VIRT-273 # ARMv8.2-ATS1E1 ] [VIRT-276 # ARMv8.2-UAO ] All three now merged. [VIRT-349 # QEMU SVE2 Support ] Refreshed an old patch set tidying up pmul. [VIRT-327 # Richard's upstream QEMU work ] Patch review: - ARMv8.1-PMU - riscv vector extension, partial - cpu_exec_step_atomic race Refresh x86_64 vsyscall implementation Refresh aa64_va_parameter optimization Refresh vfp feature and decodetree cleanup Refresh tcg/arm epilogue expansion Refresh arm vector improvements Pass sve fmla arguments by value. Fix some advsimd vs sve extension errors r~

6 years, 2 months

1
0
0 0

[ACTIVITY] 10-14 February 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: posted v4 * GCC: * GCC-9: continued work for validation of -mpure-code on v6m: posted updated patch for latent bug on trunk * GCC upstream validation: - reported a couple of failures/regressions - fixed FDPIC build broken on trunk * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m * FDPIC GDB

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 16 2020

by Alex Bennée

VirtIO Related Work =================== This is essentially a mind-map of bullet points as we work out what concrete work items should be implemented by the TCWG Virt hackers (most likely just me ;-) Xen for Automotive ([LBI-24]) - Things that need doing - support for virtio in core (i.e. not just emulated devices) - support for virtio-iommu and sharing memory between guests (ivshmemv2?) - support virtio over ivshmemv2 (would native virtio be supported?) - support for vhost over shared memory (zero copy device emulation) - support isolating userspace emulation from hvm (vhost-user) - Why? - userspace emulation has performance benefits (exit-less, polling) - growing number of virtio devices for that guests support [LBI-24] <https://projects.linaro.org/browse/LBI-24> Virtualizing Android ([LBI-38]) - Builds on Google's work on Cuttlefish - New Android Device model using VirtIO (including VirtGPU) \o/! - Used to run on QEMU, now targeting CrosVM - Potential interest in using as a HAL layer - Potential work items - Better support for ARM in CrosVM - Is QEMU of interest to members? (emulation & tooling - unlike CrosVM) - Is a virtualised Android HAL possible - Where does Hafnium fit it? [LBI-38] <https://projects.linaro.org/browse/LBI-38> QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - re-based [a v7 branch] [VIRT-281] <https://projects.linaro.org/browse/VIRT-281> [a v7 branch] <https://github.com/stsquad/qemu/tree/gdbstub/sve-registers-v7> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id: <20200130113223.31046-10-alex.bennee(a)linaro.org> - posted [PATCH v2 00/19] testing and plugin updates Message-Id: <20200213225109.13120-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [3/3] ======================= [RFC PATCH 1/2] GitLab CI: avoid calling before_scripts on unintended jobs Message-Id: <5d0def0e-0943-3345-784d-80f8ccc318b9(a)redhat.com> [PATCH v1 00/14] tests/vm: Add support for aarch64 VMs Message-Id: <20200205212920.467-1-robert.foley(a)linaro.org> - CLOSING NOTE [2020-02-07 Fri 19:56] Some problems with hangs, not sure about using threads/file approach. Added: <2020-02-06 Thu> [PATCH 0/2] target/arm: Pass arguments by value for sve FMLA/FCMLA Message-Id: <20200212025145.24300-1-richard.henderson(a)linaro.org> Absences ======== - 17t-24th Feb Half Term - 23rd-27th March BUD20 Current Review Queue ==================== * [PATCH v16 00/10] VIRTIO-IOMMU device Message-Id: <20200214132745.23392-1-eric.auger(a)redhat.com> Added: <2020-02-14 Fri> * [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com> Added: <2020-02-14 Fri> * {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com> Added: <2020-02-13 Thu> * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> -- Alex Bennée

6 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 14 Feb

by Peter Maydell

Progress: * VIRT-241 [QEMU ISA Support for A-profile] - Looking into implementing some of the easier, smaller architecture features - Implemented ARMv8.1-VMID16 (16-bit VMID support), which is trivial for QEMU because it doesn't care much about VMIDs - Working on ARMv8.1-PMU and ARMv8.4-PMU: it turns out that we already have most of these extensions, so we just need to finish off some smaller pieces and fix one or two bugs. Sent out a patchset implementing these. - Found a bunch of ID-register related bugs in the process, which I have fixes for - Implemented the "mandatory from v8.2" ACTLR2 and HACTLR2 registers * VIRT-65 [QEMU upstream maintainership] - code review: - series from Laurent fixing a long-standing issue with handling of realtime signals in our linux-user code - imx6 model patches to fix a watchdog device bug and add the watchdog to our imx6 boards - final few unreviewed patches in rth's "PAN, ATS1E1, UAO" series - respin of the json QAPI Sphinx conversion patchset; hopefully the first half of this is now uncontroversial cleanups that can go in while the second half gets code reviewed thanks -- PMM

6 years, 3 months

1
0
0 0

[ACTIVITY] Week 06

by Yvan Roux

o LLVM: * 10.0.0 RC: - reported issues upstream - upload AArch64 binaries * IR Outliner: - looking at the branch status o Misc * Resurrected an old GNU toolchain prototype w/r to Linux kernel size reduction. * Various meetings and discussions.

6 years, 3 months

1
0
0 0

[ACTIVITY] 3-7 February 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: posted v3, no feedback yet. * GCC: * GCC-9: continued work for validation of -mpure-code on v6m: reproduced latent bug on trunk, fix accepted, but I'm still worried by it not setting all insn attributes correctly. * GCC upstream validation: - reported a couple of failures/regressions - FDPIC build broken on trunk * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m * Fix FDPIC build

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending 9 Feb 2020

by Richard Henderson

[ Linux on ARM mini-conference ] 2 days. Some interesting stuff in the future hardware directions talks. Helped out a bit with ABI history in the toolchain breakout session. Some good hallway discussion, especially re record-replay on aarch64. I should make time this weekend to produce a more complete trip report. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Posted v7 -- merged! [VIRT-262 # ARMv8.1-PAN ] [VIRT-273 # ARMv8.2-ATS1E1 ] [VIRT-276 # ARMv8.2-UAO ] Posted v3. [VIRT-327 # Richard's upstream QEMU work ] Random patch review. Updated some aa32 vfp cleanup patches; still need to re-test and post. r~

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 9 2020

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - posted [PATCH v6 00/22] gdbstub refactor and SVE support Message-Id: <20200205171031.22582-1-alex.bennee(a)linaro.org> [VIRT-281] <https://projects.linaro.org/browse/VIRT-281> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id: <20200130113223.31046-10-alex.bennee(a)linaro.org> - posted [PULL 00/16] testing updates Message-Id: <20200204184028.13708-1-alex.bennee(a)linaro.org> - did some tweaking of tooling and workflow - posted [PATCH v1 0/5] plugins/next Message-Id: <20200207150118.23007-1-alex.bennee(a)linaro.org> - posted [PATCH v2] .readthedocs.yml: specify some minimum python requirements Message-Id: <20200206163120.31899-1-alex.bennee(a)linaro.org> - posted attempted to replicate bug 1860610 Message-Id: <157973034496.4473.7342941286220324914.malonedeb(a)soybean.canonical.com> - retested v6 of the VHE series Message-Id: <20200201192916.31796-31-richard.henderson(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [2/2] ======================= [RFC PATCH 1/2] GitLab CI: avoid calling before_scripts on unintended jobs Message-Id: <5d0def0e-0943-3345-784d-80f8ccc318b9(a)redhat.com> [PATCH v1 00/14] tests/vm: Add support for aarch64 VMs Message-Id: <20200205212920.467-1-robert.foley(a)linaro.org> - CLOSING NOTE [2020-02-07 Fri 19:56] Some problems with hangs, not sure about using threads/file approach. Added: <2020-02-06 Thu> Absences ======== - 23rd-27th March BUD20 Current Review Queue ==================== * [RFC 0/9] Add an interVM memory sharing device Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com> Added: <2020-02-05 Wed> * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> * {RFC PATCH v3 000/132} Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> -- Alex Bennée

6 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 7 Jan

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - sent pullreq with some of the pending rST doc conversion work - finished the work on converting the json QAPI doc comments from texinfo to rst, and sent out a patchset for this - code review: - Cornelia's patches rstifying some s390 docs - rth's 'Reduce aa64_va_parameter overhead' patch - a patchset fixing some minor memory leaks in timer devices - rth's PAN/ATS1E1/UAO patchset - sent out an arm pullreq I seem to be currently keeping on top of the code-review queue with about an afternoon a week spent on review, which is pleasing. thanks -- PMM

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending 0202-2020

by Richard Henderson

[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Posted v5 & v6. { [VIRT-262 # ARMv8.1-PAN Privileged Access Never] [VIRT-273 # ARMv8.2-ATS1E1 ] [VIRT-276 # ARMv8.2-UAO ] Posted v2. } [VIRT-327 # Richard's upstream QEMU work ] Addressed a performance regression, of sorts, for ppc32, caused by one of my cputlb reorgs. r~

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 2 2020

by Alex Bennée

Upstream Work ([VIRT-109]) ========================== - posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id: <20200130113223.31046-10-alex.bennee(a)linaro.org> - even more furtling and messing around trying to get CI gree - very annoying docker failure I've been unable to replicate - possibly a broken parallel docker build - see [current state] - posted [PATCH] target/arm: fix TCG leak for fcvt half->double Message-Id: <20200131153439.26027-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> [current state] <https://github.com/stsquad/qemu/tree/testing/next> Misc ==== - sorting out travel for BUD20 - reading up on VirtIO for various LBI calls Completed Reviews [0/0] ======================= [PATCH 0/8] tests/vm: Add support for aarch64 VMs Message-Id: <20200124165335.422-1-robert.foley(a)linaro.org> [PATCH v2 0/4] migration: Replace gemu_log with qemu_log Message-Id: <20200117192808.129398-1-jkz(a)google.com> - CLOSING NOTE [2020-02-01 Sat 20:38] Looks ok Added: <2020-01-21 Tue> Absences ======== - 23rd-27th March BUD20 Current Review Queue ==================== * [PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE Message-Id: <20200129235614.29829-1-richard.henderson(a)linaro.org> Added: <2020-01-30 Thu> * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> * {RFC PATCH v3 000/132} Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> -- Alex Bennée

6 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 31 Jan

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - more work on rST doc conversion. I've started in on converting the documentation that we auto-generate from doc comments in json files (this covers QEMU's QMP protocol and a similar protocol for the guest-agent). I now have something that is basically the right shape and correctly handles 'Command' and 'Object' (with 'Enum' and Alternate' and some other corner cases still to do). Might be able to send a patchset out next week with luck. This is I think the last major obstacle to the rST conversion -- once it's done the rest is just simple-but-tedious conversion of the remaining document files. - code review: + aspeed 'misc fixes and extensions' patchset + "Stop wrongly programming GICR_PENDBASER.PTZ bit" bugfix patch + KVM 'adjust virtual time when VM starts/stops' patchset + last few unreviewed patches in RTH's VHE patchset respin -- PMM

6 years, 3 months

1
0
0 0

[ACTIVITY] 27-31 January 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: fixed bugs found when running the testsuite with the new option activated. Adding warnings to help understand potential placement changes. * GCC: * GCC-9: continued work for validation of -mpure-code on v6m: the patch applies cleanly in the branch, but there are unexpected failures compared to trunk. Debugging. * GCC upstream validation: - reported a couple of failures/regressions * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m

6 years, 3 months

1
0
0 0

[ACTIVITY] 27 - 31 January 2020

by Diana Picus

== Progress == * Updating lldb for the latest Morello architecture changes * Started running the tests for llvm 10.0.0-rc1 == Plan == * Check up on the release * More Morello

6 years, 3 months

1
0
0 0

[ACTIVITY] Week ending 31st January 2020

by Peter Smith

[LLD] Fixed interworking problem causing Thumb2 kernel not to Some diagnosis of LLD problem when .ctor and .init_array initialisers are used. [LLVM-MC] Upstream reviews for some methods to avoid llvm-mc making symbols inter-positionable that the code generator has assumed are not. [Morello] reviews. [Other] Clean up my Jira tickets so that they can be passed on or closed. This is my last week as a Linaro assignee, will be going back to the Arm as of next week. I've really enjoyed my time here, thank you for having me.

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending 24th January 2020

by Peter Smith

Buildbots, busy week that took up most of spare time - deploying timezone fix to containers - a couple of weekend patches that broke Arm and AArch64 bisected and followed up. - difficult to track down stage-2 failure that was difficult to work out whether there was a bug in clang, or a code-gen failure in the backend, also made it harder to bisect. Turned out that it had caused more easy to bisect failures in other projects and by the time I'd found the patch it had been fixed. [ClangBuiltLinux] LLD's simplified interworking looks to be insufficient for the linux kernel thumb-2 build. Got agreement with upstream on how to proceed. Have a patch ready to send upstream. A small amount of upstream review and bisecting some Linaro CI build failure for the -fpatchable-functions feature in Clang-10. Looks to have been resolved.

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending 26 Jan 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * tcg patch queue flush, including some VHE prereqs. * target/hppa patch queue flushing. * combined the two in-flight avr patch sets, hoping to move that project to completion. * patch review. * target/s390x local variable "leak" fix, to satisfy a static analyzer. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] * started rebasing, and addressing the collected comments from v4 in December. r~

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending Jan. 26 2020

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 0/3] current testing/next queue Message-Id: <20200122102223.20036-1-alex.bennee(a)linaro.org> - a bunch of reviews - investigation of documentation and CI failures - posted [PATCH v1 00/13] docker multiarch awareness Message-Id: <20200124204026.2107-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Misc ==== - looking at travel options for BUD20 Completed Reviews [8/8] ======================= [PATCH v2 0/5] linux-user: Implement x86_64 vsyscalls Message-Id: <20200116194341.402-1-richard.henderson(a)linaro.org> [PATCH 0/9] cputlb: Various cleanups Message-Id: <20200109024907.2730-1-richard.henderson(a)linaro.org> [PATCH] linux-user: Reserve space for brk Message-Id: <20200117230245.5040-1-richard.henderson(a)linaro.org> [PATCH] qapi: Fix code generation with Python 3.5 Message-Id: <20200116202558.31473-1-armbru(a)redhat.com> [PATCH 0/2] tests/tcg/multiarch: Add tests for implemented real Message-Id: <1579536554-30701-1-git-send-email-Filip.Bozuta(a)rt-rk.com> - CLOSING NOTE [2020-01-24 Fri 19:58] Needs to be less verbose Added: <2020-01-20 Mon> [PATCH rc2 00/25] target/avr merger Message-Id: <20200124005131.16276-1-f4bug(a)amsat.org> [PATCH 0/3] convert qemu-nbd, qemu-block-drivers to rST Message-Id: <20200116141511.16849-1-peter.maydell(a)linaro.org> [PATCH v2 0/6] buildsys: Build faster (mostly tools and linux-user) Message-Id: <20200118140619.26333-1-philmd(a)redhat.com> Absences ======== - 23rd-27th March BUD20 Current Review Queue ==================== * [PATCH 3/8] tests/vm: change wait_ssh to optionally wait for root. Message-Id: <20200124165335.422-4-robert.foley(a)linaro.org> Added: <2020-01-24 Fri> * [PATCH v2 0/4] migration: Replace gemu_log with qemu_log Message-Id: <20200117192808.129398-1-jkz(a)google.com> Added: <2020-01-21 Tue> * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> * {RFC PATCH v3 000/132} Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> -- Alex Bennée

6 years, 3 months

1
0
0 0

[ACTIVITY] 20-24 January 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: debugging * GCC: * GCC-9: continued work for validation of -mpure-code on v6m: local newlib/crt0 patches, patched simulator. Running various validation configurations * GCC upstream validation: - reported a couple of failures/regressions * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m

6 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 24 Jan

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - code review: + RTH's bug fix for the PAuth ComputePAC operation + patchset adding DMA support for Exynos4210 UARTs - small patchset documenting the right way to conditionally run expensive computations that are only needed for trace event output, and updating a handful of places that used an older (worse) method - more QEMU documentation conversion to rST; in particular wrote a Sphinx 'hxtool' extension to handle pulling out fragments of documentation from QEMU's '.hx' files which define and document command line options thanks -- PMM

6 years, 3 months

1
0
0 0

adding branch tracing and reverse debugging in GDB using Coresight etm traces

by zied guermazi

hiI am progressing in the implementation of the proposal "GDB process record and replay with ARM Coresight" https://lists.linaro.org/pipermail/coresight/2019-July/003021.html so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7). and I can collect the traces from the perf mmapped aux area. For parsing them I needed to gather information about the cpu and etm registers. those are available in the events of type PERF_RECORD_AUXTRACE_INFO in the priv section. priv is a kind of "opaque" data structure where the layout is depending on the perf pmu drivers. the implementation of perf tool gives a good example to follow. I needed also to make a wrapper around opencsd library and again perf was offering a good example to follow. those are good reasons to think about factoring out the functionality of parsing etm traces on linux system in a dedicated library that can be reused by other software, a kind of libcoresightperf.is there any plan or ongoing activities for such a library? Kind RegardsZied Guermazi

6 years, 3 months

1
0
0 0

[ACTIVITY] 20 - 24 January 2020

by Diana Picus

== Progress == * More EuroLLVM submissions reviews * More investigations into Morello bare metal debugging * Started looking into updating lldb for the latest Morello architecture changes * Asked Adhemerval to look into PR44157 == Plan == * More Morello * Keep an eye out for 10.0.0 - rc1

6 years, 3 months

1
0
0 0

[ACTIVITY] 20 - 24 Jan 2020

by Prathamesh Kulkarni

== This Week == * GCC development - PR47785: Addressed Richard's suggestions and posted patch upstream. - PR92867: Addressed Joseph's suggestions and posted patch upstream. * GCC bugzilla: - PR93397: Investigated issue. * Misc - Meetings == Next Week == - Continue ongoing tasks

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending 19 Jan 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * Implement x86_64-linux-user vsyscall page, which should keep Peter's pre-merge testing working. * Another tcg queue pull without the bits that depend on the vsyscall implementation above. * Posted v2 of some fixes to -accel option processing. * Posted v2 of some fixes to target/arm syn data syndrome bits. * Wrote some test cases for a target/arm pauth sbox fix. * Investigated a fix for memory layout of -static-pie binaries. * Random patch review. r~

6 years, 3 months

1
0
0 0

[ACTIVITY] week ending Jan. 19 2020

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - posted [PATCH v5 00/22] gdbstub refactor and SVE support (+check-tcg tweaks) Message-Id: <20200114150953.27659-3-alex.bennee(a)linaro.org> [VIRT-281] <https://projects.linaro.org/browse/VIRT-281> Upstream Work ([VIRT-109]) ========================== - played with [for-5.0 PATCH 00/11] Support for reverse debugging with GDB Message-Id: <157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower> - still broken but could be build stability - while reviewing vsyscall patches ran into qemu-x86_64, buster /sbin/ldconfig and setup_arg_pages (a mind dump) Message-Id: <874kwukmxr.fsf(a)linaro.org> - posted [qemu-web PATCH] documentation: update links to readthedocs Message-Id: <20200113103550.1133-1-alex.bennee(a)linaro.org> - we successfully recovered the qemu project name for rtd [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [3/3] ======================= [for-5.0 PATCH 00/11] Support for reverse debugging with GDB Message-Id: <157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower> - CLOSING NOTE [2020-01-13 Mon 18:00] Introduces some regressions into check-block that need to be fixed first. Added: <2020-01-06 Mon> [PATCH 0/4] migration: Replace gemu_log with qemu_log Message-Id: <20200114030138.260347-1-jkz(a)google.com> [PATCH 0/3] linux-user: Implement x86_64 vsyscalls Message-Id: <20200114210921.11216-4-richard.henderson(a)linaro.org> Current Review Queue ==================== * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> * {RFC PATCH v3 000/132} Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> * {RFC PATCH 00/10} hw/avr: Introduce the Arduino board Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org> Added: <2019-11-28 Thu> -- Alex Bennée

6 years, 3 months

1
0
0 0

[ACTIVITY] 13-17 January 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: found problems in the testsuite when the flag is activated by default * GCC: - trying to find a way to add run more validation of -mpure-code on v6m, to support a request to backport to gcc-9: need to patch newlib's crt0.S which has some offending sequences * GCC upstream validation: - updated scripts to cope with the new git repo and release branches names * misc: - infra fixes / troubleshooting / reviews - fixed problems with automatic bisection of gcc regressions == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * GCC-9: continue work for validation of -mpure-code on v6m

6 years, 3 months

1
0
0 0

[ACTIVITY] for week ending 17th January 2020

by Peter Smith

Morello - Upstream LLD INPUT_SECTION_FLAGS that I implemented downstream. Quite a few review comments to work through but I think I'm close to getting something accepted. This will hopefully come in useful for LLD with embedded systems. - Wrote down some definitions for the new relocations. LLD - landed fix for clang-built-linux-812 linux allyesconfig problem. - Quite a few upstream LLD and MC reviews Other Some research for the clang built linux conference.

6 years, 3 months

1
0
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[ACTIVITY] 13 - 17 January 2019

by Diana Picus

== Progress == * Out of office for 2 days * Reviewed EuroLLVM submissions * A bit more investigation into Morello bare metal debugging == Plan == * PR44157 * Morello bare metal debugging

6 years, 3 months

1
0
0 0

missing sound libraries in version 6.3.1

by Markus Bollinger

Hello Linaro team, I want to use your cross compiler version 6.3.1, but I miss the library asound and its header (alsa/asoundlib.h) What do I need to do to fix this ? Best regards, Markus Bollinger

6 years, 4 months

2
1
0 0

[ACTIVITY] Week 02

by Yvan Roux

* Part time at University o LLVM: * Machine Outliner: - New version submitted upstream o Misc * Various meetings and discussions.

6 years, 4 months

1
0
0 0

Fwd: about QEMU support for SVE2 POC

by Diana Picus

Hi Ana, I don't know anything about the POC myself, but I'm forwarding this so our QEMU folks can answer. Cheers, Diana ---------- Forwarded message --------- From: Ana Pazos <apazos(a)quicinc.com> Date: Fri, 10 Jan 2020 at 19:08 Subject: about QEMU support for SVE2 POC To: diana.picus(a)linaro.org <diana.picus(a)linaro.org> Cc: Ana Pazos <apazos(a)quicinc.com> Hello Diana, We at Qualcomm are trying to find out the POC for QEMU support for SVE2. We have been using QEMU with SVE support, and need to find out when SVE2 support will be added to QEMU. I assume Linaro is involved in this task. Do you know the POC? Thanks for the help! Ana.

6 years, 4 months

1
0
0 0

[ACTIVITY] 6-10 January 2020

by Christophe Lyon

== Progress == * BFD Linker: - GNU-629: non-contiguous memory support: sent updated versions with testcases and doc. * GCC: - trying to find a way to add run more validation of -mpure-code on v6m, to support a request to backport to gcc-9 - proposal to implement LLVM's -arm-assume-misaligned-load-store rejected by the community * GCC upstream validation: - reported/checked a few issues * misc: - infra fixes / troubleshooting / reviews - investigating problems with automatic bisection of gcc regressions - fixed a long-standing bug in proot == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker

6 years, 4 months

1
0
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[ACTIVITY] week ending Jan. 12 2020

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - respun [probably final iteration of gdbstub for SVE] [VIRT-281] <https://projects.linaro.org/browse/VIRT-281> [probably final iteration of gdbstub for SVE] <https://github.com/stsquad/qemu/tree/gdbstub/sve-registers-v5> Upstream Work ([VIRT-109]) ========================== - posted [PATCH v1 0/6] current testing/next (python and other fixes) Message-Id: <20200107135311.5215-1-alex.bennee(a)linaro.org> - posted [PATCH v3 0/6] semihosting read console support Message-Id: <20200108150252.6216-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/14] testing fixes and semihosting console support Message-Id: <20200109141858.14376-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/2] fix for bug 1859021 Message-Id: <20200110161626.31943-1-alex.bennee(a)linaro.org> - started looking at [for-5.0 PATCH 00/11] Support for reverse debugging with GDB Message-Id: <157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [4/4] ======================= [PATCH] freebsd: use python37 Message-Id: <20200106123746.18201-1-kraxel(a)redhat.com> - CLOSING NOTE [2020-01-07 Tue 11:13] Queued to my tree Added: <2020-01-07 Tue> [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Message-Id: <20190821162831.27811-1-georg.kotheimer(a)kernkonzept.com> - CLOSING NOTE [2020-01-07 Tue 11:27] Looks mostly ok modulo ensuring endianess is correct. Added: <2020-01-06 Mon> [PATCH v2 7/7] configure: Support -static-pie if requested Message-Id: <20191218223441.23852-6-richard.henderson(a)linaro.org> [PATCH 0/4] vl: Fixes for cleanups to -accel Message-Id: <20200109021710.1219-1-richard.henderson(a)linaro.org> Absences ======== - 6th Jan (4 day week) Current Review Queue ==================== * [PATCH v2 0/7] configure: Improve PIE and other linkage Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org> Added: <2020-01-06 Mon> * [for-5.0 PATCH 00/11] Support for reverse debugging with GDB Message-Id: <157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower> Added: <2020-01-06 Mon> * {RFC PATCH v3 000/132} Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> -- Alex Bennée

6 years, 4 months

1
0
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[ACTIVITY] week ending 12 Jan 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * TCG patch queue flush, including phase 1 increase for number of mmu_idx, on which VHE is dependent. * Random patch review. * Capstone update. * cputlb cleanup in prep for modeling ASIDs. r~

6 years, 4 months

1
0
0 0

[ACTIVITY] Week ending 10th January 2020

by Peter Smith

Morello: - Implemented INPUT_SECTION_FLAGS in LLD for the Morello toolchain, now in review. Took most of spare engineering time this week. Will attempt to upstream once committed in Morello - Fixed pr44451 upstream, it was already fixed on Morello toolchain. LLD: - Made an attempt to fix the LLD linux kernel allyesconfig + cortex-a53 erratum problem. Was not successful as kernel linker script is just about as awkward as possible for this problem. I have a good idea of what to try next. Will aim to fix early next week. - Quite a few upstream reviews, some pending from last year.

6 years, 4 months

1
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[ACTIVITY] report week ending 10 Jan

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - caught up on the backlog of email that accumulated over the Christmas break - investigated an intermittent failure of a test case on our BSD hosts which had reached a failure rate that was seriously impeding the flow of pull requests. Tracked it down to glib's g_source_ref/unref not being thread-safe unless the GSource is attached to a GMainContext; QEMU gets this right for its own use but a set of mock functions used for a few testcases were not doing so, resulting in occasional races where the GSource would get destroyed while it was still in use. - code review: + Beata's "inject DABT for load/store insns KVM couldn't emulate" patch + a minor cubieboard cleanup patchset + i.MX RNGC device emulation patch - annual review season, some time spent on that thanks -- PMM

6 years, 4 months

1
0
0 0

[ACTIVITY] 6 - 10 January 2019

by Diana Picus

== Progress == * Out of office until Tuesday * LLVM 9.0.1 - Uploaded final binaries - Still looking into PR44157 (CFI tests failing on armv7) * Morello LLDB - Trying to get bare metal debugging to work * More ARM Code of Conduct courses etc == Plan == * More Morello and PR44157

6 years, 4 months

1
0
0 0

[ACTIVITY] 2-3 January 2020

by Christophe Lyon

Short "week" == Progress == * BFD Linker: - GNU-629: non-contiguous memory support: Cleaning up, adding testcases. * GCC upstream validation: - reported/checked a few issues * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker

6 years, 4 months

1
0
0 0

[ACTIVITY] week ending 22 Dec 2019

by Richard Henderson

* Patch set cleaning up PIE/non-PIE linking - Add new support for static pie. * Another revision removing MMU_MODE_SUFFIX. * Random patch review. * Planning for Linux on ARM summit in Cambridge in February. r~

6 years, 4 months

1
0
0 0

Bot failure caused by f72d001e099871fd5943679a8377f2fcc675f860

by Michael Trent

To whom, I’m seeing a failure on this bot: -- Command Output (stderr): -- /home/buildslave/buildslave/clang-cmake-armv7-quick/stage1/bin/llvm-objdump: error: '/home/buildslave/buildslave/clang-cmake-armv7-quick/llvm/llvm/test/tools/llvm-objdump/Inputs/macho-stabs-x86_64': can't find target: : error: unable to get target for 'x86_64---macho', see --version and --triple. This is just a binary file verifier. Is it the case this bot doesn’t have a mach-o disassembler? And if so, is there a way to disable this test on this bot? Thanks! MDT

6 years, 4 months

2
2
0 0

[ACTIVITY] week ending Dec. 22 2019

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - posted [PATCH v4 00/21] gdbstub refactor and SVE support (+check-tcg tweaks) Message-Id: <20191220120438.16114-1-alex.bennee(a)linaro.org> [VIRT-281] <https://projects.linaro.org/browse/VIRT-281> GSoC Mentoring Afermath ([VIRT-348]) - started working on re-base of [TCG code quality tracking] - bit of a re-factor rethink required [TCG code quality tracking] <https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10> Upstream Work ([VIRT-109]) ========================== - posted [PULL 00/25] testing and logging updates Message-Id: <20191219104934.866-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/4] semihosting read console support Message-Id: <20191218180029.6744-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/5] semihosting read console support Message-Id: <20191220132246.6759-1-alex.bennee(a)linaro.org> [VIRT-109] <https://projects.linaro.org/browse/VIRT-109> Completed Reviews [4/4] ======================= {PATCH} Semihost SYS_READC implementation (v6) Message-Id: <20191104204230.12249-1-keithp(a)keithp.com> - CLOSING NOTE [2019-12-18 Wed 19:39] Found some issues with deadlocks, fixed and sent my own series including this patch. Added: <2019-12-06 Fri> [PATCH] docker: gtester is no longer used Message-Id: <1576632611-55032-1-git-send-email-pbonzini(a)redhat.com> - CLOSING NOTE [2019-12-20 Fri 12:20] Queued to my tree Added: <2019-12-18 Wed> {Qemu-devel} {RFC PATCH} Implement qemu_thread_yield for posix, use it in mttcg to handle EXCP_YIELD Message-Id: <20190717054655.14104-1-npiggin(a)gmail.com> - CLOSING NOTE [2019-12-20 Fri 13:11] Replied. [PATCH v2 00/28] cputlb: Remove support for MMU_MODE*_SUFFIX Message-Id: <20191216221158.29572-1-richard.henderson(a)linaro.org> Absences ======== - Christmas and New Year holidays Current Review Queue ==================== * [RFC PATCH 00/13] hw/timer/allwinner: Make it reusable Message-Id: <20191219185127.24388-1-f4bug(a)amsat.org> Added: <2019-12-19 Thu> * [PATCH v2 00/14] chardev: Use QEMUChrEvent enum in IOEventHandler typedef Message-Id: <20191218172009.8868-1-philmd(a)redhat.com> Added: <2019-12-18 Wed> * [RFC PATCH v3 000/132] Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> -- Alex Bennée

6 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 20 Dec

by Peter Maydell

Progress (covers two weeks; lost half of last week to the cold that's been going around the office here): * VIRT-65 [QEMU upstream maintainership] - code review + RTH's ARMv8.2-UAO patchset + RTH's ARMv8.1-PAN patchset + had a look at Huawei SDEI patchset; there are some things I don't like about the approach but I don't currently have any better ideas :-( Sent an email to the list to see if others have any suggestions. + Andrew Jones' patchset to pause the virtual timer when VM is paused + Some smmuv3 emulation fixes from Amazon + Support for emulating generic timers that run at platform-dependent frequency (rather than insisting they always run at 62.5MHz) - release work + herded a handful of key bugfixes into rc5; got rc5 and then the final release out of the door + got new s390 box into the set of machines we test QEMU on (IBM want to turn off the old one at the end of the year) + a couple of arm pull requests now 5.0 is open for new contributions thanks -- PMM

6 years, 4 months

1
0
0 0

[ACTIVITY] 16 - 20 December 2019

by Diana Picus

== Progress == * LLVM 9.0.1 - Had trouble with our TK1 machine - Trying to build rc3 on one of the buildbots - AArch64 rc3 looks fine * Morello - Got lldb-server working on android and it seems to behave fine - Working on getting the lldb test-suite to work in remote mode with the morello android simulator - Running into all sorts of issues with it == Plan == * More of the same * Out of office: 25-26 December, 1-7 January

6 years, 4 months

1
0
0 0

PE/COFF arm64 bdf/binutils targets

by Dimitri John Ledkov

One cannot use objcopy --target=efi-app-aarch64 because it appears that PE/COFF targets are not enabled for aarch64. Making UEFI & Windows on Snapdragon work harder. Given that Windows 10 is fully supported on aarch64, I assume it does have PE/COFF. Can someone please fix bfd to provide PE targets on aarch64? -- Regards, Dimitri.

6 years, 4 months

1
0
0 0

[ACTIVITY] 16-20 Dec 2019

by Christophe Lyon

== Progress == * GCC: - -mpure-code on v6m: committed. - investigated potential problem with -mno-unaligned-access. It was a wrong-user-code case, but maybe it would be desirable to implement an option like llvm's -arm-assume-misaligned-load-store * BFD Linker: - GNU-629: non-contiguous memory support: Now able to detect cases where input sections change size during the linker iterations and when linker-created stubs would cause overflows. * GCC upstream validation: - reported/checked a few issues * misc: - infra fixes / troubleshooting / reviews == Next == * Binutils: GNU-629: support non-contiguous memory regions in linker * Holidays: Dec 23rd-Jan 2nd

6 years, 4 months

1
0
0 0

clang-cmake-armv7-selfhost build failure

by John McCall

There’s been an ongoing failure on the clang-cmake-armv8-selfhost builder for the last day or so; see e.g.: http://lab.llvm.org:8011/builders/clang-cmake-armv7-selfhost/builds/2827/ This list is recorded as the contact information for that builder. It is apparently crashing in a tblgen backend that I just added: ``` Stack dump: 0. Program arguments: /home/buildslave/buildslave/clang-cmake-armv7-selfhost/stage1/bin/clang-tblgen -gen-clang-type-writer -I /home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include -I /home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include/clang/AST -I /home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/llvm/include /home/buildslave/buildslave/clang-cmake-armv7-selfhost/llvm/clang/include/clang/AST/TypeProperties.td --write-if-changed -o /home/buildslave/buildslave/clang-cmake-armv7-selfhost/stage1/tools/clang/include/clang/AST/AbstractTypeWriter.inc Segmentation fault (core dumped) ``` I would like to fix this, but I have no ability to reproduce it, and the crash information in the log is quite minimal. Is there a way I can get a shell on a system that can reproduce this, or at the very least get a line number for where exactly it is crashing? John.

6 years, 4 months

2
7
0 0

[ANNOUNCE] Arm provided GNU 9.2-2019.12 A-profile cross-toolchain release

by Ashok Bhat

The Arm GNU Toolchain for the A-profile Architecture ===================================================== We are pleased to announce the Arm release of the pre-built GNU cross-toolchain for the A-profile cores: GCC 9.2-2019.12. Further information about the GNU Arm toolchain and the release packages is available at Arm Developer site https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads Features ======== * Based on GCC 9.2 (See https://gcc.gnu.org/gcc-9/changes.html for details). Supported targets ================= * On Windows(x86_64): - AArch64 (bare-metal and Linux) - AArch32 (bare-metal and Linux hard-float) * On Linux(x86_64): - AArch64 (bare-metal, Linux and Linux big-endian) - AArch32 (bare-metal and Linux hard-float) * On Linux(AArch64) - AArch64 (bare-metal) - AArch32 (bare-metal and Linux hard-float) Changes since Arm release GCC 8.3-2019.03 ========================================= * Additional AArch64 hosted cross-toolchains for AArch64 (bare-metal) and AArch32 (bare-metal and Linux hard-float) * Additional Windows hosted cross-toolchains for AArch64 (Linux) and AArch32 (Linux hard-float) * Retired Linux(x86_64) toolchain for AArch64 (big-endian bare-metal) and AArch32 (Linux soft-float) * Changed toolchain naming convention to match standard target triplet naming convention, with vendor name being none. For example, arm-eabi is now arm-none-eabi. * Fixed the Windows toolchain convention to correctly include mingw-w64 instead of mingw32 Host Requirements ================== * x86-64 Linux: Ubuntu 16.04 LTS or later, or RHEL 7 or later * AArch64 Linux: Ubuntu 18.04 LTS or later, or RHEL 8 * x86 Windows: Windows 10 Package Versions ================= * GCC 9.2.1 * glibc 2.30 * binutils 2.33.1 * GDB 8.3.0 * libexpat 2.2.5 * Linux Kernel v4.20.13 * libgmp 4.3.2 * libisl 0.15 * libmpfr 3.1.6 * libmpc 1.0.3 * libiconv 1.15 Contact Arm =========== For any questions, please use the Arm Communities forums at: https://community.arm.com/tools/ Please report any bugs via the Linaro Bugzilla at: https://bugs.linaro.org/ IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 4 months

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[ACTIVITY] Week 50

by Yvan Roux

* One day off o LLVM: * Couple of failures with the bots * Machine Outliner: - Completed testcases - Validation before re-submission o Misc * Various meetings and discussions.

6 years, 4 months

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[ACTIVITY] week ending 15 Dec 2019

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] Following up on the feedback from last week on VHE and PAN, posted a patch set eliminating MMU_MODE*_SUFFIX, and the current limit of NB_MMU_IDX <= 12 that went with that. Some patch review. r~

6 years, 5 months

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[ACTIVITY] week ending Dec. 15 2019

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - posted [PATCH v3 00/20] gdbstub refactor and SVE support (+check-tcg tweaks) Message-Id: <20191211170520.7747-1-alex.bennee(a)linaro.org> GSoC Mentoring Afermath ([VIRT-348]) - started working on re-base of [TCG code quality tracking] - bit of a re-factor rethink required [TCG code quality tracking] <https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10> Upstream Work ([VIRT-109]) ========================== - posted [PATCH] target/arm: ensure we use current exception state after SCR update Message-Id: <20191209143723.6368-1-alex.bennee(a)linaro.org> - posted [PATCH v2] target/arm: ensure we use current exception state after SCR update Message-Id: <20191212114734.6962-1-alex.bennee(a)linaro.org> - did and initial tyre kicking of rth's mmu_idx clean-up patches Completed Reviews [3/3] ======================= [PATCH] target/arm: Display helpful message when hflags mismatch Message-Id: <20191209134552.27733-1-philmd(a)redhat.com> [PATCH v2 0/2] gdbstub: allow sending packet of arbitrary length Message-Id: <20191211160514.58373-1-damien.hedde(a)greensocs.com> [PATCH 0/2] tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-3-wainersm(a)redhat.com> Absences ======== - Christmas and New Year holidays Current Review Queue ==================== * {PATCH} Semihost SYS_READC implementation (v6) Message-Id: <20191104204230.12249-1-keithp(a)keithp.com> Added: <2019-12-06 Fri> * [RFC PATCH v3 000/132] Proof of concept for Meson integration Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com> Added: <2019-12-12 Thu> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> * {RFC PATCH 00/10} hw/avr: Introduce the Arduino board Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org> Added: <2019-11-28 Thu> -- Alex Bennée

6 years, 5 months

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[ACTIVITY] 9-13 Dec 2019

by Christophe Lyon

== Progress == * GCC: - -mpure-code on v6m: waiting for approval, pinged again. * BFD Linker: - GNU-629: non-contiguous memory support: Looking at how to handle the case where input sections change size during the linker iterations. * GCC upstream validation: - reported/checked a few issues * misc: - infra fixes / troubleshooting / reviews == Next == * GCC: pure-code/v6m, handle feedback * Binutils: GNU-629: support non-contiguous memory regions in linker == Future == Holidays: Dec 23rd-Jan 2nd

6 years, 5 months

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[ACTIVITY] Week ending 13th December 2019

by Peter Smith

Morello: - Updated clang driver to use lld with --image-base rather than a linker script. - LLD changes merged. - Fixed up a few problems spotted by CI and a test on the examples. - Thoughts on code sequences for an experimental descriptor based ABI. LLD: - Committed changes to fix branch patch and thunks interaction in instrumented Chromium build - Discussion about deploying BTI in large programs like Chromium with pre-compiled objects and lots of assembler files. Planned absences On holiday for the rest of the decade. First day back in the office 6th January

6 years, 5 months

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[ACTIVITY] week ending Dec. 8 2019

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - worked on [v3 rebase] - added a new test case and discovered a bug in upstream gdbserver - raised [GNU-647] to track it [v3 rebase] https://github.com/stsquad/qemu/tree/sve-registers-v3 [GNU-647] https://projects.linaro.org/browse/GNU-647 QEMU ARMv8.1 VHE ([VIRT_263]) ============================= - bunch of review and testing of rth's v4 series [VIRT_263] https://projects.linaro.org/browse/VIRT-263 Upstream Work ([VIRT-109]) ========================== - posted {PATCH v2 0/6} linux-user mmap debug cleanup Message-Id: <20191206110354.GA775461(a)stefanha-x1.localdomain> Completed Reviews [8/8] ======================= {PATCH 0/3} iotests: Check for the possibility to create large files Message-Id: <20191202101631.10003-1-thuth(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 10:14] Preparatory for the multiarch Travis tests. Added: <2019-12-02 Mon> {PATCH v2 0/2} Run tcg tests with tci on Travis Message-Id: <20191128153525.2646-1-thuth(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 10:21] will take v3 with --disable-kvm and sparc tweaks Added: <2019-11-28 Thu> {PATCH 0/2} flush CPU TB cache in breakpoint_invalidate Message-Id: <20191127220602.10827-1-jcmvbkbc(a)gmail.com> - CLOSING NOTE [2019-12-03 Tue 11:20] Needs a slightly neater solution than always flushing everything. Added: <2019-11-28 Thu> {PATCH 0/1} tests/vm: Allow to set path to qemu-img Message-Id: <20191114134246.12073-1-wainersm(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 11:37] Queued to my tree Added: <2019-11-14 Thu> {PATCH 0/4} docker: Update Travis-CI image to run acceptance tests Message-Id: <20190818231827.27573-1-philmd(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 16:03] Will wait for next iteration. {PATCH 0/4} python/qemu: New accel module and improvements Message-Id: <20191115180829.10275-1-wainersm(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 17:00] All looks good. I assume will be merged with another series that uses the new features. Added: <2019-11-28 Thu> {PATCH v7 0/8} Acceptance test: Add "boot_linux" acceptance test Message-Id: <20191104151323.9883-1-crosa(a)redhat.com> - CLOSING NOTE [2019-12-03 Tue 19:20] Broken for me with load_module failure Added: <2019-11-04 Mon> {PATCH v4 00/40} target/arm: Implement ARMv8.1-VHE Message-Id: <20191203022937.1474-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2019-12-06 Fri 18:35] Reviewed about half the patch set, will do the remainder on v5 once Peter's comments are addressed. Added: <2019-12-03 Tue> Current Review Queue ==================== * {PATCH} Semihost SYS_READC implementation (v6) Message-Id: <20191104204230.12249-1-keithp(a)keithp.com> Added: <2019-12-06 Fri> * {PATCH 0/2} tests/acceptance: Add boot vmlinux test Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com> Added: <2019-12-06 Fri> * {RFC PATCH 00/10} hw/avr: Introduce the Arduino board Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org> Added: <2019-11-28 Thu> * {RFC 0/3} tests/vhost-user-fs-test: add vhost-user-fs test case Message-Id: <20191025100152.6638-1-stefanha(a)redhat.com> Added: <2019-10-25 Fri> -- Alex Bennée

6 years, 5 months

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[ACTIVITY] 3x3 for week ending 6th December 2019

by Peter Smith

Morello: - Static linking patches committed to merge branch. - Dynamic linking patches up for review. - Agreed definition of what LLD for stage-1 looks like. - Discussions on what linker and ABI work is likely to be needed for stage-2. Linaro: Some LLD thunk/patch generation problems https://bugs.llvm.org/show_bug.cgi?id=44071 for a gigantic build of Chromium > 260 Mb .text section on AArch64. Diagnosed problems but will need to fix next week. Some support for ClangBuiltLinux with respect to some integrated assembler compatibility with GNU as. Buildbot duty. Pretty quiet, attempted to reproduce some timeouts seen on the LNT generate cmake. 3 minutes on an lightly loaded machine, exceeding 20 minutes in some cases on the heavily loaded buildbot host. Seems to have resolved itself with the latest container update. - Some changes to BTI for the Android team. All committed upstream. -- Adding PT_GNU_PROPERTY support. -- Increasing alignment of .note.gnu.property section to 8. Holiday - On holiday from Monday 16th to 3rd January inclusive. Back in office January 6th.

6 years, 5 months

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[ACTIVITY] report week ending 6 Dec

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - code review (have had a go at cutting down the backlog; down to six patchsets in my queue...): + reviewed the 'clock framework API' patchset; this is looking good, the only major question to sort out is what the right internal representation for the clock frq/period is + Paolo's series to add kernel-doc support to our Sphinx setup (which is a mashup of something I hacked together ages ago and more recent work from him) + RAS memory error support for KVM guests (mostly reviewing the easy bits and noting that others have provided code review comments on the rest) + reviewed RTH's MemTag emulation series + reviewed the bits of RTH's VHE series that Alex hadn't got to + tested an arm/acpi patchset from Huawei from March which had unfortunately fallen through the cracks. It failed 'make check' so they'll need to fix and resubmit :-( - release work: + we needed an rc4 + and it looks like we'll need an rc5 for one last important bugfix; I'm hoping we can do an rc and then actual release a few days later, though thanks -- PMM

6 years, 5 months

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[ACTIVITY] 2-6 Dec 2019

by Christophe Lyon

== Progress == * GCC: - -mpure-code on v6m: waiting for approval, pinged again. * BFD Linker: - GNU-629: non-contiguous memory support: received some feedback. Looking at how to handle the case where input sections change size during the linker iterations. * GCC upstream validation: - reported/checked a few issues * misc: - infra fixes / troubleshooting / reviews == Next == * GCC: pure-code/v6m, handle feedback * Binutils: GNU-629: support non-contiguous memory regions in linker

6 years, 5 months

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[ACTIVITY] 2 - 6 December 2019

by Diana Picus

== Progress == * LLVM 9.0.1 - Trying to bisect the arm failures * Triaging check-lldb failures on AArch64 [LLVM-512] - Finished with the unexpected failures - There are still some unexpected passes, but Omair has agreed to look into them * Morello - Managed to build android and lldb-server, currently trying to see if I can get them to work together

6 years, 5 months

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coresight drivers access from syscall interface

by zied guermazi

hi,I started implementing GDB process record and replay with ARM CoreSight as described in the rfc published early this year. Current implementation of coresight tracing in Perf is based on the sysfs interface, by accessing /sys/bus/event_source/devices/cs_etm ... file. GDB implementation of bts and ipt is based on the syscall "sys_perf_event_open".it would be nice to use the similar mechanism for realizing similar functionalities. therefore I would like to know if linux kernel (with coresight deivers) is exposing coresight drivers through the syscall sys_perf_event_open and if this is the case how shall I configure the perf_event_attr to use it. thanks Zied Guermazi

6 years, 5 months

2
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[ANNOUNCE] Linaro Binary Toolchain Release GCC 7.5-2019.12

by Maxim Kuvyrkov

The Linaro Binary Toolchain ============================ The Linaro GCC 7.5-2019.12 Release is now available. *Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for aarch64*-*-* targets From GCC 7.1 release notes: On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects conformance to the procedure call standard (AAPCS) has been fixed. The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. This is an ABI change. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 GCC 5 and GCC 6 releases will continue to be affected by the ABI bug, since changing ABI in these releases is not practical. A warning enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to diagnose codebases that might be affected by the ABI bug. Additionally, this same bug was present in AArch64 backend in development versions of GCC 7. There was no releases of GCC with this bug present in AArch64 backend, therefore the release notes does not mention this. However, be advised that any code bases built with development versions of GCC 7 need to be recompiled with released version of GCC 7 to conform to ABI. For an explanation of GCC 7 series changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html For help in porting to GCC 7 please see the following explanation: https://gcc.gnu.org/gcc-7/porting_to.html Download release packages from: (sources) http://releases.linaro.org/components/toolchain/gcc-linaro/7.5-2019.12/ (binaries) http://releases.linaro.org/components/toolchain/binaries/7.5-2019.12/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 7.5-2019.12 http://releases.linaro.org/components/toolchain/gcc-linaro/7.5-2019.12/ FSF glibc 2.25 (release/2.25) https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html Newlib 2.5 (newlib-2_5_0 tag) https://sourceware.org/ml/newlib/2016/msg01191.html GNU Binutils 2.28 (users/linaro/binutils-2_28-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 8.3 (gdb-8.3-branch) https://lists.gnu.org/archive/html/info-gnu/2019-05/msg00007.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 7 (as of Linaro GCC 7.5-2019.12) ============================================== * Runtest and gdbserver are no longer installed in the toolchain bin/ directory. Binary releases no longer include runtest at all, and gdbserver is a target tool; it is now shipped in the sysroot under usr/bin/. LDTS case #2211: gdbserver and runtest in GCC binary release are in the wrong place or have the wrong name * Gdbserver is no longer linked statically, because this is currently unsupported. Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02 https://bugs.linaro.org/show_bug.cgi?id=3344 * The Linaro GCC 7.4-2019.01 snapshot added a fix for Linaro bug 4007: "Internal compiler error with -mcpu=thunderx2t99". * The Linaro GCC 7.2-2017.09 snapshot added float and integer moves improvement for AArch64 targets. * The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration improvement for AArch64 targets and laid groundwork to enabling prefetching in more cases. * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * Performance related backports from the following snapshots have been included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06, Linaro GCC 7.1-2017.07, Linaro GCC 7.2-2017.08, Linaro GCC 7.2-2017.09, Linaro GCC 7.2-2017.10, Linaro GCC 7.2-2018.04, Linaro GCC 7.4-2019.01 and Linaro GCC 7.5-2019.11. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2018.04/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.4-2019.01/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.5-2019.11/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org -- Maxim Kuvyrkov https://www.linaro.org

6 years, 5 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 7.5-2019.12-rc1

by Maxim Kuvyrkov

The Linaro Binary Toolchain ============================ The Linaro GCC 7.5-2019.12-rc1 Release-Candidate is now available. *Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for aarch64*-*-* targets From GCC 7.1 release notes: On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects conformance to the procedure call standard (AAPCS) has been fixed. The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. This is an ABI change. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 GCC 5 and GCC 6 releases will continue to be affected by the ABI bug, since changing ABI in these releases is not practical. A warning enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to diagnose codebases that might be affected by the ABI bug. Additionally, this same bug was present in AArch64 backend in development versions of GCC 7. There was no releases of GCC with this bug present in AArch64 backend, therefore the release notes does not mention this. However, be advised that any code bases built with development versions of GCC 7 need to be recompiled with released version of GCC 7 to conform to ABI. For an explanation of GCC 7 series changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html For help in porting to GCC 7 please see the following explanation: https://gcc.gnu.org/gcc-7/porting_to.html Download release-candidate packages from: (sources) http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.5-2019.12-rc1/ (binaries) http://snapshots.linaro.org/components/toolchain/binaries/7.5-2019.12-rc1/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 7.5-2019.12-rc1 http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.5-2019.12-rc1/ FSF glibc 2.25 (release/2.25) https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html Newlib 2.5 (newlib-2_5_0 tag) https://sourceware.org/ml/newlib/2016/msg01191.html GNU Binutils 2.28 (users/linaro/binutils-2_28-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 8.3 (gdb-8.3-branch) https://lists.gnu.org/archive/html/info-gnu/2019-05/msg00007.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 7 (as of Linaro GCC 7.5-2019.12-rc1) ================================================== * Runtest and gdbserver are no longer installed in the toolchain bin/ directory. Binary releases no longer include runtest at all, and gdbserver is a target tool; it is now shipped in the sysroot under usr/bin/. LDTS case #2211: gdbserver and runtest in GCC binary release are in the wrong place or have the wrong name * Gdbserver is no longer linked statically, because this is currently unsupported. Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02 https://bugs.linaro.org/show_bug.cgi?id=3344 * The Linaro GCC 7.4-2019.01 snapshot added a fix for Linaro bug 4007: "Internal compiler error with -mcpu=thunderx2t99". * The Linaro GCC 7.2-2017.09 snapshot added float and integer moves improvement for AArch64 targets. * The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration improvement for AArch64 targets and laid groundwork to enabling prefetching in more cases. * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * Performance related backports from the following snapshots have been included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06, Linaro GCC 7.1-2017.07, Linaro GCC 7.2-2017.08, Linaro GCC 7.2-2017.09, Linaro GCC 7.2-2017.10, Linaro GCC 7.2-2018.04, Linaro GCC 7.4-2019.01 and Linaro GCC 7.5-2019.11. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2018.04/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.4-2019.01/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.5-2019.11/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org -- Maxim Kuvyrkov https://www.linaro.org

6 years, 5 months

1
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[Activity] Nov 25th ~ Nov 29nd 2019

by Luis Machado

# Progress # o Upstream GDB * ARM sim build failure with -fno-common - Sent a patch to gdb-patches. Going through rounds of reviews. * Patch reviewing and answering community questions. o GDB * GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures - Spent some more time with this in the hopes of understanding the various failure modes. Still not clear if the kernel is doing the right thing. It may be hard to adjust things on GDB's side, but i have a couple patches solving some of the problems. o Misc * Updated personal information in the HR system. # Plan # o Upstream GDB * Get approval for the fix to -fno-common build issues with ARM sim. o GDB * GNU-644 - [GDB, AArch64] gdb.base/step-over-syscalls.exp failures - Engage with kernel folks for better understanding of signal delivery scheme. Polish current fixes and submit for review.

6 years, 5 months

1
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[ACTIVITY] Week 48

by Yvan Roux

o LLVM: * Machine Outliner: - Disabled asm statements. - Added Helium LD/ST instructions support - Adding testcases o Misc * Various meetings and discussions.

6 years, 5 months

1
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[ACTIVITY] 2 weeks ending 1 Dec 2019

by Richard Henderson

7 working days, then Thanksgiving. [VIRT-262 # ARMv8.1-PAN Privileged Access Never] Finished, still need to post. [VIRT-273 # ARMv8.2-ATS1E1, AT S1E1R and AT S1E1W instruction variants ] Finished, still need to post. [VIRT-276 # ARMv8.2-UAO, PSTATE override of Unprivileged Load/Store ] Finished, still need to post. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] FIXED! Welsh sprint with AJB; found and fixed two bugs. Final bug causing guest kernel crash while booting fixed upstream by Marc Zyngier vs ptrauth. Will do some more thorough testing during rc4 and post once the development phase opens up again. [VIRT-327 # Richard's upstream QEMU work ] Review of target/hexagon skeleton. Review of arm dcpop patch set for beata. Fixed a couple of arm translator bug for clyon. Some investigation into a reported hppa-linux-user bug. While I can reproduce locally, so far I have not tracked down anything that I can prove is a translation bug. r~

6 years, 5 months

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[ACTIVITY] week ending Dec. 1 2019

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= Extend gdbstub for SVE ([VIRT-281]) - worked on [v2 rebase addressing comments] - posted {PATCH v2 00/14} gdbstub refactor and SVE support Message-Id: <20191130084602.10818-1-alex.bennee(a)linaro.org> [VIRT-281] https://projects.linaro.org/browse/VIRT-281 [working prototype] https://github.com/stsquad/qemu/tree/gdbstub/sve-registers [v2 rebase addressing comments] https://github.com/stsquad/qemu/tree/gdbstub/sve-registers-v2 QEMU ARMv8.1 VHE ([VIRT_263]) ============================= - inaugural Welsh code sprint with rth - found some new bugs, squashed some old bugs - together with recent upstream fixes SUCCESS! - can now boot a guest from a VHE enabled kernel :-) [VIRT_263] https://projects.linaro.org/browse/VIRT-263 Upstream Work ([VIRT-109]) ========================== - posted {PULL for 4.2 0/3} a few vm-test fixes Message-Id: <20191126120339.18059-1-alex.bennee(a)linaro.org> - there are still niggling netbsd failures - posted {PATCH for 4.2?} .travis.yml: drop xcode9.4 from build matrix Message-Id: <20191127132430.3681-1-alex.bennee(a)linaro.org> - investigation into [ARM HPC compiler triggered linux-user bug] - may be 64k page related as couldn't reproduce on Ubuntu - posted {PATCH v1 0/5} linux-user mmap debug cleanup Message-Id: <20191128194603.24818-1-alex.bennee(a)linaro.org> [ARM HPC compiler triggered linux-user bug] https://bugs.launchpad.net/qemu/+bug/1853826 Other Activities ================ - published [QEMU Summit and KVM Forum trip report] [QEMU Summit and KVM Forum trip report] https://collaborate.linaro.org/display/CR/20191030+QEMU+Summit+and+KVM+Foru… Absences ======== - 2nd Dec Holiday Current Review Queue ==================== * {PATCH 0/4} python/qemu: New accel module and improvements Message-Id: <20191115180829.10275-1-wainersm(a)redhat.com> Added: <2019-11-28 Thu> * {PATCH v2 0/2} Run tcg tests with tci on Travis Message-Id: <20191128153525.2646-1-thuth(a)redhat.com> Added: <2019-11-28 Thu> * {PATCH 0/2} flush CPU TB cache in breakpoint_invalidate Message-Id: <20191127220602.10827-1-jcmvbkbc(a)gmail.com> Added: <2019-11-28 Thu> * {RFC PATCH 00/10} hw/avr: Introduce the Arduino board Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org> Added: <2019-11-28 Thu> -- Alex Bennée

6 years, 5 months

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[weekly][dsg-models][linaro] report week ending 29 Nov

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] - code review: + finally got back to the reset-refactoring patchset and gave review on v5 of that. This is very nearly ready. + reviewed and got into 4.2 rc3 some patches from Marc Z fixing some missing emulation/bugs that newer Linux guest kernels trip over + rc3 out of the door; we will need an rc4, though - more time consumed by office-move thanks -- PMM

6 years, 5 months

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[ACTIVITY] Week ending 29th November 2019

by Peter Smith

[Morello] Rebase of LLD against September CUCL update complete - Painful due to LLD changing address layout (every test expected value shifted), and a naming convention change. - No functional changes needed to patch. - Submitted static linking patches for review. Will send the dynamic ones after all static linking has been merged. Wrote up notes of Linaro Tech-leads Morello Q&A. Misc: Upstream LLD reviews

6 years, 5 months

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