Note: working for Linaro every other week
== Progress ==
* PR35157 / TCWG-1308 (crash in ARM backend for VST1d64TPseudoWB_fixed
instruction):
+ after 2 attempts got now a clean patch with no testsuite regression
+ need to add testcase and it will be good to go upstream
* Track down why xdg-open launches libreoffice for .dot files and opened
Launchpad LP#1744953.
* Misc meetings
== Plan ==
* submit fix for PR35157 (crash in ARM backend for VST1d64TPseudoWB_fixed
instruction)
* fix for PR34170 / TCWG1137 (cannot select truncate in ARMv7 backend)
* start preparing slide for bswap/store merging passes presentation in
hacker room at Connect HK2018
# Progress #
* GDB is confused by the line table generated by GCC with -gcolumn-info
PR 22531. [2/5]
My preparatory patches are reviewed, mostly on C++, get encouraged to
use more fancy C++ features.
* gfortran 7.2 vs 8.0 debug information difference. [2/5]
Many gdb.fortran test fails with gfortran 8 but gfotran 7.2 is OK. I
'git bisect' gcc and find the commit causing the debug info change,
it is like a bug to me, but my compiler/fortran knowledge is too few
to claim it is a 7.2 -> 8.0 regression.
Posted my analysis to gcc@ and fortran@ mail list.
* TCWG-1040, SVE patches review. [1/5]
Review Alan's patches.
# Plan #
* PR 22531, upstream preparatory patches,
* Write patch series v2 for TCWG-1292.
--
Yao Qi
== Progress ==
* GCC
- FDPIC
- debugging CI loop
* GCC upstream validation:
- reported a few regressions
- contributed to jenkins jobs
* Infrastructure:
- looking at how to use lava to boot boards in gcc validation (with Remi)
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC/FDPIC
* GCC upstream validation
Hi,
given the following code:
-- isystem_test.cpp -------------
#include < isystem_test.h>
bool dummy_function( void )
{
return false;
}
-----------------------------------------
-- isystem_test.h ------------------
template <class _CS_cT>
class allocator
{
};
-----------------------------------------
and g++ version: arm-eabi-g++.exe (Linaro GCC 7.2-2017.11)
1. compiling with "arm-eabi-g++ -I . -g -c isystem_test.cpp"
--> OK
2. compiling with " arm-eabi-g++ -isystem . -g -c isystem_test.cpp "
--> output error:
In file included from isystem_test.cpp:3:0:
./isystem_test.h:3:1: error: template with C linkage
template <class _CS_cT>
^~~~~~~~
It seams that the option -isystem changes the include of isystems_test.h into a C include, i.e. the header content seems to be handled as C-Code
Same error behavior with arm-eabi Linaro GCC 6.4-2017.11, Linaro GCC 6.3-2017.05
-----------------
Testing the same with the mingw msys g++ compiler outputs no error:
g++.exe (Rev2, Built by MSYS2 project) 7.2.0
Copyright (C) 2017 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
---------------
Also no errors for:
arm-linux-gnueabihf-g++.exe (Linaro GCC 6.3-2017.05)
---------------
Is there a special behavior for arm-eabi g++ compiler?
Best regards
Martin Kaul
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2018.01
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn254792 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2018.02 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2018.01/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn256695
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn254791 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2018.01/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn256699
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
== Progress ==
o LLVM
* Bugzilla 33011 (MVN instruction "Upredictable" bit patterns incorrect):
- Working on upstream comments
* Working on more unpredictable handling in Tablegen
* Fixing an issue with registers class in peephole optimization
(exhibited by unpredictable patches).
* Buildbots babysitting: investigated OOM issue, offending patch reverted.
o Misc
* Various meetings and discussions.
# Progress #
* GDB is confused by the line table generated by GCC with -gcolumn-info
PR 22531. [2/5]
Chat with other two people who are changing the same file, and they
are OK to get my changes first. Commit one obvious patch, and testing
one patch series for refactor.
* TCWG-181, GDB compile feature. [2/5]
Many new test failures in gdb.compile, because it is not supported on
arm and aarch64, but we have no way to disable them. Commit two fixes
to get test better, but still many fails on arm-linux. I think I
still need a patch to disable the test form arm-linux.
* TCWG-1040, SVE patches review. [1/5]
Review Alan's patches.
# Plan #
* PR 22531, upstream preparatory patches,
* Answer questions to my pending patch series, TCWG-1292.
--
Yao Qi
== Progress ==
* GCC
- FDPIC
- fixed crash during program startup (self-relocation)
- CI loop now almost green
* GCC upstream validation:
- reported a few of regressions
- committed a few minor testsuite fixes
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC/FDPIC
* GCC upstream validation
Hi, all
I have updated my test case:
Compile passed but failed while linking.
wentao@ubuntu:~/test/lamda$ cat a.cc
#include <iostream>
using namespace std;
int main()
{
auto f = [=]() {
cout <<"Hello world"<<endl;
};
f();
return 0;
}
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ --std=gnu++11 a.cc -o arm32
/home/wentao/TeeOS/tools/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin/../lib/gcc/arm-eabi/6.3.1/../../../../arm-eabi/lib/libstdc++.a(locale.o): In function `get_locale_cache_mutex':
/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/snapshots/gcc.git~linaro-6.3-2017.05/libstdc++-v3/src/c++98/locale.cc:36: undefined reference to `__sync_synchronize'
/home/wentao/TeeOS/tools/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin/../lib/gcc/arm-eabi/6.3.1/../../../../arm-eabi/lib/libstdc++.a(future.o): In function `__future_category_instance':
/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/snapshots/gcc.git~linaro-6.3-2017.05/libstdc++-v3/src/c++11/future.cc:64: undefined reference to `__sync_synchronize'
/home/wentao/TeeOS/tools/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin/../lib/gcc/arm-eabi/6.3.1/../../../../arm-eabi/lib/libstdc++.a(locale_init.o): In function `(anonymous namespace)::get_locale_mutex()':
/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/snapshots/gcc.git~linaro-6.3-2017.05/libstdc++-v3/src/c++98/locale_init.cc:66: undefined reference to `__sync_synchronize'
collect2: error: ld returned 1 exit status
wentao@ubuntu:~/test/lamda$
������: zhangwentao (M)
����ʱ��: 2018��1��10�� 10:22
�ռ���: 'linaro-toolchain(a)lists.linaro.org'
����: Huangqiang (H); Lizefan; leijitang
����: Does linaro toolchain support c++11 ??
Hi all,
I wonder if my compiler supports C++11? If not, where could I found the compiler supports c++11 (both 32bit and 64bit arm).
THANKS a lot~~~
My compiler information is as below:
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ -v
Using built-in specs.
COLLECT_GCC=arm-eabi-g++
COLLECT_LTO_WRAPPER=/home/wentao/TeeOS/tools/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin/../libexec/gcc/arm-eabi/6.3.1/lto-wrapper
Target: arm-eabi
Configured with: '/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/snapshots/gcc.git~linaro-6.3-2017.05/configure' SHELL=/bin/bash --with-mpc=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-mpfr=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gmp=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gnu-as --with-gnu-ld --disable-libmudflap --enable-lto --enable-shared --without-included-gettext --enable-nls --disable-sjlj-exceptions --enable-gnu-unique-object --enable-linker-build-id --disable-libstdcxx-pch --enable-c99 --enable-clocale=gnu --enable-libstdcxx-debug --enable-long-long --with-cloog=no --with-ppl=no --with-isl=no --enable-multilib --with-multilib-list=aprofile --enable-threads=no --disable-multiarch --with-newlib --with-build-sysroot=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/sysroots/arm-eabi --with-sysroot=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu/arm-eabi/libc --enable-checking=release --disable-bootstrap --enable-languages=c,c++,lto --build=x86_64-unknown-linux-gnu --host=x86_64-unknown-linux-gnu --target=arm-eabi --prefix=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu
Thread model: single
gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05)
wentao@ubuntu:~/test/lamda$
===>
And more, I wrote a ��hello-world�� program using c++11, it could work with host g++, but when I change to ��arm-eabi-g++��, it does not work.
Information as below:
wentao@ubuntu:~/test/lamda$ cat a.cc
#include <iostream>
using namespace std;
typedef void(*Func)();
int main()
{
Func f = [=]() {
cout <<"Hello world"<<endl;
};
f();
return 0;
}
wentao@ubuntu:~/test/lamda$ g++ a.cc -o host
a.cc: In function ��int main()��:
a.cc:10:2: warning: lambda expressions only available with -std=c++11 or -std=gnu++11 [enabled by default]
};
^
wentao@ubuntu:~/test/lamda$ ./host
Hello world
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ a.cc -o arm32
a.cc: In function ��int main()��:
a.cc:10:2: error: cannot convert ��main()::<lambda()>�� to ��Func {aka void (*)()}�� in initialization
};
^
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ --std=gnu++11 a.cc -o arm32 # if gives �Cstd=c++11 , the error is the same.
a.cc: In function ��int main()��:
a.cc:10:2: error: cannot convert ��main()::<lambda()>�� to ��Func {aka void (*)()}�� in initialization
};
^
wentao@ubuntu:~/test/lamda$
Hi everyone,
Note 1: Working on Linaro 50% time.
Note 2: had afternoons off for the first 2 weeks of January
== Progress ==
* Week 1 (2/1 -> 5/1) working for Arm
* Fix poor screen resolution issue
* Onboarding process:
+ read all docs, setup accounts (gmail, octopus, ...)
* PR35157 / TCWG-1308 (Crash in ARM backend for VST1d64TPseudoWB_fixed
instruction):
+ reproduce in llc under gdb, start investigating
== Plan ==
* PR35157 / TCWG-1308 (Crash in ARM backend for VST1d64TPseudoWB_fixed
instruction)
# Progress #
* GDB 8.1 release.
8.1 RC was created. 8.1 will be released soon, I think.
* GDB is confused by the line table generated by GCC with -gcolumn-info
PR 22531. [3/5]
Get a working patch, but need to upstream my refactoring first. Other
two people from upstream are also changing the same file, need to
cooperate.
* Upstream patches review, [2/5]
** Review changes to dwarf2read.c,
** Review one ARMv8 OpenOCD patch,
# Plan #
* PR 22531,
* Resume my pending patches on removing MAX_REGISTER_SIZE.
--
Yao Qi
== Progress ==
o LLVM
* TCWG-1324 (failures of Clang::atomic_ops.c and frem.ll on armv8l host):
- Fix committed in mainline as r322098
* Bugzilla 33011 (MVN instruction "Upredictable" bit patterns incorrect):
- Fix submitted upstream
* Buildbots babysitting.
* LLVM scripts reviews
o Misc
* Various meetings and discussions.
== This Week ==
* GCC bugs (8/10)
- PR81703: Committed to trunk, restricted test-case to x86_64 for now.
- PR83514: Committed to trunk.
- PR82665: Upstream iteration and approved for next stage-1.
- PR83648: Upstream iteration and approved for next stage-1.
- TCWG-1329: Created patch.
- PR83570: Work in progress patch.
* libgo regression (1/10)
- Individual tests failing with makechan size out of range
- Sent patch to add failing tests to unstable-tests.txt
* Misc (1/10)
- libgo regressions
- Meetings
== Next Week ==
- TCWG-1234
- GCC bugs
== Progress ==
* GCC
- FDPIC
- understood crash during program startup (self-relocation):
self-relocated data is set read-only by the dynamic linker.
* GCC upstream validation:
- reported a couple of regressions
- helped validating a couple of patches before they are committed
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC/FDPIC
* GCC upstream validation
Hi all,
I wonder if my compiler supports C++11? If not, where could I found the compiler supports c++11 (both 32bit and 64bit arm).
THANKS a lot~~~
My compiler information is as below:
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ -v
Using built-in specs.
COLLECT_GCC=arm-eabi-g++
COLLECT_LTO_WRAPPER=/home/wentao/TeeOS/tools/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin/../libexec/gcc/arm-eabi/6.3.1/lto-wrapper
Target: arm-eabi
Configured with: '/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/snapshots/gcc.git~linaro-6.3-2017.05/configure' SHELL=/bin/bash --with-mpc=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-mpfr=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gmp=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gnu-as --with-gnu-ld --disable-libmudflap --enable-lto --enable-shared --without-included-gettext --enable-nls --disable-sjlj-exceptions --enable-gnu-unique-object --enable-linker-build-id --disable-libstdcxx-pch --enable-c99 --enable-clocale=gnu --enable-libstdcxx-debug --enable-long-long --with-cloog=no --with-ppl=no --with-isl=no --enable-multilib --with-multilib-list=aprofile --enable-threads=no --disable-multiarch --with-newlib --with-build-sysroot=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/sysroots/arm-eabi --with-sysroot=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu/arm-eabi/libc --enable-checking=release --disable-bootstrap --enable-languages=c,c++,lto --build=x86_64-unknown-linux-gnu --host=x86_64-unknown-linux-gnu --target=arm-eabi --prefix=/home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-eabi/_build/builds/destdir/x86_64-unknown-linux-gnu
Thread model: single
gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05)
wentao@ubuntu:~/test/lamda$
===>
And more, I wrote a "hello-world" program using c++11, it could work with host g++, but when I change to "arm-eabi-g++", it does not work.
Information as below:
wentao@ubuntu:~/test/lamda$ cat a.cc
#include <iostream>
using namespace std;
typedef void(*Func)();
int main()
{
Func f = [=]() {
cout <<"Hello world"<<endl;
};
f();
return 0;
}
wentao@ubuntu:~/test/lamda$ g++ a.cc -o host
a.cc: In function 'int main()':
a.cc:10:2: warning: lambda expressions only available with -std=c++11 or -std=gnu++11 [enabled by default]
};
^
wentao@ubuntu:~/test/lamda$ ./host
Hello world
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ a.cc -o arm32
a.cc: In function 'int main()':
a.cc:10:2: error: cannot convert 'main()::<lambda()>' to 'Func {aka void (*)()}' in initialization
};
^
wentao@ubuntu:~/test/lamda$ arm-eabi-g++ --std=gnu++11 a.cc -o arm32 # if gives -std=c++11 , the error is the same.
a.cc: In function 'int main()':
a.cc:10:2: error: cannot convert 'main()::<lambda()>' to 'Func {aka void (*)()}' in initialization
};
^
wentao@ubuntu:~/test/lamda$
o 3 days off
== Progress ==
o LLVM
* TCWG-1317 (lencod miscompilation on clang-native-arm-lnt-perf bot):
- Can't reproduce the miscompilation on the builder at
a revision where it should
- Issue fixed on the bot
* TCWG-1324 (failures of Clang::atomic_ops.c and frem.ll on armv8l host):
- Built the toolchains and start to investigate
* Buildbots babysitting:
- Investigate and reported upstream regressions
o Misc
* Catch-up after vacations
== This Week ==
* GCC bugs (8/10)
a) PR83501 - Committed to trunk.
b) PR82665 - Upstream iteration, waiting for final approval.
c) PR83648 - Upstream iteration.
d) PR81703 - Created a fix.
e) PR83661 - Work in progress patch.
* Public Holiday (2/10)
== Next Week ==
- Continue ongoing tasks
* 1 day off (Monday)
== Progress ==
* GCC
- FDPIC
- debugging crash during program startup (self-relocation)
- fixed linker assert when using -static
* GCC upstream validation:
- reported a couple of regressions
- incremental improvements for more robustness, and easier
configuration of validations
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC/FDPIC
* GCC upstream validation
* New year holiday
# Progress #
* GDB 8.1 release.
8.1 branch is created. Fix GDB and GDBserver build failure in
release mode. Patches are posted.
Looking at several test fails caused by new GCC emitting multiple
line entries for the same line but with different columns, like,
i = 1; j = 2;
GDB can't step over the whole source line, and program stops at the
middle of the source line.
# Plan #
* GDB 8.1 release.
* Resume my pending patches on removing MAX_REGISTER_SIZE.
--
Yao Qi
Hi,
I am using the following linaro toolchain and need to create a license
manifest in terms what are the packages are there, what license they use.
https://releases.linaro.org/components/toolchain/binaries/
5.2-2015.11-2/aarch64-linux-gnu/
I don't see any such manifest in the release archive nor in the toolchain
archive. If such manifest is available then would you please point me to it.
--
*Ronak A Desai*
1 day off (Friday)
== Progress ==
* GCC
- FDPIC
- debugging crash during program startup (self-relocation), and
linker assert when using -static
* GCC upstream validation:
- reported a couple of regressions, tested a couple of patches for upstream
- incremental improvements for more robustness, and easier
configuration of validations
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
Holidays until Jan 2nd, 2018
Merry Christmas and happy new year!
# Progress #
* GDB 8.1 release. [2/10]
Triage regressions on aarch64 and arm.
* PR 21698. [3/10]
During the patch review, I doubt the patch fixes an invalid
python use in gdb. The GDB doc is quite unclear on how
that python api should be used. Ask the python api owner to
clarify.
* Misc, [5/10]
Two days travel to Manchester.
# Plan #
* GDB 8.1 release. Fix regressions.
--
Yao Qi
# Progress #
* TCWG-1125, ARMv8 tagged address support in GDB.
Finish v3, and committed. Done. [5/10]
* TCWG-1040,
Update my patches to remove the last use of MAX_REGISTER_SIZE.
No response, people are busy on release.
* GDB 8.1 release. [2/10]
PR gdb/21698. It is a regression. Fixed.
* Misc, [3/10]
# Plan #
* GDB 8.1 release, testing for ARM and AArch64.
--
Yao Qi
== Progress ==
o Linaro GCC/Validation
* 6.4 an 7.2 2017.11 snapshots deployed.
o LLVM ramp-up
* Buildbots babysitting:
- Investigate and reported upstream regressions
* Patch benchmarking job (TCWG-1306):
- Start to look at it
* Upstream BZ 32999:
- Still on-going
o Misc
* Various meetings and discussions.
== Progress ==
* GCC
- FDPIC
- debugged linker assert while building gcc target libs
- now debugging crash during program startup (self-relocation)
* GCC upstream validation:
- reported a couple of regressions
- a few more improvements to handle random infrastructure problems
- experimenting with new builders
* Infrastructure:
- updated Jenkins job for GCC upstream monitoring
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC/FDPIC
* GCC upstream validation
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.11
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn254792 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2018.02 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.11/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn254792
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn254791 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn254791
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
* One day off
* One day sick and half one in the snow
== Progress ==
o Linaro GCC/Validation
* GCC 6.4 and 7.2 binary releases deployed
* 2017.11 snapshots:
- 6.4 and 7.2 ready to be deployed
o LLVM ramp-up
* Upstream BZ 32999:
- Struggled to construct the testcases which
produce the DAGs needed for a good coverage
- Re-working sub-vectors indexes logic to handle
these testcases.
o Misc
* Various meetings and discussions.
# Progress #
* TCWG-1040, [6/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Post the whole patch series as an RFC. There are 15 patches, but I
rewrote them in seven times. This version is quite satisfying.
Targeting to GDB 8.2. One patch can't be merged until 8.1 is
branched.
* TCWG-1125, ARMv8 tagged address support in GDB.
Writing v3. [2/10]
* Misc, [2/10]
# Plan #
* TCWG-1125,
* GDB 8.1 release. Testing for ARM and AArch64.
--
Yao Qi
== This Week ==
* TCWG-1234 (6/10)
- Using dfs to compute bb dist
- Reading through rest of PRE/SCCVN to better understand the infrastructure
* PR82808 (2/10)
- Trying to find an approach to pass parm_type from all callers.
- Martin posted a patch to address the parm_type issue.
* Misc (2/10)
- Meetings
- Filed PR83194, browsing through other PR's.
== Next Week ==
- Continue ongoing tasks
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.11 Release is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release packages from:
(sources) http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11/
(binaries) http://releases.linaro.org/components/toolchain/binaries/6.4-2017.11/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.11
http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (users/linaro/binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.11)
==============================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06, Linaro
GCC 6.4-2017.07, Linaro GCC 6.4-2017.08, Linaro GCC 6.4-2017.09 and
Linaro GCC 6.4-2017.10 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
* 2 days off (Internal Training)
== Progress ==
o Linaro GCC/Validation
* Final GCC 5.5 release deployed and announced
* GCC 6.4 and 7.2 deployed
* 2017.11 snapshots on-going (branch merges done)
o LLVM ramp-up
* Upstream BZ 32999:
- Addressing upstream comments.
* Upstream BZ 35272:
- Analysed and commented upstream.
o Misc
* Various meetings and discussions.
== Plan ==
o Continue on on-going LLVM Bugs.
o Wednesday off
# Progress #
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Commit my 1/6 patch series. Prepare 2/6 patch series. Need to be
sync'ed with GDB 8.1 release.
* TCWG-1159, [4/10] GDB flexible target description conversion.
Commit patch for tic6x, and ready to post patches for nios2.
* Run GDB testsuite with CLANG. [1/10]
Commit my patches, but leave some controversial patches in my tree.
Now, I get some reasonable GDB test result with clang.
* Upstream patches review. [1/10]
Approved four Alan's patches.
# Plan #
* ARMv8 tagged pointer support in GDB.
* Update my patches to remove the last use of MAX_REGISTER_SIZE.
--
Yao Qi
== Progress ==
* GCC
- FDPIC: hitting a linker assert while building gcc target libs
* GCC upstream validation:
- reported a few regressions, fixed a couple of obvious errors
- struggling with ST-internal infrastructure difficulties
* Infrastructure:
- looking at ABE & building a native toolchain from a manifest
* misc (conf-calls, meetings, emails, ....)
- became 1 year older :)
== Next ==
* GCC/FDPIC
* GCC upstream validation
== This Week ==
* PR82665 (3/10)
- Submitted patch upstream
- Blocked on POINTER_DIFF_EXPR patch by Marc Glisse.
* PR82808 (1/10)
- Submitted another fix but was rejected by Richard.
* TCWG-1234 (4/10)
- Tried tweaking with register allocator, but to no effect
- Trying to think about possible approaches for stage-3 fixes.
* Misc (2/10)
- Meetings
- Managed to get autofdo working
== Next Week ==
- Continue ongoing tasks
== Progress ==
* GCC
- FDPIC: rebased binutils patches, debugging CI loop.
* GCC upstream validation:
- iterating on qemu/sanitizers problems.
Found a bug in arm sanitizer libs, already fixed upstream.
Requested a new merge in GCC.
- reported a few regressions
* Infrastructure:
- looking at ABE & building a native toolchain from a manifest
* misc (conf-calls, meetings, emails, ....)
- started looking at hcqc
== Next ==
* GCC/FDPIC
* GCC upstream validation
# Progress #
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Get everything in shape. Post my 1/6 patch series.
* TCWG-1159, [4/10] GDB flexible target description conversion.
Post patch for tic6x, and write the patch for nios2.
* ILP32 GDB. [1/10]
Chat with Maxim, triage some test failures.
* Open GCC PR 83010.
AArch64 GCC doesn't generate DW_AT_location for TLS variable. It
causes some GDB test failures. CLANG+GOLD can correctly generate
DW_AT_location.
* Run GDB testsuite with CLANG. [1/10]
Post three patches to GDB testsuite to compile test cases with CLANG.
# Plan #
* TCWG-1125, ARMv8 tagged address support in GDB.
--
Yao Qi
Hi Linaro Team,
I'm currently using toolchain
gcc-linaro-7.1.1-2017.08-x86_64_arm-eabi.tar.xz
<https://releases.linaro.org/components/toolchain/binaries/latest/arm-eabi/g…>
to
develop my bera-metal programs.
My compile option is "-marm -march=armv7-a -mtune=cortex-a9 -mlittle-endian
-mfloat-abi=hard -mfpu=neon"
I found an issue, when I use memcpy, and if the DEST or SOURCE address is
not 4 bytes aligned, the system hangs.
It seems that this toolchain doesn't support using hard float and NEON ?
My question is does this toolchain support hard float and NEON in the
newlib C library?
If I want to use hard float and NEON, how can I do that?
Your reply is more appreciated!!
Over the last couple of months arm64 community and us have tested various aspects of ILP32 toolchain and, while most of toolchain works as expected, several features are still missing. Most of the work left is on GDB side, especially using LP64 GDB to debug ILP32 applications.
1. [GCC] GCC sanitizers (ASAN, UBSAN) are not supported for ILP32.
-- TCWG is working on implementing sanitizer support for ILP32.
2. [GLIBC] LP64 glibc libthread_db does not support ILP32. This causes failures when LP64 GDB is trying to debug ILP32 threaded application. It is expected by users to be able to use LP64 GDB to debug ILP32 applications (LP64 AArch64 GDB can successfully debug AArch32 applications already!).
-- Steve, do you plan to work on adding libthread_db support for ILP32?
3. [GDB] Handle ILP32 siginfo layout. Kernel siginfo layout is different between LP64 and ILP32.
4. [GDB] Inferior call passing pointer argument. GDB may need update to handle 32-bit pointer vs 64-bit pointer.
5. Handle shared libraries. GDB needs to read a linked list out of the inferior, and that list is about the libraries loaded already. LP64 and ILP32 may have different layouts.
6. [GDB] GDB resolves ifunc functions, needs to read auxv (HWCAP) from the inferior. auxv is different on LP64 and ILP32.
7. [GDB] Gdbserver support for ILP32.
--
Maxim Kuvyrkov
www.linaro.org
== This Week ==
* TCWG-1234 (2/10)
- Came up with another fix which works on my test-case but not on
actual regression
* PR82808 (2/10)
- Modified patch based on upstream suggestions.
* PR82665 (4/10)
- Untested fix
* Misc (2/10)
- Meetings
- Reading ipa mod/ref paper
- Looked at autofdo
== Next Week ==
- Continue ongoing tasks
== Progress ==
o Linaro GCC/Validation
* GCC 6 and 7 2017.11 RC1 deployed
* Fixed Binutils branch used for 5.5 release
* Investigate and fixed Python3 issues in release notes script
(patch under review)
o LLVM ramp-up
* Upstream bug 32999:
- Still tracking corner cases
* Looking at zero/sign-extension elimination status
o Misc
== Plan ==
o Release handover
o LLVM tasks (Bug 32999, sign-extension)
Hi all,
I just upload an sysroot image for ILP32 meant to be used on both testing
and development on dev-01.tcwglab [1]. It is based on out current ILP32
GCC 7 sysroot plus some tools and it is meant to easier development and
testing. It should have all native required tools for GNU development:
glibc 2.27 (arm/ilp32 branch)
gcc 7.2.1 (linaro/gcc-7-branch)
binutils 2.28.2 (linaro_binutils-2_28-branch)
gmp 6.1.2
mpfr 3.1.6
mpc 1.0.3
coreutils 8.28
bash 4.4.12
gnumake 4.2 (plus a patch to fix glob usage on glibc 2.27)
gawk 4.2
perl 5.26.1
textinfo 6.5
bison 3.0.3
m4 1.4.18
libtool 2.4.5
flex 2.6.4
tcl 8.6.7
expect 5.45.3
dejagnu 1.6
sed 4.4
diffutils 3.6
tar 1.29
gzip 1.8
finutils 4.6.0
I could build and check glibc and binutils and bootstrap gcc. The binutils
and gcc tests are working (dejagnu/expect/tcl is installed).
To actually get a working VMs to run ILP32 you need a kernel built with different
branch than either canonical Linus tree or linux stable. Easier way is to use
Maxim's automated script to start a qemu aarch64 instance on r1-a7:
$ WORKSPACE=`pwd` bash -x ~maxim.kuvyrkov/src/jenkins-scripts/start-container-qemu.sh \
--weight 2 --node r1-a7 --arch arm64 --distro xenial --task test --prefix ilp32_ \
--kernel_url https://people.linaro.org/~maxim.kuvyrkov/norov-Image --initrd_url \
https://cloud-images.ubuntu.com/releases/16.04/release/unpacked/ubuntu-16.0… \
--session-name ilp32-$USER --newuser $USER --cp_file ~/.ssh/authorized_keys
You can then log in the machine as usual ('ssh -P r1-a7.aus-colo') and download
the sysroot from dev-01.tcwglab. Just uncompress it and issue the usual
chroot command:
$ mkdir aarch64-linux-gnu_ilp32/proc; sudo mount -t proc proc aarch64-linux-gnu_ilp32/proc
$ mkdir aarch64-linux-gnu_ilp32/sys; sudo mount -t sysfs sys aarch64-linux-gnu_ilp32/sys
$ mkdir aarch64-linux-gnu_ilp32/dev; sudo mount -o bind /dev aarch64-linux-gnu_ilp32/dev
$ sudo chroot aarch64-linux-gnu_ilp32
A useful package missing is GDB and python, I plan to get them built and I will
update the image on dev-01.tcwglab during this week.
[1] /home/tcwg-buildslave/public_html/images/ilp32/aarch64-linux-gnu_ilp32.tar.bz2
Hi,
I put HCQC(HPC compiler quality checker) on GitHub.
URL: https://github.com/Linaro/hcqc
Any comments or suggestions are very welcome.
I am going to improve README.md overall and to add more test programs.
I will also report the analysis results using HCQC on hpc-sig-devel.
The attached PDF file was used to explain HCQC at HPC-SIG SC meeting(11/7).
I think you can reproduce the results on this slide if you modify the
following part of the configuration file:
hcqc/config/clang-config.json
"COMMAND" : "/usr/bin/clang",
"VERSION" : "4.0.1",
hcqc/config/gcc-config.json
"COMMAND" : "/usr/bin/gcc-7",
"VERSION" : "7.1.1",
which you need to fix to suit your environment.
[image: https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif]
Best regards,
--
--------------------------------------
Masaki Arai
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.11-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11-rc1/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/6.4-2017.11-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.11-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11-rc1/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.11-rc1)
==================================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06, Linaro
GCC 6.4-2017.07, Linaro GCC 6.4-2017.08, Linaro GCC 6.4-2017.09 and
Linaro GCC 6.4-2017.10 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
Hi Maxim, all,
Alex Matveev and I try to enable LTO optimization for Linux kernel
on ARM64. The work is based on patches from Andi Kleen, and is not
complete yet. Maxim recommended to work tightly with toolchain group
to understand how to fix problems better - on kernel or compiler side.
Links:
My unfinished branch:
https://github.com/norov/linux/tree/lto
Andi Kleen tree:
https://github.com/andikleen/linux-misc/tree/lto-411-1
Sami Tolvanen's recent work for clang:
https://lkml.org/lkml/2017/11/3/606
Question we have for now:
There's mrs_s/msr_s macro that doesn't work with LTO - linker
complains very loudly that macro is either not declared, or declared
multiple times. (To reproduce - try to build my kernel branch w/o last
patch).
The same (?) problem is observed with clang, and people there
considered it as feature, not a bug.
https://bugs.llvm.org/show_bug.cgi?id=19749
We have the fix for both clang and gcc, but it looks hacky. Maybe it
worth to fix mrs/msr issue on toolchain side?
Thanks,
Yury
Short week (off Wed/Thu/Fri)
== Progress ==
* GCC
- FDPIC: looking at patch stacks
* GCC upstream validation:
- got feedback from upstream about qemu and asan interaction since
recent merge: need to disable LSAN on arm.
- using qemu-2.7 again enables to workaround the timeout issues
observed last week
- worked on improving timeout handling
- restarted validations, but....
- validations on-hold since Nov 1st because of an ST-internal
infrastructure problem
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
* 3 days off
== Progress ==
o Linaro GCC/Validation
o LLVM
* Continue ramp-up
* Upstream bug 32999:
- Reworked the fix and validate it
- Ready to be submitted upstream
* Start to look at sign-extension elimination status
o Misc
== Plan ==
o Release handover (5 release, 6 and 7 RCs)
o LLVM tasks (Bug 32999, sign-extension)
# Progress #
* TCWG-1040, [6/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Commit clean up and refactor patches. Find more clean up patches
in my tree. Keep upstreaming them. The design and implementation
of removing MAX_REGISTER_SIZE becomes more and more clear.
* TCWG-1125, [2/10] ARMv8 tagged address support in GDB.
v2 patches were posted. No comments yet.
* aarch64: PR 19806: watchpoints: false negatives + PR 20207 contiguous
ones. Patch review. [1/10]
* Think about the TODOs for GDB ILP32 support, write them down, and send
it to Maxim. [1/10]
# Plan #
* TCWG-1040, TCWG-1125.
--
Yao Qi
Hi ,
I am a SW engineer that use Linaro-toolchain to build images,
Recently, I encounter some issue about enable NEON features on ARMv8 processor platform.
I cat cpuinfo, can not find neon and vfp feature enable in list, the image was build with aarch-64 toolchian;
While, the image built by armv7l toolchain can list "neon and vfp" in cpuinfo.
I want to verify from your side,
1. if the toolchain of aarch64 version already enable" neon and vfp " in default, Because I do not find some build items that related with "neon",
2. If not supported defaultly, can you give some suggestion to enable it.
Thanks & B.R.
Joy Deng
== This Week ==
* TCWG-1005 (4/10)
- Iteration on upstream feedback and validated patch
- Committed to trunk in r254140.
* Reverse of TCWG-1253 transform (3/10)
- Adding reverse transform for div pattern in expand
* TCWG-1234 (2/10)
- Experimenting with "unhoisting" approach
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing and backlog tasks from JIRA
- Go through IPA mod/ref paper
* One day off
== Progress ==
o Linaro GCC/Validation
* Releases handover
- GCC 5.5 source snapshot and RC1 deployed
- GCC 6 and 7 RCs under construction
o LLVM
* Continue ramp-up
* Upstream bug 32999:
- Validating a fix
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== Progress ==
* GCC
- FDPIC: started reading docs and looking at patches
- Neon intrinsics PR71233: duplicates will be removed from the next doc update
* GCC upstream validation:
- since ubsan merge with upstream, validation of arm targets is now
broken. Switching back to qemu-2.7 seems to avoid qemu deadlocks, but
there are still new asan test failures after the merge.
- reduced the dejagnu timeout to avoid global 'make check' timeouts,
but this caused some testcases to become zombies, in turn causing
problems in the ST compute farm.
- validation on-hold until next so that I can experiment a bit more
with workarounds
- reported another qemu bug
- reported a couple of regressions/breakages in binutils
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
* Short week (off Wed/Thu/Fri)
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Post the clean up and refactor patches.
* TCWG-1125, [4/10]
ARMv8 tagged address support in GDB.
v2 patches are posted. Take care of breakpoint and watchpoint on
tagged address carefully.
* ILP32 GDB branch. [1/10]
Branch is created! Done.
* Misc, meeting, [1/10]
# Plan #
* Update my patches to remove the last use of MAX_REGISTER_SIZE.
* GDB flexible target description conversion. Upstream patches.
--
Yao Qi
Hi,
We are evaluating LInaro GCC5.4 readiness for ARMv8.2-A extension support but can't find direct answer if all the features has been supported/backported.
Can you point me to the answer?
Thanks,
Vincent
-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
== Progress ==
o Linaro GCC/Validation
* Releases handover
- Monthly snapshots for GCC 6 and 7 deployed
- GCC 5 final release handled by Mark
* Branch merge done
* Tarball and release ready to be deployed
* RC1 planned for w43
o LLVM
* Continue ramp-up
* Working on upstream bug 32999:
[ARM] Missed vpadd combine opportunity
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== This Week ==
* TCWG-1234 (4/10)
- Patch inhibits if-conversion for couple of tests.
* TCWG-1253 (3/10)
- Fixed regressions with the patch
* Took Monday off for recovering from travel (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1253, TCWG-319
# Progress #
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Before I send them upstream, I find some bits that I can improve,
but finally, many things are changed. Need to get them in shape,
and think about the design again.
* TCWG-1125, [4/10]
ARMv8 tagged address support in GDB.
GDB/GDBserver needs to remove the top one byte of virtual address
before pass it to kernel. Patch v1 was reviewed, and GDB internal
caching needs updated for tagged address, because tagged address and
non-tagged address should be mapped to the same cache entry in GDB.
* GDB flexible target description conversion [1/10]
Finished the conversion for tic6x and nios2. To be posted.
* ILP32 GDB branch. [1/10]
Got Steve Ellcey's patches, one bfd patch and one gdb patch.
No GDBserver patches. Will create branch with them.
# Plan #
* ILP32 GDB branch.
* ARMv8 tagged address support in GDB.
* Update my patches to remove the last use of MAX_REGISTER_SIZE.
--
Yao Qi
== Progress ==
* GCC
- FDPIC: started reading docs
- testsuite cleanup
* GCC upstream validation:
- reported 2 bugs in qemu-armeb
- noise reduction: polishing dejagnu local patches
- since ubsan merge with upstream, validation of arm targets is now
much longer (typically 1h30 to 6h), leading to timeouts most of the
time
* Infrastructure:
- improved GCC bisect job/scripts
- updated ABE to allow overriding cpu/fpu/tune/arch etc...
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.10
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the
procedure
call standard (AAPCS). The bug affects some C++ code where class objects
are
passed by value to functions and could result in incorrect or inconsistent
code
being generated. If the option -Wpsabi is enabled (on by default) the
compiler
will emit a diagnostic note for code that might be affected by this ABI
change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn253626 and
includes performance improvements and bug fixes backported from mainline
GCC.
The contents of this snapshot will be part of the 2017.11 stable[2]
quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn253626
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn253668 and
includes performance improvements and bug fixes backported from mainline
GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn253668
o Subscribe to the important Linaro mailing lists and join our IRC channels
to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
o Linaro GCC/Validation
* Continue releases handover
- Branch merges done
- Monthly snapshots about to be deployed
o LLVM
* Jira cards review
* Checked/updated cards related to upstream BZ
* Continue ramp-up
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== This Week ==
* TCWG-1234 (5/10)
- Posted analysis upstream with a test-case.
- Have a workaround that disables hoisting when only single stmt is to
be hoisted.
- Investigating solution to limit distance between hoisted def. and it's uses.
* TCWG-1005 (2/10)
- Did changes based on upstream feedback from Honza, validated patch.
- Waiting for final approval from Honza before committing.
* Sick leave (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1005
* One day off after Connect
== Progress ==
o Linaro GCC/Validation
* Handover releases to ARM on-going.
o LLVM
* Continue ramp-up
o Misc
* Various meetings and discussions.
* Debrief Connect inside ST
== Plan ==
o Continue release handover
o LLVM Jira card: cleanup and find first tasks to do
== This Week ==
* TCWG-1234: code-hoisting regression (3/10)
- Have a workaround that fixes the particular regression (but may
introduce another)
- Trying to cross build benchmarks
- Investigating PRE and code-hoisting optimizations
* TCWG-1005: malloc attr propagation (3/10)
- Iteration based on upstream feedback.
* TCWG-1253 (1/10)
- Committed patch last week to add patterns for div and cmp against 0.
- Patch to transform rshift and cmp against 0 to cmp between operands
in upstream review.
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1005
== Connect ==
* Various discussions on GNU toolchain roadmap
== Progress ==
* GCC
- committed fix for PR71727 (strict-align bug on aarch64), backported
to gcc-7-branch
- small fixes in the testsuite
* GCC upstream validation:
- problems with internal infrastructure, but validation results OK
- reported a couple of regressions/new failures
- ran validations for a couple of tentative patches
- noise reduction: looking at how to report randomly killed processes
* misc (conf-calls, meetings, emails, ....)
- Connect feedback (internal)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/deprecated-IT blocks
# Progress #
* GDB SVE patches review. [4/10]
Finished my patches to remove the last use of MAX_REGISTER_SIZE. Send
them to Alan to review.
* GDB flexible target description follow-up. [4/10]
Committed some patches to improve GDB build, so that we can easily
share code of target description between GDB and GDBserver. Done.
* File Linaro Connect expense, and misc. [2/10]
# Plan #
* On holiday, Mon - Thu.
* Either GDB target description work,or ILP32 GDB branch.
--
Yao Qi
On 24 July 2017 at 18:38, Christophe Lyon <christophe.lyon(a)linaro.org> wrote:
>
>
> Le 24 juil. 2017 18:30, "Ard Biesheuvel" <ard.biesheuvel(a)linaro.org> a écrit
> :
>
> On 18 July 2017 at 13:54, Christophe Lyon <christophe.lyon(a)linaro.org>
> wrote:
>> On 13 July 2017 at 13:50, Christophe Lyon <christophe.lyon(a)linaro.org>
>> wrote:
>>> On 12 July 2017 at 19:33, Ard Biesheuvel <ard.biesheuvel(a)linaro.org>
>>> wrote:
>>>> On 12 July 2017 at 18:27, Alexei Fedorov <Alexei.Fedorov(a)arm.com> wrote:
>>>>>
>>>>> Christophe, Leif, Ard, Ryan at al.
>>>>>
>>>>>
>>>>> We are observing unaligned memory access fault with UEFI code compiled
>>>>> by
>>>>> Linaro GCC 6.3.1 & 7.1.1 using -O3 optimisation option.
>>>>>
>>>>> The fault occures at the very early stage of UEFI boot with MMU not
>>>>> being
>>>>> enabled yet.
>>>>>
>>>>> The failing function is CalculateSum8() from
>>>>> edk2\MdePkg\Library\BaseLib\CheckSum.c:
>>>>>
>>>>>
>>>>> UINT8
>>>>> EFIAPI
>>>>> CalculateSum8 (
>>>>> IN CONST UINT8 *Buffer,
>>>>> IN UINTN Length
>>>>> )
>>>>> {
>>>>> UINT8 Sum;
>>>>> UINTN Count;
>>>>>
>>>>> ASSERT (Buffer != NULL);
>>>>> ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
>>>>>
>>>>> for (Sum = 0, Count = 0; Count < Length; Count++) {
>>>>> Sum = (UINT8) (Sum + *(Buffer + Count));
>>>>> }
>>>>>
>>>>> return Sum;
>>>>> }
>>>>>
>>>>> & the instruction which causes the exception is "ldr q1, [x1], 16"
>>>>> which
>>>>> accesses Buffer = 0xE0000048 pointed by X1 register, see the part of
>>>>> generated assembly code:
>>>>>
>>>>>
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:49: for (Sum = 0, Count
>>>>> = 0;
>>>>> Count < Length; Count++) {
>>>>> .loc 1 49 0 is_stmt 1
>>>>> cbz x19, .L10 // Length,
>>>>> .L4:
>>>>> sub x0, x19, #1 // tmp150, Length,
>>>>> cmp x0, 14 // tmp150,
>>>>> bls .L11 //,
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:42: {
>>>>> .loc 1 42 0
>>>>> movi v0.4s, 0 // vect_Sum_19.24
>>>>> lsr x2, x19, 4 // bnd.18, Length,
>>>>> mov x1, x20 // ivtmp.29, Buffer
>>>>> mov x0, 0 // ivtmp.28,
>>>>> .LVL4:
>>>>> .p2align 3
>>>>> .L7:
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:50: Sum = (UINT8) (Sum
>>>>> +
>>>>> *(Buffer + Count));
>>>>> .loc 1 50 0 discriminator 3
>>>>> ldr q1, [x1], 16 // vect__6.23, MEM[(const UINT8
>>>>> *)vectp_Buffer.21_38]
>>>>> add x0, x0, 1 // ivtmp.28, ivtmp.28,
>>>>> cmp x0, x2 // ivtmp.28, bnd.18
>>>>> add v0.16b, v0.16b, v1.16b // vect_Sum_19.24, vect_Sum_19.24,
>>>>> vect__6.23
>>>>> bcc .L7 //,
>>>>>
>>>>> ...
>>>>>
>>>>> Although all AARCH64 code is compiled with "-mstrict-align" option
>>>>> which
>>>>> according to GCC 3.18.1 AArch64 Options:
>>>>>
>>>>> "-mstrict-align
>>>>>
>>>>> Avoid generating memory accesses that may not be aligned on a natural
>>>>> object
>>>>> boundary as described in the architecture specification."
>>>>>
>>>>>
>>>>> the generated code doesn't comply with this description. In this case
>>>>> X1 =
>>>>> Buffer @0xE0000048 and is not aligned to 16 bytes boundary.
>>>>>
>>>>> The similiar code is generated by GCC 6.3.1-2017.05 but 5.3.1-2016.05
>>>>> compiler produces only 16 bytes aligned memory accesses when loading Q1
>>>>> register.
>>>>>
>>>>>
>>>>> I attached the simple test file which can be compiled by running GCC
>>>>> compilation with
>>>>>
>>>>> -c test.c -O3 -mstrict-align -save-temps
>>>>>
>>>>> to see the difference between code generated by 7.1.1 & 5.3.1 GCC
>>>>> versions.
>>>>>
>>>>> It seems that 5.3.1 ignores "-mstrict-align" option at all and always
>>>>> generates aligned pointers for loading Q1 register, 7.1.1 & 6.3.1 also
>>>>> ignore the option but generate slighly different code with unaligned
>>>>> access
>>>>> enabled.
>>>>>
>>>>>
>>>>> Please share your thoughts regading this issue.
>>>>>
>>>>
>>>> Hello Alexei,
>>>>
>>>> This does look like a compiler bug to me. 'Buffer' is a pointer to
>>>> unsigned char, and so the compiler should never emit the ldr
>>>> instruction under -mstrict-align.
>>>>
>>>> In the mean time, we could work around this with adding
>>>> -mgeneral-regs-only in all places where -mstrict-align is being
>>>> passed. In general, I don't really see the point of supporting the use
>>>> of FP/ASIMD registers in UEFI beyond ensuring that our builds are
>>>> compatible with 3rd party binaries that do use them.
>>>>
>>>
>>> Hello Alexei,
>>>
>>> I agree with Ard: it looks like a compiler bug, I'm looking at it.
>>>
>>> And indeed in the mean time, using -mgeneral-regs-only should
>>> workaround your problem.
>>>
>>
>> Hello,
>>
>> As a follow-up, I've posted a patch:
>> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01063.html
>>
>> We'll see if maintainers agree.
>>
>
> Thanks. By the looks of it, nobody cared to respond, right?
>
>
> Not yet and we are used to slow response.
>
> In addition I'm on holidays until Aug 21st so I won't ping until then.
>
>
Hi all,
My patch was finally accepted last week and committed.
I also backported it to the gcc-7-branch, so that the problem will
be fixed in the next gcc-7 release (either FSF or Linaro).
Thanks,
Christophe
# Progress #
* Flexible GDB target description work. [5/10]
As we'll add more and more files, need to clean up GDB build first.
Patch is OK, but need to reduce the duplication first. Yet another
clean up.
Start to think about the design of removing last usage of
MAX_REGISTER_SIZE. Still ongoing.
* Misc, [5/10]
** File cauldron expense.
** Improve gdb_mbuild.sh to build GDB for different supported targets.
# Plan #
* Connect.
--
Yao Qi
== Progress ==
o Linaro GCC/Validation
* Completed backports and branch merges
* Delivered 7.2 and 6.4 monthly source snapshots
* Reviewed infra patches
* Still some patches pending on upstream reviews
o LLVM
* Still learning
o Misc
* Various meetings and discussions.
== Plan ==
o Close remaining GCC tasks
Two weeks
* GNU Cauldron and vacation, [12/20]
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/20]
Commit my patches, and fix some build failures. Done.
* Cauldron presentation and Linaro Connect SFO17 presentation. [3/20]
Done.
* Misc, catch up email, [1/20]
# Plan #
* Prepare a prototype about regcache, and compare with Alan's
implementation.
* Continue my target description work, for other non-actively-maintained
target descriptions.
--
Yao Qi
== Progress ==
* Infrastructure:
- patch reviews
* Benchmarking:
- minor bug fixes
* Snapshots/releases
- branch merge reviews
* GCC upstream validation:
- PR82120: adding a -mbranch-cost option to the arm backend does not
help with pr81588.c test failing on cortex-a5
- incorrectly reported a regression due to bisect problems (worth
100% chocolate ;-)
- still working on further reducing false alams
- problems with internal infrastructure
* binutils/gdb upstream validation:
- gdbserver build fixed by Yao
* GCC
- investigating portability of ubsan to bare-metal targets
- 'ARMv8 deprecated IT blocks' patch finally committed. Will look at
the remaining warnings.
* misc (conf-calls, meetings, emails, ....)
- Connect preparation (slides, ...)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/deprecated-IT blocks
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.09
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn252337 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.11 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn252337
* Backports from mainline:
- Backport of [Bugfix] [AArch32] PR target/77308 surprisingly large
stack usage for sha512 on arm
- Backport of [AArch32] Fix ldrd offsets
- Backport of [AArch32] Remove %? string from some Advanced SIMD patterns
- Backport of [AArch64] Add optimized implementation of mersenne twister
- Backport of [AArch64] Add RDMA support to falkor port
- Backport of [AArch64] Fix big endian float immediate moves
- Backport of [AArch64] Fix missing optimization for CMP+AND
- Backport of [AArch64] Fix pattern guard relaxations that are
allowing more constants than they should
- Backport of [AArch64] Fix ThunderX fp vectorizer cost model
- Backport of [AArch64] Generate MLA when multiply + add vector by scalar
- Backport of [AArch64] Implement ALU_BRANCH fusion
- Backport of [AArch64] Improve aarch64 conditional compare usage
- Backport of [AArch64] Improve thunderx_vect_cost some more
- Backport of [AArch64] Move the check for any_condjump_p from
sched-deps to target macros
- Backport of [AArch64] Only allow 0s unconditionally for floating
point values
- Backport of [AArch64] Optimize float immediate moves-HF/DF/SF mode
- Backport of [AArch64] Optimize float immediate moves-infrastructure
- Backport of [AArch64] Optimize float immediate moves-testsuite
- Backport of [AArch64] Optimize integer immediate moves with partial masks
- Backport of [Tesstuite] Fix dg-require-stack-check
- Backport of [Testsuite] [AArch32] Add -mfloat-abi=hard to arm_neon_ok
- Backport of [Testsuite] [AArch64] Fix dbl_mov_immediate_1.c test
- Backport of [Testsuite] [AArch64] gcc.target/aarch64/ccmp_2.c: New test
- Backport of [Cleanup] [AArch32] PR target/68535 arm.c: 5 * set but not used
- Backport of [Doc] [AArch64] Clean up AArch64 options
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn252072 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn252072
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
The Linaro Toolchain Working Group (TCWG) is pleased to announce our first
preview-grade ILP32 binary cross-toolchain.
Linaro is supporting AArch64 community effort to introduce ILP32 ABI for
AArch64 Linux, and TCWG will be providing preview-grade ILP32 binary
cross-toolchains alongside our normal release candidates. These toolchains
will be built using community-supported branches for ILP32 ABI of Linux kernel
and Glibc.
This first delivery is based on Linaro GCC 7.1-2017.08-rc1 sources and
available at:
http://snapshots.linaro.org/components/toolchain/binaries/7.1-2017.08-rc1/a…
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
== Progress ==
* Infrastructure:
- patch reviews
* Benchmarking:
- more experiments to reduce noise.
- board reboot + several iterations + use of only 1 core seems to
give manageable results, at the expense of execution time
- old 'deprecated IT blocks' patch benchmarked again with this setup, seems ok
* GCC upstream validation:
- further reduced noise ("random" pass/failures)
- reported a few regressions, looking at improving some testcases
related to branch-cost on arm
* binutils/gdb upstream validation:
- gdbserver build broken on trusty, sent an email to Yao
* GCC
- investigating portability of ubsan to bare-metal targets
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Benchmarking
* GCC upstream validation
* GCC/ubsan
== Progress ==
o Linaro GCC/Validation
* Working on release process
* Reviewed infra patches
* Still some patches pending on upstream reviews
o LLVM
* Familiarizing with LLVM environment
o Misc
* Various meetings and discussions.
* Booked everything for SFO17
== Plan ==
o Backports for 2017.09 snapshot
* 3 days off
== Progress ==
o Linaro GCC/Validation
* Investigating upstream bugzilla PR81863
* Other patches are still pending on upstream reviews
* Working on release process
o Misc
* Various meetings and discussions.
== Plan ==
o PR81863, ...
== This Week ==
* Type promotion (6/10)
- Benchmarking on ARM and AArch64
- Experimenting with pass order to reduce redundancies
- Preparing the patch to send upstream
* PR78809 (2/10)
- Prototype patch done
- Working through testsuite fallout
* PR78736 (1/10)
- Iteration on upstream feedback. Waiting for approval from Fortran
maintainers for
libgfortran changes
* Misc (1/10)
- Submitted https://review.linaro.org/#/c/21111/
- Meetings
== This Week ==
- Submit patch fo type promotion upstream.
- GNU Cauldron 2017
Status of two weeks.
* Bank holiday on Monday and I am off on Tue and Wed. [6/20]
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/20]
Post my target description v4 patches. They should be ready to
check in, however, I am sidetracked by GNU Cauldron presentation.
* Cauldron presentation. [5/20]
Write the presentation for my target description work above. Ongoing.
latex+beamer+tikz is quite powerful to make presentation.
* My Linaro Connect SFO17 presentation is accepted.
Need to write it in google doc later.
* Review Alan H.'s patches. [2/20]
* Misc [3/20]
# Plan #
* Finish my Cauldron presentation,
* Commit my target description v4 patches, if time allows,
* Off on Wed, and fly to Prague. Back to office on 14th Sep.
--
Yao Qi
Hi,
On 26 August 2017 at 18:10, Pinski, Andrew <Andrew.Pinski(a)cavium.com> wrote:
>> However there might be pushback from upstream maintainers as this makes the structure bigger
>> by adding a field. This could have implications for memory usage of the compiler.
>
> I looked into the structure, adding this field is not going to make the structure bigger for either ILP32 or LP64 targets. If you want, you use bit-fields; there is one bool already there which means you can fit 8 bits in the same area as currently taken up by that one.
Yes. I should have checked the mem_attrs structure. This does have at
least a byte left unlike some other tightly packed structures (gimple
and some tree structures in gcc).
Thanks,
Kugan
>> Alternatively, we maybe able to get this info from dwarf info when we compile with -g ?
>
> I doubt you can. He wants to know if an instruction is a spill location. The location of a variable might be recorded in -g (if it was an user variable) but not that does present the data for all temps being spilled.
>
> I think the patch is actually a good one in general just needs some cleanup.
>
> As for these comments:
>>> For example, GCC calls `output_asm_insn' directly from the `define_insn'
>>> definition in the aarch64.md file without an insn object(`output_asm_insn'
>>> calls `output_asm_operand_names').
>>> This occurs in "*cb<optab><mode>1" and
>>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>
> Spills in GCC will always be via the mov* patterns (they are special).
> Now really *aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult should be fixed for a different reason; it does unneeded work. The fix would be something like (untested):
> {
> operands[2] = GEN_INT (aarch64_fpconst_pow_of_2 (operands[2]));
> return "fcvtz<su>\t%<GPI:w>0, %<GPF:s>1, %2";
> }
>
> Thanks,
> Andrew
>
>
> -----Original Message-----
> From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Kugan Vivekanandarajah
> Sent: Saturday, August 26, 2017 12:40 AM
> To: Renato Golin <renato.golin(a)linaro.org>
> Cc: Jim Wilson <jim.wilson(a)linaro.org>; hpc-sig-devel(a)linaro.org; Linaro Toolchain <linaro-toolchain(a)lists.linaro.org>
> Subject: Re: [hpc-sig-devel] GCC extensions for `hcqc'
>
> Hi,
>
> On 26 August 2017 at 04:04, Renato Golin <renato.golin(a)linaro.org> wrote:
>> +linaro-toolchain, hoping to get more eyes into it.
>>
>> cheers,
>> --renato
>>
>> On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote:
>>> Hi,
>>>
>>> I extended GCC 7.1(or GCC 7.2) for `hcqc'.
>>> I would be grateful if you could give me a comment about whether this
>>> extension is acceptable and whether this extension should be pushed
>>> upstream.
>
> I think this is a useful info. However there might be pushback from upstream maintainers as this makes the structure bigger by adding a field. This could have implications for memory usage of the compiler.
> Alternatively, we maybe able to get this info from dwarf info when we compile with -g ? Jim may have some input here (cc ing him).
>
> Thanks,
> Kugan
>
>>>
>>> The extended GCC's output using the option ` -fverbose-asm' is as
>>> follows:
>>>
>>> ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill)
>>> ^^^^^^^^^^^^^^^^^^^ This
>>> code shows that this instruction accesses a memory area for spill
>>> codes.
>>> I made the following changes to GCC 7.1(or GCC 7.2).
>>> The related files are under `hcqc/patch/gcc-7.1.0-add'.
>>>
>>> (1) rtl.h
>>>
>>> I added flag information to `struct mem_attrs' that means whether it
>>> is a spill memory area or not.
>>>
>>> +
>>> + /* True if the MEM is for spill. */
>>> + bool for_spill_p;
>>>
>>> Also, I added an access macro for this additional field.
>>>
>>> + /* For a MEM rtx, true if its MEM is for spill. */ #define
>>> + MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p)
>>> +
>>>
>>> (2) emit-rtl.c
>>>
>>> I added a code to turn on flags for spill memory area in function
>>> `set_mem_attrs_for_spill'.
>>>
>>> + attrs.for_spill_p = true;
>>>
>>> (3) final.c
>>>
>>> I added code to print that information in function
>>> `output_asm_operand_names'
>>> if the memory is a spill memory area,
>>>
>>> +
>>> + if (MEM_P (op) && MEM_FOR_SPILL_P (op))
>>> + {
>>> + HOST_WIDE_INT size = MEM_SIZE (op);
>>> + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte
>>> + Folded
>>> Spill)", size);
>>> + }
>>>
>>> The above changes are implemented similarly as Clang/LLVM.
>>> Unfortunately, it is difficult for GCC to print the above "(?-byte
>>> Folded Spill)"
>>> for memory access instructions only in the same manner as Clang/LLVM.
>>> The reason is that GCC executes the above `output_asm_operand_names'
>>> even in situations where any instruction object(insn) does not exist
>>> when outputting assembly code.
>>> For example, GCC calls `output_asm_insn' directly from the `define_insn'
>>> definition in the aarch64.md file without an insn object(`output_asm_insn'
>>> calls `output_asm_operand_names').
>>> This occurs in "*cb<optab><mode>1" and
>>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>>>
>>> From this fact, `hcqc' extracts and accumulates memory access
>>> instructions from the assembly code with the comment "(?-byte Folded
>>> Spill)".
>>>
>>> The above extensions are commonly available on almost any architecture.
>>> Also, these extensions do not affect the execution of the resulting
>>> assembly code since additional outputs are only in comments.
>>>
>>> Best regards,
>>> --
>>> --------------------------------------
>>> Masaki Arai
>>>
>> _______________________________________________
>> linaro-toolchain mailing list
>> linaro-toolchain(a)lists.linaro.org
>> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
> _______________________________________________
> linaro-toolchain mailing list
> linaro-toolchain(a)lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
o Linaro GCC/Validation
* Delivered monthly source snapshots
* Released GCC 6 and 7 2017.08 binary releases
* Completed PR 80287:
- Added new testcase on trunk and GCC 7 branch.
- Fix backported on gcc-6-branch.
* Investigating upstream bugzilla PR81863
* Other patches are still pending on upstream reviews
o Misc
* Various meetings and discussions.
== Plan ==
o Off until Aug 31th
o PR81863, ...
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.08 Release is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release packages from:
(sources)
http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
(binaries)
http://releases.linaro.org/components/toolchain/binaries/6.4-2017.08/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.08
http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.08)
==============================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06 and Linaro
GCC 6.4-2017.07 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
== This Week ==
* Type promotion (4/10)
- Looking at perf regressions on ppc64
- Enabling at -O2 with vrp removes some perf regressions
- Did benchmarking for code-size
- Issues with benchmarking for performance
* PR78809 (2/10)
- WIP patch
* PR78736 (1/10)
- Updated patch based on upstream feedback
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- type-promotion, PR78736, PR78809
+linaro-toolchain, hoping to get more eyes into it.
cheers,
--renato
On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote:
> Hi,
>
> I extended GCC 7.1(or GCC 7.2) for `hcqc'.
> I would be grateful if you could give me a comment about whether
> this extension is acceptable and whether this extension should be
> pushed upstream.
>
> The extended GCC's output using the option ` -fverbose-asm' is
> as follows:
>
> ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill)
> ^^^^^^^^^^^^^^^^^^^
> This code shows that this instruction accesses a memory area
> for spill codes.
> I made the following changes to GCC 7.1(or GCC 7.2).
> The related files are under `hcqc/patch/gcc-7.1.0-add'.
>
> (1) rtl.h
>
> I added flag information to `struct mem_attrs' that means whether
> it is a spill memory area or not.
>
> +
> + /* True if the MEM is for spill. */
> + bool for_spill_p;
>
> Also, I added an access macro for this additional field.
>
> + /* For a MEM rtx, true if its MEM is for spill. */
> + #define MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p)
> +
>
> (2) emit-rtl.c
>
> I added a code to turn on flags for spill memory area in function
> `set_mem_attrs_for_spill'.
>
> + attrs.for_spill_p = true;
>
> (3) final.c
>
> I added code to print that information in function
> `output_asm_operand_names'
> if the memory is a spill memory area,
>
> +
> + if (MEM_P (op) && MEM_FOR_SPILL_P (op))
> + {
> + HOST_WIDE_INT size = MEM_SIZE (op);
> + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte Folded
> Spill)", size);
> + }
>
> The above changes are implemented similarly as Clang/LLVM.
> Unfortunately, it is difficult for GCC to print the above "(?-byte Folded
> Spill)"
> for memory access instructions only in the same manner as Clang/LLVM.
> The reason is that GCC executes the above `output_asm_operand_names'
> even in situations where any instruction object(insn) does not exist when
> outputting assembly code.
> For example, GCC calls `output_asm_insn' directly from the `define_insn'
> definition in the aarch64.md file without an insn object(`output_asm_insn'
> calls `output_asm_operand_names').
> This occurs in "*cb<optab><mode>1" and
> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>
> From this fact, `hcqc' extracts and accumulates memory access
> instructions from the assembly code with the comment "(?-byte Folded
> Spill)".
>
> The above extensions are commonly available on almost any architecture.
> Also, these extensions do not affect the execution of the resulting assembly
> code since additional outputs are only in comments.
>
> Best regards,
> --
> --------------------------------------
> Masaki Arai
>
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.08
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn251138 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.11 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn251138
* Backports from mainline:
- [Bugfix] [AArch32] PR target/79665: Improve Cortex-A53 shift bypass
- [Bugfix] PR lto/69866 lto1: internal compiler error: in
add_symbol_to_partition_1, at lto/lto-partition.c:158
- [AArch32] Improve Cortex-A53 FP scheduler
- [AArch64] Add rcpc extension
- [AArch64] Do not increase data alignment at -Os and with -fconserve-stack.
- [AArch64] Emit SIMD moves as mov
- [AArch64] Enable software prefetching (-fprefetch-loop-arrays) for
ThunderX 88xxx
- [AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse
- [AArch64] Fix failing lrint inline tests on bare-metal
- [AArch64] Fix ILP32 memory access
- [AArch64] Improve/correct ThunderX 1 cost model for Arith_shift
- [AArch64] Improve dup pattern
- [AArch64] Inline calls to lrint when possible
- [AArch64] Literal vector construction through vcombine is poor
- [Misc] Fold (A / (1 << B)) to (A >> B)
- [Testsuite] [AArch32] Allow arm_arch_*_ok to test several macros
- [Testsuite] [AArch32] Make gcc.target/arm/its.c more robust
- [Testsuite] [AArch32] Require arm_arch_v8a_ok for sdiv_costs_1.c
- [Testsuite] [AArch32] sdiv_costs_1.c: Disable on softfloat
- [Testsuite] [AArch32] sdiv_costs_1.c: Require arm_v8_vfp_ok
- [Testsuite] [AArch32] sdiv_costs_1.c: Use dg-add-options
- [Cleanup] [AArch64] Rearrange the processors in aarch64-cores.def
- [Cleanup] Update comment about is_leaf
- [Doc] [AArch64] Document RcPc extension
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn251111 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn251111
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
* Mon - Wed off [6/10]
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [3/10]
Commit another three patches, about GDBserver unit tests. Rebase
patches, and prepare series v4.
* Misc, [1/10]
# Plan #
* TCWG-1162, triage the aarch64-elf GDB test result with QEMU.
* TCWG-1159, rebase my GDB target description patches, and post v4.
--
Yao Qi