== This Week ==
* TCWG-1234 (2/10)
- Came up with another fix which works on my test-case but not on
actual regression
* PR82808 (2/10)
- Modified patch based on upstream suggestions.
* PR82665 (4/10)
- Untested fix
* Misc (2/10)
- Meetings
- Reading ipa mod/ref paper
- Looked at autofdo
== Next Week ==
- Continue ongoing tasks
== Progress ==
o Linaro GCC/Validation
* GCC 6 and 7 2017.11 RC1 deployed
* Fixed Binutils branch used for 5.5 release
* Investigate and fixed Python3 issues in release notes script
(patch under review)
o LLVM ramp-up
* Upstream bug 32999:
- Still tracking corner cases
* Looking at zero/sign-extension elimination status
o Misc
== Plan ==
o Release handover
o LLVM tasks (Bug 32999, sign-extension)
Hi all,
I just upload an sysroot image for ILP32 meant to be used on both testing
and development on dev-01.tcwglab [1]. It is based on out current ILP32
GCC 7 sysroot plus some tools and it is meant to easier development and
testing. It should have all native required tools for GNU development:
glibc 2.27 (arm/ilp32 branch)
gcc 7.2.1 (linaro/gcc-7-branch)
binutils 2.28.2 (linaro_binutils-2_28-branch)
gmp 6.1.2
mpfr 3.1.6
mpc 1.0.3
coreutils 8.28
bash 4.4.12
gnumake 4.2 (plus a patch to fix glob usage on glibc 2.27)
gawk 4.2
perl 5.26.1
textinfo 6.5
bison 3.0.3
m4 1.4.18
libtool 2.4.5
flex 2.6.4
tcl 8.6.7
expect 5.45.3
dejagnu 1.6
sed 4.4
diffutils 3.6
tar 1.29
gzip 1.8
finutils 4.6.0
I could build and check glibc and binutils and bootstrap gcc. The binutils
and gcc tests are working (dejagnu/expect/tcl is installed).
To actually get a working VMs to run ILP32 you need a kernel built with different
branch than either canonical Linus tree or linux stable. Easier way is to use
Maxim's automated script to start a qemu aarch64 instance on r1-a7:
$ WORKSPACE=`pwd` bash -x ~maxim.kuvyrkov/src/jenkins-scripts/start-container-qemu.sh \
--weight 2 --node r1-a7 --arch arm64 --distro xenial --task test --prefix ilp32_ \
--kernel_url https://people.linaro.org/~maxim.kuvyrkov/norov-Image --initrd_url \
https://cloud-images.ubuntu.com/releases/16.04/release/unpacked/ubuntu-16.0… \
--session-name ilp32-$USER --newuser $USER --cp_file ~/.ssh/authorized_keys
You can then log in the machine as usual ('ssh -P r1-a7.aus-colo') and download
the sysroot from dev-01.tcwglab. Just uncompress it and issue the usual
chroot command:
$ mkdir aarch64-linux-gnu_ilp32/proc; sudo mount -t proc proc aarch64-linux-gnu_ilp32/proc
$ mkdir aarch64-linux-gnu_ilp32/sys; sudo mount -t sysfs sys aarch64-linux-gnu_ilp32/sys
$ mkdir aarch64-linux-gnu_ilp32/dev; sudo mount -o bind /dev aarch64-linux-gnu_ilp32/dev
$ sudo chroot aarch64-linux-gnu_ilp32
A useful package missing is GDB and python, I plan to get them built and I will
update the image on dev-01.tcwglab during this week.
[1] /home/tcwg-buildslave/public_html/images/ilp32/aarch64-linux-gnu_ilp32.tar.bz2
Hi,
I put HCQC(HPC compiler quality checker) on GitHub.
URL: https://github.com/Linaro/hcqc
Any comments or suggestions are very welcome.
I am going to improve README.md overall and to add more test programs.
I will also report the analysis results using HCQC on hpc-sig-devel.
The attached PDF file was used to explain HCQC at HPC-SIG SC meeting(11/7).
I think you can reproduce the results on this slide if you modify the
following part of the configuration file:
hcqc/config/clang-config.json
"COMMAND" : "/usr/bin/clang",
"VERSION" : "4.0.1",
hcqc/config/gcc-config.json
"COMMAND" : "/usr/bin/gcc-7",
"VERSION" : "7.1.1",
which you need to fix to suit your environment.
[image: https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif]
Best regards,
--
--------------------------------------
Masaki Arai
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.11-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11-rc1/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/6.4-2017.11-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.11-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.11-rc1/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.11-rc1)
==================================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06, Linaro
GCC 6.4-2017.07, Linaro GCC 6.4-2017.08, Linaro GCC 6.4-2017.09 and
Linaro GCC 6.4-2017.10 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
Hi Maxim, all,
Alex Matveev and I try to enable LTO optimization for Linux kernel
on ARM64. The work is based on patches from Andi Kleen, and is not
complete yet. Maxim recommended to work tightly with toolchain group
to understand how to fix problems better - on kernel or compiler side.
Links:
My unfinished branch:
https://github.com/norov/linux/tree/lto
Andi Kleen tree:
https://github.com/andikleen/linux-misc/tree/lto-411-1
Sami Tolvanen's recent work for clang:
https://lkml.org/lkml/2017/11/3/606
Question we have for now:
There's mrs_s/msr_s macro that doesn't work with LTO - linker
complains very loudly that macro is either not declared, or declared
multiple times. (To reproduce - try to build my kernel branch w/o last
patch).
The same (?) problem is observed with clang, and people there
considered it as feature, not a bug.
https://bugs.llvm.org/show_bug.cgi?id=19749
We have the fix for both clang and gcc, but it looks hacky. Maybe it
worth to fix mrs/msr issue on toolchain side?
Thanks,
Yury
Short week (off Wed/Thu/Fri)
== Progress ==
* GCC
- FDPIC: looking at patch stacks
* GCC upstream validation:
- got feedback from upstream about qemu and asan interaction since
recent merge: need to disable LSAN on arm.
- using qemu-2.7 again enables to workaround the timeout issues
observed last week
- worked on improving timeout handling
- restarted validations, but....
- validations on-hold since Nov 1st because of an ST-internal
infrastructure problem
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
* 3 days off
== Progress ==
o Linaro GCC/Validation
o LLVM
* Continue ramp-up
* Upstream bug 32999:
- Reworked the fix and validate it
- Ready to be submitted upstream
* Start to look at sign-extension elimination status
o Misc
== Plan ==
o Release handover (5 release, 6 and 7 RCs)
o LLVM tasks (Bug 32999, sign-extension)
# Progress #
* TCWG-1040, [6/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Commit clean up and refactor patches. Find more clean up patches
in my tree. Keep upstreaming them. The design and implementation
of removing MAX_REGISTER_SIZE becomes more and more clear.
* TCWG-1125, [2/10] ARMv8 tagged address support in GDB.
v2 patches were posted. No comments yet.
* aarch64: PR 19806: watchpoints: false negatives + PR 20207 contiguous
ones. Patch review. [1/10]
* Think about the TODOs for GDB ILP32 support, write them down, and send
it to Maxim. [1/10]
# Plan #
* TCWG-1040, TCWG-1125.
--
Yao Qi
Hi ,
I am a SW engineer that use Linaro-toolchain to build images,
Recently, I encounter some issue about enable NEON features on ARMv8 processor platform.
I cat cpuinfo, can not find neon and vfp feature enable in list, the image was build with aarch-64 toolchian;
While, the image built by armv7l toolchain can list "neon and vfp" in cpuinfo.
I want to verify from your side,
1. if the toolchain of aarch64 version already enable" neon and vfp " in default, Because I do not find some build items that related with "neon",
2. If not supported defaultly, can you give some suggestion to enable it.
Thanks & B.R.
Joy Deng
== This Week ==
* TCWG-1005 (4/10)
- Iteration on upstream feedback and validated patch
- Committed to trunk in r254140.
* Reverse of TCWG-1253 transform (3/10)
- Adding reverse transform for div pattern in expand
* TCWG-1234 (2/10)
- Experimenting with "unhoisting" approach
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing and backlog tasks from JIRA
- Go through IPA mod/ref paper
* One day off
== Progress ==
o Linaro GCC/Validation
* Releases handover
- GCC 5.5 source snapshot and RC1 deployed
- GCC 6 and 7 RCs under construction
o LLVM
* Continue ramp-up
* Upstream bug 32999:
- Validating a fix
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== Progress ==
* GCC
- FDPIC: started reading docs and looking at patches
- Neon intrinsics PR71233: duplicates will be removed from the next doc update
* GCC upstream validation:
- since ubsan merge with upstream, validation of arm targets is now
broken. Switching back to qemu-2.7 seems to avoid qemu deadlocks, but
there are still new asan test failures after the merge.
- reduced the dejagnu timeout to avoid global 'make check' timeouts,
but this caused some testcases to become zombies, in turn causing
problems in the ST compute farm.
- validation on-hold until next so that I can experiment a bit more
with workarounds
- reported another qemu bug
- reported a couple of regressions/breakages in binutils
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
* Short week (off Wed/Thu/Fri)
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Post the clean up and refactor patches.
* TCWG-1125, [4/10]
ARMv8 tagged address support in GDB.
v2 patches are posted. Take care of breakpoint and watchpoint on
tagged address carefully.
* ILP32 GDB branch. [1/10]
Branch is created! Done.
* Misc, meeting, [1/10]
# Plan #
* Update my patches to remove the last use of MAX_REGISTER_SIZE.
* GDB flexible target description conversion. Upstream patches.
--
Yao Qi
Hi,
We are evaluating LInaro GCC5.4 readiness for ARMv8.2-A extension support but can't find direct answer if all the features has been supported/backported.
Can you point me to the answer?
Thanks,
Vincent
-----------------------------------------------------------------------------------
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== Progress ==
o Linaro GCC/Validation
* Releases handover
- Monthly snapshots for GCC 6 and 7 deployed
- GCC 5 final release handled by Mark
* Branch merge done
* Tarball and release ready to be deployed
* RC1 planned for w43
o LLVM
* Continue ramp-up
* Working on upstream bug 32999:
[ARM] Missed vpadd combine opportunity
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== This Week ==
* TCWG-1234 (4/10)
- Patch inhibits if-conversion for couple of tests.
* TCWG-1253 (3/10)
- Fixed regressions with the patch
* Took Monday off for recovering from travel (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1253, TCWG-319
# Progress #
* TCWG-1040, [4/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Before I send them upstream, I find some bits that I can improve,
but finally, many things are changed. Need to get them in shape,
and think about the design again.
* TCWG-1125, [4/10]
ARMv8 tagged address support in GDB.
GDB/GDBserver needs to remove the top one byte of virtual address
before pass it to kernel. Patch v1 was reviewed, and GDB internal
caching needs updated for tagged address, because tagged address and
non-tagged address should be mapped to the same cache entry in GDB.
* GDB flexible target description conversion [1/10]
Finished the conversion for tic6x and nios2. To be posted.
* ILP32 GDB branch. [1/10]
Got Steve Ellcey's patches, one bfd patch and one gdb patch.
No GDBserver patches. Will create branch with them.
# Plan #
* ILP32 GDB branch.
* ARMv8 tagged address support in GDB.
* Update my patches to remove the last use of MAX_REGISTER_SIZE.
--
Yao Qi
== Progress ==
* GCC
- FDPIC: started reading docs
- testsuite cleanup
* GCC upstream validation:
- reported 2 bugs in qemu-armeb
- noise reduction: polishing dejagnu local patches
- since ubsan merge with upstream, validation of arm targets is now
much longer (typically 1h30 to 6h), leading to timeouts most of the
time
* Infrastructure:
- improved GCC bisect job/scripts
- updated ABE to allow overriding cpu/fpu/tune/arch etc...
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.10
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the
procedure
call standard (AAPCS). The bug affects some C++ code where class objects
are
passed by value to functions and could result in incorrect or inconsistent
code
being generated. If the option -Wpsabi is enabled (on by default) the
compiler
will emit a diagnostic note for code that might be affected by this ABI
change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn253626 and
includes performance improvements and bug fixes backported from mainline
GCC.
The contents of this snapshot will be part of the 2017.11 stable[2]
quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn253626
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn253668 and
includes performance improvements and bug fixes backported from mainline
GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn253668
o Subscribe to the important Linaro mailing lists and join our IRC channels
to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
o Linaro GCC/Validation
* Continue releases handover
- Branch merges done
- Monthly snapshots about to be deployed
o LLVM
* Jira cards review
* Checked/updated cards related to upstream BZ
* Continue ramp-up
o Misc
* Various meetings and discussions.
== Plan ==
o Continue release handover and LLVM ramp-up
== This Week ==
* TCWG-1234 (5/10)
- Posted analysis upstream with a test-case.
- Have a workaround that disables hoisting when only single stmt is to
be hoisted.
- Investigating solution to limit distance between hoisted def. and it's uses.
* TCWG-1005 (2/10)
- Did changes based on upstream feedback from Honza, validated patch.
- Waiting for final approval from Honza before committing.
* Sick leave (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1005
* One day off after Connect
== Progress ==
o Linaro GCC/Validation
* Handover releases to ARM on-going.
o LLVM
* Continue ramp-up
o Misc
* Various meetings and discussions.
* Debrief Connect inside ST
== Plan ==
o Continue release handover
o LLVM Jira card: cleanup and find first tasks to do
== This Week ==
* TCWG-1234: code-hoisting regression (3/10)
- Have a workaround that fixes the particular regression (but may
introduce another)
- Trying to cross build benchmarks
- Investigating PRE and code-hoisting optimizations
* TCWG-1005: malloc attr propagation (3/10)
- Iteration based on upstream feedback.
* TCWG-1253 (1/10)
- Committed patch last week to add patterns for div and cmp against 0.
- Patch to transform rshift and cmp against 0 to cmp between operands
in upstream review.
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234, TCWG-1005
== Connect ==
* Various discussions on GNU toolchain roadmap
== Progress ==
* GCC
- committed fix for PR71727 (strict-align bug on aarch64), backported
to gcc-7-branch
- small fixes in the testsuite
* GCC upstream validation:
- problems with internal infrastructure, but validation results OK
- reported a couple of regressions/new failures
- ran validations for a couple of tentative patches
- noise reduction: looking at how to report randomly killed processes
* misc (conf-calls, meetings, emails, ....)
- Connect feedback (internal)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/deprecated-IT blocks
# Progress #
* GDB SVE patches review. [4/10]
Finished my patches to remove the last use of MAX_REGISTER_SIZE. Send
them to Alan to review.
* GDB flexible target description follow-up. [4/10]
Committed some patches to improve GDB build, so that we can easily
share code of target description between GDB and GDBserver. Done.
* File Linaro Connect expense, and misc. [2/10]
# Plan #
* On holiday, Mon - Thu.
* Either GDB target description work,or ILP32 GDB branch.
--
Yao Qi
On 24 July 2017 at 18:38, Christophe Lyon <christophe.lyon(a)linaro.org> wrote:
>
>
> Le 24 juil. 2017 18:30, "Ard Biesheuvel" <ard.biesheuvel(a)linaro.org> a écrit
> :
>
> On 18 July 2017 at 13:54, Christophe Lyon <christophe.lyon(a)linaro.org>
> wrote:
>> On 13 July 2017 at 13:50, Christophe Lyon <christophe.lyon(a)linaro.org>
>> wrote:
>>> On 12 July 2017 at 19:33, Ard Biesheuvel <ard.biesheuvel(a)linaro.org>
>>> wrote:
>>>> On 12 July 2017 at 18:27, Alexei Fedorov <Alexei.Fedorov(a)arm.com> wrote:
>>>>>
>>>>> Christophe, Leif, Ard, Ryan at al.
>>>>>
>>>>>
>>>>> We are observing unaligned memory access fault with UEFI code compiled
>>>>> by
>>>>> Linaro GCC 6.3.1 & 7.1.1 using -O3 optimisation option.
>>>>>
>>>>> The fault occures at the very early stage of UEFI boot with MMU not
>>>>> being
>>>>> enabled yet.
>>>>>
>>>>> The failing function is CalculateSum8() from
>>>>> edk2\MdePkg\Library\BaseLib\CheckSum.c:
>>>>>
>>>>>
>>>>> UINT8
>>>>> EFIAPI
>>>>> CalculateSum8 (
>>>>> IN CONST UINT8 *Buffer,
>>>>> IN UINTN Length
>>>>> )
>>>>> {
>>>>> UINT8 Sum;
>>>>> UINTN Count;
>>>>>
>>>>> ASSERT (Buffer != NULL);
>>>>> ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
>>>>>
>>>>> for (Sum = 0, Count = 0; Count < Length; Count++) {
>>>>> Sum = (UINT8) (Sum + *(Buffer + Count));
>>>>> }
>>>>>
>>>>> return Sum;
>>>>> }
>>>>>
>>>>> & the instruction which causes the exception is "ldr q1, [x1], 16"
>>>>> which
>>>>> accesses Buffer = 0xE0000048 pointed by X1 register, see the part of
>>>>> generated assembly code:
>>>>>
>>>>>
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:49: for (Sum = 0, Count
>>>>> = 0;
>>>>> Count < Length; Count++) {
>>>>> .loc 1 49 0 is_stmt 1
>>>>> cbz x19, .L10 // Length,
>>>>> .L4:
>>>>> sub x0, x19, #1 // tmp150, Length,
>>>>> cmp x0, 14 // tmp150,
>>>>> bls .L11 //,
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:42: {
>>>>> .loc 1 42 0
>>>>> movi v0.4s, 0 // vect_Sum_19.24
>>>>> lsr x2, x19, 4 // bnd.18, Length,
>>>>> mov x1, x20 // ivtmp.29, Buffer
>>>>> mov x0, 0 // ivtmp.28,
>>>>> .LVL4:
>>>>> .p2align 3
>>>>> .L7:
>>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:50: Sum = (UINT8) (Sum
>>>>> +
>>>>> *(Buffer + Count));
>>>>> .loc 1 50 0 discriminator 3
>>>>> ldr q1, [x1], 16 // vect__6.23, MEM[(const UINT8
>>>>> *)vectp_Buffer.21_38]
>>>>> add x0, x0, 1 // ivtmp.28, ivtmp.28,
>>>>> cmp x0, x2 // ivtmp.28, bnd.18
>>>>> add v0.16b, v0.16b, v1.16b // vect_Sum_19.24, vect_Sum_19.24,
>>>>> vect__6.23
>>>>> bcc .L7 //,
>>>>>
>>>>> ...
>>>>>
>>>>> Although all AARCH64 code is compiled with "-mstrict-align" option
>>>>> which
>>>>> according to GCC 3.18.1 AArch64 Options:
>>>>>
>>>>> "-mstrict-align
>>>>>
>>>>> Avoid generating memory accesses that may not be aligned on a natural
>>>>> object
>>>>> boundary as described in the architecture specification."
>>>>>
>>>>>
>>>>> the generated code doesn't comply with this description. In this case
>>>>> X1 =
>>>>> Buffer @0xE0000048 and is not aligned to 16 bytes boundary.
>>>>>
>>>>> The similiar code is generated by GCC 6.3.1-2017.05 but 5.3.1-2016.05
>>>>> compiler produces only 16 bytes aligned memory accesses when loading Q1
>>>>> register.
>>>>>
>>>>>
>>>>> I attached the simple test file which can be compiled by running GCC
>>>>> compilation with
>>>>>
>>>>> -c test.c -O3 -mstrict-align -save-temps
>>>>>
>>>>> to see the difference between code generated by 7.1.1 & 5.3.1 GCC
>>>>> versions.
>>>>>
>>>>> It seems that 5.3.1 ignores "-mstrict-align" option at all and always
>>>>> generates aligned pointers for loading Q1 register, 7.1.1 & 6.3.1 also
>>>>> ignore the option but generate slighly different code with unaligned
>>>>> access
>>>>> enabled.
>>>>>
>>>>>
>>>>> Please share your thoughts regading this issue.
>>>>>
>>>>
>>>> Hello Alexei,
>>>>
>>>> This does look like a compiler bug to me. 'Buffer' is a pointer to
>>>> unsigned char, and so the compiler should never emit the ldr
>>>> instruction under -mstrict-align.
>>>>
>>>> In the mean time, we could work around this with adding
>>>> -mgeneral-regs-only in all places where -mstrict-align is being
>>>> passed. In general, I don't really see the point of supporting the use
>>>> of FP/ASIMD registers in UEFI beyond ensuring that our builds are
>>>> compatible with 3rd party binaries that do use them.
>>>>
>>>
>>> Hello Alexei,
>>>
>>> I agree with Ard: it looks like a compiler bug, I'm looking at it.
>>>
>>> And indeed in the mean time, using -mgeneral-regs-only should
>>> workaround your problem.
>>>
>>
>> Hello,
>>
>> As a follow-up, I've posted a patch:
>> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01063.html
>>
>> We'll see if maintainers agree.
>>
>
> Thanks. By the looks of it, nobody cared to respond, right?
>
>
> Not yet and we are used to slow response.
>
> In addition I'm on holidays until Aug 21st so I won't ping until then.
>
>
Hi all,
My patch was finally accepted last week and committed.
I also backported it to the gcc-7-branch, so that the problem will
be fixed in the next gcc-7 release (either FSF or Linaro).
Thanks,
Christophe
# Progress #
* Flexible GDB target description work. [5/10]
As we'll add more and more files, need to clean up GDB build first.
Patch is OK, but need to reduce the duplication first. Yet another
clean up.
Start to think about the design of removing last usage of
MAX_REGISTER_SIZE. Still ongoing.
* Misc, [5/10]
** File cauldron expense.
** Improve gdb_mbuild.sh to build GDB for different supported targets.
# Plan #
* Connect.
--
Yao Qi
== Progress ==
o Linaro GCC/Validation
* Completed backports and branch merges
* Delivered 7.2 and 6.4 monthly source snapshots
* Reviewed infra patches
* Still some patches pending on upstream reviews
o LLVM
* Still learning
o Misc
* Various meetings and discussions.
== Plan ==
o Close remaining GCC tasks
Two weeks
* GNU Cauldron and vacation, [12/20]
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/20]
Commit my patches, and fix some build failures. Done.
* Cauldron presentation and Linaro Connect SFO17 presentation. [3/20]
Done.
* Misc, catch up email, [1/20]
# Plan #
* Prepare a prototype about regcache, and compare with Alan's
implementation.
* Continue my target description work, for other non-actively-maintained
target descriptions.
--
Yao Qi
== Progress ==
* Infrastructure:
- patch reviews
* Benchmarking:
- minor bug fixes
* Snapshots/releases
- branch merge reviews
* GCC upstream validation:
- PR82120: adding a -mbranch-cost option to the arm backend does not
help with pr81588.c test failing on cortex-a5
- incorrectly reported a regression due to bisect problems (worth
100% chocolate ;-)
- still working on further reducing false alams
- problems with internal infrastructure
* binutils/gdb upstream validation:
- gdbserver build fixed by Yao
* GCC
- investigating portability of ubsan to bare-metal targets
- 'ARMv8 deprecated IT blocks' patch finally committed. Will look at
the remaining warnings.
* misc (conf-calls, meetings, emails, ....)
- Connect preparation (slides, ...)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/deprecated-IT blocks
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.09
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn252337 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.11 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn252337
* Backports from mainline:
- Backport of [Bugfix] [AArch32] PR target/77308 surprisingly large
stack usage for sha512 on arm
- Backport of [AArch32] Fix ldrd offsets
- Backport of [AArch32] Remove %? string from some Advanced SIMD patterns
- Backport of [AArch64] Add optimized implementation of mersenne twister
- Backport of [AArch64] Add RDMA support to falkor port
- Backport of [AArch64] Fix big endian float immediate moves
- Backport of [AArch64] Fix missing optimization for CMP+AND
- Backport of [AArch64] Fix pattern guard relaxations that are
allowing more constants than they should
- Backport of [AArch64] Fix ThunderX fp vectorizer cost model
- Backport of [AArch64] Generate MLA when multiply + add vector by scalar
- Backport of [AArch64] Implement ALU_BRANCH fusion
- Backport of [AArch64] Improve aarch64 conditional compare usage
- Backport of [AArch64] Improve thunderx_vect_cost some more
- Backport of [AArch64] Move the check for any_condjump_p from
sched-deps to target macros
- Backport of [AArch64] Only allow 0s unconditionally for floating
point values
- Backport of [AArch64] Optimize float immediate moves-HF/DF/SF mode
- Backport of [AArch64] Optimize float immediate moves-infrastructure
- Backport of [AArch64] Optimize float immediate moves-testsuite
- Backport of [AArch64] Optimize integer immediate moves with partial masks
- Backport of [Tesstuite] Fix dg-require-stack-check
- Backport of [Testsuite] [AArch32] Add -mfloat-abi=hard to arm_neon_ok
- Backport of [Testsuite] [AArch64] Fix dbl_mov_immediate_1.c test
- Backport of [Testsuite] [AArch64] gcc.target/aarch64/ccmp_2.c: New test
- Backport of [Cleanup] [AArch32] PR target/68535 arm.c: 5 * set but not used
- Backport of [Doc] [AArch64] Clean up AArch64 options
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn252072 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn252072
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
The Linaro Toolchain Working Group (TCWG) is pleased to announce our first
preview-grade ILP32 binary cross-toolchain.
Linaro is supporting AArch64 community effort to introduce ILP32 ABI for
AArch64 Linux, and TCWG will be providing preview-grade ILP32 binary
cross-toolchains alongside our normal release candidates. These toolchains
will be built using community-supported branches for ILP32 ABI of Linux kernel
and Glibc.
This first delivery is based on Linaro GCC 7.1-2017.08-rc1 sources and
available at:
http://snapshots.linaro.org/components/toolchain/binaries/7.1-2017.08-rc1/a…
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
== Progress ==
* Infrastructure:
- patch reviews
* Benchmarking:
- more experiments to reduce noise.
- board reboot + several iterations + use of only 1 core seems to
give manageable results, at the expense of execution time
- old 'deprecated IT blocks' patch benchmarked again with this setup, seems ok
* GCC upstream validation:
- further reduced noise ("random" pass/failures)
- reported a few regressions, looking at improving some testcases
related to branch-cost on arm
* binutils/gdb upstream validation:
- gdbserver build broken on trusty, sent an email to Yao
* GCC
- investigating portability of ubsan to bare-metal targets
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Benchmarking
* GCC upstream validation
* GCC/ubsan
== Progress ==
o Linaro GCC/Validation
* Working on release process
* Reviewed infra patches
* Still some patches pending on upstream reviews
o LLVM
* Familiarizing with LLVM environment
o Misc
* Various meetings and discussions.
* Booked everything for SFO17
== Plan ==
o Backports for 2017.09 snapshot
* 3 days off
== Progress ==
o Linaro GCC/Validation
* Investigating upstream bugzilla PR81863
* Other patches are still pending on upstream reviews
* Working on release process
o Misc
* Various meetings and discussions.
== Plan ==
o PR81863, ...
== This Week ==
* Type promotion (6/10)
- Benchmarking on ARM and AArch64
- Experimenting with pass order to reduce redundancies
- Preparing the patch to send upstream
* PR78809 (2/10)
- Prototype patch done
- Working through testsuite fallout
* PR78736 (1/10)
- Iteration on upstream feedback. Waiting for approval from Fortran
maintainers for
libgfortran changes
* Misc (1/10)
- Submitted https://review.linaro.org/#/c/21111/
- Meetings
== This Week ==
- Submit patch fo type promotion upstream.
- GNU Cauldron 2017
Status of two weeks.
* Bank holiday on Monday and I am off on Tue and Wed. [6/20]
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/20]
Post my target description v4 patches. They should be ready to
check in, however, I am sidetracked by GNU Cauldron presentation.
* Cauldron presentation. [5/20]
Write the presentation for my target description work above. Ongoing.
latex+beamer+tikz is quite powerful to make presentation.
* My Linaro Connect SFO17 presentation is accepted.
Need to write it in google doc later.
* Review Alan H.'s patches. [2/20]
* Misc [3/20]
# Plan #
* Finish my Cauldron presentation,
* Commit my target description v4 patches, if time allows,
* Off on Wed, and fly to Prague. Back to office on 14th Sep.
--
Yao Qi
Hi,
On 26 August 2017 at 18:10, Pinski, Andrew <Andrew.Pinski(a)cavium.com> wrote:
>> However there might be pushback from upstream maintainers as this makes the structure bigger
>> by adding a field. This could have implications for memory usage of the compiler.
>
> I looked into the structure, adding this field is not going to make the structure bigger for either ILP32 or LP64 targets. If you want, you use bit-fields; there is one bool already there which means you can fit 8 bits in the same area as currently taken up by that one.
Yes. I should have checked the mem_attrs structure. This does have at
least a byte left unlike some other tightly packed structures (gimple
and some tree structures in gcc).
Thanks,
Kugan
>> Alternatively, we maybe able to get this info from dwarf info when we compile with -g ?
>
> I doubt you can. He wants to know if an instruction is a spill location. The location of a variable might be recorded in -g (if it was an user variable) but not that does present the data for all temps being spilled.
>
> I think the patch is actually a good one in general just needs some cleanup.
>
> As for these comments:
>>> For example, GCC calls `output_asm_insn' directly from the `define_insn'
>>> definition in the aarch64.md file without an insn object(`output_asm_insn'
>>> calls `output_asm_operand_names').
>>> This occurs in "*cb<optab><mode>1" and
>>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>
> Spills in GCC will always be via the mov* patterns (they are special).
> Now really *aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult should be fixed for a different reason; it does unneeded work. The fix would be something like (untested):
> {
> operands[2] = GEN_INT (aarch64_fpconst_pow_of_2 (operands[2]));
> return "fcvtz<su>\t%<GPI:w>0, %<GPF:s>1, %2";
> }
>
> Thanks,
> Andrew
>
>
> -----Original Message-----
> From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Kugan Vivekanandarajah
> Sent: Saturday, August 26, 2017 12:40 AM
> To: Renato Golin <renato.golin(a)linaro.org>
> Cc: Jim Wilson <jim.wilson(a)linaro.org>; hpc-sig-devel(a)linaro.org; Linaro Toolchain <linaro-toolchain(a)lists.linaro.org>
> Subject: Re: [hpc-sig-devel] GCC extensions for `hcqc'
>
> Hi,
>
> On 26 August 2017 at 04:04, Renato Golin <renato.golin(a)linaro.org> wrote:
>> +linaro-toolchain, hoping to get more eyes into it.
>>
>> cheers,
>> --renato
>>
>> On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote:
>>> Hi,
>>>
>>> I extended GCC 7.1(or GCC 7.2) for `hcqc'.
>>> I would be grateful if you could give me a comment about whether this
>>> extension is acceptable and whether this extension should be pushed
>>> upstream.
>
> I think this is a useful info. However there might be pushback from upstream maintainers as this makes the structure bigger by adding a field. This could have implications for memory usage of the compiler.
> Alternatively, we maybe able to get this info from dwarf info when we compile with -g ? Jim may have some input here (cc ing him).
>
> Thanks,
> Kugan
>
>>>
>>> The extended GCC's output using the option ` -fverbose-asm' is as
>>> follows:
>>>
>>> ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill)
>>> ^^^^^^^^^^^^^^^^^^^ This
>>> code shows that this instruction accesses a memory area for spill
>>> codes.
>>> I made the following changes to GCC 7.1(or GCC 7.2).
>>> The related files are under `hcqc/patch/gcc-7.1.0-add'.
>>>
>>> (1) rtl.h
>>>
>>> I added flag information to `struct mem_attrs' that means whether it
>>> is a spill memory area or not.
>>>
>>> +
>>> + /* True if the MEM is for spill. */
>>> + bool for_spill_p;
>>>
>>> Also, I added an access macro for this additional field.
>>>
>>> + /* For a MEM rtx, true if its MEM is for spill. */ #define
>>> + MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p)
>>> +
>>>
>>> (2) emit-rtl.c
>>>
>>> I added a code to turn on flags for spill memory area in function
>>> `set_mem_attrs_for_spill'.
>>>
>>> + attrs.for_spill_p = true;
>>>
>>> (3) final.c
>>>
>>> I added code to print that information in function
>>> `output_asm_operand_names'
>>> if the memory is a spill memory area,
>>>
>>> +
>>> + if (MEM_P (op) && MEM_FOR_SPILL_P (op))
>>> + {
>>> + HOST_WIDE_INT size = MEM_SIZE (op);
>>> + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte
>>> + Folded
>>> Spill)", size);
>>> + }
>>>
>>> The above changes are implemented similarly as Clang/LLVM.
>>> Unfortunately, it is difficult for GCC to print the above "(?-byte
>>> Folded Spill)"
>>> for memory access instructions only in the same manner as Clang/LLVM.
>>> The reason is that GCC executes the above `output_asm_operand_names'
>>> even in situations where any instruction object(insn) does not exist
>>> when outputting assembly code.
>>> For example, GCC calls `output_asm_insn' directly from the `define_insn'
>>> definition in the aarch64.md file without an insn object(`output_asm_insn'
>>> calls `output_asm_operand_names').
>>> This occurs in "*cb<optab><mode>1" and
>>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>>>
>>> From this fact, `hcqc' extracts and accumulates memory access
>>> instructions from the assembly code with the comment "(?-byte Folded
>>> Spill)".
>>>
>>> The above extensions are commonly available on almost any architecture.
>>> Also, these extensions do not affect the execution of the resulting
>>> assembly code since additional outputs are only in comments.
>>>
>>> Best regards,
>>> --
>>> --------------------------------------
>>> Masaki Arai
>>>
>> _______________________________________________
>> linaro-toolchain mailing list
>> linaro-toolchain(a)lists.linaro.org
>> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
> _______________________________________________
> linaro-toolchain mailing list
> linaro-toolchain(a)lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
o Linaro GCC/Validation
* Delivered monthly source snapshots
* Released GCC 6 and 7 2017.08 binary releases
* Completed PR 80287:
- Added new testcase on trunk and GCC 7 branch.
- Fix backported on gcc-6-branch.
* Investigating upstream bugzilla PR81863
* Other patches are still pending on upstream reviews
o Misc
* Various meetings and discussions.
== Plan ==
o Off until Aug 31th
o PR81863, ...
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.08 Release is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release packages from:
(sources)
http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
(binaries)
http://releases.linaro.org/components/toolchain/binaries/6.4-2017.08/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.08
http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.08)
==============================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06 and Linaro
GCC 6.4-2017.07 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
== This Week ==
* Type promotion (4/10)
- Looking at perf regressions on ppc64
- Enabling at -O2 with vrp removes some perf regressions
- Did benchmarking for code-size
- Issues with benchmarking for performance
* PR78809 (2/10)
- WIP patch
* PR78736 (1/10)
- Updated patch based on upstream feedback
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- type-promotion, PR78736, PR78809
+linaro-toolchain, hoping to get more eyes into it.
cheers,
--renato
On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote:
> Hi,
>
> I extended GCC 7.1(or GCC 7.2) for `hcqc'.
> I would be grateful if you could give me a comment about whether
> this extension is acceptable and whether this extension should be
> pushed upstream.
>
> The extended GCC's output using the option ` -fverbose-asm' is
> as follows:
>
> ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill)
> ^^^^^^^^^^^^^^^^^^^
> This code shows that this instruction accesses a memory area
> for spill codes.
> I made the following changes to GCC 7.1(or GCC 7.2).
> The related files are under `hcqc/patch/gcc-7.1.0-add'.
>
> (1) rtl.h
>
> I added flag information to `struct mem_attrs' that means whether
> it is a spill memory area or not.
>
> +
> + /* True if the MEM is for spill. */
> + bool for_spill_p;
>
> Also, I added an access macro for this additional field.
>
> + /* For a MEM rtx, true if its MEM is for spill. */
> + #define MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p)
> +
>
> (2) emit-rtl.c
>
> I added a code to turn on flags for spill memory area in function
> `set_mem_attrs_for_spill'.
>
> + attrs.for_spill_p = true;
>
> (3) final.c
>
> I added code to print that information in function
> `output_asm_operand_names'
> if the memory is a spill memory area,
>
> +
> + if (MEM_P (op) && MEM_FOR_SPILL_P (op))
> + {
> + HOST_WIDE_INT size = MEM_SIZE (op);
> + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte Folded
> Spill)", size);
> + }
>
> The above changes are implemented similarly as Clang/LLVM.
> Unfortunately, it is difficult for GCC to print the above "(?-byte Folded
> Spill)"
> for memory access instructions only in the same manner as Clang/LLVM.
> The reason is that GCC executes the above `output_asm_operand_names'
> even in situations where any instruction object(insn) does not exist when
> outputting assembly code.
> For example, GCC calls `output_asm_insn' directly from the `define_insn'
> definition in the aarch64.md file without an insn object(`output_asm_insn'
> calls `output_asm_operand_names').
> This occurs in "*cb<optab><mode>1" and
> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult".
>
> From this fact, `hcqc' extracts and accumulates memory access
> instructions from the assembly code with the comment "(?-byte Folded
> Spill)".
>
> The above extensions are commonly available on almost any architecture.
> Also, these extensions do not affect the execution of the resulting assembly
> code since additional outputs are only in comments.
>
> Best regards,
> --
> --------------------------------------
> Masaki Arai
>
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.08
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn251138 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.11 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.2+svn251138
* Backports from mainline:
- [Bugfix] [AArch32] PR target/79665: Improve Cortex-A53 shift bypass
- [Bugfix] PR lto/69866 lto1: internal compiler error: in
add_symbol_to_partition_1, at lto/lto-partition.c:158
- [AArch32] Improve Cortex-A53 FP scheduler
- [AArch64] Add rcpc extension
- [AArch64] Do not increase data alignment at -Os and with -fconserve-stack.
- [AArch64] Emit SIMD moves as mov
- [AArch64] Enable software prefetching (-fprefetch-loop-arrays) for
ThunderX 88xxx
- [AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse
- [AArch64] Fix failing lrint inline tests on bare-metal
- [AArch64] Fix ILP32 memory access
- [AArch64] Improve/correct ThunderX 1 cost model for Arith_shift
- [AArch64] Improve dup pattern
- [AArch64] Inline calls to lrint when possible
- [AArch64] Literal vector construction through vcombine is poor
- [Misc] Fold (A / (1 << B)) to (A >> B)
- [Testsuite] [AArch32] Allow arm_arch_*_ok to test several macros
- [Testsuite] [AArch32] Make gcc.target/arm/its.c more robust
- [Testsuite] [AArch32] Require arm_arch_v8a_ok for sdiv_costs_1.c
- [Testsuite] [AArch32] sdiv_costs_1.c: Disable on softfloat
- [Testsuite] [AArch32] sdiv_costs_1.c: Require arm_v8_vfp_ok
- [Testsuite] [AArch32] sdiv_costs_1.c: Use dg-add-options
- [Cleanup] [AArch64] Rearrange the processors in aarch64-cores.def
- [Cleanup] Update comment about is_leaf
- [Doc] [AArch64] Document RcPc extension
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn251111 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn251111
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
* Mon - Wed off [6/10]
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [3/10]
Commit another three patches, about GDBserver unit tests. Rebase
patches, and prepare series v4.
* Misc, [1/10]
# Plan #
* TCWG-1162, triage the aarch64-elf GDB test result with QEMU.
* TCWG-1159, rebase my GDB target description patches, and post v4.
--
Yao Qi
== Progress ==
o Linaro GCC/Validation
* Completed 6.4 and 7.2 branch merges
* Snapshots delayed due to gerrit config upgrade issues
* Investigating upstream bugzilla PR81863
* Other patches are still pending on upstream reviews
o Misc
* Various meetings and discussions.
== Plan ==
o Complete monthly snapshot and binary releases
o PR81863, ...
== This Week ==
* type promotion (7/10)
- Refactored patch
- Resolved all functional regressions on arm, aarch64, ppc64.
* PR78809 (1/10)
* Misc (2/10)
- pinged patches for malloc propagation and PR78736
- Public holiday
== Next Week ==
- Validation and Benchmarking of type-promotion pass
- PR78809
In a recent github thread
<https://github.com/OP-TEE/optee_os/issues/1708#issuecomment-320245973> it
was suggested that I ask this list about what the exact reasons for the
lack of C++ support are, and how/if they break down by C++ feature so as to
gauge a possible investment in remedying this situation at least partially.
In other words, suppose I changed the build process to include libstdc++,
libgcc, and libgcc_eh (and/or other runtime support commonly linked with
C++ programs), what features of C++ would work/still fail? And what
implementation work would be required to implement the missing features?
On a related note, are there intrinsic properties of the secure environment
that may conflict with running C++ code, if any?
Thank you.
- Godmar
== Progress ==
o Linaro GCC/Validation
* Delivered GCC 6 and 7 2017.08 release candidates binaries
* Preparing backports for 2017.08 source snapshots
* reviewed infra patches
o Misc
* Various meetings and discussions.
== Plan ==
o Complete backports and branch merges for snapshots
o Tuesday off
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [3/10]
Split the patch series, and post unrelated stuff first.
Patches will be easily reviewed in this way.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Committed the first 4 patches, and leave the rest
4 patches for review.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [4/10]
Resolved the newlib issue. Get my first newlib patch merged.
Successfully run GDB testsuite with QEMU system mode. It should
be similar to running with OpenOCD.
* Upstream review. [1/10]
** Review some memory leaks fixes.
** One patch about armv8.3 pointer authentication.
Next week:
* On holiday, and back on Thu.
* TCWG-1162, triage the aarch64-elf GDB test result with QEMU.
* TCWG-1159, rebase my GDB target description patches, and post v4.
--
Yao Qi
The Linaro Binary Toolchain
============================
The Linaro GCC 6.4-2017.08-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08-rc1/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/6.4-2017.08-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.4-2017.08-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08-rc1/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.0 (gdb-8.0-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.4-2017.08-rc1)
==================================================
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.0.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06 and Linaro
GCC 6.4-2017.07 .
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
The Linaro Binary Toolchain
============================
The Linaro GCC 7.1-2017.08-rc1 Release-Candidate is now available.
*Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for
aarch64*-*-* targets
>From GCC 7.1 release notes:
On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects
conformance to the procedure call standard (AAPCS) has been fixed. The
bug affects some C++ code where class objects are passed by value to
functions and could result in incorrect or inconsistent code being
generated. This is an ABI change. If the option -Wpsabi is enabled (on
by default) the compiler will emit a diagnostic note for code that
might be affected.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
GCC 5 and GCC 6 releases will continue to be affected by the ABI bug,
since changing ABI in these releases is not practical. A warning
enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to
diagnose codebases that might be affected by the ABI bug.
Additionally, this same bug was present in AArch64 backend in
development versions of GCC 7. There was no releases of GCC with this
bug present in AArch64 backend, therefore the release notes does not
mention this. However, be advised that any code bases built with
development versions of GCC 7 need to be recompiled with released
version of GCC 7 to conform to ABI.
For an explanation of GCC 7 series changes please see the following
website:
https://gcc.gnu.org/gcc-7/changes.html
For help in porting to GCC 7 please see the following explanation:
https://gcc.gnu.org/gcc-7/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08-rc1/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/7.1-2017.08-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 7.1-2017.08-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08-rc1/
FSF glibc 2.25 (release/2.25)
https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html
Newlib 2.5 (newlib-2_5_0 tag)
https://sourceware.org/ml/newlib/2016/msg01191.html
GNU Binutils 2.28 (linaro-local/linaro_binutils-2_28-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
FSF GDB 8.0 (gdb-8.0-branch)
https://sourceware.org/ml/gdb-announce/2017/msg00003.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 7 (as of Linaro GCC 7.1-2017.08-rc1)
===========================[ANNOUNCE] Linaro Binary Toolchain
Release-Candidate GCC 7.1-2017.08-rc1=======================
* The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration
improvement for AArch64 targets and laid groundwork to enabling
prefetching in more cases.
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* Performance related backports from the following snapshots have been
included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06 and Linaro
GCC 7.1-2017.07.
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [3/10]
Patches are still not reviewed. Keep going to change x86 target
descriptions. Post two patches to clean up them first.
* TCWG-561, Handle unavailable memory during frame unwinding. [3/10]
Patches are posted.
* PR 21818, GDB crashes with executable for armv5te. [1/10]
Patch is tested, and to be posted.
* Upstream review, [2/10]
** ADI patches review, advice on how to match the output in gdb tests,
** Some disassembly regression caused by my previous patches,
** Help people to triage their GDB issues because I don't have the env
to reproduce them.
* Misc, [1/10]
# Plan #
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards.
Post my newlib patches upstream, and continue to test with
QEMU and OpenOCD respectively.
* TCWG-1159, New design of GDB/GDBserver target description
--
Yao Qi
o Back from vacation Wednesday.
== Progress ==
o Linaro GCC/Validation
* Discussed/checked needs for newlib and binutils to include in binaries
* Preparing RCs (release notes, ...)
* pinged my unreviewed upstream patches
* reviewed infra patches
o Misc
* Various meetings and discussions.
== Plan ==
o 2017.08 GCC 6 and 7 release candidates, backports, ...
== This Week ==
* malloc propagation (4/10)
- Resolved bootstrap comparison failure
- Patch passes validation with and without LTO.
- Working on handling indirect calls.
* type promotion (3/10)
- Created patche for resolving ICE with armv3/armv5t.
- Have got a hack-ish patch to address interference between type promotion and
widening_mul/bswap optimizations, but needs improvement.
* Misc (3/10)
- Meetings
- Visa interview
== Next Week ==
- Continue with malloc propagation, type promotion
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [3/10]
Looks people who can review my patches is on holiday, so I committed
7 patches and leave the rest 19 patches there. Need to think about
how to make people more confident on these patches.
* PR 21717, PR 21555, fixed. Pushed to master and 8.0 branch.
[1/10]
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [3/10]
I can run gdb regression tests with OpenOCD on HiKey. After I power
cycle the board, the first several tests can run, but the following
tests failed because the board goes to an odd state. Something wrong
in OpenOCD side.
Try GDB aarch64 bare-metal debugging with QEMU, and then find a bug
in newlib which doesn't initialize FPU, so some FPU instruction will
trigger und exception.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Lear C++ move assignment and move constructor. Finish the code, and
testing the patches.
* Send my GDB target description talk abstract to Linaro SFO17.
* Misc [1/10]
# Plan #
* Mon and Tue off.
* TCWG-561, TCWG-1159.
--
Yao Qi
4 day week.
[TCWG-614] Range Extension Thunks
- Rebased due to upstream refactoring
- Pinged but no upstream review progress
[Compiler-rt]
Clang no longer always uses base PCS for all the builtins it expands
such as the _Complex helpers.
- Added tests to make sure RTABI 4.1.2 Floating Point helpers all use
softfp in Clang D35538 and llvm D35904.
- Reviewer pointed out useful script update_llc_test_checks.py that
can simplify writing of llc tests. Well worth checking out
[LLD]
Looks like lld use in Android may be becoming more likely, major
blocking feature is lack of Cortex-A53 erratum fix 843419.
- I've commented on the upstream PR https://bugs.llvm.org/show_bug.cgi?id=33463
- I've written some test cases and have started a prototype implementation
Submitted Linaro Connect presentation proposal for Functional Safety
and Development tools.
Plans:
In priority order:
- range extension thunks
- Cortex-A53 843419
- Compiler-rt
== Progress ==
* TCWG-1205 - Minor tweaks to Jenkins LLVM jobs [1/10]
- Sent a few patches to make the Jenkins jobs more friendly and/or
fix them for new changes in the upstream release script
* TCWG-1206 - Investigate timeouts on buildbots [1/10]
- Had some mysterious timeouts on some of the buildbots
- Didn't manage to reproduce, will keep an eye out in case it happens again
* TCWG-1199, 1200 - LLVM 5.0.0 for ARM and AArch64 [1/10]
- RC1 is out, there are some failures in some libunwind and
sanitizer tests; reported upstream
* TCWG-1194 - [ARM GlobalISel] Support simple, static globals [4/10]
- Committed some simple stuff and sent a patch for upstream review
* TCWG-1209 - [MIR] Print ARM constant pools [1/10]
- Printing target-specific constant pools is trivial, but testing is
a bit problematic
- All current MIR tests read in and then print out the same MIR,
which means that we'd have to add support for target-specific constant
pools in the parser as well
- This is complicated by the fact that at a first glance the parser
doesn't seem to handle any other target-specific stuff and I'm not
sure it's ok to pull ARMConstantPool into it
* Misc [2/10]
- Mailing lists, code reviews, meetings
== Plan ==
* Figure out what to do about TCWG-1209
* More code reviews and global isel
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [1/10]
Commit one patch of v3. No review comments. Usually it means I don't
review patches, so other people don't review my patches.
* PR 21555. [3/10]
Think it again, and fix it with a better approach. Patches are posted.
* PR 21717. [2/10]
Fix a bug on getting/setting FPSCR on VFPv2. I am surprised that we don't
find it before. Testing patches.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [1/10]
Blocked by OpenOCD bugs. Chat with OpenOCD maintainer to make sure
these bugs are opened in the right place.
* TCWG-561, [3/10]
I finish the patches, but not confident because I use copy-and-swap idiom
for the first time. Need more time to bake it, write unit tests, etc. Maybe,
still need to read "More effective C++" further.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards.
Blocked by OpenOCD bugs. Chat with OpenOCD maintainer to make sure
these bugs are opened in the right place. Matthew (who contributed OpenOCD
AArch64) pinged me on irc, but he lost connection immediately. Probably, he
contact me for the OpenOCD bugs.
* Think about presenting GDB target description work in Linaro SFO17,
may add some SVE stuff if possible, to make it more attractive.
# Plan #
* TCWG-1159,
* PR 21717, 21555,
* TCWG-561,
* Register the presentation for Linaro SFO17,
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Support globals [6/10]
- This is going to be very hairy because of all the different
relocation models (PIC, ROPI etc), differences between ELF and MachO,
and differences between targets with MOVT or without it
- Started adding support for simple, statically linked globals, it
might take me a while to get all the pseudoinstructions right even for
this simple case
* Misc [4/10]
- Meetings, mailing lists, code reviews, buildbots
== Plan ==
* More GlobalISel
* More code reviews
== Progress ==
* Infrastructure/validation:
- minor fixes in the release jobs
* Benchmarking:
- fixes on reporting scripts
- using more iterations didn't produce more stable results (still noise)
- trying to reboot the boards before running the benchs
* GCC upstream validation:
- further reduced noise ("random" pass/failures)
- sent a patch to fix an aarch64 problem with -mstrict-align
* misc (conf-calls, meetings, emails, ....)
== Next ==
Holidays until August 21st
[TCWG-614] Range Thunks
Finally managed to get some review on the entirety of the Range Thunks
patches. Have reorganised the patches and wrote some documentation to
make it easier to review. Responded to all review comments so far.
Compiler-rt
A long tail of frustration.
Managed to get a hello world semi-hosting test case running on the
latest QEMU running newlib-nano. This was much more difficult than I
expected due to:
- The semihosting startup code of newlib does a semi-hosting call for
top of memory regardless of whether the heap and stack location have
been identified in a linker-script.
- The QEMU semihosting response to top of memory is not helpful
leaving the stack location in an invalid memory location (latest QEMU
requires emulation of a board and not a generic machine)
- QEMU doesn't data-abort when writing to a stack location, so my
return address is helpfully read back as 0x0
Worked around by providing a large enough memory size to QEMU that the
semihosting call for top of memory returns 0, allowing newlib to use
the values in the linker script. Will probably need to spend some time
to write my own startup code that just uses the linker script for the
heap and stack.
Building compiler-rt for v6-m and v7-m has been much more difficult
than I expected as well. I've managed to find a configuration that
works, although it relies on some experimental work in moving
compiler-rt to the runtimes directory.
Plans for next week:
- LLD is top priority
- Get testing for compiler-rt working via qemu on v7-m, the recipe
that works for build does not support testing. I've got to either
extract the cmake magic flags or find a way to plumb through the runes
that make the tests work to the recipe I've got.
- On holiday Thursday, Friday and the following Monday
* Short week (Friday off)
== Progress ==
* Infrastructure/validation:
* Benchmarking:
- production scripts are now up-to-date, still observing noise on
some benchmarks
- fixed a couple of small issues with the scripts
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch with de-require-stack-check
- looking at a problem with unaligned accesses
* misc (conf-calls, meetings, emails, ....)
== This Week ==
* PR78736 (2/10)
- Submitted patch upstream
* type-promotion (3/10)
- Scheduling path-splitting before type-promotion fixes the regression
with path-split-1.c
- Created patch to fix issues with type-promotion interfering with
widening_mul and bswap
optimizations
* malloc-propagation (4/10)
- Updated patch, passes bootstrap+test on x86_64
- Working through ICE's with lto-bootstrap
* Misc (1/10)
- Meetings
== Progress ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64 [5/10]
- Committed upstream
- Also refactored the existing code a bit
* TCWG-1190 - [ARM GlobalISel] Support G_BR and G_BRCOND [2/10]
- Committed upstream
* TCWG-1191 - Test zorg patch [1/10]
- Test a patch for running the test-suite with the CMake producer on
the buildbots
* Misc [3/10]
- Meetings, mailing lists, code reviews, buildbots
== Plan ==
* More GlobalISel
* More code reviews
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [2/10]
v3 are posted, after fixing some regressions introduced by improper
merge. No comments from upstream yet.
* PR 21555. [2/10]
Has already a fix, but I am not satisfied. Post an RFC for a
discussion in general. My fix is to fix each GDB backend one by one,
while my RFC is about fixing it in GDB core side.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [4/10]
OpenOCD doesn't support semi-hosting, so I pass --specs=nosys.specs to
aarch64-none-elf gcc, but linker can't find a symbol from newlib.
Looks nobody tests aarch64-none-elf gcc with --specs=nosys.specs
before. Hack in newlib here and there, and get compiler/linker happy.
I can download code to HiKey via OpenOCD, but "continue" becomes
"single step". Open two OpenOCD bugs upstream. My work is blocked by
OpenOCD bugs.
* Upstream patches review. [2/10]
** Review sparc64 adi patch v3,
** Investigate and review the patch fixing GDB crashes on amd64-linux,
** Review Alan H.'s patch, and discuss on the design,
** Some conversation with Maciej on MIPS16 and microMIPS disassembler,
because my disassembler rework breaks MIPS.
# Plan #
* PR 21555,
* TCWG-1159
* TCWG-561,
# Issue #
* TCWG-1162 is blocked by OpenOCD bugs.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.07
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.1+svn250046 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.08 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.1+svn250046
* Backport of [Bugfix] [AArch32] PR target/71778 ICE using
non-constant argument to Neon intrinsic that requires constant
arguments
* Backport of [Bugfix] [AArch64] PR target/71663 aarch64 Vector
initialization can be improved slightly
* Backport of [AArch32] Enable FP16 vector arithmetic operations
* Backport of [AArch32] Fix ARM bootstrap failure due to an odd warning
* Backport of [AArch32] Modify idiv costs for Cortex-A53
* Backport of [AArch64] Add combine pattern for storing lane zero of a vector
* Backport of [AArch64] Add HF vector modes to lane-to-lane INS pattern
* Backport of [AArch64] Add prefetch configuration to aarch64 backend
* Backport of [AArch64] Adjust costs so udiv is preferred over sdiv
when both are valid
* Backport of [AArch64] Allow CMP+SHIFT when comparing with zero
* Backport of [AArch64] Allow const0_rtx operand for atomic
compare-exchange patterns
* Backport of [AArch64] Emit tighter strong atomic compare-exchange
loop when comparing against zero
* Backport of [AArch64] Enable -fprefetch-loop-arrays at given
optimization level
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [AArch64] Fix subreg bug in scalar copysign
* Backport of [AArch64] Peephole for SUBS
* Backport of [AArch64] Simplify call, call_value, sibcall,
sibcall_value patterns
* Backport of [AArch64] Update prefetch tuning parameters for qdf24xx.
* Backport of [AArch64] Use SUBS for parallel subtraction and
comparison with immediate
* Backport of [Misc] Add debug counter for loop array prefetching
* Backport of [Misc] Improve debug output of loop data prefetching
* Backport of [Cleanup] [AArch32] Complete legend for ARM register
allocation in arm.h
* Backport of [Cleanup] [AArch32] Fix comment for
cmse_nonsecure_call_clear_caller_saved
* Backport of [Cleanup] [AArch32] Fix typo in comment in arm_expand_prologue
* Backport of [Testsuite] [AArch32] Add MOVT testing for ARMv8-M Baseline
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn250045 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the 2017.08 stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn250045
* Linaro BZ #3040 -- CC1 and cc1plus cannot convert UTF-8: Regenerate
intl configure
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Achievements:
Some progress on Range Thunks. [TCWG-614]
- I have all the enabling patches that allow assignAddresses() to be
run multiple times committed.
- Need review for the actual range thunks implementation itself.
Compiler-rt [TCWG-1156]
- Clang (as opposed to llvm) is assuming that all builtins for ARM are
mandated to have a soft-float interface. I have a tentative patch but
need to test it a bit more first.
- Found out a bit more about the structure of how compiler-rt, and why
it behaves differently when I use the default target and
auto-detection of toolkit as opposed to supplying the target via
options.
-- There is quite a bit of hidden magic and hacks going on in the
default case, some of it I don't think is quite right. For example
Compiler-rt seems to conflate architecture with abi.
Set myself the task of getting compiler-rt tests running on v6-m with
testing on qemu.
- v6-m is the only auto-detected default target that I haven't been
able to reproduce results on.
- A review claimed that tests had been run on qemu, and I'm now trying
to work out how to reproduce this with clang and an arm-none-eabi
sysroot.
-- Not having a lot of luck so far, latest qemu only supports
emulation of 2 cortex-m3 dev-boards and I have yet to make a
standalone program that works [*]
-- I'm not looking forward to plumbing in the options to make the
arm-none-eabi testing work.
[*] I thought I would try semi-hosting first, but it turns out the
default semihosting startup code supplied with arm-none-eabi replaces
my heap and stack locations with a semi-hosting call to get top of
memory which qemu gives an inappropriate result for a dev-board
emulation with non contiguous memory. Would like to see if I can get
this working via a quick experiment to rewrite the start-up code,
although for the full tests I may fall back to retargeting the IO via
an emulated serial port.
Plans:
- First priority is range thunks for lld
- Second priority is getting a v6m test of compiler-rt to check for
any latent problems
- Submit clang patch when I know it works for all the supported platforms
- Look into v7-m support, particularly v7-m + single precision floating point.
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [7/10]
It takes me a lot of time making the patch series v3 work, to address
review comments, to fix regressions, and to make sure each commit
doesn't break build. Almost done.
Looks 30 patches in one series is my limit, and wonder how does other
people manage large patch series.
* Help people runing GDB tests, and get some fails. It turns out we
encounter PR 21555. [1/10]
* Misc, [2/10]
# Plan #
* TCWG-1159
* PR 21555
* TCWG-561,
--
Yao Qi
== This Week ==
* PR78736 (4/10)
- Improved patch to not warn for enums with equal value ranges
- Caused fallouts in libgomp and libgfortran
- Large kernel fallout!
* type promotion (5/10)
- Looking at interference between path-splitting and type-promotion
optimizations
- miscompilation of memcpy-bi.c on
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
== Progress ==
* Infrastructure/validation:
- abe patch for bug #3040 committed, now we need to fix
regression-detection because it builds a toolchain that does not
support this fix (lacks a gcc patch)
- upgrade of dejagnu used for binutils validation fixed the random
errors we were seeing
* Benchmarking:
- production scripts were not up-to-date, but the new ones have a
conflict/dependency on ntp
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch with de-require-stack-check
* misc (conf-calls, meetings, emails, ....)
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- The bot is finally upstream and working well
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP for s32 [7/10]
- Committed support for 32-bit floating point compares, both
hardware and software
* TCWG-1141 - Add "push" capability [1/10]
- Finally committed llvm-push
* Misc [1/10]
- Mailing lists, meetings, buildbots
== Plan ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64
== Activity ==
- Rebased and posted for review all my range-thunks work for LLD as
there had been some interest from some individuals on IRC in trying
out the patch.
-- Seems to work for them
-- Hoped that this might provoke upstream into looking and reviewing
the patches but no such luck.
- Landed the patch that sets _GLOBAL_OFFSET_TABLE_ so that FreeBSD can
link on ARM
- Some other small lld patches
- Investigations into whether an X86 patch might affect CFI generation
for AArch64.
Spent some time banging my head against the compiler-rt build system
to try and see if I can get a cross-compiled build and test run on
Qemu when my compiler-rt target != the default target (i.e. I want to
build clang with ARM and AArch64 targets and cross-build and test all
the ARM compiler-rt targets from that)
- Thwarted by what seems to be inconsistent decisions about
auto-detection of options, what is an architecture, target, sub-target
and abi.
- By passing in all auto-generated options by steam I'm still hitting
some problems with some tests that have an external assembly file.
Found numerous other small inconsistencies that I'll need to write up.
== Plans ==
- Ping the Range Thunks reviews again.
- Compiler-rt
Aim to get to the point where I can write a coherent mail to llvm-dev
explaining what I think is wrong and what I think needs changing.
== Progress ==
o Linaro GCC/Validation (7/10)
* Fixed AArch64 GCC options documentation
ARM part clean-up on-going
* libgomp/mingw patch: Upstream review pending
* pc-relative-literal-loads patch for GCC 6 branch: Upstream review pending
reviewed fxi for trunk.
* Following upstream discussions on stack clash CVE:
- One AArch64 specific commit done (backport in our branch on-going)
- Fix still under discussion upstream, nothing committed yet
* catching-up with re-association work
* libunwind support
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o backports for 2017.07, CVE, ...
== This Week ==
* Type promotion (6/10)
- Created patch to fix ICE with pr81083.c on ppc64
- Investigated mis-compilation of memcpy-bi.c on ppc64
* Malloc propagation (1/10)
- Working on patch based on feedback received.
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Type promotion: Look at miscompilation bug, and investigate
performance regression for path
splitting optimization
- Malloc propagation
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Moved to the public silent master, ready for the final move on
Monday if it's stable until then
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [5/10]
- Most of the functionality is implemented, but I intend to do a lot
of refactoring before committing
* TCWG-1174 - [ARM GlobalISel] Support G_SELECT [1/10]
- Committed upstream
* Misc [3/10]
- Mailing lists, buildbots, discussions
== Plan ==
* Wrap up TCWG-1172
* More GlobalISel
* More code reviews
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/10]
People agree on the direction this patch series goes to! Still
need to polish v3.
Started to write v3 to address comments, split patches, and rebase
patches, etc...
My Cauldron talk "A flexible GDB target
description for processor diversity " is registered.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Decided how to do it, coding.
* Investigate the usage of obstack in GNU toolchain. [1/10]
We recently add a convenient class wrapper for obstack in GDB, and
I think it is better to "upstream" it to inlcude/ so that GCC can use
it as well. Did some archeology on C++ transition in GCC, find some
difficulties. Still good to know some GCC maintainers' preference on
C++.
* Travel, [1/10]
** US EVUS enrollment, to update my US visa information.
** Figure out the Cauldron flight.
* Misc, meeting, [2/10].
# Plan #
* TCWG-1159, patch v3.
--
Yao Qi
== Progress ==
* Infrastructure/validation:
- iterated on patch for bug #3040: 1 abe patch to use libiconv, 1
linaro-gcc-6 patch (partial backport to make enable-nls and libiconv
work together)
* Benchmarking:
- noticed large differences in bench results from one run to another
while looking at "deprecated it block" patch
- trying less aggressive configuration
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch (for arm-neon flags)
* misc (conf-calls, meetings, emails, ....)
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [3/10]
Update patches to address review comments. Commit three patches.
Need to post V3.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Think about the plan.
* Upstream patches review. [3/10]
** Review IBM kernel-awareness patches.
** Review sparc64 adi patch.
** Review Alan's patch on removing MAX_REGISTER_SIZE. Evaluate other
better but expensive approach.
* Misc, [2/10]
Write a STL container allocator which uses stack instead of heap.
Underestimate the complexity of C++. Need to replace some std::vector
with my vector with stack_allocator in GDB. It should be also useful
to Alan.
# Plan #
* TCWG-1159, send v3.
* TCWG-561, Handle unavailable memory during frame unwinding.
--
Yao Qi
[TCWG-614] Range extension thunks
- No progress on upstream reviews from maintainers this week
I have received some interest on IRC and on at least one of the
reviews from other people wanting the feature so I'm hoping that this
may speed up the process.
- I've committed to rebasing and posting the full patch-set for review
so that interested people can take it and test.
PR31159 Tracked down why LLD wasn't correctly linking ARM BSD port
- lld only provides a dummy absolute value for _GLOBAL_OFFSET_TABLE_
- llvm-mc doesn't transform .word _GLOBAL_OFFSET_TABLE_ - . into
R_ARM_BASE_PREL like GNU as does, this relocation doesn't use the
value of _GLOBAL_OFFSET_TABLE_ . Instead we get R_ARM_REL32 which
needs _GLOBAL_OFFSET_TABLE_ to be set correctly. PR335511
- Patch accepted upstream will commit today
Misc:
- lld consultancy for Android
- Help to fix build error on clang for ARM colleague
- Query on lld behaviour with respect to .ARM.extab, I think lld
behaviour is within spec, but it may be producing larger files so
probably enough to argue the case for a small patch.
-No time to spend on compiler-rt this week
Plans:
- Post all the range-thunk patches for the people interested in it.
- Commit patches accepted last week
== Progress ==
* Out of office on Friday [2/10]
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Committed a quick fix and started seeing green builds on this, we
can probably move it upstream soon
* TCWG-836 - Replace D01s by Scaleway boards [2/10]
- Set up a selfhost buildbot on one of the Scaleway boards
- It is very, very slow, I did some performance experiments but
there's probably more that can be attempted here
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- The hard float part is implemented, fiddling with the soft float now
- Forked some of that work into a different story for supporting G_SELECT
* TCWG-1174 - [ARM GlobalISel] Support G_SELECT [1/10]
- In progress
* Misc [2/10]
- Mailing lists, code reviews
- TCWG-1136 - LLVM 4.0.1 - Spun up and uploaded the final release candidate
- TCWG-1177 - Investigate failure on clang-cmake-aarch64-lld -
Bisected and reverted a commit upstream
== Plan ==
* More GlobalISel
* More buildbots
* More code reviews
== Progress ==
o Linaro GCC/Validation (7/10)
* Prepared a fix for libgomp/mingw build issue. Submitted upstream
* Analysed ubuntu bug report on unsupported relocations:
- https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1695093
- Identified it as upstream PR 79041
- Fix submitted upstream
* Following upstream discussions on stack clash CVE
- Releases re-spins will done once the issue will be fixed upstream
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o CVE, on-going patches and infra
== Progress ==
* Infrastructure/validation:
- looking at bug #3040
* Benchmarking:
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported a few regressions
- sent a couple of patches (testsuite, ARM_FEATURE_COPROC)
* misc (conf-calls, meetings, emails, ....)
== Progress ==
o Linaro GCC/Validation (7/10)
* backports and branch merges for linaro branches 5, 6 and 7
* released GCC 6 and 7 2017.06 sources snapshots
* Fxed GCC 5 branch merge
* analyzed various infrastructure instabilities
* Mingw32 libgomp build issue due to configure issue, working on a fix
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o complete GCC 5 sources snapshot
o Fix libgomp problem and continue on re-association
== Progress ==
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- In progress
* TCWG-1168 - [ARM GlobalISel] Support G_ICMP [3/10]
- Done, going to commit upstream
* TCWG-1136 - LLVM 4.0.1 [1/10]
- Spinned up rc3
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [2/10]
- Investigated the timeouts in the test-suite and reported upstream
- Sent a patch to increase the threshold for those tests on AArch64,
waiting for feedback
* TCWG-1166 - Investigate Clang diag-flags.cpp failure [1/10]
- Bisected and reverted upstream
* Misc [1/10]
- Mailing lists, meetings etc
== Plan ==
* Wrap up TCWG-1168 and 1172
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [1/10]
Finish writing the commit log and changelog. Patches are posted.
* TCWG-1167, Test AArch32 GDB on AArch64 Linux kernel. [3/10]
Such configuration shows one regression. It is whether condition
checked failed UDF triggers Undefined Instruction Exception or not.
GDB's assumption is NO, but Peter M. told me that it is implementation
defined, so GDB has to handle both.
* gdb/objdump disassembler unification. Done. [1/10]
Commit the the left over patch.
* Pick up Alan H.'s C++ template patch, and post it again. Learned a
lot on C++ 11 default template parameter and SFINAE. Patch is
committed.
* Upstreams review. [3/10]
** Encourage people to build GDB with CLANG. Resist the objections
from other people, and write the "policy" about using other compilers
to build GDB.
** Review IBM's kernel-awareness v4 patches.
* Misc, [2/10].
# Plan #
Get chance to back to my interrupted works:
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode.
* TCWG-561, Handle unavailable memory during frame unwinding.
--
Yao Qi
== Progress ==
* Infrastructure/validation:
- still some random results, and still ssh connexion problems with
several machines
- improving abe-bisect script
* Benchmarking:
* GCC:
- 'deprecated IT-blocks' patch: looking at the generated code to
understand the regressions
* GCC upstream validation:
- reported a couple of regressions on trunk, a few bisects, helped
validating some ARM patches
- working on further reducing noise ("random" pass/failures)
- include qemu traces in the logs when a testcase aborts, to help debug
* misc (conf-calls, meetings, emails, ....)
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.06
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.1+svn249190 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.08 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.1+svn249190
* Backport of [Bugfix] [AArch32] PR target/71607 Fix ICE when loading constant
* Backport of [Bugfix] [AArch64] PR target/80671
config/aarch64/cortex-a57-fma-steering.c:416: bad statement order
* Backport of [Bugfix] PR tree-optimization/79697 unused realloc(0, n)
not eliminated
* Backport of [Bugfix] PR tree-optimization/80613 ICE in
is_gimple_reg_type with -O2
* Backport of [AArch32] Add a new target hook to compute the frame layout
* Backport of [AArch32] Add fuchsia support to libgcc
* Backport of [AArch32] FreeBSD arm libgcc config.host
* Backport of [AArch32] Model Cortex-A53 load forwarding
* Backport of [AArch64] Accept more addressing modes for PRFM
* Backport of [AArch64] Add aes and sha reservations for Thunderx2t99
* Backport of [AArch64] Add crc reservations for Thunderx2t99
* Backport of [AArch64] Improve float to int moves
* Backport of [AArch64] Set jump alignment to 4 for Cortex cores
* Backport of [AArch64] Tighten move constraints for symbolic operands
* Backport of [Misc] Check the alternate cost model just as costs_lt_p
* Backport of [Misc] Record equivalences for spill registers
* Backport of [Testsuite] [AArch32] Only test
tls-disable-literal-pool.c if target supports native TLS
* Backport of [Testsuite] [AArch32] Replace absolute line numbers in
gcc.target/arm
* Backport of [Testsuite] [AArch64] Replace absolute line numbers in
gcc.target/aarch64
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn249140 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the 2017.08 stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn249140
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
LLD
- Committed refactoring patches to enable long range thunks. This
should unblock progress towards upstreaming patches.
- Rebased and sent out for review first patches in series. Expecting
slow but steady progress as I hope to not need much more large scale
refactoring.
== Plans ==
Compiler-rt
- Investigated cross-compilation and testing via qemu user mode
emulation. It seems to be possible to do so, although fiddly to set up
Plans for this week:
- LLD long range thunks
- Build up a task list for compiler-rt
- Likely take Friday on holiday