== Progress ==
- ldr rt,= implementation transform to MOV committed upstream
[TCWG-468] [PR25722]]
-- Thanks to Renato for committing.
- Started looking at what would be needed to port lld to ARM
-- The ELF lld port looks to have a fairly small amount of
architecture specific hooks. Decided that I would learn fastest by
just trying to do an ARM only prototype port to see if I could get
hello world on linux working.
-- spent too much time trying to think about how to best implement the
group relocations for the PLT sequences then remembered that for a
quick prototype I could use larger sequences that didn't need the
relocations.
== Plan ==
- Continue working on an ARM LLD port. Will hopefully have a good idea
of what the scope of work needed is next week.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.05 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn236106 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.05/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn236106
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.3+svn236108 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn236108
* Backport of [Bugfix] [AArch32] PR target/70711 Fix big-endian ARMv8.1-A builds
* Backport of [Bugfix] [AArch64] PR target/70044 -flto turns on
-fomit-frame-pointer
* Backport of [AArch32] Reduce size of arm1020e automaton
* Backport of [AArch64] Fix SIMD predicate
* Backport of [AArch64] Fix thinko in handling of
-momit-leaf-frame-pointer option
* Backport of [Testsuite] [AArch32] Tests for arm_restrict_it patterns
in thumb2.md
* Backport of [Testsuite] gcc-dg: handle all return values when
shouldfail is set
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 3 days off (Mon/Thu/Fri) [6/10]
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071; found the cause of the bug,
working on a fix.
* Rework LLVM helper scripts [TCWG-571] [1/10]
- Addressed code review comments.
- The interface changes to llvm-projs and llvm-sync are now committed.
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- Come up with a fix for PR24071
* Rework LLVM helper scripts [TCWG-571]
- Investigate git worktree and how it could be factored into our
scripts (llvm-projs, llvm-build)
o 2 days off (4/10)
== Progress ==
o Extended validation (4/10)
* Change extended native job to use multiple scm
* Investigate validation issues when binary tarballs are created
o Linaro GCC (1/10)
* Finalized and submitted new Linaro development branch script.
o Misc (1/10)
* Various meetings and discussions.
== Plan ==
o Create Linaro GCC 6 branches
o Continue on validation and upstream work.
* 2 days off (Thu/Fri)
== Progress ==
* Validation
- restarted validations for pending backports, after the various
branches updates
- started looking at armv8l vs arm results differences
* GCC
- checked trunk regression reports
- updated AArch32 Neon intrinsics tests. Patch series almost ready
for submission
* Misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation
- cleanup
- reviews
- armv8l vs arm
* GCC
- trunk monitoring: check why builds were killed after timeout
- more intrinsics tests
== This Week ==
* LTO (7/10)
a) TCWG-548 (2/10)
- Fixed a minor bug in the patch
- Results of variable partitions with chromium: http://pastebin.com/fLD2JzgP
- Significant difference in size of last partition could probably
indicate sth wrong with
patch (all unpartitioned variables go to last partition).
b) TCWG-528 (3/10)
- Posted upstream after bootstrap+test passed on ppc64le-linux-gnu
- Addressed Richard's comments.
c) TCWG-299 (2/10)
- Firefox built on aarch64 natively (r1-a12) non LTO with gcc-5 branch
- Fails to build with trunk due to issues in firefox codebase (PR70722)
- Fails to build on armhf with following error: http://pastebin.com/9xydVtjj
* TCWG-72 (2/10)
- Rebased patch
- Addressed Ramana's comments
* Misc (1/10)
- Meetings
== This Week ==
- LTO: benchmark section anchors patch, submit patch for
increase_alignment upstream, firefox
- TCWG-72: Test and submit upstream
* Monday off [2/10]
# Progress #
* TCWG-468, ldr rt, =immediate
Have a feature complete implementation. Passes existing regression tests.
Still need to add more tests for new functionality and see if
implementation can be tidied up a bit
* Setting up a local chromebook to run the regression-tests. Should
now be able to run test suite on ARM relatively easily.
# Plan #
* Complete TCWG-468 and send upstream for review.
* Pick something else up.
* Monday off [2/10]
# Progress #
* TCWG-518, arm linux range stepping patches. [5/10]
Tried different ways to manage breakpoints, but the program still
gets SIGILL from time to time. Post my WIP patches upstream to see
if people have some ideas on this.
* TCWG-547, [1/10].
Try two approaches but give up due to the quite aggressive interface
changes. Fortunately, the change in the third approach is quite
small, testing the patch.
* Misc, meeting, [2/10]
# Plan #
* TCWG-518, TCWG-547
--
Yao
== Progress ==
* GCC Stage-1 (5/10)
- Posted patches and revised based on review
- PR40921 and PR63586
- Getting ready post type promotion pass again
* Linaro bug (2/10)
- BUG 2195 and BIG 1979
- Investigation with trunk and educed test case shows Missing commit
* Misc (1/10)
- GCC Lists
* Public holiday (2/10)
== Plan ==
* Attend to pending stage1 patches
o 1 day off (2/10)
== Progress ==
o Extended validation (2/10)
* Extended validation now operational,
reporting enhancements investigations.
* Looked at gdb/guality unstable results.
* Reviewed some jobs.
o Linaro GCC (2/10)
* Scripted new Linaro development branch process.
o Upstream GCC (1/10)
* Digging in libatomic code.
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o 2 days off (Thu/Fri)
o Continue on validation and upstream work.
== This Week ==
* LTO (6/10)
a) TCWG-128 (1/10)
- committed patch for adding param lto-max-partition, which
can now be used as workaround for building chromium with minimal
number of required partitions.
- committed patch for setting default value of lto-min-partition to 10000.
b) TCWG-528 (1/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch_increase_alignment.diff
- Cross tested on arm*-*-*, aarch64*-*-* and bootstrapped and tested
on aarch64-linux-gnu
- I want to cross test once for ppc64 since that's also affected.
c) TCWG-548 (4/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch-vars-3.diff
- Cross tested for arm*-*-* and aarch64*-*-*
* TCWG-319 (2/10)
- Comparing diff's of vect for arm and armeb shows, armeb not
supporting unaligned access
- Looking thru arm backend code to see why this happens.
* Validation (1/10)
- Script to build chromium
* Misc (1/10)
- Looked at PR70848, PR60172
- Meetings
== Next Week ==
LTO: section anchors, increase_alignment pass
TCWG-319: Continue investigation
Validation: Try to get the script merged to tcwg-buildapp repo.
# Progress #
* TCWG-466, ADRL pseudo instruction support in integrated assembler. I
couldn't find a way of putting ADRL into the assembler in a
maintainable way. Managed to work out a pretty close approximation of
ADRL in a macro so I added it to upstream PR. Put the results of the
my investigations into TCWG-466. Agreed with Renato's initial
diagnosis of won't fix.
* TCWG-468, Transform LDR rn, =expr pseudo instruction into MOV. I'm
more hopeful with this one. I've got a prototype that delays the
emission of the constant pool entry to a point where the
transformation can occur.
* Try out the build and push scripts. Had a frustrating day of chasing
down missing dependencies from my Ubuntu 12.04 machine while building
lldb. Should be resolved now.
# Plan #
* UK national holiday on Monday.
* Continue with TCWG-468. I've got a tablegen prototype that treats
LDR rd,= as a real pseudo instruction. Need to finish Thumb and
Thumb2. Next step after that is to do the transformation to MOV.
* Will spend any other time investigating LLD
# Progress #
* TCWG-518, range stepping on arm-linux. Rebase my patches, and choose
a different approach which is better. However, GDBserver crashes in
some cases, and I am investigating the crash. [5/10]
* TCWG-547, make some progress on the upstream discussion. We agree to
do it in a cleaner way but some GDB internal interface needs some
changes. [2/10]
* Read some articles about exception handling, this one is quite useful,
https://gcc.gnu.org/ml/gcc/2002-07/msg00391.html [1/10]
* Meeting, upstream patch review. [2/10]
# Plan #
* TCWG-518, TCWG-547
--
Yao
== Progress ==
* Rework LLVM helper scripts [TCWG-571] [4/10]
- Code review + minor improvements to the scripts
- Started a discussion about the interfaces of some of the scripts
(llvm-projs, llvm-sync)
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071
- Discovered that the assert is only triggered for
aarch64-linux-gnueabi, whereas arm-linux-gnueabi behaves as expected
(prints the error but doesn't assert afterwards). This has proven
useful for figuring out the intended behavior of the code.
* Move buildbots to CMake 3.4.3 [TCWG-573] [1/10]
- Helped move some of the bots (llvm-a15-*) to CMake 3.4.3
* Misc [2/10]
- Buildbot monitoring
- Meetings
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- Come up with a fix for PR24071
* Rework LLVM helper scripts [TCWG-571]
- Start a review for the new interface to llvm-projs/llvm-sync, so
we can have some concrete support for further discussion
- Investigate git worktree and how it could be factored into our
scripts (llvm-projs, llvm-build)
* Move buildbots to CMake 3.4.3 [TCWG-573]
- Help with the llvm-chrome-* bots if necessary
* OOO on Monday
== Progress ==
* Validation
- armvl8 differences between master and stable branches understood
(master defaulted to Thumb)
- updated ABE stable branch for validation
- ABE now uses linaro-local/stable DejaGnu branch
- updated ABE legacy version to use this DJ branch too, and updated
the Foundation Model path
- updated Jenkins jobs accordingly
* Backports
- created a few backports for our gcc-5 branch, to prepare handover
- slight documentation update
* GCC
- enhancements to validation harnesses to better handle
infrastructure problems
- using monitoring and regressions reports
* Cortex-strings
- updated a few aarch64 mem* routines from newlib versions
* Support
- finally reproduced the Windows-hosted toolchain bugs
by rebuilding in a properly updated Jessie chroot.
- building the next release in Trusty container should fix
these problems
* Misc (confi-calls, meetings, emails, ....)
== Next ==
* Validation: cleanup & reviews
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
As a note, all the builders we use for binary releases run Trusty still. I haven't tried Jessie (should work fine),but I know that newer Mingw releases fail to compile GCC 5.x.
- rob -
-------- Original message --------
From: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: 04/22/2016 14:00 (GMT-07:00)
To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
Subject: [ACTIVITY] 18-22 April 2016
* 3 days off
== Progress ==
* Validation:
- fixed ABE master and stable branches to use 'ssh -t' instead of
'ssh -tt' when cross-testing
- trying to assert master vs stable before the array branch merge,
noticed differences on armv8l
- created linaro-local/stable Dejagnu branch (currently a copy of
master). Prepared ABE config patches to use it.
* GCC
- infrastructure problems (ST compute farm), leading to a lot of
noise in the validations (and wrong regression reports upstream)
- enabled gcc-6-branch monitoring
- added GCC-6 tab to the backports spreadsheet
* Support
- Windows-hosted toolchain crashes: it seems the builders we use to
make the release run Jessie and not Trusty. Tried to rebuild a
toolchain in a Jessie chroot, but the script failed (works under
Trusty)
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation
- check that using linaro-local/stable Dejagnu branch works well
- create validation reference points before array branch merge
- understand/fix armv8l validation differences between master/stable
ABE branches
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
* Support
- Windows-hosted toolchain bug
* Snapshots
- prepare a few backports for our gcc-5 branch
* Cortex-strings update
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Failures reduced to 15 fails and 4 errors after fixing stepping bug.
-- Investigated remaining issues some of them are known issues and
others will need further investigation.
LLDB ARM Thread Stepping Problem [TCWG-566] [5/10]
-- Problems caused because incorrect reporting of PLT entry size set by linker.
-- Submitted a fix after analysis that logical size of PLT entry
should be greater than 4bytes.
-- Fix accepted and committed upstream.
LLDB Buildbot Setup [TCWG-241] [1/10]
-- Random change in results finally caught. It was due to inconsistent network.
-- Progress halted to fix arm-linux-gnueabihf bugs.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB Chromebook Test Stability [TCWG-563]
-- Continue to resolve and investigate chromebook test failures.
LLDB Buildbot Setup [TCWG-241]
-- Start AArch64 tester evaluations.
Progress:
- On holiday all week, at ACCU conference. I've put some highlights at
the end of the message.
- Did some more investigation into TCWG-466 ADRL support in integrated
assembler during breaks.
-- Not looking good, to do this properly bumps up against a lot of
design decisions and restrictions made by the LLVM assembler (designed
as compiler target, not to be user friendly).
-- There are ways it could be implemented with restrictions, but it is
debateable whether it is worth doing at all.
-- On the plus side I've got a much better idea of how the assembler
works and what restrictions exist on each stage of the journey from a
line in the .s file to emission in the object. Will add some comments
to the LDR r0, =expr TCWG as well.
-- On the negative side the :upper16: and :lower16: operators for MOVT
and MOVW don't look to be correct in the presence of addends. Will
need to investigate further to see what the scope of the problem is.
Plan:
- Dump results of TCWG-466 investigation into Jira.
- Take a look at and post a comment on Adhemerval's revised TLS patch,
even if it is just looks fine in the hope of pushing it forward a bit
more.
- Catch up with Renato's scripts and documents for LLVM sub-group.
- Work out what to do with TCWG-466, if the answer is put it down,
find something else to look at.
ACCU Highlights/Report:
Tough stuff in modern C++
A deep dive into some of the newer areas of C++ such as:
- rvalue references and forwarding (universal) references
- How to use SFINAE (mostly std::enable_if) to select algorithms
optimised for particular template instantiations
- Variadic templates. Including all sorts of strange ways to (ab)use
expansion of parameter packs.
C++ WG21 SG14 Gaming and low-latency study group
- A new study group aiming to represent the gaming (primarily), but
also embedded and high frequency trading concerns.
- Motto seemed to be make sure "Don't pay for what you don't use" is enforced.
Most interested in:
-- No exceptions configurations
-- No RTTI
-- More performance out of the STL (see EA STL
https://github.com/electronicarts/EASTL)
-- Add ring buffers and support for unitialised memory, fixed point
numbers, flat-map, standardised simd vector types
Using sentinels
- An example of how using two sentinels in an implementation of
std::partion speeds up the algorithm by saving comparisons. Can speed
up quicksort by a few percent
Constexpr in C++14
- Example showing how you could build a string to enum map, operating
entirely at compile time, and its subsequent negative effects on
compile time!
Concepts Lite
- Concepts missed the C++17 standard, this presentation went into the
current Technical Standard (optional) and how concepts would likely be
implemented in C++(20?)
- Not surprising to see that concepts still missed C++17 as there is
only one implementation and one non-trivial use case (ranges) and
there are still unresolved questions to be answered.
Introduction to Julia
- Really a comparison of Julia to the author's favoured language of common lisp.
- Was impressed at how "lispy" Julia was whilst retaining high performance.
- Liked the mathematical syntax
- Didn't like the python like parts that seemed to be added to try and
get people to migrate from python, but were non "lispy".
# Progress #
* TCWG-545, patches are committed. Done. [3/10]
* TCWG-167, ARM reverse debugging bug fixes. All test fails are
fixed. Done. [2/10].
* PR 19947. The fix is approved, but the patch triggering the bug
needs update. [2/10]
* Help to fix broken ARM GDB after C++ switch. [2/10].
GDB mainline is a C++ program in default. Exception
handling in GDB is broken on non-x86 host (ARM, AArch64, AIX, at
least) because readline (C library) calls C++ GDB code, but exception
unwinding can't cross the C function ("foreign frame"). The problem
is fixed by catching all exceptions before return to readline, and
re-throw them after return from readline back to GDB.
* Misc, [1/10]
** Hack QEMU so that I can run gdb regression testsuite with qemu-arm.
# Plan #
* TCWG-518, rebase patches on mainline, test, and post patches if
nothing wrong.
* PR 19947, TCWG-561,
* TCWG-547
--
Yao
== Progress ==
o Extended validation (5/10)
* Created new extend validation job which handles native/cross
validation and benchmarking.
* Identified and discussed dejagnu Linaro branch issue.
o Upstream GCC (2/10)
* Start to look at libatomic ARMv8.1 support
o Misc (3/10)
* Various meetings
* Support team members on benchmarking and validation.
== Plan ==
o Continue on extended validation and Libatomic
== This Week ==
* LTO (5/10)
a) Section anchors
- another wasted prototype: http://pastebin.com/5MXFqrZY
- will follow Richard's suggestion to put variable in partition that
references it most, we can make this smarter incrementally if required.
b) Retested patch for lto-max-partition
c) Retested increase_alignment pass patch and wrote test cases for it.
* Validation (2/10)
a) Script to build chromium
- works with armhf (with assumptions about my environment)
- issues with gclient sync failure which in turn does not generate
LASTCHANGE file causing
build to fail.
* Public Holiday (2/10)
- Mahavir Jayanti
* Misc (1/10)
- Meetings
== Next Week ==
- LTO: section anchors, post patches upstream for lto-max-partition
and increase_alignment.
- TCWG-319: Look at why armeb is failing to vectorize test-cases.
- Validation: chromium
== This week ==
* Bugzilla 67321 - [ARM] Exploit Wide Add operations when appropriate (1)
- Re-based to GCC 6, re-validated and committed upstream
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (1)
- Re-based and re-validated
- Need to create new bug as problem description does not match issue
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store (3/10)
- Developed new patch for arm that detects failures with negative numbers
- Debugging failures where constant is too large
* TCWG-247 - Create Validation Job to run on GCC Trunk Commit (3/10)
- Fleshed out additional portions of script and submitted for code review
- Still issues to be resolved in script as noted in git review
* Misc (2/10)
- Meetings
- Multiple interactions with ARM IT to configure and setup new laptop
== Next week ==
* TCWG-247
- Finish script
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store
- Finalize arm patch and validate
* Bugzilla 70008 - create new bug and submit upstream patch
* 3 days off
== Progress ==
* Validation:
- fixed ABE master and stable branches to use 'ssh -t' instead of
'ssh -tt' when cross-testing
- trying to assert master vs stable before the array branch merge,
noticed differences on armv8l
- created linaro-local/stable Dejagnu branch (currently a copy of
master). Prepared ABE config patches to use it.
* GCC
- infrastructure problems (ST compute farm), leading to a lot of
noise in the validations (and wrong regression reports upstream)
- enabled gcc-6-branch monitoring
- added GCC-6 tab to the backports spreadsheet
* Support
- Windows-hosted toolchain crashes: it seems the builders we use to
make the release run Jessie and not Trusty. Tried to rebuild a
toolchain in a Jessie chroot, but the script failed (works under
Trusty)
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation
- check that using linaro-local/stable Dejagnu branch works well
- create validation reference points before array branch merge
- understand/fix armv8l validation differences between master/stable
ABE branches
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
* Support
- Windows-hosted toolchain bug
* Snapshots
- prepare a few backports for our gcc-5 branch
* Cortex-strings update
== Progress ==
* Inline assembly constraints support for ARM [TCWG-560] [1/10]
- Started investigating Bug24071
* Intro to LLVM buildbots [1/10]
- Got accustomed to the buildbot monitoring page
- Learned how to connect to the bots/perform really basic maintenance
* Misc [8/10]
- Onboarding checklists, policies, meetings etc [6/10]
- Laptop setup [2/10]
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- More investigations for Bug24071
* Misc
- Finish reading Octopus policies
- Review scripts for working with LLVM
Hi All,
I don't whether this is the right community mailing list to post
support or not. Please correct me if i am wrong.
I am trying to cross compile gcc to ARM as static binaries and as part
of this, i am facing below issue. My build system is Ubuntu and using
[1] gcc branch. Let me know what i can share more information to you.
arm-linux-gnueabi-g++ -static -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE
-fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
-Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute
-pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings
-DHAVE_CONFIG_H -static-libstdc++ -static-libgcc -static -pthread -o
xgcc gcc.o ggc-none.o \
c/gccspec.o libcommon-target.a \
libcommon.a ../libcpp/libcpp.a
../libbacktrace/.libs/libbacktrace.a ../libiberty/libiberty.a
../libdecnumber/libdecnumber.a
gcc.o:(.rodata+0x5acc): undefined reference to
`host_detect_local_cpu(int, char const**)'
collect2: error: ld returned 1 exit status
make[2]: *** [xgcc] Error 1
[1] svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch
--
Thanks & Regards,
M.Srikanth Kumar.
== Progress ==
LLDB Buildbot Setup [TCWG-241] [1/10]
-- Created a new factory for LLDB buildbots. Halted plan to migrate
till turning chromebook build green.
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Investigated some failures some of them were fixed by a systemZ
support large patch set.
-- Failures reduced to 36 locally with some tweaks. Buildbot still
showing random results.
LLDB ARM Thread Stepping Problem [TCWG-566] [5/10]
-- Only happening on Arm linux targets.
-- Spent good bit of time debugging this issue. There are multiple
problems but root cause is same.
-- Initial investigation reveals frame unwinding issues from .plt section.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB ARM Thread Stepping Problem [TCWG-566]
-- Further debugging and investigation of this issue.
-- Figure out a fix for stepping problem on arm linux.
== Progress ==
o GCC 2016.04 source snapshot (4/10)
* Reviewed on-going backports
* Merged from FSF GCC 5 branch
* Packaged and released snaphot
o Extended validation (3/10)
* Native validation identifies upstream issues
- Fixed Glibc warnings raised by GCC 6, committed in Glibc master
* Looking at bkk16 job switch to multijob..
o Misc (3/10)
* Various meetings
== Plan ==
o Continue on extended validation
o GCC ARMv8.1 builtins fix.
== This week ==
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store (1/10)
- Arm backend is not recognizing that some constants can be encoded
using modified immediate
- This is causing constant to be split and additional code generated
- Range of constants allowed differs between Arm and Thumb2
- Created prototype patch to allow additional ARM modified immediate
instructions
- Began work on Thumb2 patch
* TCWG-247 - Create Validation Job to run on GCC Trunk Commit (2/10)
- Developed shell portion of script to read and parse web page with
builder information
- Developing rest of yaml script including trigger on specified interval
* Misc meeting (1/10)
* Vacation (6/10)
- April 11 - 13
== Next week ==
* TCWG-247
- Finish script
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store
- Finalize arm patch and validate
- Make progress on Thumb2 patch
== Progress ==
* Support (2/10)
- Closing some inline asm constraint bugs that were fixed or user error
- Finished PR16275
* Background (8/10)
- Code review, meetings, discussions, general support, etc.
- Lost track of how many meetings and email threads I had
- Mostly about helping newcomers, managing Android/LLDB/LLD expectations
- Also hardware planning, LLVMLinux revival, checking Swift
Progress:
- Read up on AARCH64 TLS and LLD code base
- Commented on upstream patch in hope of getting approval from the code-owners
- TCWG-466 Implement ADRL pseudo in LLVM assembler
-- Slow progress as the pseudo instruction does not fit well into the
existing architecture
-- On the positive side I have learned quite a bit about how the LLVM
assembler works
-- Will make a decision next week whether it is worth actively
pursuing TCWG-466. Supporting ADRL is not high priority and whatever
fix I come up with may be difficult to get accepted upstream. I'd
still like to keep trying, at least as a background task, but I think
that there is higher priority work that can be done instead.
Next Week:
On holiday (hopefully added correctly to Linaro google calendar). I'll
be at the ACCU conference.
== Progress ==
* Validation
- finally identified what caused several random results: use of 'ssh
-tt' to acces the remote tester. I don't know the real cause.
* GCC
- reported a few regressions in trunk
- a few backports
- AdvSIMD intrinsics tests: built the list of AArch64 intrinsics not
yet covered
- support on a few bug reports
* Misc (conf-calls, meetings, emails, ....)
== Next ==
* Holidays Mon/Tue/Wed
* Validation
- consolidation on stdout/stderr problems
- extended validation
* GCC:
- trunk monitoring, report regressions if needed
- start monitoring the just-created gcc-6 branch
- more intrinsics tests
- switch backport activity to gcc-6 branch, update tools, etc...
# Progress #
* TCWG-545, 7 patches are approved, and 1 patch needs update, which
needs the change somewhere else. [3/10]
* TCWG-547, patch is pending. Pinged Pedro on IRC, to be reviewed, but
no response.
* TCWG-167, [3/10]. ARM reverse debugging fixes. Post one patch to fix
test case. Testing another patch to give high priority of epilogue
unwinder.
* Upstream patch review, [2/10]. Spend more time on this due to long
patch review backlog. The more I reviewed, the sooner my patches will
be reviewed by others.
* Misc, [2/10]
** Look at the slowness of gdb regression test in jekins validation, but
can't reproduce it.
** Share some knowledge of watchpoint implementation in GDB to the
people, who need the equivalent or similar things in LLDB.
# Plan #
* TCWG-545, TCWG-547, TCWG-167.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.04 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn234898 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn234898
* Backport of [Bugfix] [AArch32] Fix PR target/70496
* Backport of [Bugfix] [AArch32] PR driver/70132: Avoid double fclose
in driver-arm.c
* Backport of [Bugfix] [AArch32] PR rtl-optimization/69904: Disallow
copying/duplicating of load-exclusive operations
* Backport of [Bugfix] [AArch32] PR target/62254 Fix for ARMv3
* Backport of [Bugfix] [AArch32] PR target/69614
* Backport of [Bugfix] [AArch32] PR target/70566 Check that condition
register is dead in tst-imm -> lsls-imm Thumb2 peepholes
* Backport of [Bugfix] [AArch32] PR testsuite/70553
* Backport of [Bugfix] [AArch64] PR rtl-optimization/70398 LRA
* Backport of [Bugfix] PR 69400: Invalid 128-bit modulus result
* Backport of [Bugfix] PR middle-end/70370
* Backport of [AArch32] 1/2 Cortex-R8 support
* Backport of [AArch32] Add initial support for the Cortex-A32
* Backport of [AArch32] Add support for Cortex-A35
* Backport of [AArch32] Delete ASM_OUTPUT_DEF and fall back to default
.set directive
* Backport of [AArch64] 1/3 Enable CRC by default for armv8.1-a
* Backport of [AArch64] 2/3 Rework the code to print extension strings (pr70133)
* Backport of [AArch64] 3/3 Fix up for pr70133
* Backport of [AArch64] [ACLE][NEON] Implement vcvt*_s64_f64 and
vcvt*_u64_f64 NEON intrinsics
* Backport of [AArch64] Add extra tuning parameters for target processors
* Backport of [AArch64] Add support for Cortex-A35
* Backport of [AArch64] Only update assembler .arch directive when necessary
* Backport of [Testsuite] [AArch32] 2/2 Cortex-R8 support
* Backport of [Testsuite] [AArch64] PR target/70113 fix pr63304_1 testcase
* Backport of [Testsuite] [AArch64] Skip
gcc.target/aarch64/assembler_arch_1.c if assembler does not support it
* Backport of [Testsuite] Avoid GDB being blocked on signals
* Backport of [Testsuite] Fix testsuite for Cortex-R8 support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
== Progress ==
* Type promotion pass (2/10)
- Benchmarking
* LTO (7/10)
- Refactoring tree-vrp to share common parts
- Looking at open enhancement bugzilla and working on them
* Misc (1/10)
- GCC Lists
== Plan ==
* LTO and VRP
== Progress ==
LLDB Buildbot Setup [TCWG-241] [9/10]
-- Migration of local master/slave setup to Linaro LLVM lab.
-- Setup slave to be able to connect to chromebook for lldb remote testing.
-- Modified Android build scripts to work with chromebook in llvm lab.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB Buildbot Setup [TCWG-241]
-- Write a new factory for linux based lldb script commands
-- Break down and tweak scripts with better logical steps.
-- Migrate current setup to use new factory.
LLDB development [TCWG-563]
-- Look into failing tests on chromebook tester and see if some of
them can be fixed.
== Progress ==
o Extended validation (5/10)
* Dejagnu remote layout patch finalized and committed upstream
(will be part of the coming 1.6 Dejagnu release)
* GCC guality test fix committed in trunk.
* Native armv8l validation unblocked, but still slow (more than 8hrs)
Analysis on-going.
* Start to work on enhancement:
include cross validation and benchmark trigger.
o Misc (5/10)
* Lot of meetings (Internal, training, Benchmarking, ...)
== Plan ==
o Monthly snaphsot (review backports, branch merge)
o Continue on extended validation
o GCC ARMv8.1 builtins fix.
== Progress ==
Transition week into Linaro toolchain group from ARM to replace Bernie [*]
- Some ARM handover work done.
- Started looking into https://llvm.org/bugs/show_bug.cgi?id=24350 (TCWG-466
ADRL support)
-- Checked behaviour of ADRL on armasm and GNU as
-- Worked out what I need to do in LLVM to make ADRL work, looks like
nothing hugely complicated but a lot of plumbing through various layers.
- Started reading about AArch64 TLS descriptor implementation. I'm familiar
with the AArch32 traditional model so I need to bridge the gap a bit.
== Plans ==
- Post some review comments on Adhemeval's TLS patch with the hope of
unblocking it.
- Start implementing support for ADRL in the integrated assembler
== Planned Absences ==
Holiday 18th - 22nd April (Attending ACCU conference in Bristol). I think
I've put that in the shared holiday calendar correctly.
[*] Hello to everyone I didn't manage to meet at Linaro Connect. I've been
working in ARM's proprietary compiler team, with much of that time spent on
armlink and the other non-compiler tools.
# Progress #
* TCWG-167, ARM reverse debugging bug fixes. [4/10]
Four patches are committed. All FAILs are fixed if test case is
compiled with -fomit-frame-pointer. Some FAILs when
-fno-omit-frame-pointer are caused by epilogue unwinder doesn't parse
epilogue correctly if FP is involved. File TCWG-562 to track it.
* TCWG-545, TCWG-547, patches are pending. Maintainer is busy on
something else.
* Triage the regression gdb.base/jit.exp. [1/10]
We need a pending patch series to address this issue. Ask Pedro how
to review them.
* TCWG-561, handle unavailable memory during frame unwinding. [3/10]
Think about it and write a prototype.
* Misc, patches review and meeting, [2/10].
# Plan #
* Take a look at the slow native arm-linux-gnueabihf gdb test.
* TCWG-562, Tweak epilogue unwinder to handle FP.
* TCWG-545, TCWG-547, ping.
* TCWG-561, finish the prototype.
--
Yao
My dear friends,
I'm trying to build C++ code for Linux running on am ARM Cortex A8 (TI
AM335x). For a first try, I'm using the simplest program I can think of:
/* main.cpp */
int main() {
return 0;
}
Under Linux with the 'normal' GCC, that works fine, but under Windows 7
with the Linaro toolchain, it fails with the following message:
C:\firedect\dev\workspace\Test-Linux-ARM_1> "\Program Files (x86)\GNU
Tools ARM Embedded\gcc-linaro-4.9-2016.02-i686-ming
w32_arm-linux-gnueabi\bin\arm-linux-gnueabi-g++.exe" main.cpp
c:/program files (x86)/gnu tools arm
embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/bin/ld.exe:c:/program
files (x86)/gnu tools arm
embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/lib/libstdc++.so:
file format not recognized; treating as linker script
c:/program files (x86)/gnu tools arm
embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/bin/ld.exe:c:/program
files (x86)/gnu tools arm
embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/lib/libstdc++.so:1:
syntax error
collect2.exe: error: ld returned 1 exit status
C:\firedect\dev\workspace\Test-Linux-ARM_1> "\Program Files (x86)\GNU
Tools ARM Embedded\gcc-linaro-5.3-2016.02-i686-ming
w32_arm-linux-gnueabihf\bin\arm-linux-gnueabihf-g++.exe" main.cpp
c:/program files (x86)/gnu tools arm
embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/bin/ld.exe:c:/program
files (x86)/gnu tools arm
embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/lib/libstdc++.so:
file format not recognized; treating as linker script
c:/program files (x86)/gnu tools arm
embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/bin/ld.exe:c:/program
files (x86)/gnu tools arm
embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/lib/libstdc++.so:1:
syntax error
collect2.exe: error: ld returned 1 exit status
As you can see, I have tested two versions of the toolchain, which show
the same behavior.
Do you have any idea what's going wrong here? I'd appreciate any help
you can provide!
--
Kind regards,
Gunnar Arndt
Hi list,
I hit another weird problem after use gcc 5.3 (If I use gcc 4.9, there is no any
issue) with android.
With arm gcc 5.3, the C++ apps crash in one class constructor call. And gdb
shows some vtbl items of the class are not relocated.
With arm gcc 4.9, if set breakpoint in that constructor, we could see the vtbl
items of the class are relocated.
And Yes. I know the android bionic loader take response to do relocation. But if
it works with gcc 4.9, I suppose bionic loader work well (unless gcc 5.3 create
some new situation not handled by it).
I attached the vtbl dump in gdb for gcc 5.3 and 4.9 both. We could see all valid
entries in vtbl are relocated in 4.9 dump. But not all entries in vtbl are
relocated in 5.3 dump (the address is not started with 0xf).
Suggestions/hints are welcome. Thanks a lot.
Regards
Yin, Fengwei
On Thu, Mar 31, 2016 at 5:12 AM, fengwei.yin <fengwei.yin(a)linaro.org> wrote:
> Because gcc 4.9 could build this file without any issue, I apply
> --save-temps
> with gcc 4.9. The ii file is attached. Can't see significant differences.
There is a patch in gcc-5 to make unified assembler syntax the
default. Unfortunately, it changes how extended asms work, which is
perhaps a bug. The message claims it doesn't affect extended asms,
but it does.
https://gcc.gnu.org/ml/gcc-patches/2015-11/msg01196.html
The interesting bit is the change to ASM_APP_OFF.
gcc-4.9 emits a .thumb after the extended asm to switch back into
thumb mode just in case. gcc-5.3 instead emits .syntax unified, which
doesn't change the arm/thumb mode, just the syntax supported. This is
arguably a bug, but this doesn't immediately help you. It could take
a little time to get gcc-5.x source fixed, and then the compiler
binary releases. Or alternatively we could fix the asm to work with
gcc 5.
Jim
== Progress ==
o Extended validation (7/10)
* Fixed and improved extended native validation
* Discussed proposed patch in dejagnu on process killing mechanism
* Testing a fix/workaround in GCC guality tests
* Re-implemented and tested fix for dejagnu remote layout
o Misc (3/10)
* Various meetings
== Plan ==
o Continue on extended validation
o Finalize DejaGNU patches, GCC ARMv8.1 builtins fix.
== This week ==
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Additional investigation and preliminary implementation
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store (1/10)
- Investigation
* TCWG-247 - Create Validation Job to run on GCC Trunk Committ (5/10)
- Began writing shell script.
* Misc meeting (1/10)
== Next week ==
* TCWG-247
- Make additional prgoress on prototype
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM)
- Additional investigation and preliminary implementation
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store
- Investigation
* Vacation
- April 8 - April 12
== Progress ==
* Holiday (2/10)
* Support (1/10)
- Reapplying fix for PR16275 (D18701)
- Conclusion is that original approach will be the same as GCC
- Additional flags will have to be agreed upon across compilers
* Buildbot (2/10)
- Setting up LLDB buildbot with Omair
- Precarious infrastructure is unstable, hope it holds on until the
new rack is complete
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- More team management stuff (access/procedure/meeting with newcomers)
- Planning the lab move, resources, costs, schedule
* Monday off [2/10]
# Progress #
* TCWG-167, ARM reverse debugging bug fixes. [4/10]
Two patches are posted. Two patches are being tested. They fix
207 FAILs (242 -> 35) in gdb.reverse.
* TCWG-545, no progress, patches are pending for review.
* TCWG-547, [2/10]. Write a patch as Pedro suggested, so we have
sense which patch is better. No response.
* Misc, [2/10]
** Upstream discussions on get syscall number on execve exit. Can't
get such thing from kernel side, need to figure out how to do it
in GDB side.
** Investigate a little bit on 32-bit DWARF on AArch64.
# Plan #
* TCWG-167, TCWG-545, TCWG-547
--
Yao
== This Week ==
* LTO (7/10)
a) TCWG-534 (ipa-comdats):
- Patch posted upstream: https://gcc.gnu.org/ml/gcc/2016-03/msg00254.html
- Investigating ICE with patch for comdat-2.C
b) TCWG-128 (branch out of range error):
- Posted patch upstream:
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00032.html
c) intra-procedural vrp:
- Looking to implement replacement_order algorithm for early vrp from the paper:
https://engineering.purdue.edu/paramnt/publications/1381.pdf
* Validation (2/10)
- Reviews on tcwg-buildapp from Christophe and Maxim
- prototype job ran successfully.
* Misc (1/10)
- Meetings
== Next Week ==
* LTO:
- Try to implement replacement order algorithm for vrp
- Continue investigating ipa-comdats ICE and address upstream comments.
- Gather stats for chromium LTO build
* Validation:
- write script to build chromium
On Wed, Mar 30, 2016 at 6:26 PM, fengwei.yin <fengwei.yin(a)linaro.org> wrote:
> Thanks a lot for your quick response. The .ii file was attached.
In UnwindFromContext, there is an asm that forces the assembler into ARM mode.
if (ucontext == nullptr) {
int ret = (({ unw_tdep_context_t *unw_ctx = (&context_); register unsigned \
long *unw_base asm ("r0") = unw_ctx->regs; __asm__ __volatile__ ( ".align 2\nbx\
pc\nnop\n.code 32\n" "stmia %[base], {r0-r15}\n" "orr %[base], pc, #1\nbx %[ba\
se]" : [base] "+r" (unw_base) : : "memory", "cc"); }), 0);
The ".code 32" puts us in ARM mode.
GCC still thinks that we are in thumb mode though, and continues to
emit thumb instructions, some of which have no arm mode equivalent,
e.g. cbnz and cbz.
I don't see any convenient push/pop for thumb/arm mode. This is
probably a macro expanded into the asm. You could have two versions
of the asm, one that gets used when __thumb__ is defined and one that
gets used when __thumb__ is not defined. The __thumb__ version would
switch back into thumb mode at the end with a ".thumb" pseudo-op.
Or alternatively, don't build with -mthumb.
Jim
Hi folks,
I am trying to use arm gcc 5.3 to build part of android AOSP and hit
following issue with arm gcc 5.3:
The gcc cmd line is like:
/opt/work/acadine/mem_shrink/B2G-v2.5/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-5.3-linaro/bin/arm-linux-androideabi-g++
-I external/libcxx/include -I system/core/libbacktrace -I
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates
-I
out/target/product/linaro_arm/gen/SHARED_LIBRARIES/libbacktrace_intermediates
-I libnativehelper/include/nativehelper -I system/core/base/include -I
external/libunwind/include -isystem system/core/include -isystem
system/media/audio/include -isystem hardware/libhardware/include
-isystem hardware/libhardware_legacy/include -isystem
hardware/ril/include -isystem libnativehelper/include -isystem
frameworks/native/include -isystem frameworks/native/opengl/include
-isystem frameworks/av/include -isystem frameworks/base/include -isystem
out/target/product/linaro_arm/obj/include -isystem
bionic/libc/arch-arm/include -isystem bionic/libc/include -isystem
bionic/libc/kernel/uapi -isystem bionic/libc/kernel/uapi/asm-arm
-isystem bionic/libm/include -isystem bionic/libm/include/arm -c
-fno-exceptions -Wno-multichar -msoft-float -ffunction-sections
-fdata-sections -funwind-tables -fstack-protector -Wa,--noexecstack
-Werror=format-security -D_FORTIFY_SOURCE=2 -fno-short-enums
-no-canonical-prefixes -fno-canonical-system-headers -march=armv7-a
-mfloat-abi=softfp -mfpu=vfpv3-d16 -include
build/core/combo/include/arch/linux-arm/AndroidConfig.h -I
build/core/combo/include/arch/linux-arm/ -Wno-psabi -mthumb-interwork
-DANDROID -fmessage-length=0 -W -Wall -Wno-unused -Winit-self
-Wpointer-arith -Werror=return-type -Werror=non-virtual-dtor
-Werror=address -Werror=sequence-point -DNDEBUG -g -Wstrict-aliasing=2
-fgcse-after-reload -frerun-cse-after-loop -frename-registers -DNDEBUG
-UDEBUG -fvisibility-inlines-hidden -DANDROID -fmessage-length=0 -W
-Wall -Wno-unused -Winit-self -Wpointer-arith -Wsign-promo -std=gnu++11
-Werror=return-type -Werror=non-virtual-dtor -Werror=address
-Werror=sequence-point -DNDEBUG -UDEBUG -mthumb -Os -fomit-frame-pointer
-fno-strict-aliasing -fno-rtti -Wall -Werror -fPIC -D_USING_LIBCXX
-std=gnu++11 -Werror=int-to-pointer-cast
-Werror=pointer-to-int-cast -MD -MF
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates/UnwindCurrent.d
-o
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates/UnwindCurrent.o
system/core/libbacktrace/UnwindCurrent.cpp
And I got error:
/tmp/ccZ40ViQ.s: Assembler messages:
/tmp/ccZ40ViQ.s:1752: Error: selected processor does not support ARM
mode `cbnz r6,.L91'
/tmp/ccZ40ViQ.s:1758: Error: selected processor does not support ARM
mode `cbnz r0,.L92'
/tmp/ccZ40ViQ.s:1763: Error: selected processor does not support ARM
mode `cbz r1,.L107'
/tmp/ccZ40ViQ.s:1941: Error: selected processor does not support ARM
mode `cbz r6,.L100'
But if I use the arm gcc 4.9, there is no any build issue.
the "-dumpspecs" output of gcc 5.3 was attached. Thanks.
Regards
Yin, Fengwei
The Linaro Binary Toolchain
============================
The Linaro GCC 4.9-2016.02 Release is now available.
Notice: All Linaro GCC 4.9 series toolchain users should migrate to
the latest version of the Linaro GCC 4.9 toolchain in order to
mitigate potential security exposure to CVE-2015-7545. See the NEWS
section below for details.
Download release packages from:
http://releases.linaro.org/components/toolchain/gcc-linaro/4.9-2016.02/http://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 4.9-2016.02
FSF eglibc 2.19 (eglibc.git/linaro_eglibc-2_19)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.24 (linaro_binutils-2_24-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro Linux Version 3.17-2014.10 (linux-linaro-3.17-2014.10)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 4.9-2016.02
================================
* The armv8l-linux-gnueabihf targetted toolchain is now built using
--with-mode=thumb (like all of the other cross toolchains) rather than
the default which is ARM mode.
* Applied fix for CVE-2015-7545 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
Linaro eglibc 2.19 (linaro_eglibc-2_19).
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* See the following Linaro GCC snapshot:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
The Linaro Binary Toolchain
============================
The Linaro GCC 4.9-2016.02-rc1 Release-Candidate is now available.
Notice: All Linaro GCC 4.9 series toolchain users should migrate to
the latest version of the Linaro GCC 4.9 toolchain in order to
mitigate potential security exposure to CVE-2015-7545. See the NEWS
section below for details.
Download release-candidate packages from:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2016.02-rc1/http://snapshots.linaro.org/components/toolchain/binaries/4.9-2016.02-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 4.9-2016.02-rc1
FSF eglibc 2.19 (eglibc.git/linaro_eglibc-2_19)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.24 (linaro_binutils-2_24-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro Linux Version 3.17-2014.10 (linux-linaro-3.17-2014.10)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 4.9-2016.02-rc1
====================================
* Applied fix for CVE-2015-7545 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
Linaro eglibc 2.19 (linaro_eglibc-2_19).
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* See the following Linaro GCC snapshot:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
== Progress ==
* Validation
- extended validation: updated ABE patch after review
- investigating how to actually separate stdout/stderr streams in dejagnu
- still seeing random results (mostly in the sanitizers tests) in
the Cambridge lab
* GCC
- no progress on Win32-hosted toolchain bug: cannot reproduce it
from a manually built toolchain
- advSIMD/Neon intrinsics tests: cleanup on-going
- bug 2125: forwarded upstream, quickly fixed by R.Biener, backport
in progress
- Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- more on extended validation
- random tests investigation
- more on stdout/stderr
* GCC:
- trunk monitoring, report regressions if needed
- intrinsics tests cleanup
o Easter Monday off (2/10)
== Progress ==
o Extended validation (5/10)
* Worked on benchmarking integration
* Analyzed failures due to --tarbin and --check ABE's flags
* Analyzed native AArch32 timeout (due to guality/GDB testcase)
o Misc (3/10)
* Various meetings
== Plan ==
o Continue on extended validation
o Finalize DejaGNU patches, GCC ARMv8.1 builtins fix.
== Progress ==
* Type promotion pass (6/10)
- Fixed major false positive uninit warnings
= Changed tree-ssa-uinit to handle SEXT_EXPR
= preserving TREE_NO_WARNING set by SRA
= Somemore fixes to preserve debug loc
- There are still some more but this is mainly due to how
tree-ssa-uinit is designed
- Working through the output patterns; some are simple changes but
some needs more analysis
- Planning to create a branch with the latest version for easy review
* Bugs (1/10)
- PR70359
* Misc (1/10)
- GCC Lists
* Public holiday (2/10)
== Plan ==
* Type promotion pass benchmarking
* Perf with LTO
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (4/10)
- Resolved all thumb2 failures
- Posted new patch upstream
* TCWG-247 - Create Validation Job to run on GCC Trunk Commits (1/10)
- Investigation into Python API for discovering when Jenkins builders
are idle
* Laptop hardware failure debugging (2/10)
- Requested a new laptop from Arm
* Misc meeting (1/10)
* Good Friday holiday (2/10)
== Next week ==
* TCWG-247
- Create prototype implementation
== This Week ==
* LTO (4/10)
- Committed r234490 to fix PR70366
- Spent unnecessary time tracking down known (invalid) bug PR65778
- LTO and branch out of range error:
- patch to introduce max partition size param
- experimenting with partition sizes to find value close to 16 mb limit.
* Validation (2/10)
- Pushed script to it's own repo
- Reviews from Christophe on tcwg-buildapp job
* Public Holidays (4/10)
== Next Week ==
- Continue ongoing tasks
== Progress ==
* Support (2/10)
- Investigating a bit more PR16275, need some bigger changes in Clang/LLVM
* Background (6/10)
- Code review, meetings, discussions, general support, etc.
- Planning for a bigger team (git, Jenkins, infrastructure, documentation)
- Receiving new team members, planning start up tasks
- Android NDK discussion, investigation
Realising my activity report has been almost useless for the past month or so...
# Progress #
* TCWG-532, done. [1/10]
Canonicalize ARM syscall patch is committed.
* TCWG-167, patch is posted for review. [4/10]
Add ARM epilogue unwinder in GDB, which fixes many gdb.reverse test
fails.
* TCWG-545, V2 are posted. [1/10]
* TCWG-547, [2/10] patches are reviewed, almost OK, but some changes are
needed.
* Talk with Jojo Ma.
* Open tickets to install buildbot-slave on gcc compile farm for GDB
buildbot setup.
# Plan #
* Holiday on Friday and next Monday.
* TCWG-167, TCWG-545, TCWG-547.
--
Yao
== Progress ==
* Validation
- extended validation: submitted ABE patch for discussion
- noticed random results on some tests in the Cambridge lab.
maybe caused by excessive load on the tester, or stdout/stderr problems
- investigating how to actually separate stdout/stderr streams in dejagnu
* GCC:
- branch merge review for 2016.03 snapshot
- AdvSIMD/Neon intrinsics tests: more cleanup, wondering about
poly128_t prototypes
* Misc (conf calls, meetings, emails, ....)
== Next ==
* Validation:
- more on extended validation
- random tests investigation
- more on stdout/stderr
* GCC:
- trunk monitoring, report regressions if needed
- intrinsics tests cleanup
== This Week ==
* LTO (3/10)
a) section anchors:
- prototype patch to bind functions to global vars
- looked at balanced partitioning
b) chromium LTO build fails with ICE on trunk for arm-linux-gnueabihf:
http://pastebin.com/sX6yKLBP
c) ipa-comdat
- Looked at the pass.
- trying to address TODO: put symbol in it's own comdat section
* Validation (1/10)
- prototype job in bash.
* Holidays (6/10)
== Next Week ==
Continue ongoing tasks
Port to microinstance - TCWG-432 [5/10]
* Non-lab side of minimal trust benchmarking
* More investigation of runtime anomalies
* Reordered builder phases to do useful work while waiting for targets
* Updated everything to work with benchmarking LAVA user (rather than
running as me)
Automated backport benchmarking - TCWG-352 [2/10]
* Cycles of review/development/testing
Controlled image builds - TCWG-360 [1/10]
* More failures to get image to boot on Juno
Log critical data - TCWG-349 [1/10]
* Everything now logged, except where it depends on TCWG-360
Misc - [1/10]
=Plan=
Finish non-lab side of minimal trust benchmarking
Commit backport benchmarking, review permitting
Tweak microinstance in reaction to lab work
More Juno image work
More runtime anomaly work
=Availability=
Off from this Friday, back for three days from Monday 4th April
Return to ARM on Thursday 7th April
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10)
- Resolved 50% of thumb2 failures
- Resolved issues with overlapping registers and not setting
condition codes
- Wrote compile only test cases that pass validation
* TCWG-247 - Create Validation Job to run on GCC Trunk Commits (2/10)
- Investigation into Python API for discovering when Jenkins builders
are idle
* Linaro connect recovery day (2/10)
* Misc meeting (1/10)
== Next week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names
- Resolve remaining thumb2 issues
* TCWG-247
- Create prototype implementation
= Progress ==
* Day off (2/10)
- After Connect, recuperating, jet lagging
* EuroLLVM (6/10)
- Flying Wed to Barcelona, attending conference
- Back on Saturday
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
- Planning for a bigger team (git, Jenkins, infrastructure)
* Sick on Monday [2/10]
# Progress #
* AArch64/ARM linux syscall for process record. [2/10] TCWG-532
ARM patch (fixing the register for syscall arg pass) is committed.
Canonicalize ARM syscall patch is posted for review.
* Support range stepping on arm-linux. [4/10] TCWG-545
Preparatory patches fixing bugs when "single step the instruction
branch to itself" are being reviewed. Pedro thinks my patches may
not work in some rare cases, and I spend some time writing the case
and prove it won't happen.
* Misc [2/10]
** file expense,
** upstream patch review,
# Plan #
* TCWG-532
* TCWG-545
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.03 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn234210 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn234210
* Backport of [Bugfix] [AArch64] [Linaro #1994] Disable
pcrelative_literal_loads with fix-cortex-a53-843419
* Backport of [Bugfix] [AArch64] [Linaro #2123] Fix dependency of gcc-plugin.h
* Backport of [Bugfix] [AArch32] PR target/62554 target/69610 Fix for ARMv3
* Backport of [Bugfix] [AArch32] PR target/69161: Don't ignore mode
when matching comparison operator in cstore-like patterns
* Backport of [AArch32] Enable instruction fusion of AES instructions
on ARM for Cortex-A53 and Cortex-A57
* Backport of [AArch64] Add missing return in aarch64_internal_mov_immediate
* Backport of [AArch64] Enable instruction fusion of dependent AESE;
AESMC and AESD; AESIMC pairs
* Backport of [AArch64] Fix installed plugin headers for aarch64, m68k and c6x
* Backport of [AArch64] GCC 6 regression in vector performance. - Fix
vector initialization to happen with lane load instructions
* Backport of [AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
* Backport of [Testsuite] [AArch64] add check for aarch64 in
check_effective_target_section_anchors
* Backport of [Testsuite] Print markers to stderr to avoid races with
sanitizer output
* Backport of [Misc] Fix ChangeLog for 233518
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
== Progress ==
o BKK16 remote (5/10)
* Followed TCWG sessions
* Extended validation:
- worked with Kugan
- implemented job for native validation
o GCC dev. (4/10)
* Remote validation sanitizing:
- iterate on the output pattern fix
- testing a fix for stderr/stdin ordering issue
* Gave some support on __sync builtins, preparing a fix for armv8.1
o Misc (1/10)
* Various meetings
== Plan ==
o GCC 5 branch merge, and 2016.03 snapshot
o Continue on-going tasks
Port to microinstance - TCWG-432 [17/10]
* Investigating difference between LAVA and 'desktop Juno' runtimes
** Some of this was down to piles of /dev/console output - redirecting
to file improved SPEC build time by 75%!
** Some cases make sense, others remain unexplained
** Might just go away if we update the Juno image
* Wrote up how to do benchmarking for minimal-trust cases
** Needs both lab and development work
* Merged another large tranche of changes back to benchmarking branch
** Microinstance more or less functional, main instance benchmarking
seems unbroken
** But some more tweaks to make as Lab work happens
* Prepared backport benchmarking for merge
Misc [3/10]
=Plan=
* Submit backport benchmarking for review
* Tweak uinstance in reaction to lab work
* Implement the non-lab side of minimal-trust benchmarking
* Return to looking at Juno image generation
* Look some more at LAVA/desktop runtime differences
* Implement small improvements, if time
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Resolved thumb2 failures
- Negdi2 was not generating instruction to set condition codes
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (1/10)
- Created new patch using new predicate that matches arm and thumb2
constraints
- Received approval to GCC 7 stage 1
* Bugzilla 70014 - [ARM] Predicate does not match constraint
(*subsi3_carryin_const) (1/10)
- Fix checked into trunk
* Linaro Connect meetings (5/10)
== Next week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names
- Create compile only test cases and re-run validation testing
- Post new patch upstream
Hey,
Regarding the GCC ABI 5 issue, I was wondering what's the policy
behind updating packages on stable updates for both Debian and Ubuntu.
Our time frame is a bit constrained, and we definitely will have to
take some hard decisions in the next six months, so I'd like to
understand everything that is at stake before I have my own opinion.
LLVM has a 6 month major cycle, releasing around February / August.
Major releases are allowed to break the ABI. Major breakages need one
release warning period.
Ubuntu has a 6 month release cycle, around April / October. IIUC,
major releases are allowed to have new versions of packages, but
updates for the next few years have to keep within the same major
release.
Debian has a -1 years release cycle (heh), and has the same major /
minor policy, which makes it a lot harder to update major versions.
However, I believe unstable is still not closed, nor will be in August
this year, so updating to LLVM 3.9 will not be a problem, but it will
mean users will have to wait a bit more to get a working LLVM.
The time frame is then:
3.8.0 released March (without the fix)
Ubuntu X released April
3.9.0 releases August (hopefully with a fix)
Ubuntu X+1 released October
Debian freezes ??
LLVM 3.8.1 ??
If we don't back-port GCC ABI 5 into 3.8.1, Ubuntu users will not have
the fix ever, unless you *can* update to 3.9.0 in August.
Ubuntu X+1 will be fine using 3.9, as will Debian after August, unless
you guys freeze before that.
I believe both Debian and Ubuntu have a trunk-based LLVM package for
experimental use only, and it would be bad, but not completely broken,
to recommend users to use that meanwhile.
If Debian freezes *before* 3.9.0 is out, or if Ubuntu can't update to
3.9.0 on April's release, then we'll have a strong reason to back-port
the change to 3.8.x. If not, even though it will be uncomfortable for
users until August, the argument is not that strong and will be hard
to get it through.
Any comments? Ideas? Does any of that make sense?
cheers,
--renato
Hi,
I have been comparing the stock gcc 5.2 and the Linaro 5.2 (Linaro GCC
5.2-2015.11-1) and have noticed a difference with the __sync
intrinsics.
Here is the simple test case
--- cut here ---
int add_int(int add_value, int *dest)
{
return __sync_add_and_fetch(dest, add_value);
}
--- cut here ---
Compiling with the stock gcc 5.2 (-S -O3) I get
---------
add_int:
.L2:
ldaxr w2, [x1]
add w2, w2, w0
stlxr w3, w2, [x1]
cbnz w3, .L2
mov w0, w2
ret
---------
Wheras with Linaro gcc 5.2 I get
---------
add_int:
.L2:
ldxr w2, [x1]
add w2, w2, w0
stlxr w3, w2, [x1]
cbnz w3, .L2
dmb ish
mov w0, w2
ret
---------
Why the extra (unnecessary?) memory barrier?
Also, is it worthwhile putting a prfm before the ldaxr. EG
add_int:
prfm pst1strm, [x1]
.L2:
ldaxr w2, [x1]
See the following thread
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html
All the best,
Ed
== Progress ==
o GCC dev. (7/10)
* Remote validation sanitizing:
- fixed last issues in dejagnu patch and submitted it uptsream
- 2 more cleanup/fix dejagnu patches submitted and merged upstream
- proposed a fix/workaround for the output pattern issues (>400
failures removed with this patch)
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Try to follow connect remotely
o Extended validation work
== Progress ==
* GCC bugs:
- #2073 tried to reproduce it with a manually-built toolchain. No luck
* GCC validation:
- added support to choose simulated cpu (different from --with-cpu)
* GCC:
- completing Neon intrinsics tests, to prepare cleanup
* Validation:
- small improvements
* Misc (conf calls, meetings, emails, ...)
== Next ==
Remote Connect
== Progress ==
* Support (5/10)
- Working on PR17193
- Continue review on D17141
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- Connect preparations
- GCC ABI 5 discussions
- Assessing Swift calling convention impact ARM back-end
- Interviews
# Progress #
* TCWG-545, Handle "branch-to-self" instruction in single stepping.
[5/10] Patches are posted upstream for review.
* TCWG-532, one patch is committed and one patch is posted for review.
[2/10]
* Tweak ARM process record. [2/10]
Two patches are pushed in. Many test fails are fixed.
* FSF patches review. [1/10].
# Plan #
* Linaro Connect.
--
Yao
Hi,
I have just switched to gcc 5.2 from 4.9.2 and the code quality does seem to have improved significantly. For example, it now seems much better at using ldp/stp and it seems to has stopped gratuitous use of the SIMD registers.
However, I still have a few whinges:-)
See attached copy.c / copy.s (This is a performance critical function from OpenJDK)
pd_disjoint_words:
cmp x2, 8 <<< (1)
sub sp, sp, #64 <<< (2)
bhi .L2
cmp w2, 8 <<< (1)
bls .L15
.L2:
add sp, sp, 64 <<< (2)
(1) If count as a 64 bit unsigned is <= 8 then it is probably still <= 8 as a 32 bit unsigned.
(2) Nowhere in the function does it store anything on the stack, so why
drop and restore the stack every time. Also, minor quibble in the
disass, why does sub use #64 whereas add uses just '64' (appreciate this
is probably binutils, not gcc).
.L15:
adrp x3, .L4
add x3, x3, :lo12:.L4
ldrb w2, [x3,w2,uxtw] <<< (3)
adr x3, .Lrtx4
add x2, x3, w2, sxtb #2
br x2
(3) Why use a byte table, this is not some sort of embedded system. Use
a word table and this becomes.
.L15:
adrp x3, .L4
add x3, x3, :lo12:.L4
ldr x2, [x3, x2, lsl #3]
br x2
An aligned word load takes exactly the same time as a byte load and we
save the faffing about calculating the address.
.L10:
ldp x6, x7, [x0]
ldp x4, x5, [x0, 16]
ldp x2, x3, [x0, 32] <<< (4)
stp x2, x3, [x1, 32] <<< (4)
stp x6, x7, [x1]
stp x4, x5, [x1, 16]
(4) Seems to be something wrong with the load scheduler here? Why not
move the stp x2, x3 to the end. It does this repeatedly.
Unfortunately as this function is performance critical it means I will
probably end up doing it in inline assembler which is time consuming,
error prone and non portable.
* Whinge mode off
Ed
== Progress ==
o GCC dev. (7/10)
* Remote validation sanitizing:
- Implemented and tested a pure dejagnu fix (the actual
implementation works fine for GCC but might be an issue in a different
context, a cleaner fix almost done)
- Found a latent issue in GCC profiling test harness
* ARM and AArch64 backends LRA cleanup:
- Looked at the remaining artifacts, will prepare a patch for GCC 7
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Finalize and submit dejagnu fix
Port to microinstance - TCWG-432 [7/10]
* Merged last few months of development back to benchmarking branch
* Restored support for multiple targets per builder
* Updated builder landed, altered jobs to work with it
** Removed assumption that host filesystem is non-persistent
** Stacked up test runs for the weekend
Transfer secret management to LAVA [1/10]
* LAVA jobs now use a within-LAVA key to access sources
Misc [2/10]
* Unsuccessful fiddling with heat-monitoring tools on Juno
* Usual background of mail and meetings
=Plan=
* Fallout from weekend test runs
** Some failure is going on, need to investigate
* Update docs and Jenkins configs w.r.t. last week's activity
* Further investigation on a couple of LAVA issues that are causing me pain
** Un-deserializable bundles
** Inaccessible image reports
* Continue assessing target stability/looking at inconsistent results
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (6/10)
- Tested and posted SImode and DImode patch upstream
- Feedback recommended supporting thumb2 in addition to arm architectures
- Patch to support thumb2 fails on all thumb architectures;
investigating failures
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (2/10)
- Created new bug, developed and successfully tested patch
- Fix posted upstream
* Bugzilla 70014 - [ARM] Predicate does not match constraint
(*subsi3_carryin_const) (1/10)
- Created new bug and patch
* Misc (1/10)
== Next week ==
* Bugzilla 69663 - Cleanup by merging patterns using mode iterators,
submit upstream
* Bugzilla 70008 - Respond to upstream comments as appropriate
* Bugzilla 70014 - Post patch and respond to upstream comments
* Travel to Linaro Connect beginning March 3rd
== This Week ==
* LTO (6/10)
- TCWG 528:
a) reduced test-case for the case when decl node gets visited multiple times
b) updated patch not to walk artificial record decls (typeinfo
objects) as per Richard's suggestion.
submitted upstream, waiting for review.
- benchmarking: Aarch64 SPEC2006-int benchmarks complete
- looked at pr57703
- Slides
* setting up perf on chromebook (2/10)
- perf doc
- got perf running on chromebook by manually building it and set of
(clumsy) workarounds.
- perf annotate shows no output and perf stat shows "not supported" for almost
all entires except "page faults"
- will give a try to dual boot chrubuntu on chromebook
* half-day sick leave (1/10)
- doctor's appointment for eye inflammation
* Misc (1/10)
- Meetings
== Next Week ==
- LTO
- tcwg-310
- look at jenkins tutorial in collaborate wiki
== Progress ==
* Support (4/10)
- Updating patch D17141 for Darwin, resubmitting, discussions.
- Understanding PR21778, may need changes to SLP
- Benchmarking some scheduler choices for A17
* Release (1/10)
- 3.8.0 RC3 validation
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- Sifting through CVs, interviews, etc.
# Progress #
* Support range stepping on arm-linux. TCWG-518. [5/10]
Post patch series about "the thread is stepping over breakpoint but
it spawns child thread". The fix is OK but the test case changes are
being reviewed.
The more I test my range stepping patches, the more existing bugs I
find. Looking at the bug "software single step the instruction
branch to self."
* AArch64 linux syscall for record/replay. TCWG-532. [1/10]
Patch is out for review.
* Fix some ARM reverse debugging bugs. TCWG-183. [1/10]
Patch is pushed in. The original implementation wasn't carefully
reviewed, so I am sure there are bugs somewhere else.
* Patch review on arm tracepoint support. [1/10]
One patch is approved but I insist that another patch should be done
in generic part instead of ARM specific part, but the author wants do
it in ARM specific part because he things it is simpler.
* Misc [2/10]
** Go through the Linux kernel awareness GDB patches quickly, the first
reaction is "split your patch, please".
** Go to London to collect my passport.
# Plan #
* Support range stepping on arm-linux. TCWG-518.
* TCWG-167, TCWG-532.
* Prepare for the Linaro Connect travel.
--
Yao
Hi All,
Does linaro distributes arm-gcc as a pre-built static tool chain
distribution? If yes, where can i download them from. Please point me some
location from where i can download.
--
Thanks & Regards,
M.Srikanth Kumar.
Bug with compiler flag handling - (no ticket) [2/10]
* Coremark-Pro was ignoring compiler flags
* Fixed that, made flag handling consistent across all benchmarks
Release benchmarking via Jenkins - TCWG-348 [1/10]
* Seems to work with test workload
Port to microinstance - TCG-432 [3/10]
* Looked at some inconsistent results
* Worried that one of the Junos may be sick, but unproven for now
Backport benchmarking via Jenkins - TCWG-352 [1/10]
* Finished 'general benchmarking' job
* Switched backport job to build/test cross-compilers
* Recent backport results bundles are corrupted, unable to work out why
Document benchmarking infrastructure - TCWG-496 [1/10]
* Documented Jenkins interface
Misc [2/10]
=Plan=
If updated builder becomes available, convert uinstance job to use it
Continue assessing target stability/looking at inconsistent results
Rework LAVA scripts to permit multiple targets per builder
Hi all,
I download the pre-built toolchain for one of our armv6 board.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
After plug it into Yocto as an external toolchain, it failed to install it
correctly.
../meta-linaro/meta-linaro-toolchain/recipes-devtools/external-linaro-toolchain/
external-linaro-toolchain.bb, do_install
| DEBUG: Executing shell function do_install
| cp: cannot stat
`/opt/gcc-linaro-arm-none-eabi-4.8-2014.04_linux/arm-none-eabi/libc/lib/*':
No such file or directory
Any suggestion?
Thanks,
Joel