- linaro-toolchain - lists.linaro.org

[ACTIVITY] 20-24 June 2016

by Diana Picus

== Progress == * Out of office on Monday and Tuesday [4/10] * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10] - First patch committed upstream (6 features / properties) - Another patch in upstream review (5 features / properties) - Working on another series of patches * Use member initializers in ARMSubtarget [TCWG-659] [1/10] - Trivial refactoring suggested during code review for TCWG-623 - Committed upstream * Unbreak the selfhost bots [TCWG-661] [1/10] - Currently bisecting the issue affecting clang-cmake-thumbv7-full-sh (in progress) - Tried bisecting one of the issues affecting clang-cmake-armv7-selfhost and clang-cmake-armv7-selfhost-neon, but the test board died in the process; Renato is trying to reproduce on one of his boards * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Finally committed upstream == Plan == * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] * Unbreak the selfhost bots [TCWG-661]

9 years, 2 months

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[Activity] 20-24 June 2016

by Peter Smith

== Progress == * TCWG-653 Add interworking thunks to LLD Investigated and reported upstream bug in existing implementation. This has been fixed by reverting the change that introduced it. Got some feedback about whether I would need to strictly follow existing Thunk implementation. Implemented an alternative thunk mechanism that should generalise to supporting range extension and interworking thunks. It is passing the existing lld regression tests. == Plans == Finish off support for and add tests for ARM/Thumb interwork. Tidy up and submit upstream.

9 years, 2 months

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[ACTIVITY] 20-24 June 2016

by Christophe Lyon

== Progress == * Validation - experimenting backport-multijob - noticed dejagnu problems when trying to kill processes that timed out - abe and jenkins configs patches / reviews * Backports/snapshots - restarted a few validations, to try to recover from disk full issues * GCC - neon-testgen.ml removal patch sent upstream - PR 67591 (ARM v8 Thumb IT blocks deprecated) - followup on vect.exp's check_vect() support for old arm cores. - neon-fp16 tests consistency patch posted - a couple of regressions flagged on trunk * cortex-strings - updated aarch64/strlen * Support * misc (conf-calls, meetings, emails, ....) == Next == * Validation: - patch reviews - look at xenial, docker builders * Backports - restart the ones that failed due to disk space issues * GCC - monitor trunk regressions - fix "check_vect" guard in gcc.dg/vect tests - pr 67591 - advsimd tests

9 years, 2 months

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[ACTIVITY] Week 24

by Yvan Roux

== Progress == o Extended Validation (1/10) - Benchmarking job babysitting. o Linaro GCC (5/10) - Merged FSF GCtC 6 branch - Reviewed backports (very tedious because of infra issues) - Released June snapshots (5.4 and 6.1) o Upstream GCC (2/10) - ARMv8.1 libatomic: Reading and code analysis. o Misc (2/10) * Various meetings and discussions. == Plan == o Continue on-going tasks (libatomic, benchamrking)

9 years, 2 months

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[ACTIVITY] 13 - 17 June 2016

by Yao Qi

# Progress # * TCWG-333, ISA bit treatment in ARM thumb mode. [2/10] Post a patch to skip the test for thumb mode. Finish the prototype which shows many issues that I can't overcome. Convince myself that we should skip the test rather than support that in GDB. * TCWG-518, ARM range stepping patches. [3/10]. 11 of 12 patches are approved, and some of them are already committed. Need to address one comment that merge to execution paths into one, which requires some big changes in GDBserver for linux. * TCWG-651, Support 'catch syscall' in remote for aarch64 and arm.[3/10] My patches are posted upstream. * TCWG-556, aarch64 gdb buildbot. [1/10] They are online. http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-m64/ http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-native-gdbserver-m64 * TCWG-654, Build both cross/native arm/aarch64 gcc 5.4.1 to replace the gcc in my gdb tests. Ongoing. [1/10] # Plan # * Follow up all of them above, * Holiday from Wed - Fri. -- Yao

9 years, 2 months

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[ACTIVITY] 30 May-3 June 2016

by kugan

== Progress == 1 day public holidays IPA VRP - Implemented a version of early VRP. - Verified with simple test cases. - Some test cases are failing in regression testing, looking into it. - Some design decisions need to be firmed up with the upstream discussions. == Plan == - Follow upon remaining upstream patches - IPA VRP

9 years, 2 months

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[ACTIVITY] 13 - 17 June 2016

by Prathamesh Kulkarni

== This Week == * LTO (8/10) a) TCWG-558 (4/10) - added read/write summaries for streaming variables whose alignment we want to increase - patch posted upstream b) TCWG-548 (4/10) - implemented prototype patch * Benchmarking (1/10) - Issues with submitting toolchain tarballs. - #3632 completed * Misc (1/10) - Meetings == Next Week == TCWG-558: address upstream reviews. TCWG-548: validate and benchmark patch, and improve prototype implementation ipa-vrp: Continue working on ipa-vrp.

9 years, 2 months

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[ACTIVITY] 13-17 June 2016

by Diana Picus

== Progress == * Out of office on Monday [2/10] * Remove exit-on-error flag from CodeGen tests [TCWG-604] [1/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Patch fixing the ARM test (PR27765) - committed upstream - Submitted a patch removing the flag from llc - accepted upstream, pending on approval of AMDGPU patch * Use git worktree in llvm helper scripts [TCWG-587] [2/10] - Merged. Working on some follow-up stories - Change interface to llvm-build [TCWG-629] - Modify llvm-build to accept the targets defined by CMake - Fix a bug in llvm-env [TCWG-644] - Initially went unnoticed due to zsh vs bash differences - Allow cloning from read-only repo [TCWG-652] - This is so non-TCWG people can use our helper scripts * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [5/10] - Submitted a patch extracting 6 new subtarget features - Investigating more features that could be extracted == Plan == * OOO on Monday and Tuesday * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]

9 years, 3 months

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[ACTIVITY] 13-17 June 2016

by Christophe Lyon

== Progress == * Validation - disk full on builders: analysis simply shows that we need more disk :) - updated "buildapp" job to support building the Linux kernel. We need more dev packages installed in the *build* schroots for it to work though. * Backports/snapshots - fsf-6 branch merge review * GCC - small cleanup in neon* effective-target tests done - re-testing neon-testgen.ml removal patch - PR 67591 (ARM v8 Thumb IT blocks deprecated) - followup on vect.exp's check_vect() support for old arm cores. * Support * Misc (conf-calls, meetings, emails, ...) == Next == * Validation: - patch reviews * Backports - restart the ones that failed due do disk space issues * GCC - monitor trunk regressions - fix "check_vect" guard in gcc.dg/vect tests - hopefully test-neongen.ml removal - pr 67591 - advsimd tests

9 years, 3 months

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Activity 13th - 16th June 2016

by Peter Smith

== Progress == TCWG-611 Initial Thumbv7a support for LLD committed upstream. Interworking is supported via BLX only. This is enough to run hello world on a modern arm-linux-gnueabihf target. TCWG-653 Interworking veneer support for LLD The existing support for veneers (thunks in LLD terminology) is Mips specific for non-pi to pi calls. Unless there is something I'm missing it looks broken in the general case as well. I have an implementation of minimal veneers that I'm not particular happy with, but can experiment with to see what the implementation options are. I am likely to need to go via and RFC first. Holiday on Friday. == Next Week == Continue working on TCWG-653.

9 years, 3 months

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[ANNOUNCE] Linaro GCC 5 and 6 2016.06 snapshots

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.06 snapshot of both Linaro GCC 5 and Linaro GCC 6 source packages. Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn237469 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.1+svn237469 * Backport of [Bugfix] [AArch32] PR target/69857 Remove bogus early return false; in gen_operands_ldrd_strd * Backport of [AArch32] Add mode to probe_stack set operands * Backport of [AArch32] arm/ieee754-df.S: Fix typos in comments * Backport of [AArch32] Do not set ARM_ARCH_ISA_THUMB for armv5 * Backport of [AArch32] Error out for incompatible ARM multilibs * Backport of [AArch32] Fix costing of sign-extending load in rtx costs * Backport of [AArch32] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC * Backport of [AArch32] Use proper output modifier for DImode register in store exclusive patterns * Backport of [AArch64] 1/4 Add the missing support of vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64 * Backport of [AArch64] 2/4 Extend vector mutiply by element to all supported modes * Backport of [AArch64] 3/4 Reimplement multiply by element to get rid of inline assembly * Backport of [AArch64] 4/4 Reimplement vmvn* intrinscis, remove inline assembly * Backport of [AArch64] Adjust SIMD integer preference * Backport of [AArch64] Delete ASM_OUTPUT_DEF and fallback to default .set directive * Backport of [AArch64] Don't define a macro when a variable will do * Backport of [AArch64] Fix shift attributes * Backport of [AArch64] Improve aarch64_case_values_threshold setting * Backport of [AArch64] print_operand should not fallthrough from register operand into generic operand * Backport of [AArch64] Remove aarch64_simd_attr_length_move * Backport of [AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true * Backport of [AArch64] Simplify ashl<mode>3 expander for SHORT modes * Backport of [AArch64] Simplify reduc_plus_scal_v2[sd]f sequence * Backport of [AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled * Backport of [AArch64] Update documentation of AArch64 options for GCC6 * Backport of [AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets * Backport of [Testsuite] [AArch32] 01/11 Fix typo in vreinterpret.c test comment * Backport of [Testsuite] [AArch32] 02/11 Remove useless #ifdefs from these tests: vmul, vshl and vtst * Backport of [Testsuite] [AArch32] 03/11 AdvSIMD tests: be more verbose * Backport of [Testsuite] [AArch32] 04/11 Add forgotten vsliq_n_u64 vsliq_n_s64 tests * Backport of [Testsuite] [AArch32] 05/11 Add missing vreinterpretq_p{8,16} tests * Backport of [Testsuite] [AArch32] 06/11 Add missing vtst_p16 and vtstq_p16, and vtst_p{8,16} and vtstq_p{8,16} tests * Backport of [Testsuite] [AArch32] 07/11 Add vget_lane fp16 tests * Backport of [Testsuite] [AArch32] 08/11 Add missing vstX_lane fp16 tests * Backport of [Testsuite] [AArch32] 09/11 Add missing vrnd{,a,m,n,p,x} tests * Backport of [Testsuite] [AArch32] 10/11 Add missing tests for intrinsics operating on poly64 and poly128 types * Backport of [Testsuite] [AArch32] 11/11 Add missing tests for vreinterpret, operating of fp16 type * Backport of [Testsuite] [AArch64] Fix vmul_elem_1.c on big-endian * Backport of [Testsuite] [AArch64] Guard float64_t with __aarch64__ * Backport of [Testsuite] [AArch64] Skip cpu-diagnostics tests when overriding -mcpu * Backport of [Testsuite] gcc-dg: handle all return values when shouldfail is set * Backport of [Testsuite] PR70227, skip g++.dg/lto/pr69589_0.C on targets without -rdynamic support * Backport of [Testsuite] PR tree-optimization/57206 * Backport of [Testsuite] Skip tail call tests on Thumb-1 targets * Backport of [Misc] Increase default value of lto-min-partition to 10000 * Backport of [Misc] introduce --param max-lto-partition for having an upper bound on partition size * Backport of [Cleanup] [AArch32] Fix typos in *thumb1_mulsi3 comment * Backport of [Cleanup] [AArch32] Remove unused TARGET_ARM_V*M macros * Backport of [Cleanup] [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes * Backport of [Cleanup] [AArch64] Remove an unused reload hook * Backport of [Cleanup] Convert conditional compilation on WORD_REGISTER_OPERATIONS * Backport of [Cleanup] Remove spurious debug code * Backport of [Cleanup] Move wrong ChangeLog entry from toplevel to gcc ChangeLog * Backport of [Doc] Fix minor doc bugs, signalling typo, major version changes rare Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn237113 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06/ Interesting changes in this GCC source package snapshot include: Updates to GCC 5.6+svn237113 * Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/69245: Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is the default node to recalculate optab availability * Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/70002: Make aarch64_set_current_function play nice with pragma resetting Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

9 years, 3 months

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Error: non-constant expression in ".if" statement

by Jérôme Forissier

Hi, I've stumbled across an assembler error message that I don't understand. bl1/aarch64/bl1_exceptions.S: Assembler messages: bl1/aarch64/bl1_exceptions.S:53: Error: non-constant expression in ".if" statement It occurs when building ARM Trusted Firmware with aarch64-linux-gnu-gcc that ships with Ubuntu 16.04. It does _not_ occur with an older Linaro toolchain. More details in [1]. The .align directives in the vector_base and vector_entry macros _do_ make a difference. Are they the cause of the problem? Would you recommend writing the code differently? Or is it a compiler bug? [1] https://github.com/ARM-software/tf-issues/issues/401 Thanks, -- Jerome

9 years, 3 months

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[TCWG] Split-stack for aarch64

by Adhemerval Zanella

Hi all, First sorry for the long message, but I am kinda stuck on an issue with my split-stack work for aarch64, so any new eyes to check if I am doing things properly would be really helpful. I pushed my current work on a local gcc git [1] and glibc [2] branches. The current code show not issue with the placed C tests, but there is one elusive GO tests that fails for some reason. The glibc patch is pretty simple: it adds a tcbhead_t field (__private_ss) which will be used to hold the split stack thread value. Different from stack protector, split-stack requires a pointer per thread and it is used frequently on *every* function prologue. So faster access is through TCB direct access (one instruction less than TLS initial-exec). I plan to digress a little more about why I decided to use TCB access, but in a short the advantages are: 1. It is faster than TLS initial-exec 2. Does not require any static or dynamic relocation The rest of patch is just to add a versioned symbol so either static or dynamic linking fails for an older glibc (to prevent split-stack binaries to run on non-supported glibcs). The GCC patch is more complex, but it follows the already implemented split-stack support on other architectures (x86, powerpc64, s390). Basically you add hooks to generate the required prologue and other bits (C varargs requires some work) and add some runtime support on libgcc (morestack.S). Split-stack idea is basically as this: let say you have a function that requires a very large stack allocation that might fail at runtime (due ulimit -s limit). Split-stack add some instrumentation that check if the stack allocation will fail based on initial value and allocates stack segments as required. So basically a function would be instrumented as: function foo ss := TCB::__private_ss if SP + stack_allocation_size > ss call __morestack // function code What __morestack basically does is create a new stack segment with some slack (using a platform neutral code), change the stack pointer and continue run the function. So a stack frame for a function that called __morestack is as: foo \_ __morestack \_ // function code And when the function code finished its execution (including all possible function calls), it returns to __morestack so it restore the old stack pointer and arguments. Now, this is the most straightforward usage of __morestack. However GO language allows a construct [3] that allows a function to register a callback that is called at end of its scope that allows to 'recover' from some runtime execution failure. And this is the remaining GO tests that fails [4]. What it basically does is run a set of tests that allocate some different structure and try to access it in different invalid way to check if accessing a know null pointer is caught by the runtime (GO adds null pointer checks for some constructs). 9 func main() { 10 ok := true 11 for _, tt := range tests { 12 func() { 13 defer func() { 14 if err := recover(); err == nil { 15 println(tt.name, "did not panic") 16 ok = false 17 } 18 }() 19 tt.fn() 20 }() 21 } 22 if !ok { 23 println("BUG") 24 } 25 } 41 var tests = []struct{ 42 name string 43 fn func() 44 }{ 76 {"*bigstructp", func() { use(*bigstructp) }}, 108 type BigStruct struct { 109 i int 110 j float64 111 k string 112 x [128<<20]byte 113 l []byte 114 } So basically here it tries to allocate a very big structure (BigStruct with about 128 MBs) on stack and since it does not have stack allocation it will need to call __morestack. Now, if have patient to read until now, the way GCCGO does that is by throwing an exception to unwind the stack and to add some CFI directives in both generated code and morestack to correct handling the unwinding. So if GCC generates the unwind information for the objects and if __morestack have the correct unwind information it should, so I presume my patch is failing in either define the correct exception handler directives in morestack.S or I am failing in generate the correct __morestack call. The __morestack call is done at 'aarch64_expand_split_stack_prologue' in my patch as: -- + /* Call __morestack with a non-standard call procedure: x10 will hold + the requested stack pointer and x11 the required stack size to be + copied. */ + args_size = crtl->args.size >= 0 ? crtl->args.size : 0; + reg11 = gen_rtx_REG (DImode, R11_REGNUM); + emit_move_insn (reg11, GEN_INT (args_size)); + use_reg (&call_fusage, reg11); + + /* Set up a minimum frame pointer to call __morestack. The SP is not + save on x29 prior so in __morestack x29 points to the called SP. */ + aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, 16); + + insn = emit_call_insn (gen_call (gen_rtx_MEM (DImode, morestack_ref), + const0_rtx, const0_rtx)); + add_function_usage_to (insn, call_fusage); + + reg29 = gen_rtx_REG (Pmode, R29_REGNUM); + cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg29, cfi_ops); + reg30 = gen_rtx_REG (Pmode, R30_REGNUM); + cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg30, cfi_ops); + insn = emit_insn (aarch64_gen_loadwb_pair (DImode, stack_pointer_rtx, + reg29, reg30, 16)); + + /* Reset the CFA to be SP + FRAME_SIZE. */ + new_cfa = stack_pointer_rtx; + cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops); + REG_NOTES (insn) = cfi_ops; + RTX_FRAME_RELATED_P (insn) = 1; + + emit_use (gen_rtx_REG (DImode, LR_REGNUM)); + + emit_insn (gen_split_stack_return ()); -- I do not add any stack frame allocation for the call, so it might a source of issues. Another issue might in morestack.S unwinding directives that is not following the ABI correctly. I am revising it using GCC generated exceptions examples. [1] https://git.linaro.org/toolchain/gcc.git/shortlog/refs/heads/linaro-local/a… [2] https://git.linaro.org/toolchain/glibc.git/shortlog/refs/heads/azanella/spl… [3] https://blog.golang.org/defer-panic-and-recover [4] gcc/testsuite/go.test/test/nilptr2.go

9 years, 3 months

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[ACTIVITY] 06 - 10 June 2016

by Omair Javaid

=== This Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [3/10] -- Implementation successful without the need for instruction emulation. -- Watchpoint hit detection fixed with ptrace reporting hit address correctly. -- Used up watchpoint HitAddress function to return back the real address to host. Investigation of Nexus devices kernel issues.[TCWG-622] [2/10] -- Figured out steps to build custom kernel for Neuxs7. -- Kernel fails to boot though. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] [2/10] -- Submitted a patch to report back correct reason for watchpoint creation failure. Miscellaneous [3/10] -- Meetings, emails, discussions etc. -- A look into LLDB xfail decorators to fail on the basis of arm ABI. -- Out of office on Thursday 9th June for visa interview. === Next Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Finish up work, test and submit for review upstream. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] -- Patch review and further progress. Miscellaneous -- Testsuite Makefile.rulez update still pending, hopefully will be done this week. -- Xfail decorator updates to xfail based on ARM ABI.

9 years, 3 months

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[ACTIVITY] 30 May - 03 June 2016

by Omair Javaid

=== This Week === Investigation of Nexus devices kernel issues.[TCWG-622] [6/10] -- Figured out source trees for various android devices and checked out kernel code. -- Comparison between watchpoint implementation of different kerenel sources supported by Nexus devices. -- Figured a way to burn a custom rom with updated kernel on Nexus 7. -- Figured Kconfig issue that was causing watchpoints not to be detected on Nexus 7. -- Watchpoint installation still doesnt work on Nexus 7. LLDB buildbot updates and maintenance [TCWG-241] [2/10] -- Upgraded cmake version after migration to new version. -- Migrating local buildbot setup (builders and testers) to ubuntu xenial 16.04 -- Buildbot restart after power outage. Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Out of office on Tuesday 31st 2016 for visa documents preparation. === Next Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Continue work on hardware watchpoint support. Investigation of Nexus devices kernel issues.[TCWG-622] -- Figured out steps to build custom kernel for Neuxs7. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] -- Investigate possible ways to solve this issue. Miscellaneous -- Out of office on Thursday 9th June for visa interview.

9 years, 3 months

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[ACTIVITY] 6 - 10 June 2016

by Yao Qi

* One day off on Thu [2/10] # Progress # * TCWG-639, non-8-byte-aligned watchpoint is missed on aarch64. [4/10]. It is caused by limited kernel BAS support. RedHat reports this problem and posts a patch. Good to see they start to contribute to aarch64 GDB, but I don't like the patch. Spend much time writing a prototype to prove their patch is not perfect. We agree to fix this problem by extend RSP fortunately. * TCWG-333, [3/10] I follow the way how mips does, and fix some bugs. * TCWG-547, TCWG-518, blocked in upstream review. * Misc, meetings. [1/10] # Plan # * TCWG-333, TCWG-556. * Ping TCWG-547, TCWG-518. -- Yao

9 years, 3 months

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[ACTIVITY] Week 23

by Yvan Roux

== Progress == o Extended Validation (4/10) - Investigate and reported Glibc/libsanitizer issue https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71445 - Looked at benchmark job issues - Discuss benchmark/lava notification mechanism o Linaro GCC (1/10) - Merged FSF GCC 5.4 branch o Upstream GCC (3/10) - ARMv8.1 libatomic investigation: seems to work fine when enabling multilib on AArch64 need to investigate completeness of the support. o Misc (2/10) * Various meetings and discussions. * Backlfip patch reviews == Plan == o Backport reviews and June snapshots o Continue libatomic o Benchmarking job fixes.

9 years, 3 months

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[ACTIVITY] 6 - 10 June 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) a) committed r237207 to fix unresolved test-cases added in r236503 (1/10) b) move increase_alignment pass to regular pass (3/10) - Patch iterations based on suggestions from Honza and Richard - Understanding lto streaming and decl merging code c) TCWG-548 (1/10) - WIP patch * TCWG-319 (1/10) - updated patch submitted upstream: - changing vect_hw_misalign causes regression for vect-align-1.c * Benchmarking (1/10) - Benchmark successfully ran for linaro-gcc-5 submitted by Yvan - Benchmark for fsf-gcc-6 failed both with prebuilt route and letting job build the benchmark * Misc (3/10) - Meetings - Travel to Mumbai for Schengen Visa appointment == Next Week == - Try to get patch committed for increase_alignment - TCWG-319: Look at vect-align-1.c regression - TCWG-548: Complete implementation and validate patch. - ipa-vrp: Experiment with Kugan's patch.

9 years, 3 months

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[ACTIVITY] 6-10 June 2016

by Christophe Lyon

== Progress == * Validation - disk full on one builder caused problem during the validation of the long series of backports. We'll have to refine the cleanup policy. - switch to docker on-hold until the builders are upgraded * ABE - looked a bit at the gdb/gdbserver issue * Backports - used a script to process the spreadsheet and submitted all the backports that backflip was able to complete in batch mode (a lot!) - fsf-5-branch merge review * GCC - regression reports on trunk, chasing problems that occur in corner case configurations - One of the Neon intrinsics tests I committed recently wrongly executed v8 Neon code on v7 HW: I didn't catch this earlier because of a bug in qemu, promptly fixed by Peter Maydell - neon-testgen.ml removal delayed because other cleanup is desirable before (fixing neon* effective-target tests on-going) - started looking at PR 67591 (ARM v8 Thumb IT blocks deprecated) * Support - started looking at bug 2315 * Misc (conf-calls, meetings, emails, ...) == Next == * Validation: - patch reviews - look at disk management/cleanup * Backports - check validation results * GCC - monitor trunk regressions - fix "check_vect" guard in gcc.dg/vect tests - fix neon* effective-target - hopefully test-neongen.ml removal - pr 67591 - advsimd tests

9 years, 3 months

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[ACTIVITY] 6-10 June 2016

by Peter Smith

== Progress == TCWG-607 Initial ARM port for LLD committed upstream. Hello World on an ARM with an ARM only gcc libc is possible, but not much else. TCWG-611 Initial Thumb support sent for upstream review. Interworking is possible at the BLX level but full interworking support (veneers/thunks) isn't there yet. With this patch it will be possible to do Hello World with a recent Linaro gcc release. TCWG-634 llvm-mc putting out R_ARM_THM_PC24 for B<cond>.W instead of R_ARM_THM_PC19. Simple fix now committed upstream. == Plans == Interworking thunks for lld. The existing thunk design is very simple and only supports one type of thunk per target. For interworking we need at least two (ARM to Thumb) and (Thumb to ARM). I think it might be possible to fit a basic implementation just good enough for ARMv7a to be correct into the existing mechanism, however just one more thunk type will need a more sophisticated design. Current thought is to try and implement the basic design to learn a bit more about the mechanism as it will hopefully not take too long.

9 years, 3 months

1
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Linaro GCC vs Valgrind

by William Mills

Hello, We have been using Linaro GCC 5.x[1] and valgrind. When the optimizer is turned on valgrind complains about writes beyond the current stack pointer. With the optimizer off, the problem report goes away. I have my own conclusion about what is going on but I won't bias you with it. Here are the facts: All files and logs attached as 10K tar.gz if it survives this maillist. test.c: #include <stdio.h> int main(int argc,char** argv) { int i; for (i = 1; i < argc; i++) { printf("argument is %s\n", argv[i]); } return 0; } $ arm-linux-gnueabihf-gcc -march=armv7ve -marm -mfpu=neon \ -mfloat-abi=hard -mcpu=cortex-a15 -O2 -g \ -o test-fail test.c $ valgrind --leak-resolution=high --track-origins=yes \ --trace-children=yes --leak-check=full --error-limit=no \ ./test-fail arg1 arg2 arg3 ==20011== Memcheck, a memory error detector ==20011== Copyright (C) 2002-2015, and GNU GPL'd, by Julian Seward et al. ==20011== Using Valgrind-3.11.0 and LibVEX; rerun with -h for copyright info ==20011== Command: ./test-fail arg1 arg2 arg3 ==20011== ==20011== Invalid write of size 4 ==20011== at 0x10300: main (test.c:4) ==20011== Address 0xbdbfcb58 is on thread 1's stack ==20011== 24 bytes below stack pointer ==20011== 000102f8 <main>: 102f8: e3500001 cmp r0, #1 102fc: da000014 ble 10354 <main+0x5c> 10300: e16d41f8 strd r4, [sp, #-24]! ; 0xffffffe8 ^^^^^^^^ Complaint is here 10304: e1a05001 mov r5, r1 10308: e3a04001 mov r4, #1 1030c: e1cd60f8 strd r6, [sp, #8] 10310: e300748c movw r7, #1164 ; 0x48c 10314: e1a06000 mov r6, r0 10318: e3407001 movt r7, #1 1031c: e58d8010 str r8, [sp, #16] 10320: e58de014 str lr, [sp, #20] 10324: e2844001 add r4, r4, #1 10328: e5b51004 ldr r1, [r5, #4]! 1032c: e1a00007 mov r0, r7 10330: ebffffe4 bl 102c8 <printf@plt> 10334: e1560004 cmp r6, r4 10338: 1afffff9 bne 10324 <main+0x2c> 1033c: e1cd40d0 ldrd r4, [sp] 10340: e3a00000 mov r0, #0 10344: e1cd60d8 ldrd r6, [sp, #8] 10348: e59d8010 ldr r8, [sp, #16] 1034c: e28dd014 add sp, sp, #20 10350: e49df004 pop {pc} ; (ldr pc, [sp], #4) 10354: e3a00000 mov r0, #0 10358: e12fff1e bx lr Without the optimizer, the code looks different and valgrind does not issue any errors. 000103d8 <main>: 103d8: e52db008 str fp, [sp, #-8]! ^^^^^^^ Valgrind does not complain about this 103dc: e58de004 str lr, [sp, #4] 103e0: e28db004 add fp, sp, #4 103e4: e24dd010 sub sp, sp, #16 103e8: e50b0010 str r0, [fp, #-16] 103ec: e50b1014 str r1, [fp, #-20] ; 0xffffffec 103f0: e3a03001 mov r3, #1 103f4: e50b3008 str r3, [fp, #-8] 103f8: ea00000b b 1042c <main+0x54> 103fc: e51b3008 ldr r3, [fp, #-8] 10400: e1a03103 lsl r3, r3, #2 10404: e51b2014 ldr r2, [fp, #-20] ; 0xffffffec 10408: e0823003 add r3, r2, r3 1040c: e5933000 ldr r3, [r3] 10410: e1a01003 mov r1, r3 10414: e30004a4 movw r0, #1188 ; 0x4a4 10418: e3400001 movt r0, #1 1041c: ebffffa9 bl 102c8 <printf@plt> 10420: e51b3008 ldr r3, [fp, #-8] 10424: e2833001 add r3, r3, #1 10428: e50b3008 str r3, [fp, #-8] 1042c: e51b2008 ldr r2, [fp, #-8] 10430: e51b3010 ldr r3, [fp, #-16] 10434: e1520003 cmp r2, r3 10438: baffffef blt 103fc <main+0x24> 1043c: e3a03000 mov r3, #0 10440: e1a00003 mov r0, r3 10444: e24bd004 sub sp, fp, #4 10448: e59db000 ldr fp, [sp] 1044c: e28dd004 add sp, sp, #4 10450: e49df004 pop {pc} ; (ldr pc, [sp], #4) [1] 5.3-2016.02 for Yocto-project and cross-compile 5.2 on the ARM target "since Linaro hasn’t yet fixed building 5.3 from recipes yet." Both versions give the same results for this test program. ---------------- William A. Mills Chief Technologist, Open Solutions, SDO Texas Instruments, Inc. 20450 Century Blvd Germantown MD 20878 240-643-0836

9 years, 3 months

3
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[ACTIVITY] 6-10 June 2016

by Diana Picus

== Progress == * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing the MIR tests (PR27770) - committed upstream - Submitted a patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Submitted a patch fixing the ARM test (PR27765) - in upstream review * Use git worktree in llvm helper scripts [TCWG-587] [1/10] - Minor fixes during the review, hopefully we can wrap it up soon * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [3/10] - Investigated uses of isCortexA*, isSwift etc in the ARM backend - Started extracting subtarget features for the easy ones * LLVM ARM 3.8.1 [TCWG-642] [1/10] - Ran the ARM tests for the LLVM 3.8.1 release * Investigate clang-cmake-thumbv7-a15-full-sh failure [TCWG-635] [1/10] - Found patch that was causing problems, started discussion about it on the mailing list == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Address any code review comments - After committing the 2 remaining patches, we should be able to remove the flag and wrap this up * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] - Extract more subtarget features * OOO on Monday

9 years, 3 months

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[ACTIVITY] 30 May - 3 June 2016

by Prathamesh Kulkarni

== This Week == * LTO (6/10) a) increase_alignment (2/10) - posted patch upstream to convert it to regular pass b) TCWG-548 (3/10) - Lava job #3424 failed with timeout (same as #3370) - Experimenting with partition sizes with and without the patch for different benchmarks, results consistently show a significant difference in last partition size. - Trying a new approach. c) TCWG-535 (1/10) - posted partial patch upstream: https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00143.html * TCWG-72 (2/10) - Further patch iterations - Approved by Richard * Misc (2/10) - Looked at function versioning. - Wrote patch to address missing diagnostic in C/C++ FE, fails on bootstrap. - Meetings == Next Week == - TCWG-548: Implement new approach and experiment with it. - ipa-vrp: Apply Kugan's prototype patch, and test it, sync on early vrp. - TCWG-72, TCWG-319, TCWG-535, increase_alignment: ping for reviews. - Travel to Mumbai on Monday for Schengen Visa appointment

9 years, 3 months

1
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[ACTIVITY] Week 22

by Yvan Roux

== Progress == o Upstream GCC (4/10) - Continuing ARMv8.1 libatomic investigation (some infra issues now fixed) o Misc (6/10) * Various meetings and discussions. * patch reviews * Benchmarking notification investigation * Booked Hotel and flights for tcwg sprint == Plan == o Continue libatomic o GCC 5.4 branch merge o Benchmarking notification

9 years, 3 months

1
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[ACTIVITY] 30 May - 3 June 2016

by kugan

== Progress == Fixed Bugs and posted patches for review - PR71281 and PR71408 PR66726 - Convert expr - Found way to handle this well and posted a patch. IPA VRP - Started with a simple implementation for intra-procedural early VRP by refactoring tree-vrp. - Still need to handle range dominance - Ran into a latent issue in tree-vrp. Looking into it. == Plan == - Follow upon remaining upstream patches - IPA VRP

9 years, 3 months

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Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 3 June 2016 at 17:10, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote: > Do keep in mind you are comparing a 11 year old project and a 11 month > old one. There is a lot more churn on the 11 month old one. LLD is at least 5 years old. Every time you re-write it doesn't reset history. > Again, I am truly sorry we were unable to come up with a perfect > design the first time. For the record, I don't think it is perfect > yet. There will likely be more big changes to lld. That is the cost of > trying to build as good a linker as we can. This is not about what you do. It's about *how* you do it. We have developers trying to create a linker. They are working on LLD because Chris wanted a true LLVM linker. But it seems that you want a project that you can do whatever you want, whenever you want. This is *NOT* open source. Right now, LLD is *nothing more* than Rui's and Rafael's pet project. I cannot recommend Linaro to collaborate on those terms, and I sincerely recommend anyone that is listening to this thread to not do so either. > Being open source doesn't mean I get to implement what someone else > wants. You are more than welcome to send patches, but they have avoid > harming the rest of the linker. In particular, at this early stage > they cannot harm its development. Once we have a mature project we can > actually evaluate tradeoff. We're clearly not welcome to send patches. We did, and you re-wrote it and committed without asking the original author. So, the plan is to wait for you to finish the initial implementation alone? Again? What do we do in the interim? How many times are we going to go through this? I have waited 2 years before LLD was barely useful, then Adhemerval implemented the AArch64 back-end. Then you destroyed and now we have waited another year, but we're still unable to collaborate. If anything, now it's even harder than it was last year. Why can't we help with the design, too? We know about ARM and AArch64, that's what we do, and we can provide you with the expertise without having to go on your own doing everything. That is the whole point of collaborative development, and it seems that you're missing this point. > And just like we did, you are more than welcome to try to write > something better. Please let us know how it goes. Is this the position of every LLD developer? Rui, Nick, Chris? I'm seriously looking for others to chime in and let me know if that is the final stance on LLD, so that I can finally write it off and go work on another linker. If the official position is that LLD is a project that only Rui and Rafael can design and implement for another 2~3 years, I *cannot* recommend Linaro and its members to participate. cheers, --renato

9 years, 3 months

2
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[ACTIVITY] 1st June - 3rd June 2016

by Peter Smith

== Progress == - Holiday Monday/Tuesday - Finished writing initial support for ARM in lld. Posted upstream as RFC, no comments so far. - Implemented, but not tested the static Thumb relocations present in the arm-linux-gnueabihf-gcc -- I'd forgotten how much I hated the Thumb 2 instruction encodings. == Plan == - Add tests for Thumb relocations - Start thinking about how interworking can be implemented in lld

9 years, 3 months

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[ACTIVITY] 30 May-3 June 2016

by Yao Qi

* Monday off [2/10] # Progress # * TCWG-518, arm linux range stepping. [4/10] Finished V2, and send them out for review. More bugs in existing GDBserver are found, fixed them as well. 8 patches become 12 patches. * Upgrade linux kernel on chromebook to verify Russell King's ptrace fix. http://lists.infradead.org/pipermail/linux-arm-kernel/2016-May/431972.html [3/10] This may be the cause of unstable result of GDB floating point tests, and they are tracked by GNUTOOLS-4858. 4.6.1 is running on chromebook now, but haven't try the patch yet. * TCWG-547, "align software single step in other targets with arm's implementation". Patches are pending for review. Pinged Pedro to give a review. * Misc, [1/10] ** Commit fix to PR 19998, and review the follow-up patch. ** meeting and training, # Plan # * TCWG-518, TCWG-547, TCWG-333 -- Yao

9 years, 3 months

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[ACTIVITY] 30 May-3 June 2016

by Diana Picus

== Progress == * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing the MIR tests (PR27770) - still in upstream review - Submitted another patch fixing two other BPF tests (PR27768/9) - committed upstream - Submitted a patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Investigating the ARM test (PR27765) * Use git worktree in llvm helper scripts [TCWG-587] [4/10] - In review, hopefully we can wrap it up soon * Misc [2/10] - More LLVM backend education (MI level), ARM ARM etc == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Fix the ARM test * Use git worktree in llvm helper scripts [TCWG-587] - Fix a regression in the error-handling - Address review comments

9 years, 3 months

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[ACTIVITY] 30 May-3 June 2016

by Christophe Lyon

== Progress == * Validation - trying to improve cleanup job such that they skip offline nodes - reviews * Backports - successful backport for our gcc-6 branch * GCC - regressions reports on trunk - preparing removal of neon-testgen.ml * Misc (conf-calls, meetings, emails, ....) == Next == * Validation - prepare switch to docker for buildfarm job - cleanup * Backports * GCC - trunk monitoring - more on AdvSIMD intrinsics

9 years, 3 months

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Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 2 June 2016 at 23:22, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote: > Because the patch includes way too much and doesn't explain what it is doing. So let me get this straight: someone publishes a patch, you don't like it, you do some private investigations and commit whatever you want without even notifying the original authors? I don't know how you work at your company, but this is not how open source development works. This is not the first time either that you step over people's toes with your "design decisions" that you don't share with anyone. Last year, Adhemerval has worked for three months to get the LLD AArch64 back-end working and out of the blue, no warning, the whole back-end was yanked. It doesn't matter if it was the right decision or not in the long term, we don't just yank things, especially not before some deliberation on the list. See how long is taking for the new pass manager to be enabled, or FastIsel or the new Selection, or the new register allocators, etc. That's not how open source works and I assumed you knew that. > That is a general problem with aarch64, the documentation is missing > and comments have to make due. I had a lot of work to rewrite the > original aarch64 patches to be in line with the rest of lld and I > didn't want to have to do the same for tls. You shouldn't be rewriting *any* patch, but asking the original authors to do that themselves. There is a pattern that I'm seeing and that's that *you* refuse or dismiss more patches than most other people. There are many of your comments on reviews that are just personal, and then you step over people's toes and commits yourself. This does not scale. But more importantly, it puts into doubt the validity of the tool you're so hardly defending. You see, 3 years ago, I was asked to choose between MCLinker and LLD. MCLinker was a linker for all purposes, but Chris Lattner convinced me that LLD is the LLVM linker, and we should be focusing all efforts there. It goes against the commercial interests of Linaro members to choose such a premature technology, and it did put them back years of development, because MCLinker was very close to ready, and MediaTek, despite what people said, was very willing to accept our help. But in the interest of the community, and the open source nature of my work, I have decided to pursue LLD and managed to convince Linaro to put two people working on it. But now, I'm re-evaluating all my strategy, and sincerely, I do not trust the LLD community anymore. > The delay was because of the above mentioned issues. I wanted to make > sure there was a solid foundation. Some patches are quick to review, others take 6 months. If you work in open source you have *got* to understand that. If you're not willing to take that cost, than please, refrain from working open source. > Sorry, no. I understand your position, but you have to understand mine. I therefore call into question your ability to care about such an important project of the LLVM community. I sincerely believe that your actions are harming the project, and the people trying to help. I appreciate the value of your contribution, I really do, but if you don't change your way to handle open source contributions, LLD will, whether you like it or not, become irrelevant and be replaced. Such is the nature of open source. cheers, --renato

9 years, 3 months

2
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Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 2 June 2016 at 20:49, Rafael Espindola via llvm-commits <llvm-commits(a)lists.llvm.org> wrote: > Author: rafael > Date: Thu Jun 2 14:49:53 2016 > New Revision: 271569 > > URL: http://llvm.org/viewvc/llvm-project?rev=271569&view=rev > Log: > Start adding tlsdesc support for aarch64. > > This is mostly extracted from http://reviews.llvm.org/D18960. Rafael, Why commit part of Adhemerval's patch without reviewing his request? This is a really serious breach of community trust. Not only we're waiting for reviews on the TLS set of patches and having to rebase every two weeks, but now you implemented in a way that wasn't discussed on the review, didn't mention authorship, nor asked Adhemerval for any input. If you had technical input on his patch, you should have done on the review. If you wanted him to split in smaller patches, you should have asked on the review and let *him* do it. Even if you were the code owner (which you're not), it would still be a *serious* breach of trust and respect. I hereby respectfully request that you revert your patch and let Adhemerval finish the work that he started in the way that we normally do in the LLVM community. regards, --renato

9 years, 3 months

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[ACTIVITY] 23 - 27 May 2016

by Yao Qi

* Off on Friday [2/10] # Progress # * TCWG-518, V1 got reviewed, and working on V2. Two existing bugs in GDBserver are found, and fixed. Testing them... [4/10] * Upstream patches review, all of them are about GDB python. [2/10] * Respond to Jim Wilson's question on AIX GDB build failure caused by his binutils patch for AArch64. Confirm that GDB build fail after his patch. [1/10] * Misc, [1/10] # Plan # * Bank holiday on Monday, * TCWG-518, get V2 ready for review, * Ping TCWG-561 and TCWG-547, -- Yao

9 years, 3 months

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[ACTIVITY] 23 - 27 May 2016

by Omair Javaid

=== This Week === Resolved TCWG-231 (LLDB bring up and bug fixing on HiKey 96Board) [TCWG-231] [1/10] -- Ran tests on AArch64 LLDB tests on HiKey and compared with Nexus 9 test results. -- Less than 1% difference in test results and good pass rate found. LLDB ARM: Bug fixes, integration and testing on various ARM platforms [TCWG-228] [2/10] -- Progressed towards resolution. -- Prepared close out setting up RaspberryPi2, RaspberryPi3, Hikey and Chromebook as testers. -- Compiled armhf test results. LLDB Chromebook Test Stability [TCWG-563] [2/10] -- Some further investigation on llvm-chrome-06 test failures. -- Marked and committed some xfails and reported relevant bugs if not already logged. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [1/10] -- Debugging of watchpoint handling code and tried out instruction decding. LLDB buildbot updates and maintenance [TCWG-241] [2/10] -- Improved tester script to initiate lldb-server inside a chroot. -- Monitored buildslave stability and Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Migrated laptop to Ubuntu 16.04 === Next Week === LLDB Chromebook Test Stability [TCWG-563] -- Final words on watchpoint issue on llvm-chrome-06 -- Submit updated makefile.rulez for LLDB tests. -- Report remaining bugs and commit xfails upstream. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Implement instruction decoding for watchpoint hit detection. A look into kernel code used by Nexus android devices failing watchpoint support [TCWG-622] Miscellaneous -- Out of office on Tuesday 31st 2016 for visa documents preparation.

9 years, 3 months

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[ACTIVITY] Week 21

by Yvan Roux

* ! day off (2/10) == Progress == o Extended validation (2/10) - Benchmarking comparison script on-going - Reproduced armhf schroot slowness on AArch64 Debian Jessie No issues when using Ubuntu (Trusty and Xenial). o Upstream GCC (4/10) - Started ARMv8.1 libatomic support (environment setup, code understanding, ifunc support analysis) o Misc (2/10) * Various meetings and discussions. == Plan == o Continue libatomic work

9 years, 3 months

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[ACTIVITY] 23 - 27 May 2016

by Prathamesh Kulkarni

== This Week == * TCWG-72 (6/10) - Patch iterations based on Richard's suggestions - Reworked most of convert_to_divmod() - Fixing regressions with the patch and added test-cases. - ICE with -m32 on x86_64 for DImode division/mod: https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02302.html * LTO (2/10) a) TCWG-548 (1/10) - Benchmarking jobs submitted twice and failed. b) TCWG-535 (1/10) - Figured out why ICE happens with my patch. * TCWG-319 (1/10) - Validated patch and posted upstream. * Misc (1/10) - Meetings == Next Week == - TCWG-72: Try to workaround issue with -m32 - TCWG-548: start relooking at section anchors. - TCWG-535: Post patch upstream.

9 years, 3 months

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[ACTIVITY] 23-27 May 2016

by kugan

== Progress == PR71252 - ICE in rewrite_expr_tree - Tried various options to fix this and settled on an implementation - Patches sent for upstream review - tested with cpu2006 too - One patch approved PR66726 - Convert expr - Newlib test case is failing due to mi compiled lib - Trying to reduce test case == Plan == Follow upon remaining upstream patches IPA VRP

9 years, 3 months

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[ACTIVITY] 23-27 May 2016

by Peter Smith

== Progress == * LLD Port: - Got hello world running. -- Needed a horrible hack to make lld output PLT and GOT entries for unresolved weak references with default visibility. - Wrote up in Jira the major areas of work that would be needed for a useful port. - Started putting in changes cleanly and writing tests for them. - Currently hitting a few problems with llvm-mc. I can't generate the relocations I need to test the linker. The hello world test case used mainly GCC library objects. -- Most serious is not emitting R_ARM_BASE_PREL for .word _GLOBAL_OFFSET_TABLE - (label+8) == Plan == * On holiday Monday and Tuesday * LLVM MC See how easy it would be to add missing features to llvm-mc as it would allow me to write more tests. * LLD Complete the test cases for the code I've added. Take stock of where the lld port is and decide where to go from there. Options are: - Send an RFC upstream with what I have. It is not sufficient to run hello world but should be relatively uncontroversial. - Cleanly implement the emit the unresolved weak references in the PLT and GOT so hello world will work out of the box on ARM. - Keep going until I've got Thumb2 support so I don't have to use ARM only static libraries to make hello world working. There is obviously a trade off between having a useful linker and the patch size getting out of hand.

9 years, 3 months

1
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[ACTIVITY] 23-27 May 2016

by Diana Picus

== Progress== * Remove exit-on-error flag from CodeGen tests [TCWG-604] [5/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Last week's patch fixing the MIR tests (PR27770) - still in upstream review - Last week's patch fixing an AMDGPU test (PR27762) - committed upstream - Last week's patch fixing a BPF test (PR27766) - committed upstream - Submitted another patch fixing a BPF test (PR27767) - committed upstream - Submitted another patch fixing two other BPF tests (PR27768/9) - in upstream review - Investigating one of the AMDGPU tests (PR27761) * Use git worktree in llvm helper scripts [TCWG-587] [4/10] - Started a RFC and a wiki page about the new workflow [1] - People seem to be in favour of it, but there are still some TODOs left before we can merge * Misc [1/10] - Meetings, buildbots == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Submit a patch for the AMDGPU test (PR27761) - More investigations on the ARM test (PR27765) * Use git worktree in llvm helper scripts [TCWG-587] - Finish the final touches and have a proper review [1] https://collaborate.linaro.org/display/LLVM/Git+Worktree+Proposal

9 years, 3 months

1
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[ACTIVITY] 23-27 May 2016

by Christophe Lyon

== Progress == * Validation - cleanup - Fixed regressions in abe (gcc_update, make install, gdb timestamps) - updated abe stable branch (now matches master) - various Jenkins jobs updates, prepared support for gcc-6 based toolchains - compared results of armv8l vs arm toolchains: few, expected differences due to different default tuning * GCC - regressions reports on trunk * Misc (conf-calls, meetings, emails, ....) == Next == * Validation - actually update the Backport job - prepare switch to docker for buildfarm job - cleanup * Backports * GCC - trunk monitoring - more on AdvSIMD intrinsics

9 years, 3 months

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Re: toolchain fetch issues

by Gujulan Elango, Hari Prasath (H.)

Sorry for hitting the wrong mailing list. OK I will check with HTTP instead of HTTPS. Thanks for your time & help. On May 25, 2016 11:02 PM, Jim Wilson <jim.wilson(a)linaro.org> wrote: On Wed, May 25, 2016 at 8:09 AM, Gujulan Elango, Hari Prasath (H.) <hgujulan(a)visteon.com> wrote: > I enabled the -v option of wget and I am able to see the download starts and > fails randomly after progressing to some extent i.e. 10% or 27%. The > connection is reset by peer and wget exits. I tried increasing the timeout > option of wget as well. This is some kind of networking or web server problem. We only know how to fix compiler problems here on the linaro-toolchain list. I did confirm that I can download the file OK, both via wget and via chrome.. I noticed that the https support on releases.linaro.org is not working, and I had to use http instead, but it isn't clear if that is related to your problem. Jim

9 years, 3 months

1
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toolchain fetch issues

by Gujulan Elango, Hari Prasath (H.)

Hello, We have cloned the meta-linaro layer and when we build,we are facing some issues when the do_fetch() task is executing for the gcc-source-linaro-5.1 package. I enabled the -v option of wget and I am able to see the download starts and fails randomly after progressing to some extent i.e. 10% or 27%. The connection is reset by peer and wget exits. I tried increasing the timeout option of wget as well. Any idea what's wrong. Find attached the log of the error. Thanks & Regards, Hari Prasath

9 years, 3 months

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missing gold --be8 support

by Jim Wilson

Cisco is trying to use clang/lto on big-endian arm, which apparently requires gold, and gold does not support the --be8 option which is required for ARMv7 big-endian support. Does anyone here care about this? Umesh Kalappa asked about this on the binutils mailing list https://sourceware.org/ml/binutils/2016-05/msg00209.html and discovered that it is a known bug reported 5 years ago https://sourceware.org/bugzilla/show_bug.cgi?id=13213 Jim

9 years, 3 months

3
5
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[ACTIVITY] Week 20

by Yvan Roux

== Progress == o Extended validation (7/10) * Investigate GDB instabilities: - branch tracing issue are due to builder feature support - Our 2 old builders, which don't support it, removed from x86 validation pool * Benchmarking: - Looked at Lava instance API and lava-tool usage and prerequisite - Implementing comparison script o Misc (3/10) * Various meetings and discussions. == Plan == o Continue on validation/benchmarking o Catch up with upstream work.

9 years, 3 months

1
0
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[ACTIVITY] 16 - 20 May 2016

by Omair Javaid

=== This Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [3/10] -- Made changes to NativeRegisterContext_arm64 to support multiple watchpoint slot for a single watch address. -- Enabled unaligned watchpoints and experimented with resulting false positives. LLDB Chromebook Test Stability [TCWG-563] [3/10] -- Migrated local builder to Ubuntu 16.04 xenial -- Ran LLDB testsuite with GCC 5.x.x on chromebook, raspberryPI2 -- Updated LLDB testsuite makefile.rulez to use correct cross AR and OBJCOPY LLDB buildbot updates and maintenance [TCWG-241] [2/10] -- Investigation of LLDB buildbot slave failure -- Implemented stale log deletion mechanism by making sure we keep only 10 most recent logs. LLDB upstream collaboration and Arm/AArch64 Linux port maintenance [1/10] -- Verify patches under review -- Analyzed TestTopLevelExprs on LLDB arm failure and committed xfail. Miscellaneous [1/10] -- Meetings, emails, discussions etc. -- Travel bookings for connect and TCWG sprint. === Next Week === Close out TCWG-231 (LLDB bring up and bug fixing on HiKey 96Board) -- Run and comparison of AArch64 LLDB test results vs hikey showing less than 5% difference. Close out LLDB Chromebook Test Stability [TCWG-563] -- Make sure there are no failures for which we dont know the underlying reason. -- Report remaining bugs and commit xfails upstream. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Further testing of false positive results due to allowing un-alligned watch-points. LLDB buildbot updates and maintenance [TCWG-241] -- Figure out difference of test results between local and remote chromebooks. -- Figure out a way to hide unused test slots by buildbot factory. Miscellaneous -- Migrate laptop to ubuntu 16.04 in hope of better driver support. -- Portugal visa and travel booking

9 years, 3 months

1
0
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[ACTIVITY] 16=20 May 2016

by Christophe Lyon

== Progress == * Validation - cleanup - reviews - asserting ABE master vs stable results - stopped investigation on a huge number of unexpected regressions, maybe caused by builders crashes - created a Jenkins job able to detect the base GCC branch, in order to select the right libc/binutils version - found why ABE master showed regressions with the _Pragma3 GCC test. Fix under review. - investigating recent, numerous build failures * Backports - updated backport to fix bug #2185 after Kugan analysis - drafted a script to parse the spreadsheet and generate the backflip commands as appropriate * GCC - reported a couple of regressions on trunk - Neon intrinsics tests update: committed. We are now ready to remove neon-testgen.ml == Next == * Validation - cleanup - armv8l vs arm - ABE master vs stable * GCC - trunk monitoring - more on AdvSIMD intrinsics

9 years, 3 months

1
0
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[ACTIVITY] 16 - 20 May 2016

by Kugan Vivekanandarajah

== Progress == PR40921 -missed optimization: x + (-y * z * z) => x - y * z * z - Patch committed PR63586 - x+x+x+x -> 4*x in gimple - Patch committed - There were couple of fallouts PR71179 - ICE fold_convert_loc, at fold-const.c:2360 - Patch committed PR71170 - ICE in rewrite_expr_tree, at tree-ssa-reassoc.c:3898 - Tried various options to fix this and settled on an implementation - Patch sent for upstream review == Plan == Follow upon remaining upstream patches IPA VRP

9 years, 3 months

1
0
0 0

[ACTIVITY] 16-20 March 2016

by Prathamesh Kulkarni

== This Week == * TCWG-528 (2/10) - Addressed comments from Richard and committed upstream (r236502, r236503) * TCWG-72 (5/10) - Updated patch and fixed regressions caused due to patch. * TCWG-319 (1/10) - Found why big endian vectorizer was not vectorizing the test-case with -O2. * Holiday (2/10) == Next Week == - TCWG-319: Post patch upstream and get it committed. - TCWG-72: Post patch upstream and hopefully get it committed this week. - TCWG-548: Start re-looking at section anchors.

9 years, 3 months

1
0
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[ACTIVITY] 16 - 20 May 2016

by Peter Smith

=== Progress === TCWG-591 MOVW incorrectly allowed on ARM v5 committed upstream TCWG-595 LLD port to ARM architecture I am getting close to being able to run hello world built with lld. I'm converging 1 bug at a time. - The PLT handling code is working and the loader can execute the image and starts the .init function. - Currently failing in the weak call to __gmon_start__. At present lld is removing undefined weak references from executables instead of passing them on for the dynamic loader to resolve. This may not be necessary on x86 but it is necessary on ARM. -- Just finished a hack that should make this work, although it will need some tidying up. === Plan === Get hello world working and then take stock of what I've learned and come up with a plan in Jira for what needs to be done.

9 years, 3 months

1
0
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[ACTIVITY] 16-20 May 2016

by Diana Picus

== Progress == * Add a diag handler for llc so it doesn't exit on the first error it finds [TCWG-592] [1/10] - Fixed and rebased the patch, it has been committed upstream * Inline assembly constraints support for ARM [TCWG-560] [1/10] - Rebased the patch, it has been committed upstream * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Submitted a patch fixing the MIR tests (PR27770) - in upstream review - Submitted a patch fixing an AMDGPU test (PR27762) - in upstream review - Submitted a patch fixing a BPF test (PR27766) - in upstream review - Investigated the ARM test (PR27765) * Use git worktree in llvm helper scripts [TCWG-587] [3/10] - Working on a prototype * Misc [1/10] - Meetings, buildbots, IRC issues - Got LLVM commit access, yay! == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Fix the remaining ARM, BPF and AMDGPU tests (unfortunately the ARM test seems a bit more involved, so I might pick out the others first just to get them out of the way) * Use git worktree in llvm helper scripts [TCWG-587] - Continue prototyping, start a RFC on it next week

9 years, 3 months

1
0
0 0

[ACTIVITY] 16 - 20 May 2016

by Yao Qi

# Progress # * TCWG-518, [6/10] fix all bugs, and post them upstreams for review! * PR 19998, write a patch to fix it. [2/10] * Some discussions on unstable GDB test results in validation tests. [1/10] * Meetings [1/10] # Plan # * Respond comments to my patches, * TCWG-333, think about the right fix. -- Yao

9 years, 3 months

1
0
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Re: Issues with accessing TLS of shared object

by Bill Fischofer

This may be a better question for the linaro tools group. +cc their list for the general question of conventions surrounding how shared library objects identify and access thread-local storage that they need as part of calling threads. On Tue, May 17, 2016 at 11:06 AM, Nikhil Agarwal <nikhil.agarwal(a)linaro.org> wrote: > Hi All, > > I am trying to write a shared library object over ODP. Our ODP library has > some per thread variables. When my application invokes an API of shared > object which accesses per thread variable it gives segmentation fault. > > My concern is that when a shared object is loaded dynamically, how memory > is assigned to thread specific variables defined inside shared objects. > AFAIK we need to compile it with -ftls-model=global-dynamic, which is > enabled by default when compiled with -fPIC flag, and library loader > takes care for these issues. > > I am not an expert in this area, please help me in getting to some > suitable reference pointers or some steps I might have missed. > > Thanks in advance > > Nikhil >

9 years, 4 months

3
2
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[ACTIVITY] 09 - 13 May 2016

by Omair Javaid

=== This Week === Enable LLDB testsuite to show zero failures on Hikey 96 Board (AArch64 Linux) [TCWG-231] [4/10] -- Ran multiple builds and testsuite runs to figure out latency issues. -- Investigated remaining failures and submitted appropriate bugzilla bugs. -- Committed xfails upstream. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [1/10] -- Some investigation on possible solutions and frequently encountered scenarios. LLDB Chromebook Test Stability [TCWG-563] [3/10] -- Investigation of noreturn unwinding test failure -- Investigation of step over load library call failure -- Investigation of other failures and commit xfails for reported issues. Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Portugal visa information gathering === Next Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Add code changes required to manage a watchpoint with multiple hardware watchpoint resources. LLDB Chromebook Test Stability [TCWG-563] -- Fix noreturn unwinding test failure and report relevent bug. -- Fix step over load library call failure or report relevent bug. Miscellaneous -- Portugal visa application documents preparation.

9 years, 4 months

1
0
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[ACTIVITY] 9-13 May 2016

by Christophe Lyon

== Progress == * Validation - cleanup - reviews - looked a bit a using docker from Jenkins - investigating how to select toolchain components versions depending on the gcc version * GCC - Sent Neon intrinsics tests patches. - trunk timeouts: caused by the libcilkrts merge, which has a bug on arm. Disabled cilkplus to avoid too much noise in the results. - reported a couple of regressions/bisects * Misc (conf-calls, meetings, emails, ....) - support for M-profile related queries ( multilib etc...) == Next == * Validation - cleanup - reviews - armv8l vs arm - multiple gcc branches vs other components versions handling * GCC - trunk monitoring - some dev if time permits

9 years, 4 months

1
0
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[ACTIVITY] Week 19

by Yvan Roux

== Progress == o Linaro GCC (5/10) * Linaro GCC 5.3 2016.05 snapshot - FSF branch merge + release * Linaro GCC 6.1 2016.05 snapshot - Create new branch + release o Extended validation (3/10) * Fixed validation issues when binary tarballs are created. o Misc (2/10) * Various meetings and discussions. == Plan == o Continue on validation/benchmarking o Catch up with upstream work.

9 years, 4 months

1
0
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[ACTIVITY] 9-13 May 2016

by Diana Picus

== Progress == * Add a diag handler for llc so it doesn't exit on the first error it finds [TCWG-592] [5/10] - Started a discussion about a new diagnostic handler for llc - Patch accepted upstream, but broke a few things (Renato has investigated/fixed some of them - thanks) * Inline assembly constraints support for ARM [TCWG-560] [5/10] - Patch in upstream review, but should be committed after the new llc diagnostic is in place (otherwise it's difficult to test it meaningfully) == Plan == * Add a diag handler for llc so it doesn't exit on the first error it finds [TCWG-592] - Fix the remaining issues and get the patch committed again * Inline assembly constraints support for ARM [TCWG-560] - Rebase patch and try to get it reviewed * Investigate exit-on-error on LLC [TCWG-594] - Track the tests that need the exit-on-error flag with the new diagnostic handler

9 years, 4 months

1
0
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[ACTIVITY] 9-13 May 2016

by Peter Smith

== Progress == - ldr rt,= implementation transform to MOV committed upstream [TCWG-468] [PR25722]] -- Thanks to Renato for committing. - Started looking at what would be needed to port lld to ARM -- The ELF lld port looks to have a fairly small amount of architecture specific hooks. Decided that I would learn fastest by just trying to do an ARM only prototype port to see if I could get hello world on linux working. -- spent too much time trying to think about how to best implement the group relocations for the PLT sequences then remembered that for a quick prototype I could use larger sequences that didn't need the relocations. == Plan == - Continue working on an ARM LLD port. Will hopefully have a good idea of what the scope of work needed is next week.

9 years, 4 months

1
0
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[ANNOUNCE] Linaro GCC 5 and 6 2016.05 snapshots

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.05 snapshot of both Linaro GCC 5 and Linaro GCC 6 source packages. Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn236106 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.05/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.1+svn236106 Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.3+svn236108 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn236108 * Backport of [Bugfix] [AArch32] PR target/70711 Fix big-endian ARMv8.1-A builds * Backport of [Bugfix] [AArch64] PR target/70044 -flto turns on -fomit-frame-pointer * Backport of [AArch32] Reduce size of arm1020e automaton * Backport of [AArch64] Fix SIMD predicate * Backport of [AArch64] Fix thinko in handling of -momit-leaf-frame-pointer option * Backport of [Testsuite] [AArch32] Tests for arm_restrict_it patterns in thumb2.md * Backport of [Testsuite] gcc-dg: handle all return values when shouldfail is set Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

9 years, 4 months

1
0
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[ACTIVITY] 2-6 May 2016

by Diana Picus

== Progress == * 3 days off (Mon/Thu/Fri) [6/10] * Inline assembly constraints support for ARM [TCWG-560] [3/10] - More investigations for PR24071; found the cause of the bug, working on a fix. * Rework LLVM helper scripts [TCWG-571] [1/10] - Addressed code review comments. - The interface changes to llvm-projs and llvm-sync are now committed. == Plan == * Inline assembly constraints support for ARM [TCWG-560] - Come up with a fix for PR24071 * Rework LLVM helper scripts [TCWG-571] - Investigate git worktree and how it could be factored into our scripts (llvm-projs, llvm-build)

9 years, 4 months

1
0
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[ACTIVITY] Week 18

by Yvan Roux

o 2 days off (4/10) == Progress == o Extended validation (4/10) * Change extended native job to use multiple scm * Investigate validation issues when binary tarballs are created o Linaro GCC (1/10) * Finalized and submitted new Linaro development branch script. o Misc (1/10) * Various meetings and discussions. == Plan == o Create Linaro GCC 6 branches o Continue on validation and upstream work.

9 years, 4 months

1
0
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[ACTIVITY] 2-6 May 2016

by Christophe Lyon

* 2 days off (Thu/Fri) == Progress == * Validation - restarted validations for pending backports, after the various branches updates - started looking at armv8l vs arm results differences * GCC - checked trunk regression reports - updated AArch32 Neon intrinsics tests. Patch series almost ready for submission * Misc (conf-calls, meetings, emails, ....) == Next == * Validation - cleanup - reviews - armv8l vs arm * GCC - trunk monitoring: check why builds were killed after timeout - more intrinsics tests

9 years, 4 months

1
0
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[ACTIVITY] 2 - 6 May 2016

by Prathamesh Kulkarni

== This Week == * LTO (7/10) a) TCWG-548 (2/10) - Fixed a minor bug in the patch - Results of variable partitions with chromium: http://pastebin.com/fLD2JzgP - Significant difference in size of last partition could probably indicate sth wrong with patch (all unpartitioned variables go to last partition). b) TCWG-528 (3/10) - Posted upstream after bootstrap+test passed on ppc64le-linux-gnu - Addressed Richard's comments. c) TCWG-299 (2/10) - Firefox built on aarch64 natively (r1-a12) non LTO with gcc-5 branch - Fails to build with trunk due to issues in firefox codebase (PR70722) - Fails to build on armhf with following error: http://pastebin.com/9xydVtjj * TCWG-72 (2/10) - Rebased patch - Addressed Ramana's comments * Misc (1/10) - Meetings == This Week == - LTO: benchmark section anchors patch, submit patch for increase_alignment upstream, firefox - TCWG-72: Test and submit upstream

9 years, 4 months

1
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[ACTIVITY] 02 - 06 May 2016

by Peter Smith

* Monday off [2/10] # Progress # * TCWG-468, ldr rt, =immediate Have a feature complete implementation. Passes existing regression tests. Still need to add more tests for new functionality and see if implementation can be tidied up a bit * Setting up a local chromebook to run the regression-tests. Should now be able to run test suite on ARM relatively easily. # Plan # * Complete TCWG-468 and send upstream for review. * Pick something else up.

9 years, 4 months

1
0
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[ACTIVITY] 02 - 06 May 2016

by Yao Qi

* Monday off [2/10] # Progress # * TCWG-518, arm linux range stepping patches. [5/10] Tried different ways to manage breakpoints, but the program still gets SIGILL from time to time. Post my WIP patches upstream to see if people have some ideas on this. * TCWG-547, [1/10]. Try two approaches but give up due to the quite aggressive interface changes. Fortunately, the change in the third approach is quite small, testing the patch. * Misc, meeting, [2/10] # Plan # * TCWG-518, TCWG-547 -- Yao

9 years, 4 months

1
0
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[ACTIVITY] 18 - 22 April 2016

by Kugan

== Progress == * GCC Stage-1 (5/10) - Posted patches and revised based on review - PR40921 and PR63586 - Getting ready post type promotion pass again * Linaro bug (2/10) - BUG 2195 and BIG 1979 - Investigation with trunk and educed test case shows Missing commit * Misc (1/10) - GCC Lists * Public holiday (2/10) == Plan == * Attend to pending stage1 patches

9 years, 4 months

1
0
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[Weekly] 25-29 April 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (0/10) - Pinged upstream; no response yet * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store (6/10) - Created updated patch that resolves 8/9 failures - Investigating execution failure on gcc.dg/fixed-point/convert-sat.c * TCWG-247 - Create Validation Job to run on GCC Trunk Commit (3/10) - Addressed all comments from code reviews and submitted final version * Misc (1/10) - Meetings == Next week == * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store - Resolve testsuite failure * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (0/10) - Ping upstream

9 years, 4 months

1
0
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[ACTIVITY] Week 17

by Yvan Roux

o 1 day off (2/10) == Progress == o Extended validation (2/10) * Extended validation now operational, reporting enhancements investigations. * Looked at gdb/guality unstable results. * Reviewed some jobs. o Linaro GCC (2/10) * Scripted new Linaro development branch process. o Upstream GCC (1/10) * Digging in libatomic code. o Misc (3/10) * Various meetings and discussions. == Plan == o 2 days off (Thu/Fri) o Continue on validation and upstream work.

9 years, 4 months

1
0
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[ACTIVITY] 25-29 April 2016

by Prathamesh Kulkarni

== This Week == * LTO (6/10) a) TCWG-128 (1/10) - committed patch for adding param lto-max-partition, which can now be used as workaround for building chromium with minimal number of required partitions. - committed patch for setting default value of lto-min-partition to 10000. b) TCWG-528 (1/10) - Patch: http://people.linaro.org/~prathamesh.kulkarni/patch_increase_alignment.diff - Cross tested on arm*-*-*, aarch64*-*-* and bootstrapped and tested on aarch64-linux-gnu - I want to cross test once for ppc64 since that's also affected. c) TCWG-548 (4/10) - Patch: http://people.linaro.org/~prathamesh.kulkarni/patch-vars-3.diff - Cross tested for arm*-*-* and aarch64*-*-* * TCWG-319 (2/10) - Comparing diff's of vect for arm and armeb shows, armeb not supporting unaligned access - Looking thru arm backend code to see why this happens. * Validation (1/10) - Script to build chromium * Misc (1/10) - Looked at PR70848, PR60172 - Meetings == Next Week == LTO: section anchors, increase_alignment pass TCWG-319: Continue investigation Validation: Try to get the script merged to tcwg-buildapp repo.

9 years, 4 months

1
0
0 0

[ACTIVITY] 25 - 29 April 2016

by Peter Smith

# Progress # * TCWG-466, ADRL pseudo instruction support in integrated assembler. I couldn't find a way of putting ADRL into the assembler in a maintainable way. Managed to work out a pretty close approximation of ADRL in a macro so I added it to upstream PR. Put the results of the my investigations into TCWG-466. Agreed with Renato's initial diagnosis of won't fix. * TCWG-468, Transform LDR rn, =expr pseudo instruction into MOV. I'm more hopeful with this one. I've got a prototype that delays the emission of the constant pool entry to a point where the transformation can occur. * Try out the build and push scripts. Had a frustrating day of chasing down missing dependencies from my Ubuntu 12.04 machine while building lldb. Should be resolved now. # Plan # * UK national holiday on Monday. * Continue with TCWG-468. I've got a tablegen prototype that treats LDR rd,= as a real pseudo instruction. Need to finish Thumb and Thumb2. Next step after that is to do the transformation to MOV. * Will spend any other time investigating LLD

9 years, 4 months

1
0
0 0

[ACTIVITY] 25 - 29 April 2016

by Yao Qi

# Progress # * TCWG-518, range stepping on arm-linux. Rebase my patches, and choose a different approach which is better. However, GDBserver crashes in some cases, and I am investigating the crash. [5/10] * TCWG-547, make some progress on the upstream discussion. We agree to do it in a cleaner way but some GDB internal interface needs some changes. [2/10] * Read some articles about exception handling, this one is quite useful, https://gcc.gnu.org/ml/gcc/2002-07/msg00391.html [1/10] * Meeting, upstream patch review. [2/10] # Plan # * TCWG-518, TCWG-547 -- Yao

9 years, 4 months

1
0
0 0

[ACTIVITY] 25-29 April 2016

by Diana Picus

== Progress == * Rework LLVM helper scripts [TCWG-571] [4/10] - Code review + minor improvements to the scripts - Started a discussion about the interfaces of some of the scripts (llvm-projs, llvm-sync) * Inline assembly constraints support for ARM [TCWG-560] [3/10] - More investigations for PR24071 - Discovered that the assert is only triggered for aarch64-linux-gnueabi, whereas arm-linux-gnueabi behaves as expected (prints the error but doesn't assert afterwards). This has proven useful for figuring out the intended behavior of the code. * Move buildbots to CMake 3.4.3 [TCWG-573] [1/10] - Helped move some of the bots (llvm-a15-*) to CMake 3.4.3 * Misc [2/10] - Buildbot monitoring - Meetings == Plan == * Inline assembly constraints support for ARM [TCWG-560] - Come up with a fix for PR24071 * Rework LLVM helper scripts [TCWG-571] - Start a review for the new interface to llvm-projs/llvm-sync, so we can have some concrete support for further discussion - Investigate git worktree and how it could be factored into our scripts (llvm-projs, llvm-build) * Move buildbots to CMake 3.4.3 [TCWG-573] - Help with the llvm-chrome-* bots if necessary * OOO on Monday

9 years, 4 months

1
0
0 0

[ACTIVITY] 25-29 April 2016

by Christophe Lyon

== Progress == * Validation - armvl8 differences between master and stable branches understood (master defaulted to Thumb) - updated ABE stable branch for validation - ABE now uses linaro-local/stable DejaGnu branch - updated ABE legacy version to use this DJ branch too, and updated the Foundation Model path - updated Jenkins jobs accordingly * Backports - created a few backports for our gcc-5 branch, to prepare handover - slight documentation update * GCC - enhancements to validation harnesses to better handle infrastructure problems - using monitoring and regressions reports * Cortex-strings - updated a few aarch64 mem* routines from newlib versions * Support - finally reproduced the Windows-hosted toolchain bugs by rebuilding in a properly updated Jessie chroot. - building the next release in Trusty container should fix these problems * Misc (confi-calls, meetings, emails, ....) == Next == * Validation: cleanup & reviews * GCC - trunk monitoring, report regressions if needed - more intrinsics tests

9 years, 4 months

1
0
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RE: [ACTIVITY] 18-22 April 2016

by Rob Savoye

As a note, all the builders we use for binary releases run Trusty still. I haven't tried Jessie (should work fine),but I know that newer Mingw releases fail to compile GCC 5.x. - rob - -------- Original message -------- From: Christophe Lyon <christophe.lyon(a)linaro.org> Date: 04/22/2016 14:00 (GMT-07:00) To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org> Subject: [ACTIVITY] 18-22 April 2016 * 3 days off == Progress == * Validation: - fixed ABE master and stable branches to use 'ssh -t' instead of 'ssh -tt' when cross-testing - trying to assert master vs stable before the array branch merge, noticed differences on armv8l - created linaro-local/stable Dejagnu branch (currently a copy of master). Prepared ABE config patches to use it. * GCC - infrastructure problems (ST compute farm), leading to a lot of noise in the validations (and wrong regression reports upstream) - enabled gcc-6-branch monitoring - added GCC-6 tab to the backports spreadsheet * Support - Windows-hosted toolchain crashes: it seems the builders we use to make the release run Jessie and not Trusty. Tried to rebuild a toolchain in a Jessie chroot, but the script failed (works under Trusty) * Misc (conf-calls, meetings, emails, ...) == Next == * Validation - check that using linaro-local/stable Dejagnu branch works well - create validation reference points before array branch merge - understand/fix armv8l validation differences between master/stable ABE branches * GCC - trunk monitoring, report regressions if needed - more intrinsics tests * Support - Windows-hosted toolchain bug * Snapshots - prepare a few backports for our gcc-5 branch * Cortex-strings update _______________________________________________ linaro-toolchain mailing list linaro-toolchain(a)lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

9 years, 4 months

3
6
0 0

[ACTIVITY] 18 - 22 April 2016

by Omair Javaid

== Progress == LLDB Chromebook Test Stability [TCWG-563] [3/10] -- Failures reduced to 15 fails and 4 errors after fixing stepping bug. -- Investigated remaining issues some of them are known issues and others will need further investigation. LLDB ARM Thread Stepping Problem [TCWG-566] [5/10] -- Problems caused because incorrect reporting of PLT entry size set by linker. -- Submitted a fix after analysis that logical size of PLT entry should be greater than 4bytes. -- Fix accepted and committed upstream. LLDB Buildbot Setup [TCWG-241] [1/10] -- Random change in results finally caught. It was due to inconsistent network. -- Progress halted to fix arm-linux-gnueabihf bugs. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB Chromebook Test Stability [TCWG-563] -- Continue to resolve and investigate chromebook test failures. LLDB Buildbot Setup [TCWG-241] -- Start AArch64 tester evaluations.

9 years, 4 months

1
0
0 0

[ACTIVITY] Week 16

by Peter Smith

Progress: - On holiday all week, at ACCU conference. I've put some highlights at the end of the message. - Did some more investigation into TCWG-466 ADRL support in integrated assembler during breaks. -- Not looking good, to do this properly bumps up against a lot of design decisions and restrictions made by the LLVM assembler (designed as compiler target, not to be user friendly). -- There are ways it could be implemented with restrictions, but it is debateable whether it is worth doing at all. -- On the plus side I've got a much better idea of how the assembler works and what restrictions exist on each stage of the journey from a line in the .s file to emission in the object. Will add some comments to the LDR r0, =expr TCWG as well. -- On the negative side the :upper16: and :lower16: operators for MOVT and MOVW don't look to be correct in the presence of addends. Will need to investigate further to see what the scope of the problem is. Plan: - Dump results of TCWG-466 investigation into Jira. - Take a look at and post a comment on Adhemerval's revised TLS patch, even if it is just looks fine in the hope of pushing it forward a bit more. - Catch up with Renato's scripts and documents for LLVM sub-group. - Work out what to do with TCWG-466, if the answer is put it down, find something else to look at. ACCU Highlights/Report: Tough stuff in modern C++ A deep dive into some of the newer areas of C++ such as: - rvalue references and forwarding (universal) references - How to use SFINAE (mostly std::enable_if) to select algorithms optimised for particular template instantiations - Variadic templates. Including all sorts of strange ways to (ab)use expansion of parameter packs. C++ WG21 SG14 Gaming and low-latency study group - A new study group aiming to represent the gaming (primarily), but also embedded and high frequency trading concerns. - Motto seemed to be make sure "Don't pay for what you don't use" is enforced. Most interested in: -- No exceptions configurations -- No RTTI -- More performance out of the STL (see EA STL https://github.com/electronicarts/EASTL) -- Add ring buffers and support for unitialised memory, fixed point numbers, flat-map, standardised simd vector types Using sentinels - An example of how using two sentinels in an implementation of std::partion speeds up the algorithm by saving comparisons. Can speed up quicksort by a few percent Constexpr in C++14 - Example showing how you could build a string to enum map, operating entirely at compile time, and its subsequent negative effects on compile time! Concepts Lite - Concepts missed the C++17 standard, this presentation went into the current Technical Standard (optional) and how concepts would likely be implemented in C++(20?) - Not surprising to see that concepts still missed C++17 as there is only one implementation and one non-trivial use case (ranges) and there are still unresolved questions to be answered. Introduction to Julia - Really a comparison of Julia to the author's favoured language of common lisp. - Was impressed at how "lispy" Julia was whilst retaining high performance. - Liked the mathematical syntax - Didn't like the python like parts that seemed to be added to try and get people to migrate from python, but were non "lispy".

9 years, 4 months

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[ACTIVITY] 18 - 22 April 2016

by Yao Qi

# Progress # * TCWG-545, patches are committed. Done. [3/10] * TCWG-167, ARM reverse debugging bug fixes. All test fails are fixed. Done. [2/10]. * PR 19947. The fix is approved, but the patch triggering the bug needs update. [2/10] * Help to fix broken ARM GDB after C++ switch. [2/10]. GDB mainline is a C++ program in default. Exception handling in GDB is broken on non-x86 host (ARM, AArch64, AIX, at least) because readline (C library) calls C++ GDB code, but exception unwinding can't cross the C function ("foreign frame"). The problem is fixed by catching all exceptions before return to readline, and re-throw them after return from readline back to GDB. * Misc, [1/10] ** Hack QEMU so that I can run gdb regression testsuite with qemu-arm. # Plan # * TCWG-518, rebase patches on mainline, test, and post patches if nothing wrong. * PR 19947, TCWG-561, * TCWG-547 -- Yao

9 years, 4 months

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[ACTIVITY] Week 16

by Yvan Roux

== Progress == o Extended validation (5/10) * Created new extend validation job which handles native/cross validation and benchmarking. * Identified and discussed dejagnu Linaro branch issue. o Upstream GCC (2/10) * Start to look at libatomic ARMv8.1 support o Misc (3/10) * Various meetings * Support team members on benchmarking and validation. == Plan == o Continue on extended validation and Libatomic

9 years, 4 months

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[ACTIVITY] 18 - 22 April 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) a) Section anchors - another wasted prototype: http://pastebin.com/5MXFqrZY - will follow Richard's suggestion to put variable in partition that references it most, we can make this smarter incrementally if required. b) Retested patch for lto-max-partition c) Retested increase_alignment pass patch and wrote test cases for it. * Validation (2/10) a) Script to build chromium - works with armhf (with assumptions about my environment) - issues with gclient sync failure which in turn does not generate LASTCHANGE file causing build to fail. * Public Holiday (2/10) - Mahavir Jayanti * Misc (1/10) - Meetings == Next Week == - LTO: section anchors, post patches upstream for lto-max-partition and increase_alignment. - TCWG-319: Look at why armeb is failing to vectorize test-cases. - Validation: chromium

9 years, 4 months

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[Weekly] 18-22 April 2016

by Michael Collison

== This week == * Bugzilla 67321 - [ARM] Exploit Wide Add operations when appropriate (1) - Re-based to GCC 6, re-validated and committed upstream * Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in thumb2 mode (1) - Re-based and re-validated - Need to create new bug as problem description does not match issue * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store (3/10) - Developed new patch for arm that detects failures with negative numbers - Debugging failures where constant is too large * TCWG-247 - Create Validation Job to run on GCC Trunk Commit (3/10) - Fleshed out additional portions of script and submitted for code review - Still issues to be resolved in script as noted in git review * Misc (2/10) - Meetings - Multiple interactions with ARM IT to configure and setup new laptop == Next week == * TCWG-247 - Finish script * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store - Finalize arm patch and validate * Bugzilla 70008 - create new bug and submit upstream patch

9 years, 4 months

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[ACTIVITY] 18-22 April 2016

by Christophe Lyon

* 3 days off == Progress == * Validation: - fixed ABE master and stable branches to use 'ssh -t' instead of 'ssh -tt' when cross-testing - trying to assert master vs stable before the array branch merge, noticed differences on armv8l - created linaro-local/stable Dejagnu branch (currently a copy of master). Prepared ABE config patches to use it. * GCC - infrastructure problems (ST compute farm), leading to a lot of noise in the validations (and wrong regression reports upstream) - enabled gcc-6-branch monitoring - added GCC-6 tab to the backports spreadsheet * Support - Windows-hosted toolchain crashes: it seems the builders we use to make the release run Jessie and not Trusty. Tried to rebuild a toolchain in a Jessie chroot, but the script failed (works under Trusty) * Misc (conf-calls, meetings, emails, ...) == Next == * Validation - check that using linaro-local/stable Dejagnu branch works well - create validation reference points before array branch merge - understand/fix armv8l validation differences between master/stable ABE branches * GCC - trunk monitoring, report regressions if needed - more intrinsics tests * Support - Windows-hosted toolchain bug * Snapshots - prepare a few backports for our gcc-5 branch * Cortex-strings update

9 years, 4 months

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[ACTIVITY] 18-22 April 2016

by Diana Picus

== Progress == * Inline assembly constraints support for ARM [TCWG-560] [1/10] - Started investigating Bug24071 * Intro to LLVM buildbots [1/10] - Got accustomed to the buildbot monitoring page - Learned how to connect to the bots/perform really basic maintenance * Misc [8/10] - Onboarding checklists, policies, meetings etc [6/10] - Laptop setup [2/10] == Plan == * Inline assembly constraints support for ARM [TCWG-560] - More investigations for Bug24071 * Misc - Finish reading Octopus policies - Review scripts for working with LLVM

9 years, 4 months

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Cross compilation issue

by $rik＠nth

Hi All, I don't whether this is the right community mailing list to post support or not. Please correct me if i am wrong. I am trying to cross compile gcc to ARM as static binaries and as part of this, i am facing below issue. My build system is Ubuntu and using [1] gcc branch. Let me know what i can share more information to you. arm-linux-gnueabi-g++ -static -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -DHAVE_CONFIG_H -static-libstdc++ -static-libgcc -static -pthread -o xgcc gcc.o ggc-none.o \ c/gccspec.o libcommon-target.a \ libcommon.a ../libcpp/libcpp.a ../libbacktrace/.libs/libbacktrace.a ../libiberty/libiberty.a ../libdecnumber/libdecnumber.a gcc.o:(.rodata+0x5acc): undefined reference to `host_detect_local_cpu(int, char const**)' collect2: error: ld returned 1 exit status make[2]: *** [xgcc] Error 1 [1] svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch -- Thanks & Regards, M.Srikanth Kumar.

9 years, 5 months

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[ACTIVITY] 11 - 15 April 2016

by Omair Javaid

== Progress == LLDB Buildbot Setup [TCWG-241] [1/10] -- Created a new factory for LLDB buildbots. Halted plan to migrate till turning chromebook build green. LLDB Chromebook Test Stability [TCWG-563] [3/10] -- Investigated some failures some of them were fixed by a systemZ support large patch set. -- Failures reduced to 36 locally with some tweaks. Buildbot still showing random results. LLDB ARM Thread Stepping Problem [TCWG-566] [5/10] -- Only happening on Arm linux targets. -- Spent good bit of time debugging this issue. There are multiple problems but root cause is same. -- Initial investigation reveals frame unwinding issues from .plt section. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB ARM Thread Stepping Problem [TCWG-566] -- Further debugging and investigation of this issue. -- Figure out a fix for stepping problem on arm linux.

9 years, 5 months

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[ACTIVITY] Week 15

by Yvan Roux

== Progress == o GCC 2016.04 source snapshot (4/10) * Reviewed on-going backports * Merged from FSF GCC 5 branch * Packaged and released snaphot o Extended validation (3/10) * Native validation identifies upstream issues - Fixed Glibc warnings raised by GCC 6, committed in Glibc master * Looking at bkk16 job switch to multijob.. o Misc (3/10) * Various meetings == Plan == o Continue on extended validation o GCC ARMv8.1 builtins fix.

9 years, 5 months

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[Weekly] 11-15 April 2016

by Michael Collison

== This week == * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store (1/10) - Arm backend is not recognizing that some constants can be encoded using modified immediate - This is causing constant to be split and additional code generated - Range of constants allowed differs between Arm and Thumb2 - Created prototype patch to allow additional ARM modified immediate instructions - Began work on Thumb2 patch * TCWG-247 - Create Validation Job to run on GCC Trunk Commit (2/10) - Developed shell portion of script to read and parse web page with builder information - Developing rest of yaml script including trigger on specified interval * Misc meeting (1/10) * Vacation (6/10) - April 11 - 13 == Next week == * TCWG-247 - Finish script * Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on memory store - Finalize arm patch and validate - Make progress on Thumb2 patch

9 years, 5 months

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[ACTIVITY] 11-15 April 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) a) Section anchors: - 3 iterations of prototype patch - Validated with testsuite and chromium LTO build - Submitted prototype patch upstream: https://gcc.gnu.org/ml/gcc/2016-04/msg00090.html * Bugs (1/10) - Looked at bugs 2073 and 2174 * Public Holidays (4/10) - Dr Ambedkar Jayanti and Ram Navami == Next Week == - LTO: section anchors, benchmarking - Validation: chromium

9 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (2/10) - Closing some inline asm constraint bugs that were fixed or user error - Finished PR16275 * Background (8/10) - Code review, meetings, discussions, general support, etc. - Lost track of how many meetings and email threads I had - Mostly about helping newcomers, managing Android/LLDB/LLD expectations - Also hardware planning, LLVMLinux revival, checking Swift

9 years, 5 months

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[ACTIVITY] 11 - 15 April 2016

by Peter Smith

Progress: - Read up on AARCH64 TLS and LLD code base - Commented on upstream patch in hope of getting approval from the code-owners - TCWG-466 Implement ADRL pseudo in LLVM assembler -- Slow progress as the pseudo instruction does not fit well into the existing architecture -- On the positive side I have learned quite a bit about how the LLVM assembler works -- Will make a decision next week whether it is worth actively pursuing TCWG-466. Supporting ADRL is not high priority and whatever fix I come up with may be difficult to get accepted upstream. I'd still like to keep trying, at least as a background task, but I think that there is higher priority work that can be done instead. Next Week: On holiday (hopefully added correctly to Linaro google calendar). I'll be at the ACCU conference.

9 years, 5 months

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[ACTIVITY] 11-15 April 2016

by Christophe Lyon

== Progress == * Validation - finally identified what caused several random results: use of 'ssh -tt' to acces the remote tester. I don't know the real cause. * GCC - reported a few regressions in trunk - a few backports - AdvSIMD intrinsics tests: built the list of AArch64 intrinsics not yet covered - support on a few bug reports * Misc (conf-calls, meetings, emails, ....) == Next == * Holidays Mon/Tue/Wed * Validation - consolidation on stdout/stderr problems - extended validation * GCC: - trunk monitoring, report regressions if needed - start monitoring the just-created gcc-6 branch - more intrinsics tests - switch backport activity to gcc-6 branch, update tools, etc...

9 years, 5 months

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[ACTIVITY] 11 - 15 April 2016

by Yao Qi

# Progress # * TCWG-545, 7 patches are approved, and 1 patch needs update, which needs the change somewhere else. [3/10] * TCWG-547, patch is pending. Pinged Pedro on IRC, to be reviewed, but no response. * TCWG-167, [3/10]. ARM reverse debugging fixes. Post one patch to fix test case. Testing another patch to give high priority of epilogue unwinder. * Upstream patch review, [2/10]. Spend more time on this due to long patch review backlog. The more I reviewed, the sooner my patches will be reviewed by others. * Misc, [2/10] ** Look at the slowness of gdb regression test in jekins validation, but can't reproduce it. ** Share some knowledge of watchpoint implementation in GDB to the people, who need the equivalent or similar things in LLDB. # Plan # * TCWG-545, TCWG-547, TCWG-167. -- Yao

9 years, 5 months

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[ANNOUNCE] Linaro GCC 5 2016.04 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.04 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn234898 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.05 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn234898 * Backport of [Bugfix] [AArch32] Fix PR target/70496 * Backport of [Bugfix] [AArch32] PR driver/70132: Avoid double fclose in driver-arm.c * Backport of [Bugfix] [AArch32] PR rtl-optimization/69904: Disallow copying/duplicating of load-exclusive operations * Backport of [Bugfix] [AArch32] PR target/62254 Fix for ARMv3 * Backport of [Bugfix] [AArch32] PR target/69614 * Backport of [Bugfix] [AArch32] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes * Backport of [Bugfix] [AArch32] PR testsuite/70553 * Backport of [Bugfix] [AArch64] PR rtl-optimization/70398 LRA * Backport of [Bugfix] PR 69400: Invalid 128-bit modulus result * Backport of [Bugfix] PR middle-end/70370 * Backport of [AArch32] 1/2 Cortex-R8 support * Backport of [AArch32] Add initial support for the Cortex-A32 * Backport of [AArch32] Add support for Cortex-A35 * Backport of [AArch32] Delete ASM_OUTPUT_DEF and fall back to default .set directive * Backport of [AArch64] 1/3 Enable CRC by default for armv8.1-a * Backport of [AArch64] 2/3 Rework the code to print extension strings (pr70133) * Backport of [AArch64] 3/3 Fix up for pr70133 * Backport of [AArch64] [ACLE][NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics * Backport of [AArch64] Add extra tuning parameters for target processors * Backport of [AArch64] Add support for Cortex-A35 * Backport of [AArch64] Only update assembler .arch directive when necessary * Backport of [Testsuite] [AArch32] 2/2 Cortex-R8 support * Backport of [Testsuite] [AArch64] PR target/70113 fix pr63304_1 testcase * Backport of [Testsuite] [AArch64] Skip gcc.target/aarch64/assembler_arch_1.c if assembler does not support it * Backport of [Testsuite] Avoid GDB being blocked on signals * Backport of [Testsuite] Fix testsuite for Cortex-R8 support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 5 months

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[ACTIVITY] 4 - 8 April 2016

by kugan

== Progress == * Type promotion pass (2/10) - Benchmarking * LTO (7/10) - Refactoring tree-vrp to share common parts - Looking at open enhancement bugzilla and working on them * Misc (1/10) - GCC Lists == Plan == * LTO and VRP

9 years, 5 months

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[ACTIVITY] 4 - 8 April 2016

by Omair Javaid

== Progress == LLDB Buildbot Setup [TCWG-241] [9/10] -- Migration of local master/slave setup to Linaro LLVM lab. -- Setup slave to be able to connect to chromebook for lldb remote testing. -- Modified Android build scripts to work with chromebook in llvm lab. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB Buildbot Setup [TCWG-241] -- Write a new factory for linux based lldb script commands -- Break down and tweak scripts with better logical steps. -- Migrate current setup to use new factory. LLDB development [TCWG-563] -- Look into failing tests on chromebook tester and see if some of them can be fixed.

9 years, 5 months

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[ACTIVITY] Week 14

by Yvan Roux

== Progress == o Extended validation (5/10) * Dejagnu remote layout patch finalized and committed upstream (will be part of the coming 1.6 Dejagnu release) * GCC guality test fix committed in trunk. * Native armv8l validation unblocked, but still slow (more than 8hrs) Analysis on-going. * Start to work on enhancement: include cross validation and benchmark trigger. o Misc (5/10) * Lot of meetings (Internal, training, Benchmarking, ...) == Plan == o Monthly snaphsot (review backports, branch merge) o Continue on extended validation o GCC ARMv8.1 builtins fix.

9 years, 5 months

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[ACTIVITY] 4 - 8 April 2016

by Prathamesh Kulkarni

== This Week == * LTO (6/10) a) tcwg-128: branch out of range error - Addressing upstream reviews - Patch needs approval from Honza b) section-anchors - Understanding balanced partitioning algorithm - Working on 2nd prototype: http://people.linaro.org/~prathamesh.kulkarni/section-anchors-1.diff - Looking at regressions caused due to patch: http://people.linaro.org/~prathamesh.kulkarni/section-anchors-1-compare-res… c) submitted patch to slightly refactor lto_balanced_map: - https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00341.html d) tcwg-534: ipa-comdats - found why ICE happens e) ipa-vrp - Discussions with Kugan * Validation (1/10) - Passing -static-libstdc++ works to build chromium without using chromium's sysroot. - Review 11311 - Untested script to build chromium for arm, x86: http://people.linaro.org/~prathamesh.kulkarni/build-chromium.sh * Public Holiday (2/10) * Misc (1/10) - Meetings == Next Week == - LTO: section anchors - Validation

9 years, 5 months

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[ACTIVITY] for week ending 8th April 2016

by Peter Smith

== Progress == Transition week into Linaro toolchain group from ARM to replace Bernie [*] - Some ARM handover work done. - Started looking into https://llvm.org/bugs/show_bug.cgi?id=24350 (TCWG-466 ADRL support) -- Checked behaviour of ADRL on armasm and GNU as -- Worked out what I need to do in LLVM to make ADRL work, looks like nothing hugely complicated but a lot of plumbing through various layers. - Started reading about AArch64 TLS descriptor implementation. I'm familiar with the AArch32 traditional model so I need to bridge the gap a bit. == Plans == - Post some review comments on Adhemeval's TLS patch with the hope of unblocking it. - Start implementing support for ADRL in the integrated assembler == Planned Absences == Holiday 18th - 22nd April (Attending ACCU conference in Bristol). I think I've put that in the shared holiday calendar correctly. [*] Hello to everyone I didn't manage to meet at Linaro Connect. I've been working in ARM's proprietary compiler team, with much of that time spent on armlink and the other non-compiler tools.

9 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (2/10) - Adding more tests to D18701, covering more cases - Investigating PR27250 (user error) * Buildbots (2/10) - More work around LLDB buildbots * Background (6/10) - Code review, meetings, discussions, general support, etc. - Android / AOSP discussions, meetings - Some lab planning, meetings - Helping newcomers, meetings

9 years, 5 months

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[ACTIVITY] 1 April -- 8 April

by Yao Qi

# Progress # * TCWG-167, ARM reverse debugging bug fixes. [4/10] Four patches are committed. All FAILs are fixed if test case is compiled with -fomit-frame-pointer. Some FAILs when -fno-omit-frame-pointer are caused by epilogue unwinder doesn't parse epilogue correctly if FP is involved. File TCWG-562 to track it. * TCWG-545, TCWG-547, patches are pending. Maintainer is busy on something else. * Triage the regression gdb.base/jit.exp. [1/10] We need a pending patch series to address this issue. Ask Pedro how to review them. * TCWG-561, handle unavailable memory during frame unwinding. [3/10] Think about it and write a prototype. * Misc, patches review and meeting, [2/10]. # Plan # * Take a look at the slow native arm-linux-gnueabihf gdb test. * TCWG-562, Tweak epilogue unwinder to handle FP. * TCWG-545, TCWG-547, ping. * TCWG-561, finish the prototype. -- Yao

9 years, 5 months

1
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Linaro toolchain: libstdc++.so: file format not recognized; treating as linker script

by Gunnar Arndt

My dear friends, I'm trying to build C++ code for Linux running on am ARM Cortex A8 (TI AM335x). For a first try, I'm using the simplest program I can think of: /* main.cpp */ int main() { return 0; } Under Linux with the 'normal' GCC, that works fine, but under Windows 7 with the Linaro toolchain, it fails with the following message: C:\firedect\dev\workspace\Test-Linux-ARM_1> "\Program Files (x86)\GNU Tools ARM Embedded\gcc-linaro-4.9-2016.02-i686-ming w32_arm-linux-gnueabi\bin\arm-linux-gnueabi-g++.exe" main.cpp c:/program files (x86)/gnu tools arm embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/bin/ld.exe:c:/program files (x86)/gnu tools arm embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/lib/libstdc++.so: file format not recognized; treating as linker script c:/program files (x86)/gnu tools arm embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/bin/ld.exe:c:/program files (x86)/gnu tools arm embedded/gcc-linaro-4.9-2016.02-i686-mingw32_arm-linux-gnueabi/bin/../lib/gcc/arm-linux-gnueabi/4.9.4/../../../../arm-linux-gnueabi/lib/libstdc++.so:1: syntax error collect2.exe: error: ld returned 1 exit status C:\firedect\dev\workspace\Test-Linux-ARM_1> "\Program Files (x86)\GNU Tools ARM Embedded\gcc-linaro-5.3-2016.02-i686-ming w32_arm-linux-gnueabihf\bin\arm-linux-gnueabihf-g++.exe" main.cpp c:/program files (x86)/gnu tools arm embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/bin/ld.exe:c:/program files (x86)/gnu tools arm embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/lib/libstdc++.so: file format not recognized; treating as linker script c:/program files (x86)/gnu tools arm embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/bin/ld.exe:c:/program files (x86)/gnu tools arm embedded/gcc-linaro-5.3-2016.02-i686-mingw32_arm-linux-gnueabihf/bin/../lib/gcc/arm-linux-gnueabihf/5.3.1/../../../../arm-linux-gnueabihf/lib/libstdc++.so:1: syntax error collect2.exe: error: ld returned 1 exit status As you can see, I have tested two versions of the toolchain, which show the same behavior. Do you have any idea what's going wrong here? I'd appreciate any help you can provide! -- Kind regards, Gunnar Arndt

9 years, 5 months

3
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Another weird behavior with arm gcc 5.3

by fengwei.yin

Hi list, I hit another weird problem after use gcc 5.3 (If I use gcc 4.9, there is no any issue) with android. With arm gcc 5.3, the C++ apps crash in one class constructor call. And gdb shows some vtbl items of the class are not relocated. With arm gcc 4.9, if set breakpoint in that constructor, we could see the vtbl items of the class are relocated. And Yes. I know the android bionic loader take response to do relocation. But if it works with gcc 4.9, I suppose bionic loader work well (unless gcc 5.3 create some new situation not handled by it). I attached the vtbl dump in gdb for gcc 5.3 and 4.9 both. We could see all valid entries in vtbl are relocated in 4.9 dump. But not all entries in vtbl are relocated in 5.3 dump (the address is not started with 0xf). Suggestions/hints are welcome. Thanks a lot. Regards Yin, Fengwei

9 years, 5 months

3
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2011

2010

linaro-toolchain