# Progress #
* TCWG-518, ARM range stepping patches. [2/10]
The last one is approved, and all patches are committed! Need to
enable range stepping and collect the performance data. Range
stepping should speed up remote debugging.
* TCWG-655, Workaround ARM linux kernel ptrace bug on setting VFP
registers. No response from upstreams.
* TCWG-333, Thumb mode function pointer assignment in GDB. [3/10]
Try a different approach, still causes regressions. I'll ask upstream
how to do it.
* TCWG-547, Change software_single_step interface to return a vector of
address. [4/10].
Patches are done, but need to figure out how to hook them together.
* TCWG-685, GDB 7.12 release. [1/10]
The release will be in Sep, and hopefully it can be done before the
Linaro Connect. Discuss on how/when to pick up 7.12 in Linaro
toolchain release. I am inclined to upgrade GDB in linaro release
from 7.11 to 7.12 in fall or winter.
# Plan #
* Off on Tue and Wed.
* GDB 7.12 release testing for ARM and AArch64.
* US visa application.
--
Yao
== Progress ==
TCWG-680 Some analysis on what non-compiler support would be required
for an llvm based EBC (UEFI) toolchain.
TCWG-612 ARM TLS support in LLD: Initial support and tests for
standard model upstreamed. There is still some work to be done for
corner cases where LLD's relaxations will cause assertion failures.
Static linking also needs some work as the TLS module index needs to
be written into the GOT without a dynamic relocation. I have a
prototype fix that needs cleaning up and tests written.
Did some experiments with static linking and TLS to work out what I'll
need to look at next. Discovered GNU ifunc support when static linking
is not working.
Did some thinking about what would be needed to support C++ exceptions
in LLD for ARM. This is probably the next major chunk of work as
supporting exceptions is needed when static linking against the C
library startup code.
== Plans ==
Plans for next 4 weeks:
On Sabbatical back on the 22nd August. Will probably have limited
access to email if there is anything urgent.
Peter
== Progress ==
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch committed upstream
* PR26038 - inline assembly assertion building ARM linux kernel
[TCWG-590] [2/10]
- Patch committed upstream
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Started investigating
* AArch64 Bugzilla scrub [2/10]
- Closed a couple of bugs that couldn't be reproduced
- Added a few interesting bugs to TCWG-678
* Minor updates to the helper scripts [TCWG-630, TCWG-649] [1/10]
== Plan ==
* PR24234 - [AArch64] error in backend: fixup value out of range [TCWG-681]
- Looks like a tough one :)
Hi Everyone,
I'm looking at the features of a BeagleBone Black. Its /proc/cpuinfo is below.
I think vfpd32 cpu flag means I have 32 D-registers. The cpu flags
neon and vfpv3 flags means I want something more than -mfpu=neon-fp16,
but I'm not sure what that is.
My question is, what GCC ARM option is used when we encounter the
neon, vfpv3 and vfpd32 flags?
Thanks in advance.
**********
$ cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 996.14
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc08
CPU revision : 2
Hardware : Generic AM33XX (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
Hi Everyone,
I'm having trouble with ARMv8/Aarch64. One is an early Mustang server
board (without CRC or Crypto), and the other is a LeMaker HiKey (with
CRC and Crypto). Both run Linaro:
apm-mustang: $ cat /proc/cpuinfo
Features : fp asimd evtstrm
And:
hikey: $ cat /proc/cpuinfo
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
According to the GCC folks, we can get better code generation with
-mfpu=neon-fp-armv8
(http://gcc.gnu.org/ml/gcc-help/2016-05/msg00058.html and
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). However, it
results in:
$ g++ -DDEBUG -g3 -O0 -mfpu=neon-fp-armv8 -fPIC -pipe -c cryptlib.cpp
g++: error: unrecognized command line option ‘-mfpu=neon-fp-armv8’
GNUmakefile:753: recipe for target 'cryptlib.o' failed
It looks like -mfpu=neon-fp-armv8 is a GCC 4.9 feature
(http://gcc.gnu.org/gcc-4.9/changes.html), and Linaro supplies GCC
4.9.2:
$ g++ --version
g++ (Debian/Linaro 4.9.2-10) 4.9.2
Copyright (C) 2014 Free Software Foundation, Inc.
I'm wonder why the option is not being consumed by GCC. Are there any
ideas what I should be doing differently?
Thanks in advance.
Jeff
* On holiday [6/20]
# Progress #
* TCWG-655, Workaround ARM linux kernel ptrace bug. [2/20]
After the discussion, patch is posted. Pedro is on holiday, so the
patch is pending there for review.
* TCWG-518, ARM range stepping patches. [3/20]
The last "to-be-approved" patch is posted. Pending for review.
* TCWG-333, Thumb mode function pointer assignment in GDB. [2/20]
Working on a patch to handle both ARM/thumb and PPC64.
* TCWG-179, TLS variables can't be resolved in aarch64 GDB. [4/20]
GCC doesn't produce DW_AT_location
for TLS variable, because target hook TARGET_ASM_OUTPUT_DWARF_DTPREL
isn't defined for AArch64. Thanks to Jiong and Szabolcs's help, pick
up knowledge on TLS descriptor and TLS modes quickly. Still need to
figure out how to describe the location of TLS variable in debug info
if they are unknown in compilation/link time.
* Fix gdb.gdb/*.exp and gdb.mi/mi-reverse.exp test fails. [1/20]
* Upstreams patch review. [1/20]
* LAS16, sort out the invitation letter for US visa. [1/20]
# Plan #
* TCWG-333, TCWG-518, TCWG-655 and TCWG-179
* US visa application.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.07 snapshot of Linaro GCC 6 source packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn238201 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn238201
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Hi Linaro Members,
while I am cross compiling the wpa supplicant with toolchain gcc-linaro-4.9-2015.05-x86_64_arm-linux-gnueabihf for hostapd and nl80211 mode enabled in menuconfig I am getting linker message ld:cannot find -lnl -3 (libnl) .I tried to locate the libnl libraries but they are not built in.could you please let me know how to enabled libnl in the toolchain.
Thanks
Best Regards --
Best Regards,
Rohit Kamat
CallSend SMSCall from mobileAdd to SkypeYou'll need Skype CreditFree via Skype
== Progress ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
- Committed all 3 patches upstream
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch in upstream review, had to rework it a bit
* PR26038 - inline assembly assertion building ARM linux kernel [TCWG-590]
- Patch in upstream review
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643]
- In progress (trying to break it up into a few helper functions)
* Misc
- TCWG Sprint prep (slides etc)
== Plan ==
* TCWG Sprint
* Commit TCWG-669 and address any review comments on TCWG-590
== Progress ==
TCWG-653 ARM/Thumb interworking veneers
Committed upstream after several review rounds and at least one set of
build bot failures in systems/compilers we don't have set up.
TCWG-612 ARM TLS support in LLD
Have an implementation and most of the tests. Should be ok to upstream
next week.
Found that llvm-mc doesn't implement .word sym(tlsldo). Have a simple
fix that I'll need to upstream before I can test local-dynamic.
== Plan ==
11 - 15th July TCWG Sprint
== Absences ==
25th July - 20th August Sabbatical
The Linaro Binary Toolchain
============================
The Linaro GCC 5.3-2016.05-rc2 Release-Candidate is now available.
Notice: All Linaro GCC 5 series toolchain users should migrate to the
latest version of the Linaro GCC 5 toolchain in order to mitigate
potential security exposure to CVE-2015-7547. See the NEWS section
below for details.
Download release-candidate packages from:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05-rc2/http://snapshots.linaro.org/components/toolchain/binaries/5.3-2016.05-rc2/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 5.3-2016.05-rc2
Linaro glibc 2.21 (linaro/2.21)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.25 (linaro_binutils-2_25-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 5.3-2016.05-rc2
====================================
* Increment binutils release date to 2016_02 to reflect the most recent
commit:
commit ef90a4718f535cbe6345b4e7168baea7b1972abf
Author: Matthew Wahab <matthew.wahab(a)arm.com>
Date: Tue Jan 12 16:35:30 2016 +0000
[ARM] Support ARMv8.2 RAS extension.
* Baremetal sysroot names now contain 'newlib' rather than 'glibc'.
* Manifests now contain relative paths rather than absolute paths.
* Now generating proper manifest files.
* Fixed pi requeue support in glibc 2.21 while allowing the existing
2.21 minimum kernel default setting. This was checked into the
linaro/2.21/master branch.
commit a68cafa11c500d8a49a3014c43c5152859d037ae
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
commit 6e5cb616b5b442ce8b2664ad673c0acf42a490ac
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
commit 9ac61c0047295696cbcdbc26bdc174c7bd25a3c8
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Backported support into GCC for Cortex-A32, Cortex-A35, and Cortex-R8.
* Applied fix for CVE-2015-7547 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
glibc 2.21.
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked
into GCC and binutils. It has been backported into Linaro GCC 5.3
and Linaro binutils 2.25.
* Backported -Bsymbolic-functions into Linaro binutils 2.25.
* Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC
5.2-2015.12, and Linaro GCC 5.3-2016.01-1, Linaro GCC 5.3-2016.02,
Linaro GCC 5.3-2016.03, and Linaro GCC 5.3-2016.04 have been included.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
Hi Everyone,
I have a test script from help that repeatedly builds and runs a
library under different configurations. The script includes multiple
Asan tests.
The Asan tests are producing some findings under ARM32 as shown below.
Other platforms do not include Asan findings. In addition, Valgrind
does nt produce any findings.
The test program is always built with at least -g2, and sometimes
built with -g3. However, I am not seeing the symbolication. According
to the GCC folks, asan_symbolize is not required for GCC because it
uses libbacktrace. Also see
http://bugzilla.redhat.com/show_bug.cgi?id=1250844.
Why am I lacking symbolization, and how do I achieve it?
**********
AddressSanitizer: stack-buffer-overflow on address 0xbec57b18 at pc
0x38c651 bp 0xbec579e0 sp 0xbec579e4
AddressSanitizer: stack-buffer-overflow on address 0xbedbae9c at pc
0x6553f bp 0xbedbae68 sp 0xbedbae6c
AddressSanitizer: stack-buffer-overflow on address 0xbea67b18 at pc
0x38cbc5 bp 0xbea679e0 sp 0xbea679e4
AddressSanitizer: stack-buffer-overflow on address 0xbef0fe9c at pc
0x66117 bp 0xbef0fe68 sp 0xbef0fe6c
**********
$ uname -a
Linux cubietruck 3.4.39 #35 SMP PREEMPT Tue Sep 15 17:17:33 CST 2015
armv7l armv7l armv7l GNU/Linux
$ g++ --version
g++ (Ubuntu/Linaro 4.8.2-19ubuntu1) 4.8.2
Copyright (C) 2013 Free Software Foundation, Inc.
# Progress #
* TCWG-655, Workaround ARM linux kernel ptrace bug on setting VFP
registers. [2/10]
Think about different approaches to workaround the kernel bug, but
can't work unfortunately. Propose an approach that workaround it in
gdb testing by setting affinity if the kernel is known broken.
People agree on this.
* TCWG-333, Thumb mode function pointer assignment in GDB. [3/10]
It is broken when you assign a function to a function pointer in
thumb mode in GDB. My original attempt is to skip the test, because
it is difficult to do what MIPS does nowadays. After some
discussions, I realize it is a GDB bug, and we should fix it.
Fortunately it is broken on ppc64 as well because of function
descriptor :)
* TCWG-518, ARM range stepping patches. [2/10]
V3 are reviewed, but I misunderstood one comments to V2. I'll update
patches, retest and post them.
* ARM linux kernel raises SIGILL for unknown syscall number, while GDB
expects kernel returns -ENOSYS. [2/10]
The behaviour is different from other arch. The patch in GDB side is
committed, but still need to kernel people why ARM kernel behaves
this way.
* Misc [1/10]
# Plan #
* All above,
* Off on Thur and Fri.
--
Yao
o One day off (2/10)
== Progress ==
o Extended Validation (3/10)
- Benchmarking job babysitting.
- Looked at Dejagnu issue (pid killing, resurrected an old patch)
o Upstream GCC (3/10)
- __sync bultin fix for ARMv8.1:
Careful read of the doc shows that there is no issue with the
current implementation (no need to add an extra DMB, acq/rel
semantic is sufficient in this case)
- AArch64 and ARM backend cleanup w/r to reload remaining hooks
Analysis and validation on-going
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on-going tasks
== This Week ==
* LTO (6/10)
a) TCWG-548 (2/10)
- Tweaked algorithm, which shows some improvements in reducing external
references
b) TCWG-666 (4/10)
- Had a look at bitwise-ccp
- WIP prototype patch
* Benchmarking (1/10)
- Got results for linaro-gcc-6 for coremark-pro for arm-linux-gnueabihf
* Sick Leave (2/10)
* Misc (1/10)
- Pinged for reviewing patches for TCWG-665 and TCWG-72
- Meetings
== Next Week ==
- Address upstream reviews for TCWG-665
- TCWG-666: Continue with prototype patch.
- TCWG-548: Submit upstream for feedback.
- Benchmarking: Get results for coremark-pro for aarch64-linux-gnu.
== Progress ==
TCWG-653 ARM/Thumb interworking veneers
Have completed an implementation, now in upstream review. Had initial
set of comments and posted an update. Likely to take several
iterations before commit
TCWG-612 ARM TLS support in LLD
Made a start. Looks to be more straightforward the interworking
thunks, should just be grunt-work to get done.
Updated lld slides on llvm sprint presentation.
== Plan ==
TCWG-653 and TCWG-612.
== Progress ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10]
- Committed another patch upstream, 3 more in review
* ARM: Different ABI functions based on optimization level [TCWG-669] [3/10]
- Make sure we're ABI-compliant at -O0
- Patch in upstream review, need to fix a few things
* List of active environments with llvm-env [TCWG-640] [1/10]
- Committed internally
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643] [1/10]
- In progress (trying to break it up into a few helper functions)
* PR26038 - inline assembly assertion building ARM linux kernel
[TCWG-590] [1/10]
- Started investigating
== Plan ==
* Address any review comments for TCWG-623 and TCWG-669
* Submit patches for TCWG-643 and TCWG-590
Hi Andrew,
On 27 June 2016 at 19:32, Pinski, Andrew <Andrew.Pinski(a)cavium.com> wrote:
>> No gain expected in implementing an Ifunc'ed version of the library.
>
> How did you prove that? What hardware did you run this on to prove it?
> Also have you thought at least doing an ifunc version for 128bit atomics?
up to 64bits, the calls to the libatomic routines are inlined and
armv8.1 CAS and load-operate version are used when the application is
build for armv8.1 architecture. For 128bits, a call to the lib is
made which uses the same LL/SC implementation with or without LSE
support, as CAS and load-operate instruction don't support this data
size.
I don't have armv8.1 hardware and made the analysis on the generated
assembler. Do you have use case on your side where an ifunc version
can be useful ? I'm not aware of an algorithm which can replace
effectively LL/SC implementation with shorter CAS, do you have any
pointers ? Maybe CASP can be used in some cases, I'll investigate it.
Thanks
Yvan
> Thanks,
> Andrew
>
> -----Original Message-----
> From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Yvan Roux
> Sent: Monday, June 27, 2016 1:40 AM
> To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
> Subject: [ACTIVITY] Week 25
>
> == Progress ==
> o Extended Validation (1/10)
> - Benchmarking job babysitting.
>
> o Upstream GCC (4/10)
> - ARMv8.1 libatomic: Analysis completed.
> No gain expected in implementing an Ifunc'ed version of the library.
> - Working on __sync buitlins potential fix.
>
> o Misc (5/10)
> * Various meetings and discussions.
> * Internal appraisal
>
> == Plan ==
> o Continue on-going tasks (__sync, benchmarking) _______________________________________________
> linaro-toolchain mailing list
> linaro-toolchain(a)lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
o Extended Validation (1/10)
- Benchmarking job babysitting.
o Upstream GCC (4/10)
- ARMv8.1 libatomic: Analysis completed.
No gain expected in implementing an Ifunc'ed version of the library.
- Working on __sync buitlins potential fix.
o Misc (5/10)
* Various meetings and discussions.
* Internal appraisal
== Plan ==
o Continue on-going tasks (__sync, benchmarking)
# Progress #
* TCWG-333, ISA bit treatment in ARM thumb mode.
Got some comments from Maciej (MIPS) and need to address them.
* TCWG-518, ARM range stepping patches. [2/10]
Combine the path of "proceed" and "resume" so that we only change one
place instead of two to support range stepping. Patches are being
tested.
* TCWG-655, Workaround ARM linux kernel ptrace bug... [2/10]
by pining both program and debugger on the same core in the affected
test cases.
* Off on Wed to Fri. [6/10]
# Plan #
* Continue things above,
--
Yao
== This Week ==
* LTO (8/10)
a) TCWG-558 (2/10)
- found a way to detect if stmt is inside a loop
- addressed issue with -ffat-lto-objects
- patch posted upstream, waiting for review.
b) ipa-vrp (3/10)
- Prototype patch for propagating value ranges
inter-procedurally (accidental overlap with Kugan's patches)
- Experimented and reviewed Kugan's patch.
c) TCWG-548 (2/10)
- Wrote a pass to gather stats on external references.
- Measurements with SPEC2000 with and without prototype patch
d) Had a look at pointer alignment propagation within ipa-cp pass (1/10)
* Benchmarking (1/10)
- Obtained results for linaro-gcc-5, fsf-gcc-6 for coremark-pro for
arm-linux-gnueabihf target.
- Submitted job 112 for bkk16-buildfarm-benchmark, status shows SUCCESS, but it
appears no tcwg-benchmark job references build #112.
* Misc (1/10)
- Meetings
== Next Week ==
- Continue with TCWG-548 and ipa-vrp
- Ping patches in upstream reviews
== Progress ==
* Out of office on Monday and Tuesday [4/10]
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10]
- First patch committed upstream (6 features / properties)
- Another patch in upstream review (5 features / properties)
- Working on another series of patches
* Use member initializers in ARMSubtarget [TCWG-659] [1/10]
- Trivial refactoring suggested during code review for TCWG-623
- Committed upstream
* Unbreak the selfhost bots [TCWG-661] [1/10]
- Currently bisecting the issue affecting
clang-cmake-thumbv7-full-sh (in progress)
- Tried bisecting one of the issues affecting
clang-cmake-armv7-selfhost and clang-cmake-armv7-selfhost-neon, but
the test board died in the process; Renato is trying to reproduce on
one of his boards
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Finally committed upstream
== Plan ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
* Unbreak the selfhost bots [TCWG-661]
== Progress ==
* TCWG-653 Add interworking thunks to LLD
Investigated and reported upstream bug in existing implementation.
This has been fixed by reverting the change that introduced it. Got
some feedback about whether I would need to strictly follow existing
Thunk implementation.
Implemented an alternative thunk mechanism that should generalise to
supporting range extension and interworking thunks. It is passing the
existing lld regression tests.
== Plans ==
Finish off support for and add tests for ARM/Thumb interwork.
Tidy up and submit upstream.
== Progress ==
* Validation
- experimenting backport-multijob
- noticed dejagnu problems when trying to kill processes that timed out
- abe and jenkins configs patches / reviews
* Backports/snapshots
- restarted a few validations, to try to recover from disk full issues
* GCC
- neon-testgen.ml removal patch sent upstream
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
- neon-fp16 tests consistency patch posted
- a couple of regressions flagged on trunk
* cortex-strings
- updated aarch64/strlen
* Support
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- patch reviews
- look at xenial, docker builders
* Backports
- restart the ones that failed due to disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- pr 67591
- advsimd tests
== Progress ==
o Extended Validation (1/10)
- Benchmarking job babysitting.
o Linaro GCC (5/10)
- Merged FSF GCtC 6 branch
- Reviewed backports (very tedious because of infra issues)
- Released June snapshots (5.4 and 6.1)
o Upstream GCC (2/10)
- ARMv8.1 libatomic: Reading and code analysis.
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on-going tasks (libatomic, benchamrking)
# Progress #
* TCWG-333, ISA bit treatment in ARM thumb mode. [2/10]
Post a patch to skip the test for thumb mode. Finish the prototype
which shows many issues that I can't overcome. Convince myself that
we should skip the test rather than support that in GDB.
* TCWG-518, ARM range stepping patches. [3/10].
11 of 12 patches are approved, and some of them are already
committed. Need to address one comment that merge to execution paths
into one, which requires some big changes in GDBserver for linux.
* TCWG-651, Support 'catch syscall' in remote for aarch64 and arm.[3/10]
My patches are posted upstream.
* TCWG-556, aarch64 gdb buildbot. [1/10]
They are online.
http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-m64/http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-native-gdbserver-m64
* TCWG-654, Build both cross/native arm/aarch64 gcc 5.4.1 to replace
the gcc in my gdb tests. Ongoing. [1/10]
# Plan #
* Follow up all of them above,
* Holiday from Wed - Fri.
--
Yao
== Progress ==
1 day public holidays
IPA VRP
- Implemented a version of early VRP.
- Verified with simple test cases.
- Some test cases are failing in regression testing, looking into it.
- Some design decisions need to be firmed up with the upstream
discussions.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
== Progress ==
* Out of office on Monday [2/10]
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [1/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing one of the AMDGPU tests (PR27761) - in upstream review
- Patch fixing the ARM test (PR27765) - committed upstream
- Submitted a patch removing the flag from llc - accepted upstream,
pending on approval of AMDGPU patch
* Use git worktree in llvm helper scripts [TCWG-587] [2/10]
- Merged. Working on some follow-up stories
- Change interface to llvm-build [TCWG-629] - Modify llvm-build to
accept the targets defined by CMake
- Fix a bug in llvm-env [TCWG-644] - Initially went unnoticed due to
zsh vs bash differences
- Allow cloning from read-only repo [TCWG-652] - This is so non-TCWG
people can use our helper scripts
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [5/10]
- Submitted a patch extracting 6 new subtarget features
- Investigating more features that could be extracted
== Plan ==
* OOO on Monday and Tuesday
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
== Progress ==
* Validation
- disk full on builders: analysis simply shows that we need more disk :)
- updated "buildapp" job to support building the Linux kernel. We
need more dev packages installed in the *build* schroots for it to
work though.
* Backports/snapshots
- fsf-6 branch merge review
* GCC
- small cleanup in neon* effective-target tests done
- re-testing neon-testgen.ml removal patch
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
* Support
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- patch reviews
* Backports
- restart the ones that failed due do disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- hopefully test-neongen.ml removal
- pr 67591
- advsimd tests
== Progress ==
TCWG-611 Initial Thumbv7a support for LLD committed upstream.
Interworking is supported via BLX only. This is enough to run hello
world on a modern arm-linux-gnueabihf target.
TCWG-653 Interworking veneer support for LLD
The existing support for veneers (thunks in LLD terminology) is Mips
specific for non-pi to pi calls. Unless there is something I'm missing
it looks broken in the general case as well.
I have an implementation of minimal veneers that I'm not particular
happy with, but can experiment with to see what the implementation
options are. I am likely to need to go via and RFC first.
Holiday on Friday.
== Next Week ==
Continue working on TCWG-653.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.06 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn237469 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn237469
* Backport of [Bugfix] [AArch32] PR target/69857 Remove bogus early
return false; in gen_operands_ldrd_strd
* Backport of [AArch32] Add mode to probe_stack set operands
* Backport of [AArch32] arm/ieee754-df.S: Fix typos in comments
* Backport of [AArch32] Do not set ARM_ARCH_ISA_THUMB for armv5
* Backport of [AArch32] Error out for incompatible ARM multilibs
* Backport of [AArch32] Fix costing of sign-extending load in rtx costs
* Backport of [AArch32] Tie operand 1 to operand 0 in AESMC pattern
when fusing AES/AESMC
* Backport of [AArch32] Use proper output modifier for DImode register
in store exclusive patterns
* Backport of [AArch64] 1/4 Add the missing support of vfms_n_f32,
vfmsq_n_f32, vfmsq_n_f64
* Backport of [AArch64] 2/4 Extend vector mutiply by element to all
supported modes
* Backport of [AArch64] 3/4 Reimplement multiply by element to get rid
of inline assembly
* Backport of [AArch64] 4/4 Reimplement vmvn* intrinscis, remove inline assembly
* Backport of [AArch64] Adjust SIMD integer preference
* Backport of [AArch64] Delete ASM_OUTPUT_DEF and fallback to default
.set directive
* Backport of [AArch64] Don't define a macro when a variable will do
* Backport of [AArch64] Fix shift attributes
* Backport of [AArch64] Improve aarch64_case_values_threshold setting
* Backport of [AArch64] print_operand should not fallthrough from
register operand into generic operand
* Backport of [AArch64] Remove aarch64_simd_attr_length_move
* Backport of [AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true
* Backport of [AArch64] Simplify ashl<mode>3 expander for SHORT modes
* Backport of [AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
* Backport of [AArch64] Tie operand 1 to operand 0 in AESMC pattern
when AES/AESMC fusion is enabled
* Backport of [AArch64] Update documentation of AArch64 options for GCC6
* Backport of [AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets
* Backport of [Testsuite] [AArch32] 01/11 Fix typo in vreinterpret.c
test comment
* Backport of [Testsuite] [AArch32] 02/11 Remove useless #ifdefs from
these tests: vmul, vshl and vtst
* Backport of [Testsuite] [AArch32] 03/11 AdvSIMD tests: be more verbose
* Backport of [Testsuite] [AArch32] 04/11 Add forgotten vsliq_n_u64
vsliq_n_s64 tests
* Backport of [Testsuite] [AArch32] 05/11 Add missing
vreinterpretq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 06/11 Add missing vtst_p16 and
vtstq_p16, and vtst_p{8,16} and vtstq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 07/11 Add vget_lane fp16 tests
* Backport of [Testsuite] [AArch32] 08/11 Add missing vstX_lane fp16 tests
* Backport of [Testsuite] [AArch32] 09/11 Add missing vrnd{,a,m,n,p,x} tests
* Backport of [Testsuite] [AArch32] 10/11 Add missing tests for
intrinsics operating on poly64 and poly128 types
* Backport of [Testsuite] [AArch32] 11/11 Add missing tests for
vreinterpret, operating of fp16 type
* Backport of [Testsuite] [AArch64] Fix vmul_elem_1.c on big-endian
* Backport of [Testsuite] [AArch64] Guard float64_t with __aarch64__
* Backport of [Testsuite] [AArch64] Skip cpu-diagnostics tests when
overriding -mcpu
* Backport of [Testsuite] gcc-dg: handle all return values when
shouldfail is set
* Backport of [Testsuite] PR70227, skip g++.dg/lto/pr69589_0.C on
targets without -rdynamic support
* Backport of [Testsuite] PR tree-optimization/57206
* Backport of [Testsuite] Skip tail call tests on Thumb-1 targets
* Backport of [Misc] Increase default value of lto-min-partition to 10000
* Backport of [Misc] introduce --param max-lto-partition for having an
upper bound on partition size
* Backport of [Cleanup] [AArch32] Fix typos in *thumb1_mulsi3 comment
* Backport of [Cleanup] [AArch32] Remove unused TARGET_ARM_V*M macros
* Backport of [Cleanup] [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes
* Backport of [Cleanup] [AArch64] Remove an unused reload hook
* Backport of [Cleanup] Convert conditional compilation on
WORD_REGISTER_OPERATIONS
* Backport of [Cleanup] Remove spurious debug code
* Backport of [Cleanup] Move wrong ChangeLog entry from toplevel to
gcc ChangeLog
* Backport of [Doc] Fix minor doc bugs, signalling typo, major version
changes rare
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn237113 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06/
Interesting changes in this GCC source package snapshot include:
Updates to GCC 5.6+svn237113
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/69245: Set
TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is
the default node to recalculate optab availability
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/70002: Make
aarch64_set_current_function play nice with pragma resetting
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
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[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Hi,
I've stumbled across an assembler error message that I don't understand.
bl1/aarch64/bl1_exceptions.S: Assembler messages:
bl1/aarch64/bl1_exceptions.S:53: Error: non-constant expression in
".if" statement
It occurs when building ARM Trusted Firmware with aarch64-linux-gnu-gcc
that ships with Ubuntu 16.04. It does _not_ occur with an older Linaro
toolchain. More details in [1].
The .align directives in the vector_base and vector_entry macros _do_
make a difference. Are they the cause of the problem? Would you
recommend writing the code differently? Or is it a compiler bug?
[1] https://github.com/ARM-software/tf-issues/issues/401
Thanks,
--
Jerome
Hi all,
First sorry for the long message, but I am kinda stuck on an issue
with my split-stack work for aarch64, so any new eyes to check if
I am doing things properly would be really helpful.
I pushed my current work on a local gcc git [1] and glibc [2] branches.
The current code show not issue with the placed C tests, but there
is one elusive GO tests that fails for some reason.
The glibc patch is pretty simple: it adds a tcbhead_t field
(__private_ss) which will be used to hold the split stack thread
value. Different from stack protector, split-stack requires
a pointer per thread and it is used frequently on *every* function
prologue. So faster access is through TCB direct access (one
instruction less than TLS initial-exec). I plan to digress a little
more about why I decided to use TCB access, but in a short the advantages
are:
1. It is faster than TLS initial-exec
2. Does not require any static or dynamic relocation
The rest of patch is just to add a versioned symbol so either static
or dynamic linking fails for an older glibc (to prevent split-stack
binaries to run on non-supported glibcs).
The GCC patch is more complex, but it follows the already implemented
split-stack support on other architectures (x86, powerpc64, s390).
Basically you add hooks to generate the required prologue and other
bits (C varargs requires some work) and add some runtime support on
libgcc (morestack.S).
Split-stack idea is basically as this: let say you have a function
that requires a very large stack allocation that might fail at
runtime (due ulimit -s limit). Split-stack add some instrumentation
that check if the stack allocation will fail based on initial
value and allocates stack segments as required.
So basically a function would be instrumented as:
function foo
ss := TCB::__private_ss
if SP + stack_allocation_size > ss
call __morestack
// function code
What __morestack basically does is create a new stack segment with
some slack (using a platform neutral code), change the stack pointer
and continue run the function. So a stack frame for a function
that called __morestack is as:
foo
\_ __morestack
\_ // function code
And when the function code finished its execution (including all
possible function calls), it returns to __morestack so it restore
the old stack pointer and arguments.
Now, this is the most straightforward usage of __morestack. However
GO language allows a construct [3] that allows a function to register
a callback that is called at end of its scope that allows to 'recover'
from some runtime execution failure.
And this is the remaining GO tests that fails [4]. What it basically
does is run a set of tests that allocate some different structure and
try to access it in different invalid way to check if accessing a
know null pointer is caught by the runtime (GO adds null pointer checks
for some constructs).
9 func main() {
10 ok := true
11 for _, tt := range tests {
12 func() {
13 defer func() {
14 if err := recover(); err == nil {
15 println(tt.name, "did not panic")
16 ok = false
17 }
18 }()
19 tt.fn()
20 }()
21 }
22 if !ok {
23 println("BUG")
24 }
25 }
41 var tests = []struct{
42 name string
43 fn func()
44 }{
76 {"*bigstructp", func() { use(*bigstructp) }},
108 type BigStruct struct {
109 i int
110 j float64
111 k string
112 x [128<<20]byte
113 l []byte
114 }
So basically here it tries to allocate a very big structure (BigStruct with
about 128 MBs) on stack and since it does not have stack allocation it will
need to call __morestack.
Now, if have patient to read until now, the way GCCGO does that is by
throwing an exception to unwind the stack and to add some CFI directives in
both generated code and morestack to correct handling the unwinding.
So if GCC generates the unwind information for the objects and if __morestack
have the correct unwind information it should, so I presume my patch is
failing in either define the correct exception handler directives in
morestack.S or I am failing in generate the correct __morestack call.
The __morestack call is done at 'aarch64_expand_split_stack_prologue' in
my patch as:
--
+ /* Call __morestack with a non-standard call procedure: x10 will hold
+ the requested stack pointer and x11 the required stack size to be
+ copied. */
+ args_size = crtl->args.size >= 0 ? crtl->args.size : 0;
+ reg11 = gen_rtx_REG (DImode, R11_REGNUM);
+ emit_move_insn (reg11, GEN_INT (args_size));
+ use_reg (&call_fusage, reg11);
+
+ /* Set up a minimum frame pointer to call __morestack. The SP is not
+ save on x29 prior so in __morestack x29 points to the called SP. */
+ aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, 16);
+
+ insn = emit_call_insn (gen_call (gen_rtx_MEM (DImode, morestack_ref),
+ const0_rtx, const0_rtx));
+ add_function_usage_to (insn, call_fusage);
+
+ reg29 = gen_rtx_REG (Pmode, R29_REGNUM);
+ cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg29, cfi_ops);
+ reg30 = gen_rtx_REG (Pmode, R30_REGNUM);
+ cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg30, cfi_ops);
+ insn = emit_insn (aarch64_gen_loadwb_pair (DImode, stack_pointer_rtx,
+ reg29, reg30, 16));
+
+ /* Reset the CFA to be SP + FRAME_SIZE. */
+ new_cfa = stack_pointer_rtx;
+ cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
+ REG_NOTES (insn) = cfi_ops;
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ emit_use (gen_rtx_REG (DImode, LR_REGNUM));
+
+ emit_insn (gen_split_stack_return ());
--
I do not add any stack frame allocation for the call, so it might a source
of issues.
Another issue might in morestack.S unwinding directives that is not following
the ABI correctly. I am revising it using GCC generated exceptions examples.
[1] https://git.linaro.org/toolchain/gcc.git/shortlog/refs/heads/linaro-local/a…
[2] https://git.linaro.org/toolchain/glibc.git/shortlog/refs/heads/azanella/spl…
[3] https://blog.golang.org/defer-panic-and-recover
[4] gcc/testsuite/go.test/test/nilptr2.go
=== This Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367] [3/10]
-- Implementation successful without the need for instruction emulation.
-- Watchpoint hit detection fixed with ptrace reporting hit address correctly.
-- Used up watchpoint HitAddress function to return back the real
address to host.
Investigation of Nexus devices kernel issues.[TCWG-622] [2/10]
-- Figured out steps to build custom kernel for Neuxs7.
-- Kernel fails to boot though.
LLDB hardware watchpoint capability test and skip watchpoint testing
[TCWG-622] [2/10]
-- Submitted a patch to report back correct reason for watchpoint
creation failure.
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- A look into LLDB xfail decorators to fail on the basis of arm ABI.
-- Out of office on Thursday 9th June for visa interview.
=== Next Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Finish up work, test and submit for review upstream.
LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622]
-- Patch review and further progress.
Miscellaneous
-- Testsuite Makefile.rulez update still pending, hopefully will be
done this week.
-- Xfail decorator updates to xfail based on ARM ABI.
=== This Week ===
Investigation of Nexus devices kernel issues.[TCWG-622] [6/10]
-- Figured out source trees for various android devices and checked
out kernel code.
-- Comparison between watchpoint implementation of different kerenel
sources supported by Nexus devices.
-- Figured a way to burn a custom rom with updated kernel on Nexus 7.
-- Figured Kconfig issue that was causing watchpoints not to be
detected on Nexus 7.
-- Watchpoint installation still doesnt work on Nexus 7.
LLDB buildbot updates and maintenance [TCWG-241] [2/10]
-- Upgraded cmake version after migration to new version.
-- Migrating local buildbot setup (builders and testers) to ubuntu xenial 16.04
-- Buildbot restart after power outage.
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Out of office on Tuesday 31st 2016 for visa documents preparation.
=== Next Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Continue work on hardware watchpoint support.
Investigation of Nexus devices kernel issues.[TCWG-622]
-- Figured out steps to build custom kernel for Neuxs7.
LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622]
-- Investigate possible ways to solve this issue.
Miscellaneous
-- Out of office on Thursday 9th June for visa interview.
* One day off on Thu [2/10]
# Progress #
* TCWG-639, non-8-byte-aligned watchpoint is missed on aarch64. [4/10].
It is caused by limited kernel BAS support. RedHat reports this
problem and posts a patch. Good to see they start to contribute to
aarch64 GDB, but I don't like the patch. Spend much time writing a
prototype to prove their patch is not perfect. We agree to fix this
problem by extend RSP fortunately.
* TCWG-333, [3/10] I follow the way how mips does, and fix some bugs.
* TCWG-547, TCWG-518, blocked in upstream review.
* Misc, meetings. [1/10]
# Plan #
* TCWG-333, TCWG-556.
* Ping TCWG-547, TCWG-518.
--
Yao
== Progress ==
o Extended Validation (4/10)
- Investigate and reported Glibc/libsanitizer issue
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71445
- Looked at benchmark job issues
- Discuss benchmark/lava notification mechanism
o Linaro GCC (1/10)
- Merged FSF GCC 5.4 branch
o Upstream GCC (3/10)
- ARMv8.1 libatomic investigation:
seems to work fine when enabling multilib on AArch64
need to investigate completeness of the support.
o Misc (2/10)
* Various meetings and discussions.
* Backlfip patch reviews
== Plan ==
o Backport reviews and June snapshots
o Continue libatomic
o Benchmarking job fixes.
== This Week ==
* LTO (5/10)
a) committed r237207 to fix unresolved test-cases added in r236503 (1/10)
b) move increase_alignment pass to regular pass (3/10)
- Patch iterations based on suggestions from Honza and Richard
- Understanding lto streaming and decl merging code
c) TCWG-548 (1/10)
- WIP patch
* TCWG-319 (1/10)
- updated patch submitted upstream:
- changing vect_hw_misalign causes regression for vect-align-1.c
* Benchmarking (1/10)
- Benchmark successfully ran for linaro-gcc-5 submitted by Yvan
- Benchmark for fsf-gcc-6 failed both with prebuilt route and letting
job build the benchmark
* Misc (3/10)
- Meetings
- Travel to Mumbai for Schengen Visa appointment
== Next Week ==
- Try to get patch committed for increase_alignment
- TCWG-319: Look at vect-align-1.c regression
- TCWG-548: Complete implementation and validate patch.
- ipa-vrp: Experiment with Kugan's patch.
== Progress ==
* Validation
- disk full on one builder caused problem during the validation of
the long series of backports. We'll have to refine the cleanup policy.
- switch to docker on-hold until the builders are upgraded
* ABE
- looked a bit at the gdb/gdbserver issue
* Backports
- used a script to process the spreadsheet and submitted all the
backports that backflip was able to complete in batch mode (a lot!)
- fsf-5-branch merge review
* GCC
- regression reports on trunk, chasing problems that occur in corner
case configurations
- One of the Neon intrinsics tests I committed recently wrongly
executed v8 Neon code on v7 HW: I didn't catch this earlier because of
a bug in qemu, promptly fixed by Peter Maydell
- neon-testgen.ml removal delayed because other cleanup is desirable
before (fixing neon* effective-target tests on-going)
- started looking at PR 67591 (ARM v8 Thumb IT blocks deprecated)
* Support
- started looking at bug 2315
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- patch reviews
- look at disk management/cleanup
* Backports
- check validation results
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- fix neon* effective-target
- hopefully test-neongen.ml removal
- pr 67591
- advsimd tests
== Progress ==
TCWG-607 Initial ARM port for LLD committed upstream. Hello World on
an ARM with an ARM only gcc libc is possible, but not much else.
TCWG-611 Initial Thumb support sent for upstream review. Interworking
is possible at the BLX level but full interworking support
(veneers/thunks) isn't there yet. With this patch it will be possible
to do Hello World with a recent Linaro gcc release.
TCWG-634 llvm-mc putting out R_ARM_THM_PC24 for B<cond>.W instead of
R_ARM_THM_PC19. Simple fix now committed upstream.
== Plans ==
Interworking thunks for lld. The existing thunk design is very simple
and only supports one type of thunk per target. For interworking we
need at least two (ARM to Thumb) and (Thumb to ARM).
I think it might be possible to fit a basic implementation just good
enough for ARMv7a to be correct into the existing mechanism, however
just one more thunk type will need a more sophisticated design.
Current thought is to try and implement the basic design to learn a
bit more about the mechanism as it will hopefully not take too long.
== Progress ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing the MIR tests (PR27770) - committed upstream
- Submitted a patch fixing one of the AMDGPU tests (PR27761) - in
upstream review
- Submitted a patch fixing the ARM test (PR27765) - in upstream review
* Use git worktree in llvm helper scripts [TCWG-587] [1/10]
- Minor fixes during the review, hopefully we can wrap it up soon
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [3/10]
- Investigated uses of isCortexA*, isSwift etc in the ARM backend
- Started extracting subtarget features for the easy ones
* LLVM ARM 3.8.1 [TCWG-642] [1/10]
- Ran the ARM tests for the LLVM 3.8.1 release
* Investigate clang-cmake-thumbv7-a15-full-sh failure [TCWG-635] [1/10]
- Found patch that was causing problems, started discussion about it
on the mailing list
== Plan ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Address any code review comments
- After committing the 2 remaining patches, we should be able to
remove the flag and wrap this up
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
- Extract more subtarget features
* OOO on Monday
== This Week ==
* LTO (6/10)
a) increase_alignment (2/10)
- posted patch upstream to convert it to regular pass
b) TCWG-548 (3/10)
- Lava job #3424 failed with timeout (same as #3370)
- Experimenting with partition sizes with and without the patch for
different benchmarks,
results consistently show a significant difference in last partition size.
- Trying a new approach.
c) TCWG-535 (1/10)
- posted partial patch upstream:
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00143.html
* TCWG-72 (2/10)
- Further patch iterations
- Approved by Richard
* Misc (2/10)
- Looked at function versioning.
- Wrote patch to address missing diagnostic in C/C++ FE, fails on bootstrap.
- Meetings
== Next Week ==
- TCWG-548: Implement new approach and experiment with it.
- ipa-vrp: Apply Kugan's prototype patch, and test it, sync on early vrp.
- TCWG-72, TCWG-319, TCWG-535, increase_alignment: ping for reviews.
- Travel to Mumbai on Monday for Schengen Visa appointment
== Progress ==
o Upstream GCC (4/10)
- Continuing ARMv8.1 libatomic investigation
(some infra issues now fixed)
o Misc (6/10)
* Various meetings and discussions.
* patch reviews
* Benchmarking notification investigation
* Booked Hotel and flights for tcwg sprint
== Plan ==
o Continue libatomic
o GCC 5.4 branch merge
o Benchmarking notification
== Progress ==
Fixed Bugs and posted patches for review
- PR71281 and PR71408
PR66726 - Convert expr
- Found way to handle this well and posted a patch.
IPA VRP
- Started with a simple implementation for intra-procedural early VRP
by refactoring tree-vrp.
- Still need to handle range dominance
- Ran into a latent issue in tree-vrp. Looking into it.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
On 3 June 2016 at 17:10, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote:
> Do keep in mind you are comparing a 11 year old project and a 11 month
> old one. There is a lot more churn on the 11 month old one.
LLD is at least 5 years old. Every time you re-write it doesn't reset history.
> Again, I am truly sorry we were unable to come up with a perfect
> design the first time. For the record, I don't think it is perfect
> yet. There will likely be more big changes to lld. That is the cost of
> trying to build as good a linker as we can.
This is not about what you do. It's about *how* you do it.
We have developers trying to create a linker. They are working on LLD
because Chris wanted a true LLVM linker. But it seems that you want a
project that you can do whatever you want, whenever you want.
This is *NOT* open source. Right now, LLD is *nothing more* than Rui's
and Rafael's pet project. I cannot recommend Linaro to collaborate on
those terms, and I sincerely recommend anyone that is listening to
this thread to not do so either.
> Being open source doesn't mean I get to implement what someone else
> wants. You are more than welcome to send patches, but they have avoid
> harming the rest of the linker. In particular, at this early stage
> they cannot harm its development. Once we have a mature project we can
> actually evaluate tradeoff.
We're clearly not welcome to send patches. We did, and you re-wrote it
and committed without asking the original author.
So, the plan is to wait for you to finish the initial implementation
alone? Again? What do we do in the interim? How many times are we
going to go through this?
I have waited 2 years before LLD was barely useful, then Adhemerval
implemented the AArch64 back-end. Then you destroyed and now we have
waited another year, but we're still unable to collaborate. If
anything, now it's even harder than it was last year.
Why can't we help with the design, too? We know about ARM and AArch64,
that's what we do, and we can provide you with the expertise without
having to go on your own doing everything. That is the whole point of
collaborative development, and it seems that you're missing this
point.
> And just like we did, you are more than welcome to try to write
> something better. Please let us know how it goes.
Is this the position of every LLD developer?
Rui, Nick, Chris?
I'm seriously looking for others to chime in and let me know if that
is the final stance on LLD, so that I can finally write it off and go
work on another linker.
If the official position is that LLD is a project that only Rui and
Rafael can design and implement for another 2~3 years, I *cannot*
recommend Linaro and its members to participate.
cheers,
--renato
== Progress ==
- Holiday Monday/Tuesday
- Finished writing initial support for ARM in lld. Posted upstream as
RFC, no comments so far.
- Implemented, but not tested the static Thumb relocations present in
the arm-linux-gnueabihf-gcc
-- I'd forgotten how much I hated the Thumb 2 instruction encodings.
== Plan ==
- Add tests for Thumb relocations
- Start thinking about how interworking can be implemented in lld
* Monday off [2/10]
# Progress #
* TCWG-518, arm linux range stepping. [4/10]
Finished V2, and send them out for review.
More bugs in existing GDBserver are found, fixed them as well.
8 patches become 12 patches.
* Upgrade linux kernel on chromebook to verify Russell King's ptrace
fix.
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-May/431972.html
[3/10]
This may be the cause of unstable result of GDB floating point tests,
and they are tracked by GNUTOOLS-4858.
4.6.1 is running on chromebook now, but haven't try the patch yet.
* TCWG-547, "align software single step in other targets with arm's
implementation".
Patches are pending for review. Pinged Pedro to give a review.
* Misc, [1/10]
** Commit fix to PR 19998, and review the follow-up patch.
** meeting and training,
# Plan #
* TCWG-518, TCWG-547, TCWG-333
--
Yao
== Progress ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing the MIR tests (PR27770) - still in upstream review
- Submitted another patch fixing two other BPF tests (PR27768/9) -
committed upstream
- Submitted a patch fixing one of the AMDGPU tests (PR27761) - in
upstream review
- Investigating the ARM test (PR27765)
* Use git worktree in llvm helper scripts [TCWG-587] [4/10]
- In review, hopefully we can wrap it up soon
* Misc [2/10]
- More LLVM backend education (MI level), ARM ARM etc
== Plan ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Fix the ARM test
* Use git worktree in llvm helper scripts [TCWG-587]
- Fix a regression in the error-handling
- Address review comments
On 2 June 2016 at 23:22, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote:
> Because the patch includes way too much and doesn't explain what it is doing.
So let me get this straight: someone publishes a patch, you don't like
it, you do some private investigations and commit whatever you want
without even notifying the original authors?
I don't know how you work at your company, but this is not how open
source development works.
This is not the first time either that you step over people's toes
with your "design decisions" that you don't share with anyone. Last
year, Adhemerval has worked for three months to get the LLD AArch64
back-end working and out of the blue, no warning, the whole back-end
was yanked.
It doesn't matter if it was the right decision or not in the long
term, we don't just yank things, especially not before some
deliberation on the list. See how long is taking for the new pass
manager to be enabled, or FastIsel or the new Selection, or the new
register allocators, etc.
That's not how open source works and I assumed you knew that.
> That is a general problem with aarch64, the documentation is missing
> and comments have to make due. I had a lot of work to rewrite the
> original aarch64 patches to be in line with the rest of lld and I
> didn't want to have to do the same for tls.
You shouldn't be rewriting *any* patch, but asking the original
authors to do that themselves.
There is a pattern that I'm seeing and that's that *you* refuse or
dismiss more patches than most other people. There are many of your
comments on reviews that are just personal, and then you step over
people's toes and commits yourself.
This does not scale. But more importantly, it puts into doubt the
validity of the tool you're so hardly defending.
You see, 3 years ago, I was asked to choose between MCLinker and LLD.
MCLinker was a linker for all purposes, but Chris Lattner convinced me
that LLD is the LLVM linker, and we should be focusing all efforts
there.
It goes against the commercial interests of Linaro members to choose
such a premature technology, and it did put them back years of
development, because MCLinker was very close to ready, and MediaTek,
despite what people said, was very willing to accept our help.
But in the interest of the community, and the open source nature of my
work, I have decided to pursue LLD and managed to convince Linaro to
put two people working on it. But now, I'm re-evaluating all my
strategy, and sincerely, I do not trust the LLD community anymore.
> The delay was because of the above mentioned issues. I wanted to make
> sure there was a solid foundation.
Some patches are quick to review, others take 6 months. If you work in
open source you have *got* to understand that. If you're not willing
to take that cost, than please, refrain from working open source.
> Sorry, no.
I understand your position, but you have to understand mine. I
therefore call into question your ability to care about such an
important project of the LLVM community.
I sincerely believe that your actions are harming the project, and the
people trying to help. I appreciate the value of your contribution, I
really do, but if you don't change your way to handle open source
contributions, LLD will, whether you like it or not, become irrelevant
and be replaced.
Such is the nature of open source.
cheers,
--renato
On 2 June 2016 at 20:49, Rafael Espindola via llvm-commits
<llvm-commits(a)lists.llvm.org> wrote:
> Author: rafael
> Date: Thu Jun 2 14:49:53 2016
> New Revision: 271569
>
> URL: http://llvm.org/viewvc/llvm-project?rev=271569&view=rev
> Log:
> Start adding tlsdesc support for aarch64.
>
> This is mostly extracted from http://reviews.llvm.org/D18960.
Rafael,
Why commit part of Adhemerval's patch without reviewing his request?
This is a really serious breach of community trust.
Not only we're waiting for reviews on the TLS set of patches and
having to rebase every two weeks, but now you implemented in a way
that wasn't discussed on the review, didn't mention authorship, nor
asked Adhemerval for any input.
If you had technical input on his patch, you should have done on the
review. If you wanted him to split in smaller patches, you should have
asked on the review and let *him* do it.
Even if you were the code owner (which you're not), it would still be
a *serious* breach of trust and respect.
I hereby respectfully request that you revert your patch and let
Adhemerval finish the work that he started in the way that we normally
do in the LLVM community.
regards,
--renato
* Off on Friday [2/10]
# Progress #
* TCWG-518, V1 got reviewed, and working on V2. Two existing bugs in
GDBserver are found, and fixed. Testing them... [4/10]
* Upstream patches review, all of them are about GDB python. [2/10]
* Respond to Jim Wilson's question on AIX GDB build failure caused by
his binutils patch for AArch64. Confirm that GDB build fail after
his patch. [1/10]
* Misc, [1/10]
# Plan #
* Bank holiday on Monday,
* TCWG-518, get V2 ready for review,
* Ping TCWG-561 and TCWG-547,
--
Yao
=== This Week ===
Resolved TCWG-231 (LLDB bring up and bug fixing on HiKey 96Board)
[TCWG-231] [1/10]
-- Ran tests on AArch64 LLDB tests on HiKey and compared with Nexus 9
test results.
-- Less than 1% difference in test results and good pass rate found.
LLDB ARM: Bug fixes, integration and testing on various ARM platforms
[TCWG-228] [2/10]
-- Progressed towards resolution.
-- Prepared close out setting up RaspberryPi2, RaspberryPi3, Hikey and
Chromebook as testers.
-- Compiled armhf test results.
LLDB Chromebook Test Stability [TCWG-563] [2/10]
-- Some further investigation on llvm-chrome-06 test failures.
-- Marked and committed some xfails and reported relevant bugs if not
already logged.
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367] [1/10]
-- Debugging of watchpoint handling code and tried out instruction decding.
LLDB buildbot updates and maintenance [TCWG-241] [2/10]
-- Improved tester script to initiate lldb-server inside a chroot.
-- Monitored buildslave stability and
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Migrated laptop to Ubuntu 16.04
=== Next Week ===
LLDB Chromebook Test Stability [TCWG-563]
-- Final words on watchpoint issue on llvm-chrome-06
-- Submit updated makefile.rulez for LLDB tests.
-- Report remaining bugs and commit xfails upstream.
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Implement instruction decoding for watchpoint hit detection.
A look into kernel code used by Nexus android devices failing
watchpoint support [TCWG-622]
Miscellaneous
-- Out of office on Tuesday 31st 2016 for visa documents preparation.
* ! day off (2/10)
== Progress ==
o Extended validation (2/10)
- Benchmarking comparison script on-going
- Reproduced armhf schroot slowness on AArch64 Debian Jessie
No issues when using Ubuntu (Trusty and Xenial).
o Upstream GCC (4/10)
- Started ARMv8.1 libatomic support
(environment setup, code understanding, ifunc support analysis)
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue libatomic work
== This Week ==
* TCWG-72 (6/10)
- Patch iterations based on Richard's suggestions
- Reworked most of convert_to_divmod()
- Fixing regressions with the patch and added test-cases.
- ICE with -m32 on x86_64 for DImode division/mod:
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02302.html
* LTO (2/10)
a) TCWG-548 (1/10)
- Benchmarking jobs submitted twice and failed.
b) TCWG-535 (1/10)
- Figured out why ICE happens with my patch.
* TCWG-319 (1/10)
- Validated patch and posted upstream.
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-72: Try to workaround issue with -m32
- TCWG-548: start relooking at section anchors.
- TCWG-535: Post patch upstream.
== Progress ==
PR71252 - ICE in rewrite_expr_tree
- Tried various options to fix this and settled on an implementation
- Patches sent for upstream review
- tested with cpu2006 too
- One patch approved
PR66726 - Convert expr
- Newlib test case is failing due to mi compiled lib
- Trying to reduce test case
== Plan ==
Follow upon remaining upstream patches
IPA VRP
== Progress ==
* LLD Port:
- Got hello world running.
-- Needed a horrible hack to make lld output PLT and GOT entries for
unresolved weak references with default visibility.
- Wrote up in Jira the major areas of work that would be needed for a
useful port.
- Started putting in changes cleanly and writing tests for them.
- Currently hitting a few problems with llvm-mc. I can't generate the
relocations I need to test the linker. The hello world test case used
mainly GCC library objects.
-- Most serious is not emitting R_ARM_BASE_PREL for .word
_GLOBAL_OFFSET_TABLE - (label+8)
== Plan ==
* On holiday Monday and Tuesday
* LLVM MC
See how easy it would be to add missing features to llvm-mc as it
would allow me to write more tests.
* LLD
Complete the test cases for the code I've added.
Take stock of where the lld port is and decide where to go from there.
Options are:
- Send an RFC upstream with what I have. It is not sufficient to run
hello world but should be relatively uncontroversial.
- Cleanly implement the emit the unresolved weak references in the PLT
and GOT so hello world will work out of the box on ARM.
- Keep going until I've got Thumb2 support so I don't have to use ARM
only static libraries to make hello world working.
There is obviously a trade off between having a useful linker and the
patch size getting out of hand.
== Progress==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [5/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Last week's patch fixing the MIR tests (PR27770) - still in upstream review
- Last week's patch fixing an AMDGPU test (PR27762) - committed upstream
- Last week's patch fixing a BPF test (PR27766) - committed upstream
- Submitted another patch fixing a BPF test (PR27767) - committed upstream
- Submitted another patch fixing two other BPF tests (PR27768/9) -
in upstream review
- Investigating one of the AMDGPU tests (PR27761)
* Use git worktree in llvm helper scripts [TCWG-587] [4/10]
- Started a RFC and a wiki page about the new workflow [1]
- People seem to be in favour of it, but there are still some TODOs
left before we can merge
* Misc [1/10]
- Meetings, buildbots
== Plan ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Submit a patch for the AMDGPU test (PR27761)
- More investigations on the ARM test (PR27765)
* Use git worktree in llvm helper scripts [TCWG-587]
- Finish the final touches and have a proper review
[1] https://collaborate.linaro.org/display/LLVM/Git+Worktree+Proposal
== Progress ==
* Validation
- cleanup
- Fixed regressions in abe (gcc_update, make install, gdb timestamps)
- updated abe stable branch (now matches master)
- various Jenkins jobs updates, prepared support for gcc-6 based toolchains
- compared results of armv8l vs arm toolchains: few, expected
differences due to different default tuning
* GCC
- regressions reports on trunk
* Misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation
- actually update the Backport job
- prepare switch to docker for buildfarm job
- cleanup
* Backports
* GCC
- trunk monitoring
- more on AdvSIMD intrinsics
Sorry for hitting the wrong mailing list. OK I will check with HTTP instead of HTTPS. Thanks for your time & help.
On May 25, 2016 11:02 PM, Jim Wilson <jim.wilson(a)linaro.org> wrote:
On Wed, May 25, 2016 at 8:09 AM, Gujulan Elango, Hari Prasath (H.)
<hgujulan(a)visteon.com> wrote:
> I enabled the -v option of wget and I am able to see the download starts and
> fails randomly after progressing to some extent i.e. 10% or 27%. The
> connection is reset by peer and wget exits. I tried increasing the timeout
> option of wget as well.
This is some kind of networking or web server problem. We only know
how to fix compiler problems here on the linaro-toolchain list. I did
confirm that I can download the file OK, both via wget and via
chrome.. I noticed that the https support on releases.linaro.org is
not working, and I had to use http instead, but it isn't clear if that
is related to your problem.
Jim
Hello,
We have cloned the meta-linaro layer and when we build,we are facing some issues when the do_fetch() task is executing for the gcc-source-linaro-5.1 package.
I enabled the -v option of wget and I am able to see the download starts and fails randomly after progressing to some extent i.e. 10% or 27%. The connection is reset by peer and wget exits. I tried increasing the timeout option of wget as well.
Any idea what's wrong. Find attached the log of the error.
Thanks & Regards,
Hari Prasath
Cisco is trying to use clang/lto on big-endian arm, which apparently
requires gold, and gold does not support the --be8 option which is
required for ARMv7 big-endian support. Does anyone here care about
this?
Umesh Kalappa asked about this on the binutils mailing list
https://sourceware.org/ml/binutils/2016-05/msg00209.html
and discovered that it is a known bug reported 5 years ago
https://sourceware.org/bugzilla/show_bug.cgi?id=13213
Jim
== Progress ==
o Extended validation (7/10)
* Investigate GDB instabilities:
- branch tracing issue are due to builder feature support
- Our 2 old builders, which don't support it, removed from x86
validation pool
* Benchmarking:
- Looked at Lava instance API and lava-tool usage and prerequisite
- Implementing comparison script
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Continue on validation/benchmarking
o Catch up with upstream work.
=== This Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367] [3/10]
-- Made changes to NativeRegisterContext_arm64 to support multiple
watchpoint slot for a single watch address.
-- Enabled unaligned watchpoints and experimented with resulting false
positives.
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Migrated local builder to Ubuntu 16.04 xenial
-- Ran LLDB testsuite with GCC 5.x.x on chromebook, raspberryPI2
-- Updated LLDB testsuite makefile.rulez to use correct cross AR and OBJCOPY
LLDB buildbot updates and maintenance [TCWG-241] [2/10]
-- Investigation of LLDB buildbot slave failure
-- Implemented stale log deletion mechanism by making sure we keep
only 10 most recent logs.
LLDB upstream collaboration and Arm/AArch64 Linux port maintenance [1/10]
-- Verify patches under review
-- Analyzed TestTopLevelExprs on LLDB arm failure and committed xfail.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
-- Travel bookings for connect and TCWG sprint.
=== Next Week ===
Close out TCWG-231 (LLDB bring up and bug fixing on HiKey 96Board)
-- Run and comparison of AArch64 LLDB test results vs hikey showing
less than 5% difference.
Close out LLDB Chromebook Test Stability [TCWG-563]
-- Make sure there are no failures for which we dont know the underlying reason.
-- Report remaining bugs and commit xfails upstream.
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Further testing of false positive results due to allowing
un-alligned watch-points.
LLDB buildbot updates and maintenance [TCWG-241]
-- Figure out difference of test results between local and remote chromebooks.
-- Figure out a way to hide unused test slots by buildbot factory.
Miscellaneous
-- Migrate laptop to ubuntu 16.04 in hope of better driver support.
-- Portugal visa and travel booking
== Progress ==
* Validation
- cleanup
- reviews
- asserting ABE master vs stable results
- stopped investigation on a huge number of unexpected
regressions, maybe caused by builders crashes
- created a Jenkins job able to detect the base GCC
branch, in order to select the right libc/binutils version
- found why ABE master showed regressions with the
_Pragma3 GCC test. Fix under review.
- investigating recent, numerous build failures
* Backports
- updated backport to fix bug #2185 after Kugan analysis
- drafted a script to parse the spreadsheet and generate
the backflip commands as appropriate
* GCC
- reported a couple of regressions on trunk
- Neon intrinsics tests update: committed.
We are now ready to remove neon-testgen.ml
== Next ==
* Validation
- cleanup
- armv8l vs arm
- ABE master vs stable
* GCC
- trunk monitoring
- more on AdvSIMD intrinsics
== Progress ==
PR40921 -missed optimization: x + (-y * z * z) => x - y * z * z
- Patch committed
PR63586 - x+x+x+x -> 4*x in gimple
- Patch committed
- There were couple of fallouts
PR71179 - ICE fold_convert_loc, at fold-const.c:2360
- Patch committed
PR71170 - ICE in rewrite_expr_tree, at tree-ssa-reassoc.c:3898
- Tried various options to fix this and settled on an implementation
- Patch sent for upstream review
== Plan ==
Follow upon remaining upstream patches
IPA VRP
== This Week ==
* TCWG-528 (2/10)
- Addressed comments from Richard and committed upstream (r236502, r236503)
* TCWG-72 (5/10)
- Updated patch and fixed regressions caused due to patch.
* TCWG-319 (1/10)
- Found why big endian vectorizer was not vectorizing the test-case with -O2.
* Holiday (2/10)
== Next Week ==
- TCWG-319: Post patch upstream and get it committed.
- TCWG-72: Post patch upstream and hopefully get it committed this week.
- TCWG-548: Start re-looking at section anchors.
=== Progress ===
TCWG-591 MOVW incorrectly allowed on ARM v5 committed upstream
TCWG-595 LLD port to ARM architecture
I am getting close to being able to run hello world built with lld.
I'm converging 1 bug at a time.
- The PLT handling code is working and the loader can execute the
image and starts the .init function.
- Currently failing in the weak call to __gmon_start__. At present lld
is removing undefined weak references from executables instead of
passing them on for the dynamic loader to resolve. This may not be
necessary on x86 but it is necessary on ARM.
-- Just finished a hack that should make this work, although it will
need some tidying up.
=== Plan ===
Get hello world working and then take stock of what I've learned and
come up with a plan in Jira for what needs to be done.
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [1/10]
- Fixed and rebased the patch, it has been committed upstream
* Inline assembly constraints support for ARM [TCWG-560] [1/10]
- Rebased the patch, it has been committed upstream
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Submitted a patch fixing the MIR tests (PR27770) - in upstream review
- Submitted a patch fixing an AMDGPU test (PR27762) - in upstream review
- Submitted a patch fixing a BPF test (PR27766) - in upstream review
- Investigated the ARM test (PR27765)
* Use git worktree in llvm helper scripts [TCWG-587] [3/10]
- Working on a prototype
* Misc [1/10]
- Meetings, buildbots, IRC issues
- Got LLVM commit access, yay!
== Plan ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Fix the remaining ARM, BPF and AMDGPU tests (unfortunately the ARM
test seems a bit more involved, so I might pick out the others first
just to get them out of the way)
* Use git worktree in llvm helper scripts [TCWG-587]
- Continue prototyping, start a RFC on it next week
# Progress #
* TCWG-518, [6/10]
fix all bugs, and post them upstreams for review!
* PR 19998, write a patch to fix it. [2/10]
* Some discussions on unstable GDB test results in validation tests.
[1/10]
* Meetings [1/10]
# Plan #
* Respond comments to my patches,
* TCWG-333, think about the right fix.
--
Yao
This may be a better question for the linaro tools group. +cc their list
for the general question of conventions surrounding how shared library
objects identify and access thread-local storage that they need as part of
calling threads.
On Tue, May 17, 2016 at 11:06 AM, Nikhil Agarwal <nikhil.agarwal(a)linaro.org>
wrote:
> Hi All,
>
> I am trying to write a shared library object over ODP. Our ODP library has
> some per thread variables. When my application invokes an API of shared
> object which accesses per thread variable it gives segmentation fault.
>
> My concern is that when a shared object is loaded dynamically, how memory
> is assigned to thread specific variables defined inside shared objects.
> AFAIK we need to compile it with -ftls-model=global-dynamic, which is
> enabled by default when compiled with -fPIC flag, and library loader
> takes care for these issues.
>
> I am not an expert in this area, please help me in getting to some
> suitable reference pointers or some steps I might have missed.
>
> Thanks in advance
>
> Nikhil
>
=== This Week ===
Enable LLDB testsuite to show zero failures on Hikey 96 Board (AArch64
Linux) [TCWG-231] [4/10]
-- Ran multiple builds and testsuite runs to figure out latency issues.
-- Investigated remaining failures and submitted appropriate bugzilla bugs.
-- Committed xfails upstream.
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367] [1/10]
-- Some investigation on possible solutions and frequently encountered
scenarios.
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Investigation of noreturn unwinding test failure
-- Investigation of step over load library call failure
-- Investigation of other failures and commit xfails for reported issues.
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Portugal visa information gathering
=== Next Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Add code changes required to manage a watchpoint with multiple
hardware watchpoint resources.
LLDB Chromebook Test Stability [TCWG-563]
-- Fix noreturn unwinding test failure and report relevent bug.
-- Fix step over load library call failure or report relevent bug.
Miscellaneous
-- Portugal visa application documents preparation.
== Progress ==
* Validation
- cleanup
- reviews
- looked a bit a using docker from Jenkins
- investigating how to select toolchain components versions
depending on the gcc version
* GCC
- Sent Neon intrinsics tests patches.
- trunk timeouts: caused by the libcilkrts merge, which has a bug on
arm. Disabled cilkplus to avoid too much noise in the results.
- reported a couple of regressions/bisects
* Misc (conf-calls, meetings, emails, ....)
- support for M-profile related queries ( multilib etc...)
== Next ==
* Validation
- cleanup
- reviews
- armv8l vs arm
- multiple gcc branches vs other components versions handling
* GCC
- trunk monitoring
- some dev if time permits
== Progress ==
o Linaro GCC (5/10)
* Linaro GCC 5.3 2016.05 snapshot
- FSF branch merge + release
* Linaro GCC 6.1 2016.05 snapshot
- Create new branch + release
o Extended validation (3/10)
* Fixed validation issues when binary tarballs are created.
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on validation/benchmarking
o Catch up with upstream work.
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [5/10]
- Started a discussion about a new diagnostic handler for llc
- Patch accepted upstream, but broke a few things (Renato has
investigated/fixed some of them - thanks)
* Inline assembly constraints support for ARM [TCWG-560] [5/10]
- Patch in upstream review, but should be committed after the new
llc diagnostic is in place (otherwise it's difficult to test it
meaningfully)
== Plan ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592]
- Fix the remaining issues and get the patch committed again
* Inline assembly constraints support for ARM [TCWG-560]
- Rebase patch and try to get it reviewed
* Investigate exit-on-error on LLC [TCWG-594]
- Track the tests that need the exit-on-error flag with the new
diagnostic handler
== Progress ==
- ldr rt,= implementation transform to MOV committed upstream
[TCWG-468] [PR25722]]
-- Thanks to Renato for committing.
- Started looking at what would be needed to port lld to ARM
-- The ELF lld port looks to have a fairly small amount of
architecture specific hooks. Decided that I would learn fastest by
just trying to do an ARM only prototype port to see if I could get
hello world on linux working.
-- spent too much time trying to think about how to best implement the
group relocations for the PLT sequences then remembered that for a
quick prototype I could use larger sequences that didn't need the
relocations.
== Plan ==
- Continue working on an ARM LLD port. Will hopefully have a good idea
of what the scope of work needed is next week.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.05 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn236106 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.05/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn236106
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.3+svn236108 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn236108
* Backport of [Bugfix] [AArch32] PR target/70711 Fix big-endian ARMv8.1-A builds
* Backport of [Bugfix] [AArch64] PR target/70044 -flto turns on
-fomit-frame-pointer
* Backport of [AArch32] Reduce size of arm1020e automaton
* Backport of [AArch64] Fix SIMD predicate
* Backport of [AArch64] Fix thinko in handling of
-momit-leaf-frame-pointer option
* Backport of [Testsuite] [AArch32] Tests for arm_restrict_it patterns
in thumb2.md
* Backport of [Testsuite] gcc-dg: handle all return values when
shouldfail is set
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 3 days off (Mon/Thu/Fri) [6/10]
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071; found the cause of the bug,
working on a fix.
* Rework LLVM helper scripts [TCWG-571] [1/10]
- Addressed code review comments.
- The interface changes to llvm-projs and llvm-sync are now committed.
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- Come up with a fix for PR24071
* Rework LLVM helper scripts [TCWG-571]
- Investigate git worktree and how it could be factored into our
scripts (llvm-projs, llvm-build)
o 2 days off (4/10)
== Progress ==
o Extended validation (4/10)
* Change extended native job to use multiple scm
* Investigate validation issues when binary tarballs are created
o Linaro GCC (1/10)
* Finalized and submitted new Linaro development branch script.
o Misc (1/10)
* Various meetings and discussions.
== Plan ==
o Create Linaro GCC 6 branches
o Continue on validation and upstream work.
* 2 days off (Thu/Fri)
== Progress ==
* Validation
- restarted validations for pending backports, after the various
branches updates
- started looking at armv8l vs arm results differences
* GCC
- checked trunk regression reports
- updated AArch32 Neon intrinsics tests. Patch series almost ready
for submission
* Misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation
- cleanup
- reviews
- armv8l vs arm
* GCC
- trunk monitoring: check why builds were killed after timeout
- more intrinsics tests
== This Week ==
* LTO (7/10)
a) TCWG-548 (2/10)
- Fixed a minor bug in the patch
- Results of variable partitions with chromium: http://pastebin.com/fLD2JzgP
- Significant difference in size of last partition could probably
indicate sth wrong with
patch (all unpartitioned variables go to last partition).
b) TCWG-528 (3/10)
- Posted upstream after bootstrap+test passed on ppc64le-linux-gnu
- Addressed Richard's comments.
c) TCWG-299 (2/10)
- Firefox built on aarch64 natively (r1-a12) non LTO with gcc-5 branch
- Fails to build with trunk due to issues in firefox codebase (PR70722)
- Fails to build on armhf with following error: http://pastebin.com/9xydVtjj
* TCWG-72 (2/10)
- Rebased patch
- Addressed Ramana's comments
* Misc (1/10)
- Meetings
== This Week ==
- LTO: benchmark section anchors patch, submit patch for
increase_alignment upstream, firefox
- TCWG-72: Test and submit upstream
* Monday off [2/10]
# Progress #
* TCWG-468, ldr rt, =immediate
Have a feature complete implementation. Passes existing regression tests.
Still need to add more tests for new functionality and see if
implementation can be tidied up a bit
* Setting up a local chromebook to run the regression-tests. Should
now be able to run test suite on ARM relatively easily.
# Plan #
* Complete TCWG-468 and send upstream for review.
* Pick something else up.
* Monday off [2/10]
# Progress #
* TCWG-518, arm linux range stepping patches. [5/10]
Tried different ways to manage breakpoints, but the program still
gets SIGILL from time to time. Post my WIP patches upstream to see
if people have some ideas on this.
* TCWG-547, [1/10].
Try two approaches but give up due to the quite aggressive interface
changes. Fortunately, the change in the third approach is quite
small, testing the patch.
* Misc, meeting, [2/10]
# Plan #
* TCWG-518, TCWG-547
--
Yao
== Progress ==
* GCC Stage-1 (5/10)
- Posted patches and revised based on review
- PR40921 and PR63586
- Getting ready post type promotion pass again
* Linaro bug (2/10)
- BUG 2195 and BIG 1979
- Investigation with trunk and educed test case shows Missing commit
* Misc (1/10)
- GCC Lists
* Public holiday (2/10)
== Plan ==
* Attend to pending stage1 patches
o 1 day off (2/10)
== Progress ==
o Extended validation (2/10)
* Extended validation now operational,
reporting enhancements investigations.
* Looked at gdb/guality unstable results.
* Reviewed some jobs.
o Linaro GCC (2/10)
* Scripted new Linaro development branch process.
o Upstream GCC (1/10)
* Digging in libatomic code.
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o 2 days off (Thu/Fri)
o Continue on validation and upstream work.
== This Week ==
* LTO (6/10)
a) TCWG-128 (1/10)
- committed patch for adding param lto-max-partition, which
can now be used as workaround for building chromium with minimal
number of required partitions.
- committed patch for setting default value of lto-min-partition to 10000.
b) TCWG-528 (1/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch_increase_alignment.diff
- Cross tested on arm*-*-*, aarch64*-*-* and bootstrapped and tested
on aarch64-linux-gnu
- I want to cross test once for ppc64 since that's also affected.
c) TCWG-548 (4/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch-vars-3.diff
- Cross tested for arm*-*-* and aarch64*-*-*
* TCWG-319 (2/10)
- Comparing diff's of vect for arm and armeb shows, armeb not
supporting unaligned access
- Looking thru arm backend code to see why this happens.
* Validation (1/10)
- Script to build chromium
* Misc (1/10)
- Looked at PR70848, PR60172
- Meetings
== Next Week ==
LTO: section anchors, increase_alignment pass
TCWG-319: Continue investigation
Validation: Try to get the script merged to tcwg-buildapp repo.
# Progress #
* TCWG-466, ADRL pseudo instruction support in integrated assembler. I
couldn't find a way of putting ADRL into the assembler in a
maintainable way. Managed to work out a pretty close approximation of
ADRL in a macro so I added it to upstream PR. Put the results of the
my investigations into TCWG-466. Agreed with Renato's initial
diagnosis of won't fix.
* TCWG-468, Transform LDR rn, =expr pseudo instruction into MOV. I'm
more hopeful with this one. I've got a prototype that delays the
emission of the constant pool entry to a point where the
transformation can occur.
* Try out the build and push scripts. Had a frustrating day of chasing
down missing dependencies from my Ubuntu 12.04 machine while building
lldb. Should be resolved now.
# Plan #
* UK national holiday on Monday.
* Continue with TCWG-468. I've got a tablegen prototype that treats
LDR rd,= as a real pseudo instruction. Need to finish Thumb and
Thumb2. Next step after that is to do the transformation to MOV.
* Will spend any other time investigating LLD
# Progress #
* TCWG-518, range stepping on arm-linux. Rebase my patches, and choose
a different approach which is better. However, GDBserver crashes in
some cases, and I am investigating the crash. [5/10]
* TCWG-547, make some progress on the upstream discussion. We agree to
do it in a cleaner way but some GDB internal interface needs some
changes. [2/10]
* Read some articles about exception handling, this one is quite useful,
https://gcc.gnu.org/ml/gcc/2002-07/msg00391.html [1/10]
* Meeting, upstream patch review. [2/10]
# Plan #
* TCWG-518, TCWG-547
--
Yao
== Progress ==
* Rework LLVM helper scripts [TCWG-571] [4/10]
- Code review + minor improvements to the scripts
- Started a discussion about the interfaces of some of the scripts
(llvm-projs, llvm-sync)
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071
- Discovered that the assert is only triggered for
aarch64-linux-gnueabi, whereas arm-linux-gnueabi behaves as expected
(prints the error but doesn't assert afterwards). This has proven
useful for figuring out the intended behavior of the code.
* Move buildbots to CMake 3.4.3 [TCWG-573] [1/10]
- Helped move some of the bots (llvm-a15-*) to CMake 3.4.3
* Misc [2/10]
- Buildbot monitoring
- Meetings
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- Come up with a fix for PR24071
* Rework LLVM helper scripts [TCWG-571]
- Start a review for the new interface to llvm-projs/llvm-sync, so
we can have some concrete support for further discussion
- Investigate git worktree and how it could be factored into our
scripts (llvm-projs, llvm-build)
* Move buildbots to CMake 3.4.3 [TCWG-573]
- Help with the llvm-chrome-* bots if necessary
* OOO on Monday
== Progress ==
* Validation
- armvl8 differences between master and stable branches understood
(master defaulted to Thumb)
- updated ABE stable branch for validation
- ABE now uses linaro-local/stable DejaGnu branch
- updated ABE legacy version to use this DJ branch too, and updated
the Foundation Model path
- updated Jenkins jobs accordingly
* Backports
- created a few backports for our gcc-5 branch, to prepare handover
- slight documentation update
* GCC
- enhancements to validation harnesses to better handle
infrastructure problems
- using monitoring and regressions reports
* Cortex-strings
- updated a few aarch64 mem* routines from newlib versions
* Support
- finally reproduced the Windows-hosted toolchain bugs
by rebuilding in a properly updated Jessie chroot.
- building the next release in Trusty container should fix
these problems
* Misc (confi-calls, meetings, emails, ....)
== Next ==
* Validation: cleanup & reviews
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
As a note, all the builders we use for binary releases run Trusty still. I haven't tried Jessie (should work fine),but I know that newer Mingw releases fail to compile GCC 5.x.
- rob -
-------- Original message --------
From: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: 04/22/2016 14:00 (GMT-07:00)
To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
Subject: [ACTIVITY] 18-22 April 2016
* 3 days off
== Progress ==
* Validation:
- fixed ABE master and stable branches to use 'ssh -t' instead of
'ssh -tt' when cross-testing
- trying to assert master vs stable before the array branch merge,
noticed differences on armv8l
- created linaro-local/stable Dejagnu branch (currently a copy of
master). Prepared ABE config patches to use it.
* GCC
- infrastructure problems (ST compute farm), leading to a lot of
noise in the validations (and wrong regression reports upstream)
- enabled gcc-6-branch monitoring
- added GCC-6 tab to the backports spreadsheet
* Support
- Windows-hosted toolchain crashes: it seems the builders we use to
make the release run Jessie and not Trusty. Tried to rebuild a
toolchain in a Jessie chroot, but the script failed (works under
Trusty)
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation
- check that using linaro-local/stable Dejagnu branch works well
- create validation reference points before array branch merge
- understand/fix armv8l validation differences between master/stable
ABE branches
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
* Support
- Windows-hosted toolchain bug
* Snapshots
- prepare a few backports for our gcc-5 branch
* Cortex-strings update
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Failures reduced to 15 fails and 4 errors after fixing stepping bug.
-- Investigated remaining issues some of them are known issues and
others will need further investigation.
LLDB ARM Thread Stepping Problem [TCWG-566] [5/10]
-- Problems caused because incorrect reporting of PLT entry size set by linker.
-- Submitted a fix after analysis that logical size of PLT entry
should be greater than 4bytes.
-- Fix accepted and committed upstream.
LLDB Buildbot Setup [TCWG-241] [1/10]
-- Random change in results finally caught. It was due to inconsistent network.
-- Progress halted to fix arm-linux-gnueabihf bugs.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB Chromebook Test Stability [TCWG-563]
-- Continue to resolve and investigate chromebook test failures.
LLDB Buildbot Setup [TCWG-241]
-- Start AArch64 tester evaluations.
Progress:
- On holiday all week, at ACCU conference. I've put some highlights at
the end of the message.
- Did some more investigation into TCWG-466 ADRL support in integrated
assembler during breaks.
-- Not looking good, to do this properly bumps up against a lot of
design decisions and restrictions made by the LLVM assembler (designed
as compiler target, not to be user friendly).
-- There are ways it could be implemented with restrictions, but it is
debateable whether it is worth doing at all.
-- On the plus side I've got a much better idea of how the assembler
works and what restrictions exist on each stage of the journey from a
line in the .s file to emission in the object. Will add some comments
to the LDR r0, =expr TCWG as well.
-- On the negative side the :upper16: and :lower16: operators for MOVT
and MOVW don't look to be correct in the presence of addends. Will
need to investigate further to see what the scope of the problem is.
Plan:
- Dump results of TCWG-466 investigation into Jira.
- Take a look at and post a comment on Adhemerval's revised TLS patch,
even if it is just looks fine in the hope of pushing it forward a bit
more.
- Catch up with Renato's scripts and documents for LLVM sub-group.
- Work out what to do with TCWG-466, if the answer is put it down,
find something else to look at.
ACCU Highlights/Report:
Tough stuff in modern C++
A deep dive into some of the newer areas of C++ such as:
- rvalue references and forwarding (universal) references
- How to use SFINAE (mostly std::enable_if) to select algorithms
optimised for particular template instantiations
- Variadic templates. Including all sorts of strange ways to (ab)use
expansion of parameter packs.
C++ WG21 SG14 Gaming and low-latency study group
- A new study group aiming to represent the gaming (primarily), but
also embedded and high frequency trading concerns.
- Motto seemed to be make sure "Don't pay for what you don't use" is enforced.
Most interested in:
-- No exceptions configurations
-- No RTTI
-- More performance out of the STL (see EA STL
https://github.com/electronicarts/EASTL)
-- Add ring buffers and support for unitialised memory, fixed point
numbers, flat-map, standardised simd vector types
Using sentinels
- An example of how using two sentinels in an implementation of
std::partion speeds up the algorithm by saving comparisons. Can speed
up quicksort by a few percent
Constexpr in C++14
- Example showing how you could build a string to enum map, operating
entirely at compile time, and its subsequent negative effects on
compile time!
Concepts Lite
- Concepts missed the C++17 standard, this presentation went into the
current Technical Standard (optional) and how concepts would likely be
implemented in C++(20?)
- Not surprising to see that concepts still missed C++17 as there is
only one implementation and one non-trivial use case (ranges) and
there are still unresolved questions to be answered.
Introduction to Julia
- Really a comparison of Julia to the author's favoured language of common lisp.
- Was impressed at how "lispy" Julia was whilst retaining high performance.
- Liked the mathematical syntax
- Didn't like the python like parts that seemed to be added to try and
get people to migrate from python, but were non "lispy".
# Progress #
* TCWG-545, patches are committed. Done. [3/10]
* TCWG-167, ARM reverse debugging bug fixes. All test fails are
fixed. Done. [2/10].
* PR 19947. The fix is approved, but the patch triggering the bug
needs update. [2/10]
* Help to fix broken ARM GDB after C++ switch. [2/10].
GDB mainline is a C++ program in default. Exception
handling in GDB is broken on non-x86 host (ARM, AArch64, AIX, at
least) because readline (C library) calls C++ GDB code, but exception
unwinding can't cross the C function ("foreign frame"). The problem
is fixed by catching all exceptions before return to readline, and
re-throw them after return from readline back to GDB.
* Misc, [1/10]
** Hack QEMU so that I can run gdb regression testsuite with qemu-arm.
# Plan #
* TCWG-518, rebase patches on mainline, test, and post patches if
nothing wrong.
* PR 19947, TCWG-561,
* TCWG-547
--
Yao
== Progress ==
o Extended validation (5/10)
* Created new extend validation job which handles native/cross
validation and benchmarking.
* Identified and discussed dejagnu Linaro branch issue.
o Upstream GCC (2/10)
* Start to look at libatomic ARMv8.1 support
o Misc (3/10)
* Various meetings
* Support team members on benchmarking and validation.
== Plan ==
o Continue on extended validation and Libatomic
