- linaro-toolchain - lists.linaro.org

[ACTIVITY] 15-19 Feb 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) - TCWG-528: a) addressed Richard's comments. b) investigating timeout with my patch for g++.dg/torture/pr31863.C c) using hash_map to prevent decl from getting visited more than once prevents the issue d) patch: http://people.linaro.org/~prathamesh.kulkarni/increase-struct-align.diff - Slides: mostly prepared, few tidbits (and demos) remaining - Benchmarking: couple more failures due to my silly mistakes, now in progress. * TCWG-310 (1/10) - started to look at loop peeling with perf * Public Holiday (2/10) - Shiv Jayanti * Misc (2/10) - Meetings - Committed r233426 - Looked at PR69766 caused due to r232622 == Next Week == - LTO: TCWG-528, benchmarking, slides - TCWG-310

9 years, 2 months

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[ACTIVITY] 15 - 19 February 2016

by Yao Qi

# Progress # * Support range stepping on arm-linux. TCWG-518. [4/10] My patches causes some regressions but my patches just expose the existing problem in GDBserver. Fix them and post patches upstream. * Linaro connect. [2/10] Go to London for visa application. * GDB 7.11 release. No issues from my side. The tentative date of release is Feb 26th. * Fix GDB reverse debugging tests failures. ** Add more test cases, TCWG-183/TCWG-174. [2/10] ** Fix syscall handling in reverse debugging on ARM and AArch64. TCWG-532/TCWG-167. [2/10] # Plan # * Support range stepping on arm-linux. Continue. * Fix GDB reverse debugging tests failures. Continue. * Review upstream patches. * Go to London to collect my passport. -- Yao

9 years, 2 months

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[ACTIVITY] 15-19 February 2016

by Christophe Lyon

== Progress == * Validation - AArch64 bare metal validation fixed. Patches waiting approval - noticed a few failures caused by timeouts and failure to download testcases. Maybe we are causing too much load on the builders/testers * Connect preparation - thoughts on extended validation * GCC - upstream monitoring, reported a couple a of regressions - a few backports - target attributes backport. Still having problems with our branch * Misc (conf calls, meetings, emails, ....) == Next == Holidays most of next week

9 years, 2 months

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setting loop buffer size in the gcc (aarch64)

by Virendra Kumar Pathak

Hi Toolchain Group, I am trying to study the effect of loop buffer size on loop unrolling & the way gcc (aarch64) handles this. To my understanding, Loop Buffer is like i-cache which contains pre-decoded instruction that can be re-used if branch instruction loopbacks to an instruction which is still present in the buffer. For example, in Intel’s Nehalem loop buffer size is 28 u-ops. In LLVM compiler, it seems LoopMicroOpBufferSize is for the same purpose. However, I could not find any parameter/variable inside config/aarch64 representing loop buffer size. I am using Linaro gcc 5.2.1 [Question] 1. Is there any example inside aarch64 (or in general) which uses the loop buffer size in loop unrolling decision? If yes, could you please mention the relevant files or code section? 2. Otherwise any guidance/input on adding this support in aarch64 backend assuming architecture has the loop buffer support. [My Experiments/Code Browsing] I have collected following information from code browsing. Please correct if I missed or misunderstood something. TARGET_LOOP_UNROLL_ADJUST - This target hook return the number of times a loop can be unrolled. This can be used to handle the architecture constraint such number of memory references inside a loop e.g. ix86_loop_unroll_adjust() & s390_loop_unroll_adjust(). On the same note, can this be used to handle loop buffer size too? Without above hook, in loop-unroll.c parameters like PARAM_MAX_UNROLLED_INSNS (default 200), PARAM_MAX_AVERAGE_UNROLLED_INSNS (default 80) decides the unrolling factor. e.g. nunroll = PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS) / loop->ninsns; In config/aarch64.c, I found align_loops variable in aarch64_override_options_after_change() function. I guess this an alignment done before starting the loop header in the executable. This should not play any role in loop unrolling. Right? So any guidance on how we can instruct aarch64 backend to utilize loop buffer size in deciding the loop unrolling factor? Thanks in advance for your time. -- with regards, Virendra Kumar Pathak

9 years, 2 months

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[ACTIVITY] 8 - 12 February 2016

by Omair Javaid

== Progress == LLDB development -- Handling aggregate types return values on arm-linux-gnueabihf ABI. Patch review and committed upstream. [TCWG-228] [1/10] -- Debugging of stepping issues on chromebook (arm hard float ABI) [TCWG-230] [2/10] -- Progress on vector return values and aggregate types return values with vector elements. [TCWG-531] [2/10] -- Started work on complex return values and aggregate types return values with vector elements. [TCWG-531] [2/10] -- Started writing test cases handling complex and vector return values and aggregate types return values with vector and complex elements. [TCWG-531] [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Finish work on complex return values and aggregate types return values with vector elements. [TCWG-531] -- Finish work on vector return values and aggregate types return values with vector elements. [TCWG-531] -- Finish work on test cases handling complex and vector return values. [TCWG-531]

9 years, 2 months

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[ACTIVITY] 8th - 12th February

by Bernie Ogden

Port to microinstance - TCWG-432 [2/10] * Better reporting/error trapping in dispatch scripts * Some back and forth with Lab about builder implementation * Started assessing target stability * Fixed a few bugs in reporting/bundle generation Document benchmarking infrastructure - TCWG-496 [2/10] * All done apart from Jenkins interface * Need to finish Jenkins interface first... Generate graphs for benchmarking - TCWG-268 [1/10] * Generate a bunch of filters and charts to track Coremark-Pro * Wrote up what I learned about LAVA's reporting interface EEMBC benchmarks - (no ticket) [2/10] * Checked over what we had, decided it was probably complete * Imported to our repos * Wrote up what I know about this * Moved Coremark-Pro into its own repo ** Broke some code that had worked by coincidence ** Fixed it Misc * Usual meetings/mail/etc * Some fun with what turned out to be a known bug in the linaro-media-create now used in main LAVA instance * Educated guess as to why Jenkins-triggered jobs produced no bundle ** Raised a ticket ** Think I know how to fix on my side =Plan= If updated builder becomes available, convert uinstance jobs to use it Test release benchmark job Finish backport benchmarking Document Jenkins interface Assess target stability More image reports in microinstance

9 years, 3 months

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[Weekly] 08-12 February 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10) - Successfully tested SImode add, sub, and neg overflow patterns - Developed DImode addv and subv patterns - Debugging failures in DImode overflow patterns * TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10) - Made changes corresponding to upstream review - Rebased to latest trunk - Resolved issues with new test cases - Fixed formatting and style issues - Resubmitted upstream for final review - previous review gave conditional support for GCC 7 - Successfully retested - One remaining expected failure on targets with wide add support (including aarch64) - Plan to file a upstream bugzilla * Misc (1/10) * Vacation (4/10) == Next week == * Bugzilla 69663 - Debug and resolve DImode pattern failures * Bugzilla 69008 - Restart investigation

9 years, 3 months

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[ACTIVITY] 08 - 12 February

by Kugan

== Progress == BUGS (8/10) - PR69708: * Posted a patch to fix. - PR69589: * Posted a patch to fix. - PR66726: * Omitted the patch bu that triggered a bootstrap failure for ppc64. Reverted the patch and looking into it. - Misc (2/10) * gcc/bug list * Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

9 years, 3 months

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[ACTIVITY] 8 - 12 Feb 2016

by Prathamesh Kulkarni

== This Week == * LTO/IPA (8/10) - TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-* - Submitted patch upstream to add entry for aarch64 to target-supports.exp - Experimenting with Kugan's ipa-vrp prototype - Had a look at ipa-comdat - Connect slides * benchmarking (1/10) - issues with deployment (TICKET-259) - Using Bernie's workaround for the above issue * Misc (1/10) - Meetings == Next Week == - LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements. - Investigate tcwg-310 with perf - Finish connect slides

9 years, 3 months

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[ACTIVITY]

by Renato Golin

== Progress == * Conference (2/10) - More EuroLLVM paper reviews, discussions * Support (5/10) - Looking at PR16275 (review D17141) * Background (3/10) - Code review, meetings, discussions, general support, etc. - Buildbots broken, bisects, debugging - Defining and posting Job ad (wanna work with us?)

9 years, 3 months

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[ACTIVITY] 08 - 12 February

by Yao Qi

# Progress # * Support range stepping on arm-linux. TCWG-518. [4/10] Preparatory patches are pushed in. Patches are being tested. * Linaro connect. [3/10] ** Slides are done. ** Collect documents for visa application. * GDB 7.11 release. TCWG-509. [1/10] Release branch is created. Discuss on issue related to big endian, but ARM is the only user of that code. * Patch review, especially arm tracepoint support. [2/10]. # Plan # * TCWG-518, upstream patches if tests are OK. * TCWG-172, continue look at test parity between arm and x86_64. * Go to London on Wed for visa application. -- Yao

9 years, 3 months

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ldr instruction selection in the aarch64 backend

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I have a question on the ldr instruction selection in the aarch64 backend. Could someone help me in this regards, please? I am trying to allow only type A instructions while disabling the type B. Type A example: ldr x4, [x20,x1] ---> allow Type B example: ldr x1, [x9,x3,lsl #3] ---> disable Experiment/My Understanding - aarch64_classify_address() returns true if rtx X is a valid address. If allow_reg_index_p=true then it calls aarch64_classify_index(). aarch64_classify_index() identify the address mode of second operand (op1) and accordingly calculate the shift. If shift=0 then type A is generated otherwise Type B will be generated. Thus if (shift != 0) then I am returning 'false' from aarch64_classify_index(). -------------------------patch--------- --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x, if (GET_CODE (index) == SUBREG) index = SUBREG_REG (index); + if (shift != 0) + return false; if ((shift == 0 || (shift > 0 && shift <= 3 && (1 << shift) == GET_MODE_SIZE (mode))) --------------------------------------- Result - Before change ldr x0, [x13,x0,lsl #3] After Change lsl x1, x1, #3 ldr x0, [x15,x1] Question - How the returning 'false' from aarch64_classify_index() is resulting in the selection of type A versus type B? I could not find the function which is taking the decision based on return from aarch64_classify_address(). Could someone please explain this process or point me to the relevant files or code? Please correct me if my understanding is wrong. Thanks in advance for your time and patience. -- with regards, Virendra Kumar Pathak

9 years, 3 months

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[ANNOUNCE] Linaro GCC 5 2016.02 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.02 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.05 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn233233 * Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt instructions as unconditional * Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624 * Backport of [Bugfix] [AArch32] PR target/69403: Bug in thumb2_ior_scc_strict_it pattern * Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode comparison with zero * Backport of [Bugfix] [AArch64] PR target/69176 * Backport of [Bugfix] PR target/69175 * Backport of [Bugfix] PR tree-optimization/67781 * Backport of [AArch32] Remove neon_reinterpret, use casts * Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support * Backport of [AArch64] Avoid emitting zero immediate as zero register * Backport of [AArch64] Fix jit crash on aarch64 * Backport of [AArch64] Fix -mcpu/arch=native support for LSE * Backport of [AArch64] Handle compare of zero_extract form of TST-immediate in rtx costs * Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs * Backport of [AArch64] Properly reject invalid attribute strings * Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h * Backport of [Testsuite] [AArch32] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0 * Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure when running with -march or -mcpu * Backport of [Doc] Remove outdated text from lto.texi Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 3 months

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[ACTIVITY] 1st - 5th February

by Bernie Ogden

Automated release benchmark Jenkins job - TCWG-348 [2/10] * Drafted a job, it succeeds in dispatching to the uinstance * Needs testing Port to microinstance - TCWG-432 [5/10] * Almost entirely fixing up the CPU2006 -> LAVA reporting * Should now be able to report CPU2000 results as well Misc [3/10] * Mail/meetings/etc * Connect slides =Plan= If builder is available, convert uinstance jobs to use it Test release benchmark job Produce image reports in microinstance Attempt to finish backport benchmarking Actually finish documentation

9 years, 3 months

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[ACTIVITY] 1 - 5 February 2016

by Omair Javaid

== Progress == LLDB development -- Committed patch fixing return value handling on arm-linux-gnueabihf [TCWG-228] -- Finished work on handling aggregate types return values on arm-linux-gnueabihf ABI. [TCWG-228] [5/10] -- Submitted single and double precision handlers for upstream review. [TCWG-228] -- Started work on vector return values and aggregate types return values with vector elements. [TCWG-228] [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. Public Holiday [2/10] -- Friday 5th February 2016 == Plan == LLDB development -- Update and commit aggregate type return values on arm-linux-gnueabihf ABI patch. -- Investigate issues while stepping over library functions on arm-linux-gnueabihf -- Further work on vector return values on arm-linux-gnueabihf ABI

9 years, 3 months

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[ACTIVITY] Week 05

by Yvan Roux

== Progress == o Connect slides (2/10) * Undefined behavior (slides and review) o GCC dev. (5/10) * Remote testing sanitizing: found a solution in dejaGNU and GCC implementation and test ongoing * Analysed and closed PR69590 o Misc (3/10) * Various meetings * internal discussions == Plan == o Continue on GCC testsuite o FSF branch merge and 2016.02 snapshot

9 years, 3 months

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[ACTIVITY] 1 - 5 Feb 2016

by Prathamesh Kulkarni

== This Week == * TCWG-319 (1/10) - Updated patch and re-posted, queued for stage-1 - Regression with armeb for -fvect-cost-model=cheap * TCWG-528 (1/10) - speculatively increase alignment for global structs with arrays. * Backports (3/10) - committed backport: 232688 - r232631 (partially?) reverts 232330 - modified script to follow git log <file> * benchmarking (2/10) - 464.h264ref triggered ICE for -O3 -mfloat-abi=hard -mfpu=neon, reduced it (PR69282) - Benchmarking tcwg-310 on SPEC2006 - +0.10% - Benchmarking INT SPEC2k6 for aarch64 without LTO complete. * Slides (2/10) - Read doc and created outline for most of slides, - expect to be mostly complete by next week * Misc (1/10) - Meetings == Next Week == - LTO benchmarking and slides - TCWG-528

9 years, 3 months

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[ACTIVITY] 01 - 05 Feb 2016

by Kugan

== Progress == - LTO and TCWG480 (5/10) * Started testing with the prototype patch * Still trying to figure out what is the best way to set_range_info based on IPA * i.e., how to find the SSA_NAME initialized with PARM_DECL - Misc (5/10) * gcc/bug list * Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

9 years, 3 months

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[Weekly] 01-05 February 2016

by Michael Collison

== This week == * Backports (1/10) - 232493 - Committed to Linaro branch - 232727 - Committed to Linaro branch - 232414 - Committed to Linaro branch * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10) - Implemented SImode add, sub, and neg overflow patterns - add overflow patterns pass testing - debugging failures in subv overflow patterns * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (ARM) (3/10) - Investigating Dead Store Elimination pass to determine if code can be improved * Misc (1/10) == Next week == * Personal days on February 8th and 9th * Resolve bugzilla 69663 subv issues and work on DImode patterns * Bugzilla 69008 - continue investigation * Investigate test case failure on backport 232600

9 years, 3 months

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[ACTIVITY]

by Renato Golin

== Progress == * Conferences (4/10) - Fosdem organisation, travel, video cutting (all lost) - EuroLLVM paper review, schedule, meetings * Buildbots (2/10) - Bisecting test-suite regression - Infrastructure clean up - Reverting broken patches * Support (1/10) - Looking at some bugs, fixed PR26450 * Background (3/10) - Code review, meetings, discussions, general support, etc. - Jira farming, planing, resourcing

9 years, 3 months

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[ACTIVITY] 01-05 Feb 2016

by Yao Qi

* Off from Mon. to Wed. [6/10] # Progress # * TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10] First do software single step in GDBserver side. * TCWG-509. GDB 7.11 release. [1/10] PR 19474, review Keith's patch. The patch is OK to mainline, but we don't want to take risk shipping this patch to 7.11 release. * Misc, register to Linaro Connect BKK16, and get clarifications on my visa to Thailand. [1/10] * Monitor the discussions on kenernel awareness upstreams, and comment on the display of CPSR register. # Plan # * Finish Linaro Connect slides. * TCWG-509. Anything needed for GDB 7.11 release. * TCWG-518. -- Yao

9 years, 3 months

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[ACTIVITY] 1-5 February 2016

by Christophe Lyon

== Progress == * Validation - disabled Auto Backport Engine until the patch selection is improved to avoid saturating the builders with undesirable builds. - AArch64 bare metal validation (bug #2011). Submitted a patch for dejagnu aarch64-fv8.exp, and one for our builders schroots. Will need another patch, in ABE. - timeout issues: no progress * Misc (conf calls, meetings, emails, ....) - internal discussions == Next == * Validation - debug timeout issues - cleanup

9 years, 3 months

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[ACTIVITY] 25 - 29 January 2016

by Omair Javaid

== Progress == LLDB development -- Submitted patch fixing return value handling on arm-linux-gnueabihf [TCWG-228] [5/10] -- float and double types handled in above patch did some more investigation for handling structs [TCWG-228] [2/10] -- Collecting LLDB status data, ran testsuite on different hardware and minor investigation of fails and xfails [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Update float/double return value patch after review and commit upstream -- Submit a fix for handling structs as return types on arm-linux-gnueabihf Public Holiday -- Friday 5th February 2016

9 years, 3 months

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[ACTIVITY] 25-29 January 2016

by Kugan

== Progress == - Public Holiday (2/10) - LTO and TCWG480 (4/10) * Started with a prototype for VRP * Experimenting with simple test cases - Misc (4/10) * gcc/bug list * LTO and Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

9 years, 3 months

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armhf toolchain with glibc 2.13

by Aaron R

Hi, My ARM target runs glibc 2.13 and I am having a hard time finding a linaro toolchain for it. It seems like all the ones I have found ship with glibc 2.15 (even old ones). Where can I find the binaries for a linux toolchain that targets armhf with glibc 2.13? Thanks in advance

9 years, 3 months

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[ACTIVITY] 25th - 29th January

by Bernie Ogden

Port to microinstance - TCWG-432 [4/10] * Went a few more rounds with the race condition, finally nailed it * Tidied up transfer of Coremark results to LAVA * Added metadata to LAVA results * Sketched some charts using LAVA reporting * Improved runtime benchmark logging Benchmarking infrastructure documentation - TCWG-496 [2/10] * Most everything drafted, some docs finished Controlled image builds - TCWG-360 [2/10] * Reached a better understanding of what a hwpack is * Generated a few images, none of them booted Misc [2/10] =Plan= Benchmarking-102 slides for Connect Finish documentation Backport benchmarking If builder shows up in microinstance, evaluate stability of its Junos

9 years, 3 months

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[ACTIVITY] Week 04

by Yvan Roux

o Teaching activity (3/10) == Progress == o Infra/Validation (1/10) * A couple of patches for release script. o GCC dev. (2/10) * Remote testing sanitizing: still digging. o Misc (4/10) * Various meetings (usual ones and internal ones) * Backports reviews == Plan == o Continue on GCC testsuite and opened cards.

9 years, 3 months

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[ACTIVITY] 18th - 22nd January

by Bernie Ogden

Port to microinstance - TCWG-432 [2/10] * More fallout from attempts to fix race condition * Began cleaning job submission YAML Controlled image builds - TCWG-360 [1/10] * (Re)learned how to generate images from hwpack + filesystem Struck down by flu [7/10]

9 years, 3 months

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[Weekly] 25-29 January 2016

by Michael Collison

== This week == * Backports (3/10) - 232493 - Unrelated aarch64 failure and non-thumb asan test on aarch32 big endian - 232600 - All tests pass - 232727 - unrelated non-thumb test failure asan/deep-thread-stack-1.c asan/deep-thread-stack-1.c) * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (3/10) - Development halted due to submission of related patch by Richard Henderson: - https://gcc.gnu.org/ml/gcc-patches/2016-01/txt0WQOxpo0_5.txt - Began implementation of aarch32 related patch * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (ARM) (3/10) - Additional code is being generated in default abi case with structure alignment equal to 8 - Investigating Dead Store Elimination pass to determine if code can be improved * Misc (1/10) == Next week == * Create new bugzilla for aarch32 to implement overflow standard names and continue implementation * Bugzilla 69008 - continue investigation * Work on backports as necessary

9 years, 3 months

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[ACTIVITY] 25-29 Jan 2016

by Prathamesh Kulkarni

== This Week == * PR43721 (1/10) - Submitted upstream. - GIMPLE parts approved by Richard, wants someone else to approve rtl-expansion bits. * benchmarking (1/10) - benchmarking tcwg-310 on cortex-a53, cortex-a57, r1-a12, cortex-a17 - submitted job for INT benchmarks for SPEC2006 for aarch64 * backports (2/10) - r232688 automated backport build failed for aarch64-linux-gnu on tcwg-backport-gerrit: Unrecognized macro 'GERRIT_PATCHSET_REVISION' in '#664- ${GERRIT_PATCHSET_REVISION,length=8}' Build successful on tcwg-backport-maxim - r232737, r232631 have at least 4 dependencies. - wrote bare bones script to find dependencies for revision * ccp (2/10) - enhancement to hoist stmt thru phi with all constant args - patch: http://people.linaro.org/~prathamesh.kulkarni/ccp-mov.diff - rejected by Richard, since PRE handles this case when it's trivially profitable and phiprop does similar transform. In general, it's not profitable to have this transform included. * Public Holiday (2/10) * Misc (2/10) - Meetings - Slides: short & long term activities == Next Week == - PR43721: look at using define_expand instead of hook, add test-cases and few nits - tcwg-319 - analyse with perf - LTO INT benchmarking for arm, aarch64 and x86 - LTO Slides

9 years, 3 months

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[ACTIVITY] 25-29 January 2016

by Christophe Lyon

== Progress == * Validation - Auto Backport Engine: works well, it submitted a few backports automatically. We'll need to assess the amount of work saved. - timeout issues: still investigating * GCC - TCWG-485/PR68620: patch committed - bug #1994: sent GCC patch upstream * Misc (conf calls, meetings, emails, ...) - internal meetings/discussions == Next == * Validation: - debug timeout issues - extended validation * GCC: - bug fixing

9 years, 3 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (2/10) - Installing bisect tool on ARM and AArch64 bots - SVN access broken in Austin - Investigating failures on AArch64-only bots * Release (2/10) - Running 3.8.0 benchmarks * Planning (2/10) - Finalising the roadmap for 2016/17 * Conferences (2/10) - Final arrangements to Fosdem - EuroLLVM papers in, planning format, reviewin papers * Background (2/10) - Code review, meetings, discussions, general support, etc.

9 years, 3 months

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[ACTIVITY] 25-29 January 2016

by Yao Qi

# Progress # In general, GDB mainline is in a good state. All known bugs are fixed, but still have some patches pending for review. The release can be created after these pending patches are in. * Fix fail in gdb.base/interrupt-noterm.exp. TCWG-517. Done. [2/10] * Fix fail in gdb.fortran/vla-value.exp. TCWG-521. Done. [1/10] * PR 19474. [3/10] Tried different approaches, but still cause regression. Fortunately get the right maintainer involved. Will discuss with him on this bug next week. * Range stepping doesn't work on arm-linux, which slows down stepping over a line of source. TCWG-518. [2/10] * Prepare slides for Linaro Connect. [2/10] # Plan # * Off on Mon. to Wed. * Linaro connect slides. * Thailand visa. * Other issues on GDB 7.11 release, if any. -- Yao

9 years, 3 months

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[ANNOUNCE] Linaro Binary Toolchain Release Respin GCC 5.2 2015.11-2

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2 Release Archives. http://releases.linaro.org/components/toolchain/binaries/5.2-2015.11-2/ http://releases.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11-2 The Linaro GCC 5.2 2015.11-2 binary toolchain release respin is built from the Linaro GCC-5.2-2015.11-2 release source archive. The Linaro GCC-5.2-2015.11-2 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release includes fixes for the issues specified in the Linaro GCC 5.2 2015.11-2-rc1 release-candidate. * GCC 5.2 2015.11-2-rc1 The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release-candidate includes fixes for the following issues: Linaro bug 1995 identified a problem where the installed sysroot was not in the place that the compiler expected the sysroot to be located by default. This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate. * GCC 5.2 2015.11-1 The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the Linaro GCC-5.2-2015.11-1 release source archive. The Linaro GCC-5.2-2015.11-1 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release includes fixes for the issues specified in the Linaro GCC 5.2 2015.11-1-rc1 release-candidate. * GCC 5.2 2015.11-1-rc1 The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release-candidate includes fixes for the following issues: The arm-eabi-none multi-libs are now available in the toolchain sysroot as a fix for Linaro bug 1920 and Linaro bug 1922 . Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 . Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain (arm-linux-gnueabihf triple). * GCC 5.2 2015.11 The Linaro GCC 5.2 2015.11 binary toolchain release is built from the Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

9 years, 3 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.2 2015.11-2-rc1

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2-rc1 Release-Candidate Archives. http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-2-rc1/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2-r… These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at http:// https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11-2-rc1 The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release-candidate includes fixes for the following issues: Linaro bug 1995 identified a problem where the installed sysroot was not in the place that the compiler expected the sysroot to be located by default. This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate. * GCC 5.2 2015.11-1 The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the Linaro GCC-5.2-2015.11-1 release source archive. The Linaro GCC-5.2-2015.11-1 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release includes fixes for the issues specified in the Linaro GCC 5.2 2015.11-1-rc1 release-candidate. * GCC 5.2 2015.11-1-rc1 The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. This release-candidate includes fixes for the following issues: The arm-eabi-none multi-libs are now available in the toolchain sysroot as a fix for Linaro bug 1920 and Linaro bug 1922 . Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 . Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain (arm-linux-gnueabihf triple). * GCC 5.2 2015.11 The Linaro GCC 5.2 2015.11 binary toolchain release is built from the Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

9 years, 3 months

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Linaro 4.9 toolchain has issues with allyesconfig

by Dan Murphy

Hi! When using the linaro-4.9-2015.05 toolchain on the Linux master and on Linux stable releases I am seeing a build issue below when using the allyesconfig. This does not seem to occur on the 5.2 tool chain. We cannot move to 5.2 tool chain for our releases as they are based on 4.9. LD init/built-in.o arch/arm/kernel/built-in.o:(.text.fixup+0x1d4): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely' arch/arm/kernel/built-in.o:(.text.fixup+0x1e0): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely' arch/arm/kernel/built-in.o:(.text.fixup+0x1ec): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely' drivers/built-in.o: In function `combiner_handle_cascade_irq': :(.text+0x834): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o :(.text+0x868): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o drivers/built-in.o: In function `hip04_irq_set_type': :(.text+0xad0): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o :(.text+0xb10): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o drivers/built-in.o: In function `hip04_raise_softirq': :(.text+0xc8c): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock_irqsave' defined in .spinlock.text section in kernel/built-in.o :(.text+0xdc8): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock_irqrestore' defined in .spinlock.text section in kernel/built-in.o drivers/built-in.o: In function `hip04_irq_set_affinity': :(.text+0xefc): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o :(.text+0xf78): additional relocation overflows omitted from the output make: *** [vmlinux] Error 1 Please advise to how to resolve this issue within the 4.9 Linaro tool chain Dan -- ------------------ Dan Murphy

9 years, 3 months

6
16
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[ACTIVITY] 18-22 January 2016

by Kugan

== Progress == - LTO and TCWG480 (7/10) * Read and experimented with GCC's LTO codebase. * LTO benchmarking for a15 on chromebook * Analyzed regressions with perf - Misc (3/10) * gcc/bug list * Slides for connect presentation * Backpors * Meetings == Plan == * LTO * bugs

9 years, 3 months

1
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[ACTIVITY]

by Renato Golin

== Progress == * Support (5/10) - Bug triage: reviewing the 300+ bugs on ARM - remaining 220 bugs are all still pertinent * Release (2/10) - Woes due to GCC ABI change may delay 3.8.0 release - Tested on both ARM and AArch64 with old environment, all green. * Background (3/10) - Code review, meetings, discussions, general support, etc. - EuroLLVM, FOSDEM preparations, ARM sync

9 years, 3 months

1
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[ACTIVITY] Week 03

by Yvan Roux

o Teaching activity (2/10) == Progress == o Linaro GCC (2/10) * Delivered 2016.01-1 Snapshot respin with fix for Linaro PR #2001 * Gave some support on backports o Infra/Validation (1/10) * Compared ABE master results. o GCC dev. (2/10) * Identified the way testcases are uploaded on the remote target in cross validation as the root cause of validation instabilities. Digging into GCC .exp files and DejaGNU to fix it cleanly. o Misc (3/10) * Various meetings * Start a backport/validation document == Plan == o Continue backports/validation document o Continue on the ongoing cards opened

9 years, 3 months

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[ACTIVITY] 18 - 22 January 2016

by Omair Javaid

== Progress == LLDB development -- Debugging of return value related issue coming up on chromebook ARM [TCWG-228] [2/10] -- Setup of Arm testing on AArch64 using chroot on highkey [TCWG-231] [1/10] -- Investigation of failures when setting watchpoint on vector variables [TCWG-231] [4/10] Miscellaneous [3/10] -- Meetings, emails, discussions etc. -- Travel for Thailand visa application == Plan == LLDB development -- Try a fix of return value related issue coming up on chromebook ARM -- Submit fix for failures when setting watchpoint on vector variables -- Mark triaged failures with xfail decorators and bug numbers.

9 years, 3 months

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[ACTIVITY] 11 - 15 January 2016

by Omair Javaid

== Progress == LLDB development -- Triage testsuite failures on AArch64 highkey [TCWG-231] [5/10] -- Triage testsuite failures on chromebook (armel) [TCWG-228] [3/10] Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Documents preparation for Thailand visa == Plan == LLDB development -- Create chroots for armhf and armel testing on AArch64 highkey board -- Investigate ABI related issues when returning values on armel and armhf -- Further bug triage and mark triaged failures with xfail decorators and bug numbers. Miscellaneous -- Travel for Thailand visa application submission.

9 years, 3 months

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[Weekly] 18-22 January 2016

by Michael Collison

== This week == * Backport 232414 (2/10) - Successfully backported using backflip. - Investigating one fortran failure on aarch64-linux-gnu * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (3/10) - Re-implementing using sign/zero extends * Misc (1/10) * Sick day -January 19th (2/10) * MLK Jr. Holiday - January 18th (2/10) == Next week == * Bugzilla 68543 - Complete re-implementation with zero/sign extends and test * Bugzilla 69008 - Restart investigation * USA Holiday (January 18th, MLK Day)

9 years, 3 months

1
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[ACTIVITY] 18-22 Jan 2016

by Prathamesh Kulkarni

== This Week == * PR43721 (4/10) - Patch review from Jim - Bootstrapped and tested on x86, cross-tested with arm-linux-gnueabi - Looking at regressions with arm-linux-gnueabi - Wrote test-cases * Benchmarking (2/10) - lto spec2006 benchmarking * Backport (1/10) - Build successful for r232440 and r232442, failed for r232442 * PR24293 (1/10) - Addressed comments by Marek and committed to trunk * Misc (2/10) - Meetings - PR69133 - Fixed by Honza. Instead of gating on lto_file_data as I did in my patch, gating on gimple_has_body_p() was more suitable. - Awaiting upstream response for tcwg-319 - Connect Slides outline, read doc on tree-ssa propagation and lto plugin driver. == Next Week == Continue ongoing tasks

9 years, 3 months

1
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[ACTIVITY] 18-22 January 2016

by Christophe Lyon

== Progress == * Validation - no progress in timeout issues: still didn't manage to access the logs - 1st backport workshop successful in the team. We can increase the difficulty for the next time :) - initial prototype (naive) of an auto-backporter (using backflip) when the patch are selected for inclusion * GCC - TCWG-485/PR68620: patch under review - TCWG-484/target attributes testsuite fixes: committed. - bug #1994: provided woraround to kernel team. Related to GCC PR63304. Working on a further patch for GCC. * Misc (conf calls, meetings, emails, ....) == Next == * Validation: - debug timeout issues - extended validation * GCC: - bug fixing

9 years, 3 months

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[ACTIVITY] 18 -- 22 January

by Yao Qi

# Progress # * Fix the arm software single step regression. [3/10]. Done. * TCWG-503 Done. * TCWG-491, have a patch to avoid GDB crash. Patch is pending for review. * TCWG-517. [2/10] Fix fail in gdb.base/interrupt-noterm.exp. Patch is posted. * TCWG-514. [3/10] Fix new fails in foll-exec.exp and foll-vfork.exp. Patch is pending for review. * TCWG-509, GDB 7.11 release. [2/10] GDB is in a good shape to create 7.11 branch except PR 19474. Go through GDB test results and no ARM or AArch64 specific issues. # Plan # * TCWG-509, GDB 7.11 release. * Upstream patch review. -- Yao

9 years, 3 months

1
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[ANNOUNCE - RESPIN] Linaro GCC 5 2016.01-1 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) announces the 2016.01-1 snapshot of the Linaro GCC 5 source package. This package is a respin of 2016.01 source package and contains a fix for Linaro bugzilla’s PR #2001: * [AArch64] ICE in final_scan_insn on aarch64-linux-gnu. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/ Original release notes from 2016.01 source package can be find below: --------------------------------------------------------------------------------------------------------------------- The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.01 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.02 stable [1] quarterly release. Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn232321 * Fixes Linaro Bugzillas: #1982, #1980 * Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split * Backport of [BugFix] [AArch32] PR target/68214: Delete IP-reg-clobbering call-through-mem patterns * Backport of [BugFix] [AArch32] PR target/68390 * Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add compare-of-zero_extract pattern * Backport of [BugFix] [AArch64] PR target/68696 FAIL: gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1 * Backport of [BugFix] PR rtl-optimization/68381 * Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1 instructions * Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh * Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane * Backport of [ARMv8.1] [AArch32] Add patterns for new instructions * Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1 * Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1. * Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests * Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time * Backport of [AArch32] Add attribute for compatibility with ARM pipeline models * Backport of [AArch32] Fix vector TYPE_MODE in streaming-out * Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions * Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD * Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh * Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane * Backport of [AArch64] Documentation fix for -fpic * Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] Fix a few failures with LSE enabled * Backport of [AArch64] Improve add immediate expansion * Backport of [AArch64] Improve comparison with complex immediates followed by branch/cset * Backport of [AArch64] Rework ARMv8.1 command line options * Backport of [AArch64] Update patterns to support FP zero * Backport of [AArch64] Use aarch64_sync_memory_operand in atomic_store<mode> pattern * Backport of [AArch64] Use vector wide add for mixed-mode adds * Backport of [Misc] Only restrict pure simplification in mult-extend subst case, allow other substitutions * Backport of [Testsuite] [AArch64] Skip big-endian as well for gcc.target/aarch64/got_mem_hoist_1.c * Backport of [Testsuite] Make stackalign test LTO proof * Backport of [Testsuite] Testcase for PR rtl-optimization/68381 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 3 months

1
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GCC's ABI 5

by Renato Golin

Folks, I'd like to know the general opinion on this: https://llvm.org/bugs/show_bug.cgi?id=23529 >From past experience, and my limited point of view, it seems that the GCC community decided to change the ABI, plotted some runes, conjured up a broken implementation (whose bugs people will exploit and GCC will end up keeping them) and pushed distros to follow. I don't know how much distros were involved in the original design. Did they request the changes? Or was that an internal change? How do you guys get to decide when to break the world? I also don't know how will be your policy towards the bugs that people started "using". Are you going to force them moving to a more sane implementation (by issuing compiler/linker errors) or are you going to support as legacy for the decades to come? Is there a detailed document describing all the changes, and is the GCC implementation following that to the letter, or are there still bugs in the current version? I'm not talking about an email thread, but an actual document on GCC's docs pages. All I know is that people in the Clang community waited until GCC's implementation was stable, but somehow Debian based distros started moving as if there was something unholy about the previous ABI, and we've been getting segmentation faults on Hello World! I don't know much about the changes myself, nor I was involved in the discussion, but this is now a major pain for release 3.8.0 and I thought it would be better if I sent an email to Linaro folks and members (which form most of the ARM GNU developers) instead of going on the main lists. That also gives me a bit more freedom to be more candid. I wouldn't send those questions as they are to the GCC/binutils lists, or people would kill me. I don't mean any of them as an offence, they are genuine questions from someone that is not on top of that issue. cheers, --renato

9 years, 3 months

3
3
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question on aarch64 libm

by Virendra Kumar Pathak

Hi Linaro Toochain Group, I have few questions on glibc+libm w.r.t aarch64. If possible, please provide some insight, otherwise kindly redirect me to the concerned person/forum. 1.It seems from the community patches that ARM/Linaro is optimizing glibc functions such as memcpy/memmove, string for aarch64. However, looks like some of these (e.g. memcpy/memmov) patches are still not merged in glibc. Any comment on their availability in glibc? e.g. https://www.sourceware.org/ml/libc-alpha/2015-12/msg00341.html 2. On the same note, is there any plan for optimizing/tuning libm functions (e.g. trigonometric) for aarch64? I could find any matching patches on review board. Please correct me if I am wrong. 3. Looks like ARM have released an independent version of libm for certain trigonometric functions. https://github.com/ARM-software/optimized-routines. Any plan of these optimization going in glibc's libm? Any comment on its performance improvement over GNU libm ? Thanks in advance for your time. -- with regards, Virendra Kumar Pathak

9 years, 3 months

3
4
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[ACTIVITY] 11th - 15th January

by Kugan

== Progress == - LTO and TCWG480 (6/10) * Read and experimented with GCC's LTO codebase. * Setup archlinux on chromebook and ran coremark with perf * Read referenced publications - PR66726 (2/10) * Rebased the patch * Regression tested on x86_64 and using Chritsope's setup * getting ready to post upstream - Misc (2/10) * gcc/bug list * abstract for connect presentation * Meetings == Plan == * LTO * bugs

9 years, 3 months

1
0
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[ACTIVITY] Week 02 - Bis

by Yvan Roux

o Teaching activity (2/10) == Progress == o Linaro GCC (4/10) * Completed backports for 2016.01 * Merged FSF 5 branch into Linaro 5 one * Delivered 2016.01 Snapshot * Try to reproduce Linaro PR #1988 with 2016.01. issue not reproducible o GCC dev. (3/10) * Fix armv8.1-a handling at configure time patch committed upstream in trunk and backported in our branch. * Investigate TCWG-128 (Thumb2 branch out of range with LTO) o Misc (1/10) * Various meetings == Plan == o Look at diff between ABE branches in our validation context o Continue on-going tasks

9 years, 3 months

1
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[ACTIVITY] 11th-15th January

by Bernie Ogden

Port to microinstance - TCWG-432 [3/10] * Fallout from attempts to fix race condition * Various minor fixes - simplifications, better reporting Backport benchmarking - TCWG-352 [1/10] * Decoupled 'target triple' from 'toolchain' name ** Immediately, to let me benchmark with Juno-built native gcc ** But this has been causing minor pain for a while Benchmarking infrastructure documentation - TCWG-496 [1/10] * Finished drafts of LAVA wrapper and microinstance access docs Unexpected 1/2 day off [1/10] Misc [4/10] * Unusual number of meetings * Fiddling with my git workflow * Some thinking about Benchmark-102 for Connect * Figured out why our SPEC objects were disappearing

9 years, 3 months

1
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[ACTIVITY] 11-15 Jan 2015

by Prathamesh Kulkarni

== This Week == * PR69133 (2/10) - Submitted patch upstream for review. * PR24293 (4/10) - Submitted patch upstream for review, and did changes suggested by Joseph Myers * TCWG-319 (1/10) - fp benchmarking complete, sent results upstream for review. * TCWG-72 (1/10) - Addressing Jim's comments * Public Holiday (2/10) == Next Week == Continue ongoing tasks.

9 years, 3 months

1
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[Weekly] 11-15 January 2016

by Michael Collison

== This week == * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (6/10) - Re-implementing using sign/zero extends as this was not clear from the documentation * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (1/10) - Determined to be structure alignment issue * Code review of patch posted for Bugzilla 68532 (1/10) - Completed code review and successfully tested with my vaddw patches * Bugzilla 67323 - Tested patch for TCWG-318 (non-unit stride loads) (1/10) - Patch did not generated vld3 so the bug has been reopened * TCWG-317 - No review feedback yet * Misc (1/10) == Next week == * Bugzilla 68543 - Complete re-implementation with zero/sign extends and test * Bugzilla 69008 - Determine where in compiler issue should be addressed * USA Holiday (January 18th, MLK Day)

9 years, 3 months

1
0
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[ACTIVITY]

by Renato Golin

== Progress == * Support (5/10) - Bug triage: reviewing the 300+ bugs on ARM - closing fixed ones (+35) - adding deps for meta bugs (kernel, android, ias, chromium) (~15) - moving to ARM/AArch64 components, etc. (~30) - Checking a few more kernel patches for Clang support with Arnd * Plan (3/10) - Still planning roadmap for 2016/2017 * Background (2/10) - Code review, meetings, discussions, general support, etc.

9 years, 4 months

1
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[ACTIVITY] 11-15 January 2016

by Yao Qi

# Progress # * Estimate the effort of GDB kernel-awareness work. Give comments on formal slides. [1/10] * GDB inserts breakpoints on the wrong place if these files' basename is the same. TCWG-491. At least, post a patch to avoid GDB crash. Reproduced with a simpler case, open PR 19474. [3/10] * Update document about input interrupt. [1/10] Done. Patch is committed. * TCWG-503, fix GDB test case by @progbits -> %progbits. Patch is posted. [1/10] * Clean up arm software single step code. [3/10] In progress. Some patches are committed, but some are still in my queue. The recent arm software single step change causes a regression on stepping out of signal handler. * Think about the GDB slides for Linaro Connect [1/10] # Plan # * Look into the arm software single step regression. * Post the rest of patches for arm software single step clean up. -- Yao

9 years, 4 months

1
0
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[ACTIVITY] 11-15 January 2016

by Christophe Lyon

== Progress == * Validation - a couple of fixes in the validation jobs - looking at timeouts problems with buildfarm-master * GCC - TCWG-485/PR68620: sent patch for review - TCWG-484/target attributes problems in the testsuite Rebased, but need more pending updates from Christian * Misc (conf calls, meetings, emails, ...) == Next == * Validation: more debug. Hopefully start extending validation scope * GCC: - bug fixing - check trunk regressions reported during the holidays

9 years, 4 months

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[ANNOUNCE] Linaro GCC 5 2016.01 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.01 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.02 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn232321 * Fixes Linaro Bugzillas: #1982, #1980 * Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split * Backport of [BugFix] [AArch32] PR target/68214: Delete IP-reg-clobbering call-through-mem patterns * Backport of [BugFix] [AArch32] PR target/68390 * Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add compare-of-zero_extract pattern * Backport of [BugFix] [AArch64] PR target/68696 FAIL: gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1 * Backport of [BugFix] PR rtl-optimization/68381 * Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1 instructions * Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh * Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane * Backport of [ARMv8.1] [AArch32] Add patterns for new instructions * Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1 * Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1. * Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests * Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time * Backport of [AArch32] Add attribute for compatibility with ARM pipeline models * Backport of [AArch32] Fix vector TYPE_MODE in streaming-out * Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions * Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD * Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh * Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane * Backport of [AArch64] Documentation fix for -fpic * Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions * Backport of [AArch64] Fix a few failures with LSE enabled * Backport of [AArch64] Improve add immediate expansion * Backport of [AArch64] Improve comparison with complex immediates followed by branch/cset * Backport of [AArch64] Rework ARMv8.1 command line options * Backport of [AArch64] Update patterns to support FP zero * Backport of [AArch64] Use aarch64_sync_memory_operand in atomic_store<mode> pattern * Backport of [AArch64] Use vector wide add for mixed-mode adds * Backport of [Misc] Only restrict pure simplification in mult-extend subst case, allow other substitutions * Backport of [Testsuite] [AArch64] Skip big-endian as well for gcc.target/aarch64/got_mem_hoist_1.c * Backport of [Testsuite] Make stackalign test LTO proof * Backport of [Testsuite] Testcase for PR rtl-optimization/68381 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 4 months

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[ACTIVITY] Week 02

by Yvan Roux

o Teaching activity (6/10) == Progress == o Linaro GCC (4/10) * Restart validation blocked by the last infrastructure issues * Discussed and reviewed Jenkins jobs fixes. * Tested potential upstream fixes for linaro BZ 1980 and 1982, but reverting the offending backports is a better solution. == Plan == o Complete backports and deliver 2016.01 GCC snapshot.

9 years, 4 months

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[ACTIVITY] 4th-8th January

by Bernie Ogden

Centralized benchmark source - TCWG-354 [1/10] * Fixed some bugs in Coremark reporting * Experimented some more with clang builds, set this aside for now Port to microinstance - TCWG-432 [3/10] * Fixed some false assumptions exposed by change to uinstance * Worked on LAVA side of coremark reporting Backport benchmarking - TCWG-352 [4/10] * Fixed some bugs that appeared over the holiday * Got job dispatching benchmark run to microinstance, with pointer to backport-containing toolchain * But resulting job fails Benchmarking infra documentation - TCWG-496 [1/10] * Started documenting LAVA wrapper Misc [1/10] =Plan= LAVA side of coremark reporting Fix backport-dispatched benchmark job Much more documentation

9 years, 4 months

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[Weekly] 04-08 January 2016

by Michael Collison

== This week == * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (2/10) - Fixed bugs in assembly generation in patterns - Investigated testing of overflow patterns * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (3/10) - Investigation * Code review of patch posted for Bugzilla 68532 (2/10) - This affects vaddw for aarch32 * Misc (1/10) * Vacation (2/10) == Next week == * TCWG-317 - Ping upstream * Bugzilla 68543 - Complete testing * Bugzilla 67323 - Test patch for TCWG-318 (Test non-unit stride loads) * Bugzilla 69008 - More investigation

9 years, 4 months

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[ACTIVITY] 4 - 8 Jan 2016

by Kugan

== Progress == - TCWG480 – IPA-VRP (4/10) * Continue to read/experiment with lto infrastructure * Getting ready to start discussion upstream - PR69194 and PR67714 (5/10) * Posted patch for PR69194 * Revising and testing patch for PR67714 - Misc (1/10) * gcc/bug list * Meetings == Plan == * LTO * bugs

9 years, 4 months

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[ACTIVITY] 4 - 8 January 2016

by Omair Javaid

== Progress == LLDB development -- Fixed thumb mode issues if user triggers changes to PC register [TCWG-228] [3/10] -- Triage of testsuite failures on armel chromebook [TCWG-228] [2/10] -- Update xfail decorators for arm-linux targets. Marked traiged as xfail. [TCWG-494] [3/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. Half Day Leave [1/10] -- Tooth extraction surgery. == Plan == LLDB development -- Triage more failures on armel chromebook [TCWG-228] -- Submit an updated xfail decorator for arm-linux. [TCWG-494] Miscellaneous -- Connect visa follow up.

9 years, 4 months

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[ACTIVITY] 4 - 8 Jan 2016

by Prathamesh Kulkarni

== This Week == * tcwg-72 (2/10) - Following Jim's suggestions using XEXP (remainder, 0) worked to resolve segfault for DImode case - Resolved ICE's due to (silly) mistakes. * PR69133 (4/10) - Reduced test-case following Markus's suggestions. - I think it happens because node->lto_file_data is set to NULL in lto_free_function_in_decl_state_for_node (). Commenting out the following calls from get_untransformed_body(): lto_free_section_data (file_data, LTO_section_function_body, name, data, len, decl_state->compressed); lto_free_function_in_decl_state_for_node (this); prevents the ICE. I suppose symbols with same name in same partition share state (?), so setting lto_file_data = NULL affects state of 2nd occurence of symbol and we hit the assert. If this is true, gating on lto_file_data doesn't seem unreasonable IMO to avoid ICE (the code anyway has undefined behavior due to violation of ODR). I am still not sure why this "works" for partitioning enabled (one, balanced, 1to1). * 447.deallII bug (1/10) - Bug not reproducible (verified with Kugan). * TCWG-319 benchmarking (1/10) - first job submission failed due to kernel panic - a53: base fp run completed, with-patch in progress * Misc (2/10) - Meetings - ipa

9 years, 4 months

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[ACTIVITY] 4-8 January 2016

by Christophe Lyon

== Progress == * Validation - a couple of fixes in the validation jobs - improvements to the comparison scripts * GCC - investigated bugs #1980 and #1982. Reverted the backports that introduced the problem. - TCWG-485/PR68620: resumed - TCWG-484: target attributes problems in the testsuite. Sent an updated patch, but Christian has also submitted a patch which modifies the compiler behavior. I'll have to update mine when his patch is accepted. * Misc (conf calls, meetings, emails, ....) == Next == * Validation: more cleanup. Hopefully start extending validation scope * GCC: - bug fixing - check trunk regressions reported during the holidays

9 years, 4 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (2/10) - Having a go at PR25722, too hacky for a feature that can be easily worked around. - Reviewing some kernel issues with Arnd * Planning (6/10) - Drafting 2 year plans for LLVM * Background (2/10) - Code review, meetings, discussions, general support, etc. - Catching up from long holidays

9 years, 4 months

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[ACTIVITY] 4-8 Jan 2016

by Yao Qi

# Progress # * Handle input interrupt in GDB. TCWG-424. Done. [3/10] Need to update GDB manual to clarify the expected behaviour of GDB. * Estimate the effort of GDB kernel-awareness work. Done. [1/10] * TCWG-491. Ongoing. [2/10]. Understand symbol handling in GDB. * Various patch review upstream. [2/10]. * Clean up code on arm software single step after some changes from Ericsson. Ongoing. [2/10]. # Plan # * TCWG-491. * Follow up of TCWG-424 to update GDB manual. * Clean up code on arm software single step. * Assess the ARM and AArch64 GDB test result, as 7.11 release is coming soon. -- Yao

9 years, 4 months

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Re: gcc-linaro-5.1 vs gcc-linaro-4.8

by Rob Savoye

Is it in the 2015.11-1 release ? - rob - -------- Original message -------- From: Jim Wilson <jim.wilson(a)linaro.org> Date: 01/05/2016 19:45 (GMT-07:00) To: Xiaofeng Ren <xiaofeng.ren(a)nxp.com> Cc: linaro-toolchain(a)lists.linaro.org, Zhenhua Luo <zhenhua.luo(a)nxp.com> Subject: Re: gcc-linaro-5.1 vs gcc-linaro-4.8 On Tue, Jan 5, 2016 at 4:19 PM, Xiaofeng Ren <xiaofeng.ren(a)nxp.com> wrote: > Hello Jim, > Appreciate for your comments. > I will try to manually apply that patch on my side and try it. > BTW, may I know which released Linaro gcc version include that patch? Maybe I can download it and try it quickly. > https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00025.html It was backported to our gcc-5 branch on Nov 24 by Yvan. This is after the latest release 2015-11 was made. The patch is in the December snapshot, but I think that is a source only release. http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/ You would have to build your own toolchain from that, perhaps by using abe. Jim _______________________________________________ linaro-toolchain mailing list linaro-toolchain(a)lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

9 years, 4 months

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debug information in libc.a

by Fred Peterson

Linaro TCWG, In newer toolchains that are built with ABE, libc.a contains a lot of debugging information, including the paths to the source files on the build machine. I think that's because ABE builds the libraries with -g and never strips out the debug information. I verified this with both the 4.9-2015.05 and 5.2-2015.11 binary releases with the command: arm-linux-gnueabih-objdump -g libc.a | grep '\.c' In older toolchains that were built with crosstool-ng, libc.a did not contain the paths to the source files. I guess crosstool-ng either didn't build the libraries with -g, or it stripped out the debug information later. I verified this with the 4.9-2014.09 binary release. I'm not sure whether this change was intentional, or just an oversight during the switchover to ABE. Regardless, it makes the libraries a lot bigger, and it potentially affects the end user during debugging. The source files of libc, etc. are not typically included with the binary releases. So, when a user of an ABE-built binary release chooses to step into an extern function of libc, gdb will search for the source file. It likely won't be able to access the source file along the same path that worked for the build machine, so it will search its list of source directories. Ultimately, unless the user has downloaded the source files, gdb will likely display a message like "printf.c: No such file or directory". In contrast, when a user of a crosstool-ng-built toolchain tries to step into an extern function of libc, gdb will be unaware of the name of the source file. As a result, the user will not get a message about a missing file. So, should the toolchains' libraries really contain debug information? I think it could be useful for a theoretical multilib folder that covers a -g option. On the other hand, for the usual release builds, isn't the debug information a waste of space and a source of confusion? Thanks, Fred Peterson Engineer - Developer Tools NXP Semiconductors

9 years, 4 months

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gcc-linaro-5.1 vs gcc-linaro-4.8

by Xiaofeng Ren

Hello All, I found one difference between gcc-linaro-5.1 vs gcc-linaro-4.8 while I'm doing lmbench benchmark test for our LS1043 (cortex-A53). While using gcc-linaro-4.8, gcc will generate advanced SIMD instructions (like as ld1, etc), however, gcc-linaro-5.1 will not generate advance SIMD instructions. This will cause big performance gap between gcc-4.8 and gcc-5.1 for lmbench memory bandwidth "fcp" test (bw_mem program). My compiler flags is "-O3 -mcpu=cortex-a53". I also tried several different compiler flags ("-O3 -mcpu=cortex-a53+fp+simd", "-O2 -ftree-vectorize -mcpu=cortex-a53", "-O3 -ftree-vectorize -mcpu=cortex-a53"), all of them doesn't work. Gcc-5.1 toolchain was downloaded from following link: https://snapshots.linaro.org/openembedded/sources/gcc-linaro-5.1-snapshot-2… Can I have your comments on this? Thanks Ron

9 years, 4 months

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mixed LTO support for 'ld -r'

by Nicolas Pitre

Hello toolchain gurus, In the course of Linaro's kernel tinification project, the ability to compile the Linux kernel using LTO is a frequent requirement. However the kernel makes heavy usage of 'ld -r' with .o files resulting from LTO build of .c files as well as .o files resulting from pure assembly code. This mix of LTO and non-LTO object files is not supported by upstream binutils unless a patch from H.J. Lu is applied. That patch has been available since 2013 and was last refreshed in his 2.25.51.0.4 branch last September. It is accessible here: https://git.linaro.org/toolchain/binutils-gdb.git/commit/6da5456971 I've attached a very simple test case demonstrating the problem. With the binutils-lto-mixed.patch applied, this test case compiles to a working executable. Otherwise compilation fails at the 'ld -r' step. One question and one request: - What, if anything, has prevented this patch from being merged in the master branch upstream? - In the mean time, could we include this patch in the Linaro binutils package and releases? Having this available in our toolchain releases would greatly simplify the LTO related work on the kernel. It was included in all binutils releases from H.J. Lu since 2013 and therefore has obtained significant exposure already. Thanks. Nicolas

9 years, 4 months

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[ACTIVITY] 21-23 Dec 2015

by Prathamesh Kulkarni

== This Week == * LTO 447.dealII segfault (2/10) - Breaks only with balanced partitioning, works with other types. - Worked with gcc-5.3, having issues in git bisect * Target Hook conversion (2/10) - Converted SET_ASM_OP to hook * TCWG-319 benchmarking (1/10) - fp benchmark results: a53: 7.16% r1-a12: ~3% a57: 0.35% a15: 0.64% * ipa (1/10) == Holidays upto 4th Jan ==

9 years, 4 months

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[ACTIVITY] 14 - 18 Dec 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (2/10) - Trying to address segfault with DImode * LTO ICE with 483.xalancbmk (6/10) - fighting with benchmark scripts - segfaults with ICE on -flto-partitions=none on symbol _ZThn8_N10xalanc_1_819XercesParserLiaison11resetErrorsEv demangler.com says the symbol is non-virtual thunk to: non-virtual thunk to xalanc_1_8::XercesParserLiaison::resetErrors() ./-lm.res (resolution map file) says PREVAILING_DEF_IRONLY - Trace: http://pastebin.com/vxzmQFHg - Possible fix: http://pastebin.com/rwq8z1N1 Patch passes test and bootstrap, not sure if that's correct approach however. * Target hook conversion (2/10) - Unconditionalizing ASM_OUTPUT_DEF on SET_ASM_OP and converting both to hooks.

9 years, 4 months

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[ACTIVITY] 14th - 21st December

by Bernie Ogden

NB Last _6_ working days. Centralised benchmark source - TCWG-354 [6/10] * Abe integration * Wrote up some notes on collaborate * Enabled clang build, which flushed out some bugs, now fixed * LAVA reporting script Port to microinstance - TCWG-432 [1/10] * Investigating issues with Juno boot ** One turns out to be user error ** The other is a failed heath check, passed to the admins Backport benchmarking - TCWG-352 [2/10] * Difficulties with passing information from matrix children to parent ** Came up with an ugly workaround, may have thought of a better one Misc [3/10] =Plan= Holidays until 4th January

9 years, 4 months

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[ACTIVITY] 14th-18th December

by Yao Qi

# Progress # * TCWG-156, GDB Test-Suite Parity Between Aarch64 and x86_64. Done. [4/10] After two patches are committed, except some tests written for x86_64 unnecessarily, the test results between aarch64 and x86_64 looks no difference. * TCWG-424, timeout when interrupt the inferior in remote debugging. [3/10] The fail is caused by different two problems. Two patches are ready, and being regression tested. * TCWG-171, Enable gdb core file tests when testing remotely. [1/10] Write down my conclusion as it can't be fixed. * Upstream review, [2/10] ** Review patch about handling ada aarch64 HVA array in GDB. ** Discuss target description of GDB for cortex-m device with openocd. # Plan # * Post patches upstream for TCWG-424, * Patches review. * On holiday since Wed. -- Yao

9 years, 4 months

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Linaro LLVM engagement

by Virendra Kumar Pathak

Hi All, I am interested in understanding Linaro LLVM activity. I have already gone through https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM. Could you please guide me on below questions. 1. On which LLVM & clang version, linaro is actively working now ? 2. Where can I find the latest "linaro-llvm" source code & binary? I could not find any official git repo for "linaro-llvm" at https://git.linaro.org/. 3. Could you please explain Linaro LLVM working model? How similar/different it is when compared with Linaro-GCC engagement. 4. Certain links (e.g Roadmap) at https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM ask for login credentials. Any comment on how to obtain the permission? Thanks in advance for your time. -- with regards, Virendra Kumar Pathak

9 years, 4 months

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[ACTIVITY] 14-17 December 2015

by Christophe Lyon

* 1 day off (Friday) (2/10) == Progress == * Validation: (2/10) - improvements to the comparison scripts - updated ABE stable and staging branches * GCC: (3/10) - TCWG-484: sent a new version of the patch to address problems with the testsuite and target attributes. - TCWG-485/PR68620: WIP, trying to understand the regressions introduced by my patch * Misc (conf calls, meetings, emails, ...) (3/10) == Next == Holidays until next year

9 years, 4 months

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Linaro-binutils release git tags

by Virendra Kumar Pathak

Hi All, As per release notes, linaro_binutils-2_25-2015_01-2_release should be present at http://git.linaro.org/toolchain/binutils-gdb.git. But I am not able to see any "linaro_binutils" tags on https://git.linaro.org/toolchain/binutils-gdb.git/tags. Am I doing any mistake? or on git it is renamed to something else (same as FSF binutils tags?). Apology for asking such a trivial question. Thanks for your time. -- with regards, Virendra Kumar Pathak

9 years, 4 months

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[ANNOUNCE] Linaro GCC 5 2015.12 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.12 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn231642 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn231642 * Backport of [Bugfix] [AArch32] 1/4 PR63870 Add qualifiers for NEON builtins * Backport of [Bugfix] [AArch32] 2/4 PR63870 Mark lane indices of vldN/vstN with appropriate qualifier * Backport of [Bugfix] [AArch32] 3/4 PR63870 Remove error for invalid lane numbers * Backport of [Bugfix] [AArch32] 4/4 PR63870 Remove xfails for ARM targets * Backport of [Bugfix] [AArch32] PR67305, tighten neon_vector_mem_operand on eliminable registers * Backport of [Bugfix] [AArch32] remove unused variable * Backport of [Bugfix] [AArch64] PR 63304 Fix issue with global state * Backport of [Bugfix] [AArch64] PR63304 Handle literal pools for functions > 1 MiB in size * Backport of [Bugfix] [AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check * Backport of [Bugfix] [AArch64] PR rtl-optimization/67218 * Backport of [Bugfix] PR 56036 fix typo in doc * Backport of [Bugfix] PR rtl-optimization/68236: Exit early from autoprefetcher lookahead if not in haifa sched * Backport of [Bugfix] PR tree-optimization/68234 Improve range info for loop Phi node * Backport of [AArch32] 1/4 Change GET_MODE_INNER to always return a non-void mode * Backport of [AArch32] 2/3 Make if_neg_move and if_move_neg into insn_and_split * Backport of [AArch32] 2/4 Control the FMA steering pass in tuning structures rather than as core property * Backport of [AArch32] 3/3 Expand mod by power of 2 * Backport of [AArch32] 3/4 Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m) * Backport of [AArch32] 4/4 Fix - Introduce new inline functions for GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION * Backport of [AArch32] 4/4 Introduce new inline functions for GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION * Backport of [AArch32/AArch64] 2/2 Add a new Cortex-A53 scheduling model * Backport of [AArch32] Add missing v8a cpus to the t-aprofile file * Backport of [AArch32] Fix checking RTL error in cortex_a9_sched_adjust_cost * Backport of [AArch32] Fix for testcase after r228661 * Backport of [AArch32] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs * Backport of [AArch32] libgcc: include crtfastmath * Backport of [AArch32] Unified assembler in ARM state * Backport of [AArch64] 1/2 Give AArch64 ROR (Immediate) a new type attribute * Backport of [AArch64] 1/2 Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G * Backport of [AArch64] 1/2 Rename test source file for reuse * Backport of [AArch64] 1/3 Add the option -mtls-size * Backport of [AArch64] 1/3 Expand signed mod by power of 2 using CSNEG * Backport of [AArch64] 2/2 Implement -fpic for -mcmodel=small * Backport of [AArch64] 2/2 Implement TLS IE for tiny model * Backport of [AArch64] 2/3 Rename SYMBOL_TLSLE to SYMBOL_TLSLE24 * Backport of [AArch64] 3/3 Implement local executable mode for all memory model * Backport of [AArch64] Add initial qualcomm support * Backport of [AArch64] Add missing entries in iterator vwcore * Backport of [AArch64] Cleanup whitespace in aarch64.c * Backport of [AArch64] Cortex-A57 Choose some new branch costs * Backport of [AArch64] Define TARGET_UNSPEC_MAY_TRAP_P * Backport of [AArch64] Distinct costs for sign and zero extension * Backport of [AArch64] Do not ICE after apologising for -mcmodel=large -fPIC * Backport of [AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives * Backport of [AArch64] Don't transform sign and zero extends inside mults * Backport of [AArch64] Fall back to -fPIC if no support of -fpic in binutils * Backport of [AArch64] Fix for branch offsets over 1 MiB * Backport of [AArch64] Fix ICE on (const_double:HF 0.0) * Backport of [AArch64] Fix insn types * Backport of [AArch64] Fix output assembly bug under TLSIE ILP32 * Backport of [AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immediate * Backport of [AArch64] Mark GOT related MEM rtx as const to help RTL loop IV * Backport of [AArch64] Properly handle simple arith+extend ops in rtx costs * Backport of [AArch64] Rename SYMBOL_SMALL_GOTTPREL to SYMBOL_SMALL_TLSIE * Backport of [AArch64] Restrict pic-small.c by new test directive * Backport of [AArch64] Tighten direct call pattern for sibcall to repair -fno-plt * Backport of [AArch64] Tighten direct call pattern to repair -fno-plt * Backport of [Testsuite] [AArch32] Fix thumb2-slow-flash-data.c failures * Backport of [Testsuite] [AArch32] Switch ARM to unified asm * Backport of [Testsuite] [AArch64] Add more TLS local executable testcases * Backport of [Testsuite] [AArch64] Check branch types for noplt testcases * Backport of [Testsuite] [AArch64] Fix gcc.target/aarch64/vclz.c * Backport of [Testsuite] [AArch64] Fix some target attribute inlining tests for -fPIC * Backport of [Testsuite] [AArch64] Restrict got_mem_hoist_1.c with small memory model * Backport of [Testsuite] [AArch64] Skip tiny and large code model on gcc.target/aarch64/pic-small.c * Backport of [Testsuite] Add --param sra-max-scalarization-size-Ospeed to sra-12.c * Backport of [Testsuite] Fix target selector in gcc.target/i386/noplt-[1234].c testcases * Backport of [Misc] Allow sibcalls in no-PLT PIC * Backport of [Misc] Eliminate PLT stubs for specified external functions via -fno-plt * Backport of [Misc] Fix for ICE with -g on testcase with incomplete types * Backport of [Misc] Fix memory leak and wrong invariant dependence computation in IVOPT * Backport of [Misc] Improve rtl loop inv cost by checking if the inv can be propagated to address uses * Backport of [Cleanup] [AArch32/AArch64] fix ChangeLog * Backport of [cleanup] [AArch32] Remove uses of CONST_DOUBLE_HIGH/LOW * Backport of [Cleanup] [AArch64] Delete aarch64_symbol_context which is not used * Backport of [cleanup] [AArch64] Move iterators from atomics.md to iterators.md * Backport of [cleanup] [AArch64] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOW * Backport of [Doc] [AArch64] Document several AArch64-specific test directives Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 4 months

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[ACTIVITY] 7 Nov - 11 Nov 2015

by Kugan

== Progress == - LTO (8/10) * Looked at ipa-cp * Read LTO papers * Started with ipa-vrp experiment * Reproduced spec2006 issues - Misc (2/10) * gcc/bug list * LuaJIT == Plan == * LTO

9 years, 5 months

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[ACTIVITY] 7th-11th December

by Bernie Ogden

Centralised benchmark source - TCWG-354 [6/10] * Understood CoremarkPro run rules/behaviour better * Experimented with shortening runs while still giving meaningful results * Cleaned up build/run scaffolding Port to microinstance - TCWG-432 [1/10] * Got access to microinstance, learned a bit about SSL in the process Backport benchmarking - TCWG-352 [2/10] * Fixed 'build with sysroot' code for current deliverable shape * Fixed a problem with multiple manifests =Plan= Review, test, debug build-triggers-benchmark job Finish off Coremark Pro integration Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) More support for SPEC-on-Android? =Absence= Holiday 22nd December - 1st January

9 years, 5 months

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[ACTIVITY] 7 Nov - 11 Nov 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (2/10) - Another iteration. * LTO (4/10) - Building spec with different combinations of -flto -flto-partition -flto-compression-level - Builds cleanly on AArch64, ICE's on ARM for 447.dealII with -flto - Looked at segfault with 483.xalanpack * TCWG-319 benchmarking (1/10) - fp benchmark results on: r1-a12: -0.04 % cortex-a53: -0.09 % cortex-a57: -0.14% - int benchmarks completed running for reference revision on cortex-a15 - int benchmarks with-patch runnning on cortex-a15 * TCWG-310 benchmarking (1/10) - r1-a12: 0.11% - Benchmark jobs failed on a53, a57. * Misc (2/10) - Submitted patch to fix building 450.soplex - Looked at how to write ipa pass, ipa-pure-const and ipa-cp. - Meetings == Next Week == - tcwg-319, tcwg-310 benchmarking - tcwg-72 - LTO

9 years, 5 months

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[Weekly] 07-11 December 2015

by Michael Collison

== This week == * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (7/10) - Implemented signed and unsigned add, subtract, and multiply overflow standard patterns - Investigated testing of overflow patterns * Misc (3/10) - Conference calls - Misc ARM Housekeeping - Lost connectivity due to old ARM Unix VPN Client == Next week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 - Minor code update to address upstream comment * Vacation until rest of year

9 years, 5 months

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[ACTIVITY] 7-11 December 2015

by Christophe Lyon

== Progress == * GCC (4/10) - pr68620 (fp16 transfers in big-endian mode) - checking regressions observed on trunk - had to revert my cleanup patch for target attributes tests, not sure how to handle all possible combinations of options/defaults * Validation (1/10) - small improvements in reporting * Misc (conf calls, meetings, emails, ...) (3/10) * Internal training (2/10) == Next == * Validation * GCC: bug fixes/cleanup

9 years, 5 months

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[ACTIVITY] Dec 7 - 11, 2015

by Yao Qi

* One day off on Wed. [2/10] # Progress # * Enable gdb core file tests when testing remotely, TCWG-171. I've almost had the conclusion that corefile remote testing can't be done due to limitations in dejagnu and nfs mount testing infrastructure. Need to write them down. [2/10] * Mutli-arch follow-up work, teach AArch64 GDBserver understand ARM breakpoint instructions. TCWG-460. Done. [3/10] * Review ARM GDBserver software single step patch V7. Almost OK, except some small things. [2/10] * Misc, meeting, email, [1/10] # Plan # * TCWG-424, Draft a fix for the fail in random-signal.exp. * TCWG-156, GDB test parity between AArch64 and X86_64. * One day off on Wed. or Fri. Planned absence: * Dec 24-Jan 3. -- Yao

9 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Holiday (2/10) * Release (1/20) - 3.7.1 Final, all green * Maintenance (5/10) - Fixing PR25720 - Bug cleaning: PR18921, PR13259, PR13138, PR12926, PR17963, PR18187, PR22692 - Checked strided vectorizer on ToT, EEMBC 2x geomean! * Background (2/10) - Code review, meetings, discussions, general support, etc. - Power cut, restarting bots, testing TK1, plans, etc. == Holidays == I'll be back on the 5th Jan.

9 years, 5 months

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[ACTIVITY] Nov 30 - Dec 4, 2015

by Kugan

== Progress == - PR66726 (2/10) * Testing a patch - PR63586 (2/10) * Posted a patch * Revised the patch based on testing - LuaJIT (2/10) * Setup nginx * Still haven't figured out how to use mongodb with nginx (config required). - Misc (2/10) * gcc/bug list * LTO - sick (2/10) == Plan == * bug reports * LTO

9 years, 5 months

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incomplete .arch specifiers with latest Linaro gcc5 patches on armv8?

by Robert Schiele

Hi, when working with the Linaro patches I found that a particular commit breaks our aarch64 kernel build. The patch in question is that one: commit be09330da9d0777c4a58568d137e3f8a3dbe0a0b Author: Yvan Roux <yvan.roux(a)linaro.org> Date: Tue Oct 27 21:18:19 2015 +0100 One of the things it attempts to change apparently is moving the .arch specifiers in the assembler file from a global scope to individual functions. What also happens though is that they seem to lose some information after that transformation. I observed that when building arch/arm64/crypto/aes-ce-cipher.c from the Linux kernel. This code contains inline assembly like this: static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[]) { struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm); struct aes_block *out = (struct aes_block *)dst; struct aes_block const *in = (struct aes_block *)src; void *dummy0; int dummy1; kernel_neon_begin_partial(4); __asm__(" ld1 {v0.16b}, %[in] ;" " ld1 {v1.2d}, [%[key]], #16 ;" " cmp %w[rounds], #10 ;" " bmi 0f ;" " bne 3f ;" " mov v3.16b, v1.16b ;" " b 2f ;" "0: mov v2.16b, v1.16b ;" " ld1 {v3.2d}, [%[key]], #16 ;" "1: aesd v0.16b, v2.16b ;" " aesimc v0.16b, v0.16b ;" "2: ld1 {v1.2d}, [%[key]], #16 ;" " aesd v0.16b, v3.16b ;" " aesimc v0.16b, v0.16b ;" "3: ld1 {v2.2d}, [%[key]], #16 ;" " subs %w[rounds], %w[rounds], #3 ;" " aesd v0.16b, v1.16b ;" " aesimc v0.16b, v0.16b ;" " ld1 {v3.2d}, [%[key]], #16 ;" " bpl 1b ;" " aesd v0.16b, v2.16b ;" " eor v0.16b, v0.16b, v3.16b ;" " st1 {v0.16b}, %[out] ;" : [out] "=Q"(*out), [key] "=r"(dummy0), [rounds] "=r"(dummy1) : [in] "Q"(*in), "1"(ctx->key_dec), "2"(num_rounds(ctx) - 2) : "cc"); kernel_neon_end(); } Now without this patch the compiler behaved like the following. It was invoked with: aarch64-linux-gnu-gcc -Wp,-MD,arch/arm64/crypto/.aes-ce-cipher.o.d -nostdinc -isystem /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/bin/../lib/gcc/aarch64-linux-gnu/5.2.1/include -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/include -Iarch/arm64/include/generated/uapi -Iarch/arm64/include/generated -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include -Iinclude -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/include/uapi -Iarch/arm64/include/generated/uapi -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include/uapi -Iinclude/generated/uapi -include /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include/linux/kconfig.h -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/crypto -Iarch/arm64/crypto -D__KERNEL__ -mlittle-endian -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -std=gnu89 -mgeneral-regs-only -fno-delete-null-pointer-checks -O2 --param=allow-store-data-races=0 -Wframe-larger-than=2048 -fno-stack-protector -Wno-unused-but-set-variable -fno-omit-frame-pointer -fno-optimize-sibling-calls -fno-var-tracking-assignments -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -Werror=strict-prototypes -Werror=date-time -DCC_HAVE_ASM_GOTO -Werror -march=armv8-a+crypto -D"KBUILD_STR(s)=#s" -D"KBUILD_BASENAME=KBUILD_STR(aes_ce_cipher)" -D"KBUILD_MODNAME=KBUILD_STR(aes_ce_cipher)" -c -o arch/arm64/crypto/aes-ce-cipher.o /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/crypto/aes-ce-cipher.c As a result it created a file for the assembler with the global .arch armv8-a+fp+simd+crypto at the beginning of the file. After the patch it created individual .arch armv8-a at individual places. It is not clear to me, why the extensions (fp+simd+crypto) got lost. Is that intended, such that the code needs special adaption for inline assembly using those extensions or is that loss of extensions a bug of that patch? Greetings! Robert

9 years, 5 months

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[ACTIVITY] Week 48

by Yvan Roux

== Progress == o Linaro GCC (6/10) * More backports * Compared our various flavor of validation results * Looked at bug reports and mailing list questions on our last snapshot. o Upstream work (2/10) * Continue on sanitizing gfortran testsuite o Misc (2/10) * Various meetings * Discussed benchmarking infra with Bernie == Plan == o GCC 5.3 branch merge o Continue on-going tasks o Tuesday Off

9 years, 5 months

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[ACTIVITY] 30th November - 4th December

by Bernie Ogden

Holiday [2/10] Port to microinstance - TCWG-432 [1/10] * Set up reporting for CPU2006 * Learned how to generate metadata, but not how to use it Trigger benchmarks on backports - TCWG-352 [2/10] * Figured out the rough shape * Created, didn't test, rough implementation TCWG-354 [3/10] * Build/run scaffolding for CoreMark Pro * Working for manual runs Misc [2/10] * Input validation for dispatcher script * Meeting with Ade on LAVA benchmarking * Meetings/mail/etc =Plan= Review, test, debug build-triggers-benchmark job Check CoreMark Pro run configuration, enable for automatic runs Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) More support for SPEC-on-Android?

9 years, 5 months

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[ACTIVITY] 30 Nov to 4 Dec 2015

by Prathamesh Kulkarni

* TCWG-72 (2/10) - Added new target hook to generate target-specific divmod libfunc - Builds cleanly now on x86_64, arm and arm-linux-gnueabihf - Sent to tcwg list for review * LTO spec2k6 build (2/10) - Built speck26 with LTO * Target hook (4/10) - Completed with ASM_OUTPUT_LABEL_REF - In progress - SIZE_ASM_OP to data hook, ASM_OUTPUT_SIZE_DIRECTIVE, ASM_OUTPUT_MEASURED_SIZE * Benchmarking (1/10) - tcwg-319: Job in progress for fp benchmarks with patch - tcwg-310 (loop peeling): Submitted job for running 252.eon - Both the jobs failed due to lab downtime, need to be re-run. - Received job template from Bernie for running benchmarks on cortex-a15. * Misc (1/10) - Meetings == Next Week == - Continue benchmarking spec2k6 with LTO - Look at bugs exposed by speck2k6 LTO build - Benchmarking tcwg-319, tcwg-310

9 years, 5 months

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[Weekly] 30 November - 4 December 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (0/10) - No comments/review upstream will ping for update * TCWG-316 - Exploit vector multiply by scalar instructions (4/10) - Code improvements will require standard name for vectorizer and new patterns - On hold until GCC 6 is released * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (3/10) - Initial investigation * Bugzilla 68532 - [ARM] Incorrect code result on arm big endian (2/10) - Investigation into understanding how vectorizer represents lanes vs arm big endian back end - Solution suspended until I can coordinate with Charlie * Misc (1/10) - Conference calls == Next week == * Bugzilla 68543 - Implement add and subtract overflow operations and test * TCWG-317 - Ping upstream and respond to upstream feedback * Bugzilla 68532 - Coordinate with Charlie

9 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Ill (4/10) * Support (1/10) - Bugzilla issues (PR20490, PR24635, PR24350, PR20025, PR25720, PR25722) * Benchmarks (1/10) - Checking some previous benchmark results on A57 * Buildbots (2/10) - Getting AArch64 full bot back to rotation, since it's stable now - Re-enabling libc++ prototypes on local master - Bisecting broken test-suite - Another power cut in the office sent all the bots down... :( * Background (2/10) - Code review, meetings, discussions, general support, etc. - Validating some old sanitizer bugs - FOSDEM admin

9 years, 5 months

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[ACTIVITY] 30th Nov - 04th Dec

by Yao Qi

* One day off on Monday. # Progress # * Answer ST questions about supporting multi-arch with ST jtag probe. [1/10] * TCWG-171, Enable gdb core file tests when testing remotely, [3/10]. Ongoing. * Run gdb.base/sizeof.exp with board having gdb,noinferiorio. Done. [1/10] * TCWG-460, mutli-arch follow-up work, teach AArch64 GDBserver understand ARM breakpoint instructions. Patch is approved. [2/10]. * TCWG-424, fail in gdb.base/random-signal.exp. [1/10] Root cause is identified, need to figure out how to fix it in next step. * Review ARM GDBserver software single step patch V4. # Plan # * TCWG-171, TCWG-156, TCWG-424. * Review ARM GDBserver software single step patch V5, which should be the final version, I hope. -- Yao

9 years, 5 months

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[ACTIVITY] Nov 30- Dec 4, 2015

by Christophe Lyon

== Progress == * Validation - a few cleanup patches in the comparison scripts - contribute to debug of ptys allocation problems: the tests pass when executed outside of our schroots. - improvements in the reports from the validation done in the ST Compute Farm - reported a few regressions * GCC - cleanup patch for target attributes tests, - pr68620 (fp16 transfers in big-endian mode) * Misc (conf calls, meetings, emails, ....) == Next == * Validation: monitoring, improvements * GCC: bug fixes, cleanup

9 years, 5 months

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GNU GCC development plan and its interaction with Linaro

by Virendra Kumar Pathak

Hi Linaro Toolchian Group, I am new to GCC development and have some basic question on its development process. Could you please give some insight on below questions. (Apology if they are very trivial). I have read https://gcc.gnu.org/develop.html If I am correct, gcc trunk is on gcc 6.0.0 (stage 3) at present and will becomes 6.0.1 (regression fix only) in January 2016. gcc 6.0.1 will be released as gcc 6.1.0 in April, 2016 and from there onwards gcc 6 release branch will start. However, There is also a gcc 5 branch in parallel whose current version is 5.2.1 and will be released as gcc 5.3 soon. Hopefully gcc 5.3 would be the last release in gcc 5 series. (Please correct me if I am wrong). [Questions] 1. What is the difference between experimental(gcc 6.0.0 stage 3) & gcc release branch (gcc 5.2.1)? Is there any rule which decides which changes will go where? In case, I have some patches for new aarch64 processor at present, in which branch these changes would be merged (assuming they passes reviews)? 2. How is the subversion of release branches are decided? Is it correct to say that there will be always 3 subversion of any release branch (e.g. gcc 5.1, gcc 5.2 & gcc 5.3)? 3. What is the working model between GNU GCC and Linaro GCC? Does Linaro directly accept patches? or they need to go to GNU GCC first? Thanks in advance for your time. with regards, Virendra Kumar Pathak -- with regards, Virendra Kumar Pathak

9 years, 5 months

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Fwd: Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch

by Robert Schiele

Keeping linaro-toolchain in the loop. Robert ---------- Forwarded message ---------- From: Robert Schiele <rschiele(a)gmail.com> Date: Thu, Dec 3, 2015 at 4:44 PM Subject: Re: Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch To: Yvan Roux <yvan.roux(a)linaro.org> Hi Yvan, On Thu, Dec 3, 2015 at 1:25 PM, Yvan Roux <yvan.roux(a)linaro.org> wrote: > This fix on gcc-5-branch doesn't apply on Linaro 5 branch, because we > have backported trunk revision 222624 (which renames maybe_fma to > coumpound_p) into it. So, our branch as the same code as trunk one > regarding aarch64_rtx_costs. Do you experiment any issues related to > this change ? No issues. This was just a theoretical thought and through our CI build I learned exactly what you just told me the hard way now. Sorry for the noise. Robert

9 years, 5 months

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Bug: Linaro ABE abe.sh doesn't allow timeout > 10 seconds

by Christopher Roberts

abe.sh in the ABE framework accepts a parameter to set the wget timeout when it fetches snapshots (default 10s); however that parameter has an upper threshold of 10 seconds (condition at line 996 only sets timeout to specified value if < 11). Is this intentional? It seems like it would make more sense to give it a floor instead of a ceiling or perhaps not limit the range of potential values at all. Best regards, Chris Roberts

9 years, 5 months

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why ld.so in arm-linux-gnueabihf- toolchains search so many paths ?

by Barry Song

hi guys, sorry maybe my question is stupid as i am not a toolchain guy. i have no idea why ld.so search so many paths. for example, put "-rpath" with /home/cnb1szh/test in a simple test program. then during dynamic linking at runtime, we get the below linking debug information: 30693: find library=libmytest.so [0]; searching 30693: search path=/home/cnb1szh/test/tls/v7l/neon/vfp:/home/cnb1szh/test/tls/v7l/neon:/home/cnb1szh/test/tls/v7l/vfp:/home/cnb1szh/test/tls/v7l:/home/cnb1szh/test/tls/neon/vfp:/home/cnb1szh/test/tls/neon:/home/cnb1szh/test/tls/vfp:/home/cnb1szh/test/tls:/home/cnb1szh/test/v7l/neon/vfp:/home/cnb1szh/test/v7l/neon:/home/cnb1szh/test/v7l/vfp:/home/cnb1szh/test/v7l:/home/cnb1szh/test/neon/vfp:/home/cnb1szh/test/neon:/home/cnb1szh/test/vfp:/home/cnb1szh/test (RPATH from file ./hello) 30693: trying file=/home/cnb1szh/test/tls/v7l/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/libmytest.so 30693: trying file=/home/cnb1szh/test/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/libmytest.so but we don't have /home/cnb1szh/test/tls/, /home/cnb1szh/test/v7l/, /home/cnb1szh/test/vfp/, /home/cnb1szh/test/neon/, why does the ld.so search so many paths? -barry

9 years, 5 months

3
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Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch

by Robert Schiele

Hi, I found that with the merge commit ac19ac6481a3f326d9f41403f5dadab548b2c8a6 Author: Yvan Roux <yvan.roux(a)linaro.org> Date: Wed Sep 16 10:57:42 2015 +0200 Merge branches/gcc-5-branch rev 227732. Change-Id: I2f59904b28323b1c72a8cf1bd62c9e460d95bcea the following branch that was within merge range on gcc-5-branch was lost on the linaro branch: commit b45a5cf7c1544f95578e823e25402b58fb3fbedd Author: nsz <nsz@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Tue Aug 4 16:49:54 2015 +0000 Fix broken backport patch. gcc: Backport from mainline: 2015-08-04 Szabolcs Nagy <szabolcs.nagy(a)arm.com> PR target/66731 * config/aarch64/aarch64.c (aarch64_rtx_costs): Fix NEG cost for FNMUL. (aarch64_rtx_mult_cost): Fix MULT cost with -frounding-math. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@226588 138bc75d-0d04-0410-961f-82ee72b054a4 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 691874b..eebc9c3 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5250,7 +5250,7 @@ aarch64_rtx_mult_cost (rtx x, int code, int outer, bool speed) which case FNMUL is different than FMUL with operand negation. */ bool neg0 = GET_CODE (op0) == NEG; bool neg1 = GET_CODE (op1) == NEG; - if (compound_p || !flag_rounding_math || (neg0 && neg1)) + if (maybe_fma || !flag_rounding_math || (neg0 && neg1)) { if (neg0) op0 = XEXP (op0, 0); Since this was a fix to the patch one commit ahead and also merged in the same operation and there is no further comment on why this fix was skipped, may I assume that this happened by accident and you probably want to fix that merge flaw by reapplying the missing patch? Or is there an information detail I don't have that requires this fix to be skipped on the Linaro branch? Robert

9 years, 5 months

2
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[ACTIVITY] 23rd - 27th November

by Bernie Ogden

Controlled image builds - TCWG-360 [1/10] * Tried, failed to generate bootable images Jenkins benchmarking job - TCWG-348 [5/10] * Jenkins job functional on kvms in main instance * Wrote job-dispatch script for non-Jenkins use cases Juno crashdump [1/10] * Struggled with, worked around network problems * Juno running, waiting for it to crash SPEC-on-Android [1/10] * Helped Qian to find root cause of a problem Misc [2/10] =Plan= Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) Probably more support for SPEC-on-Android

9 years, 5 months

1
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