== This week ==
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Additional investigation and preliminary implementation
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store (1/10)
- Investigation
* TCWG-247 - Create Validation Job to run on GCC Trunk Committ (5/10)
- Began writing shell script.
* Misc meeting (1/10)
== Next week ==
* TCWG-247
- Make additional prgoress on prototype
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM)
- Additional investigation and preliminary implementation
* Bugzilla 70089 - ARM/THUMB unnecessarily typecasts some rvalues on
memory store
- Investigation
* Vacation
- April 8 - April 12
== Progress ==
* Holiday (2/10)
* Support (1/10)
- Reapplying fix for PR16275 (D18701)
- Conclusion is that original approach will be the same as GCC
- Additional flags will have to be agreed upon across compilers
* Buildbot (2/10)
- Setting up LLDB buildbot with Omair
- Precarious infrastructure is unstable, hope it holds on until the
new rack is complete
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- More team management stuff (access/procedure/meeting with newcomers)
- Planning the lab move, resources, costs, schedule
* Monday off [2/10]
# Progress #
* TCWG-167, ARM reverse debugging bug fixes. [4/10]
Two patches are posted. Two patches are being tested. They fix
207 FAILs (242 -> 35) in gdb.reverse.
* TCWG-545, no progress, patches are pending for review.
* TCWG-547, [2/10]. Write a patch as Pedro suggested, so we have
sense which patch is better. No response.
* Misc, [2/10]
** Upstream discussions on get syscall number on execve exit. Can't
get such thing from kernel side, need to figure out how to do it
in GDB side.
** Investigate a little bit on 32-bit DWARF on AArch64.
# Plan #
* TCWG-167, TCWG-545, TCWG-547
--
Yao
== This Week ==
* LTO (7/10)
a) TCWG-534 (ipa-comdats):
- Patch posted upstream: https://gcc.gnu.org/ml/gcc/2016-03/msg00254.html
- Investigating ICE with patch for comdat-2.C
b) TCWG-128 (branch out of range error):
- Posted patch upstream:
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00032.html
c) intra-procedural vrp:
- Looking to implement replacement_order algorithm for early vrp from the paper:
https://engineering.purdue.edu/paramnt/publications/1381.pdf
* Validation (2/10)
- Reviews on tcwg-buildapp from Christophe and Maxim
- prototype job ran successfully.
* Misc (1/10)
- Meetings
== Next Week ==
* LTO:
- Try to implement replacement order algorithm for vrp
- Continue investigating ipa-comdats ICE and address upstream comments.
- Gather stats for chromium LTO build
* Validation:
- write script to build chromium
On Wed, Mar 30, 2016 at 6:26 PM, fengwei.yin <fengwei.yin(a)linaro.org> wrote:
> Thanks a lot for your quick response. The .ii file was attached.
In UnwindFromContext, there is an asm that forces the assembler into ARM mode.
if (ucontext == nullptr) {
int ret = (({ unw_tdep_context_t *unw_ctx = (&context_); register unsigned \
long *unw_base asm ("r0") = unw_ctx->regs; __asm__ __volatile__ ( ".align 2\nbx\
pc\nnop\n.code 32\n" "stmia %[base], {r0-r15}\n" "orr %[base], pc, #1\nbx %[ba\
se]" : [base] "+r" (unw_base) : : "memory", "cc"); }), 0);
The ".code 32" puts us in ARM mode.
GCC still thinks that we are in thumb mode though, and continues to
emit thumb instructions, some of which have no arm mode equivalent,
e.g. cbnz and cbz.
I don't see any convenient push/pop for thumb/arm mode. This is
probably a macro expanded into the asm. You could have two versions
of the asm, one that gets used when __thumb__ is defined and one that
gets used when __thumb__ is not defined. The __thumb__ version would
switch back into thumb mode at the end with a ".thumb" pseudo-op.
Or alternatively, don't build with -mthumb.
Jim
Hi folks,
I am trying to use arm gcc 5.3 to build part of android AOSP and hit
following issue with arm gcc 5.3:
The gcc cmd line is like:
/opt/work/acadine/mem_shrink/B2G-v2.5/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-5.3-linaro/bin/arm-linux-androideabi-g++
-I external/libcxx/include -I system/core/libbacktrace -I
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates
-I
out/target/product/linaro_arm/gen/SHARED_LIBRARIES/libbacktrace_intermediates
-I libnativehelper/include/nativehelper -I system/core/base/include -I
external/libunwind/include -isystem system/core/include -isystem
system/media/audio/include -isystem hardware/libhardware/include
-isystem hardware/libhardware_legacy/include -isystem
hardware/ril/include -isystem libnativehelper/include -isystem
frameworks/native/include -isystem frameworks/native/opengl/include
-isystem frameworks/av/include -isystem frameworks/base/include -isystem
out/target/product/linaro_arm/obj/include -isystem
bionic/libc/arch-arm/include -isystem bionic/libc/include -isystem
bionic/libc/kernel/uapi -isystem bionic/libc/kernel/uapi/asm-arm
-isystem bionic/libm/include -isystem bionic/libm/include/arm -c
-fno-exceptions -Wno-multichar -msoft-float -ffunction-sections
-fdata-sections -funwind-tables -fstack-protector -Wa,--noexecstack
-Werror=format-security -D_FORTIFY_SOURCE=2 -fno-short-enums
-no-canonical-prefixes -fno-canonical-system-headers -march=armv7-a
-mfloat-abi=softfp -mfpu=vfpv3-d16 -include
build/core/combo/include/arch/linux-arm/AndroidConfig.h -I
build/core/combo/include/arch/linux-arm/ -Wno-psabi -mthumb-interwork
-DANDROID -fmessage-length=0 -W -Wall -Wno-unused -Winit-self
-Wpointer-arith -Werror=return-type -Werror=non-virtual-dtor
-Werror=address -Werror=sequence-point -DNDEBUG -g -Wstrict-aliasing=2
-fgcse-after-reload -frerun-cse-after-loop -frename-registers -DNDEBUG
-UDEBUG -fvisibility-inlines-hidden -DANDROID -fmessage-length=0 -W
-Wall -Wno-unused -Winit-self -Wpointer-arith -Wsign-promo -std=gnu++11
-Werror=return-type -Werror=non-virtual-dtor -Werror=address
-Werror=sequence-point -DNDEBUG -UDEBUG -mthumb -Os -fomit-frame-pointer
-fno-strict-aliasing -fno-rtti -Wall -Werror -fPIC -D_USING_LIBCXX
-std=gnu++11 -Werror=int-to-pointer-cast
-Werror=pointer-to-int-cast -MD -MF
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates/UnwindCurrent.d
-o
out/target/product/linaro_arm/obj/SHARED_LIBRARIES/libbacktrace_intermediates/UnwindCurrent.o
system/core/libbacktrace/UnwindCurrent.cpp
And I got error:
/tmp/ccZ40ViQ.s: Assembler messages:
/tmp/ccZ40ViQ.s:1752: Error: selected processor does not support ARM
mode `cbnz r6,.L91'
/tmp/ccZ40ViQ.s:1758: Error: selected processor does not support ARM
mode `cbnz r0,.L92'
/tmp/ccZ40ViQ.s:1763: Error: selected processor does not support ARM
mode `cbz r1,.L107'
/tmp/ccZ40ViQ.s:1941: Error: selected processor does not support ARM
mode `cbz r6,.L100'
But if I use the arm gcc 4.9, there is no any build issue.
the "-dumpspecs" output of gcc 5.3 was attached. Thanks.
Regards
Yin, Fengwei
The Linaro Binary Toolchain
============================
The Linaro GCC 4.9-2016.02 Release is now available.
Notice: All Linaro GCC 4.9 series toolchain users should migrate to
the latest version of the Linaro GCC 4.9 toolchain in order to
mitigate potential security exposure to CVE-2015-7545. See the NEWS
section below for details.
Download release packages from:
http://releases.linaro.org/components/toolchain/gcc-linaro/4.9-2016.02/http://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 4.9-2016.02
FSF eglibc 2.19 (eglibc.git/linaro_eglibc-2_19)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.24 (linaro_binutils-2_24-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro Linux Version 3.17-2014.10 (linux-linaro-3.17-2014.10)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 4.9-2016.02
================================
* The armv8l-linux-gnueabihf targetted toolchain is now built using
--with-mode=thumb (like all of the other cross toolchains) rather than
the default which is ARM mode.
* Applied fix for CVE-2015-7545 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
Linaro eglibc 2.19 (linaro_eglibc-2_19).
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* See the following Linaro GCC snapshot:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
The Linaro Binary Toolchain
============================
The Linaro GCC 4.9-2016.02-rc1 Release-Candidate is now available.
Notice: All Linaro GCC 4.9 series toolchain users should migrate to
the latest version of the Linaro GCC 4.9 toolchain in order to
mitigate potential security exposure to CVE-2015-7545. See the NEWS
section below for details.
Download release-candidate packages from:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2016.02-rc1/http://snapshots.linaro.org/components/toolchain/binaries/4.9-2016.02-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 4.9-2016.02-rc1
FSF eglibc 2.19 (eglibc.git/linaro_eglibc-2_19)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.24 (linaro_binutils-2_24-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro Linux Version 3.17-2014.10 (linux-linaro-3.17-2014.10)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 4.9-2016.02-rc1
====================================
* Applied fix for CVE-2015-7545 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
Linaro eglibc 2.19 (linaro_eglibc-2_19).
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* See the following Linaro GCC snapshot:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
== Progress ==
* Validation
- extended validation: updated ABE patch after review
- investigating how to actually separate stdout/stderr streams in dejagnu
- still seeing random results (mostly in the sanitizers tests) in
the Cambridge lab
* GCC
- no progress on Win32-hosted toolchain bug: cannot reproduce it
from a manually built toolchain
- advSIMD/Neon intrinsics tests: cleanup on-going
- bug 2125: forwarded upstream, quickly fixed by R.Biener, backport
in progress
- Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- more on extended validation
- random tests investigation
- more on stdout/stderr
* GCC:
- trunk monitoring, report regressions if needed
- intrinsics tests cleanup
o Easter Monday off (2/10)
== Progress ==
o Extended validation (5/10)
* Worked on benchmarking integration
* Analyzed failures due to --tarbin and --check ABE's flags
* Analyzed native AArch32 timeout (due to guality/GDB testcase)
o Misc (3/10)
* Various meetings
== Plan ==
o Continue on extended validation
o Finalize DejaGNU patches, GCC ARMv8.1 builtins fix.
== Progress ==
* Type promotion pass (6/10)
- Fixed major false positive uninit warnings
= Changed tree-ssa-uinit to handle SEXT_EXPR
= preserving TREE_NO_WARNING set by SRA
= Somemore fixes to preserve debug loc
- There are still some more but this is mainly due to how
tree-ssa-uinit is designed
- Working through the output patterns; some are simple changes but
some needs more analysis
- Planning to create a branch with the latest version for easy review
* Bugs (1/10)
- PR70359
* Misc (1/10)
- GCC Lists
* Public holiday (2/10)
== Plan ==
* Type promotion pass benchmarking
* Perf with LTO
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (4/10)
- Resolved all thumb2 failures
- Posted new patch upstream
* TCWG-247 - Create Validation Job to run on GCC Trunk Commits (1/10)
- Investigation into Python API for discovering when Jenkins builders
are idle
* Laptop hardware failure debugging (2/10)
- Requested a new laptop from Arm
* Misc meeting (1/10)
* Good Friday holiday (2/10)
== Next week ==
* TCWG-247
- Create prototype implementation
== This Week ==
* LTO (4/10)
- Committed r234490 to fix PR70366
- Spent unnecessary time tracking down known (invalid) bug PR65778
- LTO and branch out of range error:
- patch to introduce max partition size param
- experimenting with partition sizes to find value close to 16 mb limit.
* Validation (2/10)
- Pushed script to it's own repo
- Reviews from Christophe on tcwg-buildapp job
* Public Holidays (4/10)
== Next Week ==
- Continue ongoing tasks
== Progress ==
* Support (2/10)
- Investigating a bit more PR16275, need some bigger changes in Clang/LLVM
* Background (6/10)
- Code review, meetings, discussions, general support, etc.
- Planning for a bigger team (git, Jenkins, infrastructure, documentation)
- Receiving new team members, planning start up tasks
- Android NDK discussion, investigation
Realising my activity report has been almost useless for the past month or so...
# Progress #
* TCWG-532, done. [1/10]
Canonicalize ARM syscall patch is committed.
* TCWG-167, patch is posted for review. [4/10]
Add ARM epilogue unwinder in GDB, which fixes many gdb.reverse test
fails.
* TCWG-545, V2 are posted. [1/10]
* TCWG-547, [2/10] patches are reviewed, almost OK, but some changes are
needed.
* Talk with Jojo Ma.
* Open tickets to install buildbot-slave on gcc compile farm for GDB
buildbot setup.
# Plan #
* Holiday on Friday and next Monday.
* TCWG-167, TCWG-545, TCWG-547.
--
Yao
== Progress ==
* Validation
- extended validation: submitted ABE patch for discussion
- noticed random results on some tests in the Cambridge lab.
maybe caused by excessive load on the tester, or stdout/stderr problems
- investigating how to actually separate stdout/stderr streams in dejagnu
* GCC:
- branch merge review for 2016.03 snapshot
- AdvSIMD/Neon intrinsics tests: more cleanup, wondering about
poly128_t prototypes
* Misc (conf calls, meetings, emails, ....)
== Next ==
* Validation:
- more on extended validation
- random tests investigation
- more on stdout/stderr
* GCC:
- trunk monitoring, report regressions if needed
- intrinsics tests cleanup
== This Week ==
* LTO (3/10)
a) section anchors:
- prototype patch to bind functions to global vars
- looked at balanced partitioning
b) chromium LTO build fails with ICE on trunk for arm-linux-gnueabihf:
http://pastebin.com/sX6yKLBP
c) ipa-comdat
- Looked at the pass.
- trying to address TODO: put symbol in it's own comdat section
* Validation (1/10)
- prototype job in bash.
* Holidays (6/10)
== Next Week ==
Continue ongoing tasks
Port to microinstance - TCWG-432 [5/10]
* Non-lab side of minimal trust benchmarking
* More investigation of runtime anomalies
* Reordered builder phases to do useful work while waiting for targets
* Updated everything to work with benchmarking LAVA user (rather than
running as me)
Automated backport benchmarking - TCWG-352 [2/10]
* Cycles of review/development/testing
Controlled image builds - TCWG-360 [1/10]
* More failures to get image to boot on Juno
Log critical data - TCWG-349 [1/10]
* Everything now logged, except where it depends on TCWG-360
Misc - [1/10]
=Plan=
Finish non-lab side of minimal trust benchmarking
Commit backport benchmarking, review permitting
Tweak microinstance in reaction to lab work
More Juno image work
More runtime anomaly work
=Availability=
Off from this Friday, back for three days from Monday 4th April
Return to ARM on Thursday 7th April
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10)
- Resolved 50% of thumb2 failures
- Resolved issues with overlapping registers and not setting
condition codes
- Wrote compile only test cases that pass validation
* TCWG-247 - Create Validation Job to run on GCC Trunk Commits (2/10)
- Investigation into Python API for discovering when Jenkins builders
are idle
* Linaro connect recovery day (2/10)
* Misc meeting (1/10)
== Next week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names
- Resolve remaining thumb2 issues
* TCWG-247
- Create prototype implementation
= Progress ==
* Day off (2/10)
- After Connect, recuperating, jet lagging
* EuroLLVM (6/10)
- Flying Wed to Barcelona, attending conference
- Back on Saturday
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
- Planning for a bigger team (git, Jenkins, infrastructure)
* Sick on Monday [2/10]
# Progress #
* AArch64/ARM linux syscall for process record. [2/10] TCWG-532
ARM patch (fixing the register for syscall arg pass) is committed.
Canonicalize ARM syscall patch is posted for review.
* Support range stepping on arm-linux. [4/10] TCWG-545
Preparatory patches fixing bugs when "single step the instruction
branch to itself" are being reviewed. Pedro thinks my patches may
not work in some rare cases, and I spend some time writing the case
and prove it won't happen.
* Misc [2/10]
** file expense,
** upstream patch review,
# Plan #
* TCWG-532
* TCWG-545
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.03 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn234210 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn234210
* Backport of [Bugfix] [AArch64] [Linaro #1994] Disable
pcrelative_literal_loads with fix-cortex-a53-843419
* Backport of [Bugfix] [AArch64] [Linaro #2123] Fix dependency of gcc-plugin.h
* Backport of [Bugfix] [AArch32] PR target/62554 target/69610 Fix for ARMv3
* Backport of [Bugfix] [AArch32] PR target/69161: Don't ignore mode
when matching comparison operator in cstore-like patterns
* Backport of [AArch32] Enable instruction fusion of AES instructions
on ARM for Cortex-A53 and Cortex-A57
* Backport of [AArch64] Add missing return in aarch64_internal_mov_immediate
* Backport of [AArch64] Enable instruction fusion of dependent AESE;
AESMC and AESD; AESIMC pairs
* Backport of [AArch64] Fix installed plugin headers for aarch64, m68k and c6x
* Backport of [AArch64] GCC 6 regression in vector performance. - Fix
vector initialization to happen with lane load instructions
* Backport of [AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
* Backport of [Testsuite] [AArch64] add check for aarch64 in
check_effective_target_section_anchors
* Backport of [Testsuite] Print markers to stderr to avoid races with
sanitizer output
* Backport of [Misc] Fix ChangeLog for 233518
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
== Progress ==
o BKK16 remote (5/10)
* Followed TCWG sessions
* Extended validation:
- worked with Kugan
- implemented job for native validation
o GCC dev. (4/10)
* Remote validation sanitizing:
- iterate on the output pattern fix
- testing a fix for stderr/stdin ordering issue
* Gave some support on __sync builtins, preparing a fix for armv8.1
o Misc (1/10)
* Various meetings
== Plan ==
o GCC 5 branch merge, and 2016.03 snapshot
o Continue on-going tasks
Port to microinstance - TCWG-432 [17/10]
* Investigating difference between LAVA and 'desktop Juno' runtimes
** Some of this was down to piles of /dev/console output - redirecting
to file improved SPEC build time by 75%!
** Some cases make sense, others remain unexplained
** Might just go away if we update the Juno image
* Wrote up how to do benchmarking for minimal-trust cases
** Needs both lab and development work
* Merged another large tranche of changes back to benchmarking branch
** Microinstance more or less functional, main instance benchmarking
seems unbroken
** But some more tweaks to make as Lab work happens
* Prepared backport benchmarking for merge
Misc [3/10]
=Plan=
* Submit backport benchmarking for review
* Tweak uinstance in reaction to lab work
* Implement the non-lab side of minimal-trust benchmarking
* Return to looking at Juno image generation
* Look some more at LAVA/desktop runtime differences
* Implement small improvements, if time
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Resolved thumb2 failures
- Negdi2 was not generating instruction to set condition codes
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (1/10)
- Created new patch using new predicate that matches arm and thumb2
constraints
- Received approval to GCC 7 stage 1
* Bugzilla 70014 - [ARM] Predicate does not match constraint
(*subsi3_carryin_const) (1/10)
- Fix checked into trunk
* Linaro Connect meetings (5/10)
== Next week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names
- Create compile only test cases and re-run validation testing
- Post new patch upstream
Hey,
Regarding the GCC ABI 5 issue, I was wondering what's the policy
behind updating packages on stable updates for both Debian and Ubuntu.
Our time frame is a bit constrained, and we definitely will have to
take some hard decisions in the next six months, so I'd like to
understand everything that is at stake before I have my own opinion.
LLVM has a 6 month major cycle, releasing around February / August.
Major releases are allowed to break the ABI. Major breakages need one
release warning period.
Ubuntu has a 6 month release cycle, around April / October. IIUC,
major releases are allowed to have new versions of packages, but
updates for the next few years have to keep within the same major
release.
Debian has a -1 years release cycle (heh), and has the same major /
minor policy, which makes it a lot harder to update major versions.
However, I believe unstable is still not closed, nor will be in August
this year, so updating to LLVM 3.9 will not be a problem, but it will
mean users will have to wait a bit more to get a working LLVM.
The time frame is then:
3.8.0 released March (without the fix)
Ubuntu X released April
3.9.0 releases August (hopefully with a fix)
Ubuntu X+1 released October
Debian freezes ??
LLVM 3.8.1 ??
If we don't back-port GCC ABI 5 into 3.8.1, Ubuntu users will not have
the fix ever, unless you *can* update to 3.9.0 in August.
Ubuntu X+1 will be fine using 3.9, as will Debian after August, unless
you guys freeze before that.
I believe both Debian and Ubuntu have a trunk-based LLVM package for
experimental use only, and it would be bad, but not completely broken,
to recommend users to use that meanwhile.
If Debian freezes *before* 3.9.0 is out, or if Ubuntu can't update to
3.9.0 on April's release, then we'll have a strong reason to back-port
the change to 3.8.x. If not, even though it will be uncomfortable for
users until August, the argument is not that strong and will be hard
to get it through.
Any comments? Ideas? Does any of that make sense?
cheers,
--renato
Hi,
I have been comparing the stock gcc 5.2 and the Linaro 5.2 (Linaro GCC
5.2-2015.11-1) and have noticed a difference with the __sync
intrinsics.
Here is the simple test case
--- cut here ---
int add_int(int add_value, int *dest)
{
return __sync_add_and_fetch(dest, add_value);
}
--- cut here ---
Compiling with the stock gcc 5.2 (-S -O3) I get
---------
add_int:
.L2:
ldaxr w2, [x1]
add w2, w2, w0
stlxr w3, w2, [x1]
cbnz w3, .L2
mov w0, w2
ret
---------
Wheras with Linaro gcc 5.2 I get
---------
add_int:
.L2:
ldxr w2, [x1]
add w2, w2, w0
stlxr w3, w2, [x1]
cbnz w3, .L2
dmb ish
mov w0, w2
ret
---------
Why the extra (unnecessary?) memory barrier?
Also, is it worthwhile putting a prfm before the ldaxr. EG
add_int:
prfm pst1strm, [x1]
.L2:
ldaxr w2, [x1]
See the following thread
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html
All the best,
Ed
== Progress ==
o GCC dev. (7/10)
* Remote validation sanitizing:
- fixed last issues in dejagnu patch and submitted it uptsream
- 2 more cleanup/fix dejagnu patches submitted and merged upstream
- proposed a fix/workaround for the output pattern issues (>400
failures removed with this patch)
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Try to follow connect remotely
o Extended validation work
== Progress ==
* GCC bugs:
- #2073 tried to reproduce it with a manually-built toolchain. No luck
* GCC validation:
- added support to choose simulated cpu (different from --with-cpu)
* GCC:
- completing Neon intrinsics tests, to prepare cleanup
* Validation:
- small improvements
* Misc (conf calls, meetings, emails, ...)
== Next ==
Remote Connect
== Progress ==
* Support (5/10)
- Working on PR17193
- Continue review on D17141
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- Connect preparations
- GCC ABI 5 discussions
- Assessing Swift calling convention impact ARM back-end
- Interviews
# Progress #
* TCWG-545, Handle "branch-to-self" instruction in single stepping.
[5/10] Patches are posted upstream for review.
* TCWG-532, one patch is committed and one patch is posted for review.
[2/10]
* Tweak ARM process record. [2/10]
Two patches are pushed in. Many test fails are fixed.
* FSF patches review. [1/10].
# Plan #
* Linaro Connect.
--
Yao
Hi,
I have just switched to gcc 5.2 from 4.9.2 and the code quality does seem to have improved significantly. For example, it now seems much better at using ldp/stp and it seems to has stopped gratuitous use of the SIMD registers.
However, I still have a few whinges:-)
See attached copy.c / copy.s (This is a performance critical function from OpenJDK)
pd_disjoint_words:
cmp x2, 8 <<< (1)
sub sp, sp, #64 <<< (2)
bhi .L2
cmp w2, 8 <<< (1)
bls .L15
.L2:
add sp, sp, 64 <<< (2)
(1) If count as a 64 bit unsigned is <= 8 then it is probably still <= 8 as a 32 bit unsigned.
(2) Nowhere in the function does it store anything on the stack, so why
drop and restore the stack every time. Also, minor quibble in the
disass, why does sub use #64 whereas add uses just '64' (appreciate this
is probably binutils, not gcc).
.L15:
adrp x3, .L4
add x3, x3, :lo12:.L4
ldrb w2, [x3,w2,uxtw] <<< (3)
adr x3, .Lrtx4
add x2, x3, w2, sxtb #2
br x2
(3) Why use a byte table, this is not some sort of embedded system. Use
a word table and this becomes.
.L15:
adrp x3, .L4
add x3, x3, :lo12:.L4
ldr x2, [x3, x2, lsl #3]
br x2
An aligned word load takes exactly the same time as a byte load and we
save the faffing about calculating the address.
.L10:
ldp x6, x7, [x0]
ldp x4, x5, [x0, 16]
ldp x2, x3, [x0, 32] <<< (4)
stp x2, x3, [x1, 32] <<< (4)
stp x6, x7, [x1]
stp x4, x5, [x1, 16]
(4) Seems to be something wrong with the load scheduler here? Why not
move the stp x2, x3 to the end. It does this repeatedly.
Unfortunately as this function is performance critical it means I will
probably end up doing it in inline assembler which is time consuming,
error prone and non portable.
* Whinge mode off
Ed
== Progress ==
o GCC dev. (7/10)
* Remote validation sanitizing:
- Implemented and tested a pure dejagnu fix (the actual
implementation works fine for GCC but might be an issue in a different
context, a cleaner fix almost done)
- Found a latent issue in GCC profiling test harness
* ARM and AArch64 backends LRA cleanup:
- Looked at the remaining artifacts, will prepare a patch for GCC 7
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Finalize and submit dejagnu fix
Port to microinstance - TCWG-432 [7/10]
* Merged last few months of development back to benchmarking branch
* Restored support for multiple targets per builder
* Updated builder landed, altered jobs to work with it
** Removed assumption that host filesystem is non-persistent
** Stacked up test runs for the weekend
Transfer secret management to LAVA [1/10]
* LAVA jobs now use a within-LAVA key to access sources
Misc [2/10]
* Unsuccessful fiddling with heat-monitoring tools on Juno
* Usual background of mail and meetings
=Plan=
* Fallout from weekend test runs
** Some failure is going on, need to investigate
* Update docs and Jenkins configs w.r.t. last week's activity
* Further investigation on a couple of LAVA issues that are causing me pain
** Un-deserializable bundles
** Inaccessible image reports
* Continue assessing target stability/looking at inconsistent results
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (6/10)
- Tested and posted SImode and DImode patch upstream
- Feedback recommended supporting thumb2 in addition to arm architectures
- Patch to support thumb2 fails on all thumb architectures;
investigating failures
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (2/10)
- Created new bug, developed and successfully tested patch
- Fix posted upstream
* Bugzilla 70014 - [ARM] Predicate does not match constraint
(*subsi3_carryin_const) (1/10)
- Created new bug and patch
* Misc (1/10)
== Next week ==
* Bugzilla 69663 - Cleanup by merging patterns using mode iterators,
submit upstream
* Bugzilla 70008 - Respond to upstream comments as appropriate
* Bugzilla 70014 - Post patch and respond to upstream comments
* Travel to Linaro Connect beginning March 3rd
== This Week ==
* LTO (6/10)
- TCWG 528:
a) reduced test-case for the case when decl node gets visited multiple times
b) updated patch not to walk artificial record decls (typeinfo
objects) as per Richard's suggestion.
submitted upstream, waiting for review.
- benchmarking: Aarch64 SPEC2006-int benchmarks complete
- looked at pr57703
- Slides
* setting up perf on chromebook (2/10)
- perf doc
- got perf running on chromebook by manually building it and set of
(clumsy) workarounds.
- perf annotate shows no output and perf stat shows "not supported" for almost
all entires except "page faults"
- will give a try to dual boot chrubuntu on chromebook
* half-day sick leave (1/10)
- doctor's appointment for eye inflammation
* Misc (1/10)
- Meetings
== Next Week ==
- LTO
- tcwg-310
- look at jenkins tutorial in collaborate wiki
== Progress ==
* Support (4/10)
- Updating patch D17141 for Darwin, resubmitting, discussions.
- Understanding PR21778, may need changes to SLP
- Benchmarking some scheduler choices for A17
* Release (1/10)
- 3.8.0 RC3 validation
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- Sifting through CVs, interviews, etc.
# Progress #
* Support range stepping on arm-linux. TCWG-518. [5/10]
Post patch series about "the thread is stepping over breakpoint but
it spawns child thread". The fix is OK but the test case changes are
being reviewed.
The more I test my range stepping patches, the more existing bugs I
find. Looking at the bug "software single step the instruction
branch to self."
* AArch64 linux syscall for record/replay. TCWG-532. [1/10]
Patch is out for review.
* Fix some ARM reverse debugging bugs. TCWG-183. [1/10]
Patch is pushed in. The original implementation wasn't carefully
reviewed, so I am sure there are bugs somewhere else.
* Patch review on arm tracepoint support. [1/10]
One patch is approved but I insist that another patch should be done
in generic part instead of ARM specific part, but the author wants do
it in ARM specific part because he things it is simpler.
* Misc [2/10]
** Go through the Linux kernel awareness GDB patches quickly, the first
reaction is "split your patch, please".
** Go to London to collect my passport.
# Plan #
* Support range stepping on arm-linux. TCWG-518.
* TCWG-167, TCWG-532.
* Prepare for the Linaro Connect travel.
--
Yao
Hi All,
Does linaro distributes arm-gcc as a pre-built static tool chain
distribution? If yes, where can i download them from. Please point me some
location from where i can download.
--
Thanks & Regards,
M.Srikanth Kumar.
Bug with compiler flag handling - (no ticket) [2/10]
* Coremark-Pro was ignoring compiler flags
* Fixed that, made flag handling consistent across all benchmarks
Release benchmarking via Jenkins - TCWG-348 [1/10]
* Seems to work with test workload
Port to microinstance - TCG-432 [3/10]
* Looked at some inconsistent results
* Worried that one of the Junos may be sick, but unproven for now
Backport benchmarking via Jenkins - TCWG-352 [1/10]
* Finished 'general benchmarking' job
* Switched backport job to build/test cross-compilers
* Recent backport results bundles are corrupted, unable to work out why
Document benchmarking infrastructure - TCWG-496 [1/10]
* Documented Jenkins interface
Misc [2/10]
=Plan=
If updated builder becomes available, convert uinstance job to use it
Continue assessing target stability/looking at inconsistent results
Rework LAVA scripts to permit multiple targets per builder
Hi all,
I download the pre-built toolchain for one of our armv6 board.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
After plug it into Yocto as an external toolchain, it failed to install it
correctly.
../meta-linaro/meta-linaro-toolchain/recipes-devtools/external-linaro-toolchain/
external-linaro-toolchain.bb, do_install
| DEBUG: Executing shell function do_install
| cp: cannot stat
`/opt/gcc-linaro-arm-none-eabi-4.8-2014.04_linux/arm-none-eabi/libc/lib/*':
No such file or directory
Any suggestion?
Thanks,
Joel
== This Week ==
* LTO (5/10)
- TCWG-528:
a) addressed Richard's comments.
b) investigating timeout with my patch for g++.dg/torture/pr31863.C
c) using hash_map to prevent decl from getting visited more than
once prevents the issue
d) patch: http://people.linaro.org/~prathamesh.kulkarni/increase-struct-align.diff
- Slides: mostly prepared, few tidbits (and demos) remaining
- Benchmarking: couple more failures due to my silly mistakes, now in progress.
* TCWG-310 (1/10)
- started to look at loop peeling with perf
* Public Holiday (2/10)
- Shiv Jayanti
* Misc (2/10)
- Meetings
- Committed r233426
- Looked at PR69766 caused due to r232622
== Next Week ==
- LTO: TCWG-528, benchmarking, slides
- TCWG-310
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
My patches causes some regressions but my patches just expose the
existing problem in GDBserver. Fix them and post patches upstream.
* Linaro connect. [2/10]
Go to London for visa application.
* GDB 7.11 release. No issues from my side. The tentative date of
release is Feb 26th.
* Fix GDB reverse debugging tests failures.
** Add more test cases, TCWG-183/TCWG-174. [2/10]
** Fix syscall handling in reverse debugging on ARM and AArch64.
TCWG-532/TCWG-167. [2/10]
# Plan #
* Support range stepping on arm-linux. Continue.
* Fix GDB reverse debugging tests failures. Continue.
* Review upstream patches.
* Go to London to collect my passport.
--
Yao
== Progress ==
* Validation
- AArch64 bare metal validation fixed. Patches waiting approval
- noticed a few failures caused by timeouts and failure to download
testcases. Maybe we are causing too much load on the builders/testers
* Connect preparation
- thoughts on extended validation
* GCC
- upstream monitoring, reported a couple a of regressions
- a few backports
- target attributes backport. Still having problems with our branch
* Misc (conf calls, meetings, emails, ....)
== Next ==
Holidays most of next week
Hi Toolchain Group,
I am trying to study the effect of loop buffer size on loop unrolling & the
way gcc (aarch64) handles this.
To my understanding, Loop Buffer is like i-cache which contains pre-decoded
instruction that can be re-used if branch instruction loopbacks to an
instruction
which is still present in the buffer. For example, in Intel’s Nehalem loop
buffer size is 28 u-ops. In LLVM compiler, it seems LoopMicroOpBufferSize
is for the same purpose.
However, I could not find any parameter/variable inside config/aarch64
representing loop buffer size. I am using Linaro gcc 5.2.1
[Question]
1. Is there any example inside aarch64 (or in general) which uses the loop
buffer size in loop unrolling decision? If yes, could you please mention
the relevant files or code section?
2. Otherwise any guidance/input on adding this support in aarch64 backend
assuming architecture has the loop buffer support.
[My Experiments/Code Browsing]
I have collected following information from code browsing. Please correct
if I missed or misunderstood something.
TARGET_LOOP_UNROLL_ADJUST - This target hook return the number of times a
loop can be unrolled.
This can be used to handle the architecture constraint such number of
memory references inside a loop e.g. ix86_loop_unroll_adjust() &
s390_loop_unroll_adjust().
On the same note, can this be used to handle loop buffer size too?
Without above hook, in loop-unroll.c parameters like
PARAM_MAX_UNROLLED_INSNS (default 200), PARAM_MAX_AVERAGE_UNROLLED_INSNS
(default 80) decides the unrolling factor. e.g. nunroll = PARAM_VALUE
(PARAM_MAX_UNROLLED_INSNS) / loop->ninsns;
In config/aarch64.c, I found align_loops variable in
aarch64_override_options_after_change() function.
I guess this an alignment done before starting the loop header in the
executable. This should not play any role in loop unrolling. Right?
So any guidance on how we can instruct aarch64 backend to utilize loop
buffer size in deciding the loop unrolling factor?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
== Progress ==
LLDB development
-- Handling aggregate types return values on arm-linux-gnueabihf ABI.
Patch review and committed upstream. [TCWG-228] [1/10]
-- Debugging of stepping issues on chromebook (arm hard float ABI)
[TCWG-230] [2/10]
-- Progress on vector return values and aggregate types return values
with vector elements. [TCWG-531] [2/10]
-- Started work on complex return values and aggregate types return
values with vector elements. [TCWG-531] [2/10]
-- Started writing test cases handling complex and vector return
values and aggregate types return values with vector and complex
elements. [TCWG-531] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Finish work on complex return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on vector return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on test cases handling complex and vector return
values. [TCWG-531]
Port to microinstance - TCWG-432 [2/10]
* Better reporting/error trapping in dispatch scripts
* Some back and forth with Lab about builder implementation
* Started assessing target stability
* Fixed a few bugs in reporting/bundle generation
Document benchmarking infrastructure - TCWG-496 [2/10]
* All done apart from Jenkins interface
* Need to finish Jenkins interface first...
Generate graphs for benchmarking - TCWG-268 [1/10]
* Generate a bunch of filters and charts to track Coremark-Pro
* Wrote up what I learned about LAVA's reporting interface
EEMBC benchmarks - (no ticket) [2/10]
* Checked over what we had, decided it was probably complete
* Imported to our repos
* Wrote up what I know about this
* Moved Coremark-Pro into its own repo
** Broke some code that had worked by coincidence
** Fixed it
Misc
* Usual meetings/mail/etc
* Some fun with what turned out to be a known bug in the
linaro-media-create now used in main LAVA instance
* Educated guess as to why Jenkins-triggered jobs produced no bundle
** Raised a ticket
** Think I know how to fix on my side
=Plan=
If updated builder becomes available, convert uinstance jobs to use it
Test release benchmark job
Finish backport benchmarking
Document Jenkins interface
Assess target stability
More image reports in microinstance
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Successfully tested SImode add, sub, and neg overflow patterns
- Developed DImode addv and subv patterns
- Debugging failures in DImode overflow patterns
* TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10)
- Made changes corresponding to upstream review
- Rebased to latest trunk
- Resolved issues with new test cases
- Fixed formatting and style issues
- Resubmitted upstream for final review
- previous review gave conditional support for GCC 7
- Successfully retested
- One remaining expected failure on targets with wide add support
(including aarch64)
- Plan to file a upstream bugzilla
* Misc (1/10)
* Vacation (4/10)
== Next week ==
* Bugzilla 69663 - Debug and resolve DImode pattern failures
* Bugzilla 69008 - Restart investigation
== Progress ==
BUGS (8/10)
- PR69708:
* Posted a patch to fix.
- PR69589:
* Posted a patch to fix.
- PR66726:
* Omitted the patch bu that triggered a bootstrap failure for ppc64.
Reverted the patch and looking into it.
- Misc (2/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This Week ==
* LTO/IPA (8/10)
- TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-*
- Submitted patch upstream to add entry for aarch64 to target-supports.exp
- Experimenting with Kugan's ipa-vrp prototype
- Had a look at ipa-comdat
- Connect slides
* benchmarking (1/10)
- issues with deployment (TICKET-259)
- Using Bernie's workaround for the above issue
* Misc (1/10)
- Meetings
== Next Week ==
- LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements.
- Investigate tcwg-310 with perf
- Finish connect slides
== Progress ==
* Conference (2/10)
- More EuroLLVM paper reviews, discussions
* Support (5/10)
- Looking at PR16275 (review D17141)
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- Buildbots broken, bisects, debugging
- Defining and posting Job ad (wanna work with us?)
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
Preparatory patches are pushed in. Patches are being tested.
* Linaro connect. [3/10]
** Slides are done.
** Collect documents for visa application.
* GDB 7.11 release. TCWG-509. [1/10]
Release branch is created. Discuss on issue related to big endian,
but ARM is the only user of that code.
* Patch review, especially arm tracepoint support. [2/10].
# Plan #
* TCWG-518, upstream patches if tests are OK.
* TCWG-172, continue look at test parity between arm and x86_64.
* Go to London on Wed for visa application.
--
Yao
Hi Linaro Toolchain Group,
I have a question on the ldr instruction selection in the aarch64 backend.
Could someone help me in this regards, please?
I am trying to allow only type A instructions while disabling the type B.
Type A example: ldr x4, [x20,x1] ---> allow
Type B example: ldr x1, [x9,x3,lsl #3] ---> disable
Experiment/My Understanding -
aarch64_classify_address() returns true if rtx X is a valid address. If
allow_reg_index_p=true then it calls aarch64_classify_index().
aarch64_classify_index() identify the address mode of second operand (op1)
and accordingly calculate the shift.
If shift=0 then type A is generated otherwise Type B will be generated.
Thus if (shift != 0) then I am returning 'false' from
aarch64_classify_index().
-------------------------patch---------
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info
*info, rtx x,
if (GET_CODE (index) == SUBREG)
index = SUBREG_REG (index);
+ if (shift != 0)
+ return false;
if ((shift == 0 ||
(shift > 0 && shift <= 3
&& (1 << shift) == GET_MODE_SIZE (mode)))
---------------------------------------
Result -
Before change
ldr x0, [x13,x0,lsl #3]
After Change
lsl x1, x1, #3
ldr x0, [x15,x1]
Question -
How the returning 'false' from aarch64_classify_index() is resulting in the
selection of type A versus type B?
I could not find the function which is taking the decision based on return
from aarch64_classify_address().
Could someone please explain this process or point me to the relevant files
or code?
Please correct me if my understanding is wrong.
Thanks in advance for your time and patience.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.02 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn233233
* Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt
instructions as unconditional
* Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624
* Backport of [Bugfix] [AArch32] PR target/69403: Bug in
thumb2_ior_scc_strict_it pattern
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add
patterns for QImode and HImode comparison with zero
* Backport of [Bugfix] [AArch64] PR target/69176
* Backport of [Bugfix] PR target/69175
* Backport of [Bugfix] PR tree-optimization/67781
* Backport of [AArch32] Remove neon_reinterpret, use casts
* Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support
* Backport of [AArch64] Avoid emitting zero immediate as zero register
* Backport of [AArch64] Fix jit crash on aarch64
* Backport of [AArch64] Fix -mcpu/arch=native support for LSE
* Backport of [AArch64] Handle compare of zero_extract form of
TST-immediate in rtx costs
* Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs
* Backport of [AArch64] Properly reject invalid attribute strings
* Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h
* Backport of [Testsuite] [AArch32] Fix
gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0
* Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure
when running with -march or -mcpu
* Backport of [Doc] Remove outdated text from lto.texi
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Automated release benchmark Jenkins job - TCWG-348 [2/10]
* Drafted a job, it succeeds in dispatching to the uinstance
* Needs testing
Port to microinstance - TCWG-432 [5/10]
* Almost entirely fixing up the CPU2006 -> LAVA reporting
* Should now be able to report CPU2000 results as well
Misc [3/10]
* Mail/meetings/etc
* Connect slides
=Plan=
If builder is available, convert uinstance jobs to use it
Test release benchmark job
Produce image reports in microinstance
Attempt to finish backport benchmarking
Actually finish documentation
== Progress ==
LLDB development
-- Committed patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228]
-- Finished work on handling aggregate types return values on
arm-linux-gnueabihf ABI. [TCWG-228] [5/10]
-- Submitted single and double precision handlers for upstream review.
[TCWG-228]
-- Started work on vector return values and aggregate types return
values with vector elements. [TCWG-228] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
Public Holiday [2/10]
-- Friday 5th February 2016
== Plan ==
LLDB development
-- Update and commit aggregate type return values on
arm-linux-gnueabihf ABI patch.
-- Investigate issues while stepping over library functions on
arm-linux-gnueabihf
-- Further work on vector return values on arm-linux-gnueabihf ABI
== Progress ==
o Connect slides (2/10)
* Undefined behavior (slides and review)
o GCC dev. (5/10)
* Remote testing sanitizing: found a solution in dejaGNU and GCC
implementation and test ongoing
* Analysed and closed PR69590
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Continue on GCC testsuite
o FSF branch merge and 2016.02 snapshot
== This Week ==
* TCWG-319 (1/10)
- Updated patch and re-posted, queued for stage-1
- Regression with armeb for -fvect-cost-model=cheap
* TCWG-528 (1/10)
- speculatively increase alignment for global structs with arrays.
* Backports (3/10)
- committed backport: 232688
- r232631 (partially?) reverts 232330
- modified script to follow git log <file>
* benchmarking (2/10)
- 464.h264ref triggered ICE for -O3 -mfloat-abi=hard -mfpu=neon,
reduced it (PR69282)
- Benchmarking tcwg-310 on SPEC2006 - +0.10%
- Benchmarking INT SPEC2k6 for aarch64 without LTO complete.
* Slides (2/10)
- Read doc and created outline for most of slides,
- expect to be mostly complete by next week
* Misc (1/10)
- Meetings
== Next Week ==
- LTO benchmarking and slides
- TCWG-528
== Progress ==
- LTO and TCWG480 (5/10)
* Started testing with the prototype patch
* Still trying to figure out what is the best way to set_range_info
based on IPA
* i.e., how to find the SSA_NAME initialized with PARM_DECL
- Misc (5/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This week ==
* Backports (1/10)
- 232493 - Committed to Linaro branch
- 232727 - Committed to Linaro branch
- 232414 - Committed to Linaro branch
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10)
- Implemented SImode add, sub, and neg overflow patterns
- add overflow patterns pass testing
- debugging failures in subv overflow patterns
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Personal days on February 8th and 9th
* Resolve bugzilla 69663 subv issues and work on DImode patterns
* Bugzilla 69008 - continue investigation
* Investigate test case failure on backport 232600
* Off from Mon. to Wed. [6/10]
# Progress #
* TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10]
First do software single step in GDBserver side.
* TCWG-509. GDB 7.11 release. [1/10]
PR 19474, review Keith's patch. The patch is OK to mainline, but we
don't want to take risk shipping this patch to 7.11 release.
* Misc, register to Linaro Connect BKK16, and get clarifications on my
visa to Thailand. [1/10]
* Monitor the discussions on kenernel awareness upstreams, and comment
on the display of CPSR register.
# Plan #
* Finish Linaro Connect slides.
* TCWG-509. Anything needed for GDB 7.11 release.
* TCWG-518.
--
Yao
== Progress ==
* Validation
- disabled Auto Backport Engine until the patch selection
is improved to avoid saturating the builders with undesirable
builds.
- AArch64 bare metal validation (bug #2011). Submitted a patch
for dejagnu aarch64-fv8.exp, and one for our builders schroots.
Will need another patch, in ABE.
- timeout issues: no progress
* Misc (conf calls, meetings, emails, ....)
- internal discussions
== Next ==
* Validation
- debug timeout issues
- cleanup
== Progress ==
LLDB development
-- Submitted patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228] [5/10]
-- float and double types handled in above patch did some more
investigation for handling structs [TCWG-228] [2/10]
-- Collecting LLDB status data, ran testsuite on different hardware
and minor investigation of fails and xfails [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Update float/double return value patch after review and commit upstream
-- Submit a fix for handling structs as return types on arm-linux-gnueabihf
Public Holiday
-- Friday 5th February 2016
== Progress ==
- Public Holiday (2/10)
- LTO and TCWG480 (4/10)
* Started with a prototype for VRP
* Experimenting with simple test cases
- Misc (4/10)
* gcc/bug list
* LTO and Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
Hi,
My ARM target runs glibc 2.13 and I am having a hard time finding a
linaro toolchain for it. It seems like all the ones I have found ship with
glibc 2.15 (even old ones).
Where can I find the binaries for a linux toolchain that targets armhf
with glibc 2.13?
Thanks in advance
Port to microinstance - TCWG-432 [4/10]
* Went a few more rounds with the race condition, finally nailed it
* Tidied up transfer of Coremark results to LAVA
* Added metadata to LAVA results
* Sketched some charts using LAVA reporting
* Improved runtime benchmark logging
Benchmarking infrastructure documentation - TCWG-496 [2/10]
* Most everything drafted, some docs finished
Controlled image builds - TCWG-360 [2/10]
* Reached a better understanding of what a hwpack is
* Generated a few images, none of them booted
Misc [2/10]
=Plan=
Benchmarking-102 slides for Connect
Finish documentation
Backport benchmarking
If builder shows up in microinstance, evaluate stability of its Junos
o Teaching activity (3/10)
== Progress ==
o Infra/Validation (1/10)
* A couple of patches for release script.
o GCC dev. (2/10)
* Remote testing sanitizing: still digging.
o Misc (4/10)
* Various meetings (usual ones and internal ones)
* Backports reviews
== Plan ==
o Continue on GCC testsuite and opened cards.
Port to microinstance - TCWG-432 [2/10]
* More fallout from attempts to fix race condition
* Began cleaning job submission YAML
Controlled image builds - TCWG-360 [1/10]
* (Re)learned how to generate images from hwpack + filesystem
Struck down by flu [7/10]
== This week ==
* Backports (3/10)
- 232493 - Unrelated aarch64 failure and non-thumb asan test on
aarch32 big endian
- 232600 - All tests pass
- 232727 - unrelated non-thumb test failure
asan/deep-thread-stack-1.c asan/deep-thread-stack-1.c)
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (3/10)
- Development halted due to submission of related patch by Richard
Henderson:
- https://gcc.gnu.org/ml/gcc-patches/2016-01/txt0WQOxpo0_5.txt
- Began implementation of aarch32 related patch
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Additional code is being generated in default abi case with
structure alignment equal to 8
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Create new bugzilla for aarch32 to implement overflow standard names
and continue implementation
* Bugzilla 69008 - continue investigation
* Work on backports as necessary
== This Week ==
* PR43721 (1/10)
- Submitted upstream.
- GIMPLE parts approved by Richard, wants someone else to approve
rtl-expansion bits.
* benchmarking (1/10)
- benchmarking tcwg-310 on cortex-a53, cortex-a57, r1-a12, cortex-a17
- submitted job for INT benchmarks for SPEC2006 for aarch64
* backports (2/10)
- r232688 automated backport build failed for aarch64-linux-gnu on
tcwg-backport-gerrit:
Unrecognized macro 'GERRIT_PATCHSET_REVISION' in '#664-
${GERRIT_PATCHSET_REVISION,length=8}'
Build successful on tcwg-backport-maxim
- r232737, r232631 have at least 4 dependencies.
- wrote bare bones script to find dependencies for revision
* ccp (2/10)
- enhancement to hoist stmt thru phi with all constant args
- patch: http://people.linaro.org/~prathamesh.kulkarni/ccp-mov.diff
- rejected by Richard, since PRE handles this case when it's
trivially profitable and phiprop does similar transform. In general,
it's not profitable to have this transform included.
* Public Holiday (2/10)
* Misc (2/10)
- Meetings
- Slides: short & long term activities
== Next Week ==
- PR43721: look at using define_expand instead of hook, add test-cases
and few nits
- tcwg-319 - analyse with perf
- LTO INT benchmarking for arm, aarch64 and x86
- LTO Slides
# Progress #
In general, GDB mainline is in a good state. All known bugs are fixed,
but still have some patches pending for review. The release can be
created after these pending patches are in.
* Fix fail in gdb.base/interrupt-noterm.exp. TCWG-517. Done. [2/10]
* Fix fail in gdb.fortran/vla-value.exp. TCWG-521. Done. [1/10]
* PR 19474. [3/10]
Tried different approaches, but still cause regression.
Fortunately get the right maintainer involved. Will discuss with
him on this bug next week.
* Range stepping doesn't work on arm-linux, which slows down stepping
over a line of source. TCWG-518. [2/10]
* Prepare slides for Linaro Connect. [2/10]
# Plan #
* Off on Mon. to Wed.
* Linaro connect slides.
* Thailand visa.
* Other issues on GDB 7.11 release, if any.
--
Yao
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2 Release Archives.
http://releases.linaro.org/components/toolchain/binaries/5.2-2015.11-2/http://releases.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2/
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2
The Linaro GCC 5.2 2015.11-2 binary toolchain release respin is built from
the Linaro GCC-5.2-2015.11-2 release source archive. The Linaro
GCC-5.2-2015.11-2 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-2-rc1 release-candidate.
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2-rc1
Release-Candidate Archives.
http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-2-rc1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2-r…
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at http://
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
Hi!
When using the linaro-4.9-2015.05 toolchain on the Linux master and on Linux stable releases
I am seeing a build issue below when using the allyesconfig. This does not seem to occur on the 5.2 tool chain.
We cannot move to 5.2 tool chain for our releases as they are based on 4.9.
LD init/built-in.o
arch/arm/kernel/built-in.o:(.text.fixup+0x1d4): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1e0): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1ec): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
drivers/built-in.o: In function `combiner_handle_cascade_irq':
:(.text+0x834): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0x868): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_type':
:(.text+0xad0): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xb10): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_raise_softirq':
:(.text+0xc8c): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock_irqsave' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xdc8): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock_irqrestore' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_affinity':
:(.text+0xefc): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xf78): additional relocation overflows omitted from the output
make: *** [vmlinux] Error 1
Please advise to how to resolve this issue within the 4.9 Linaro tool chain
Dan
--
------------------
Dan Murphy
== Progress ==
* Support (5/10)
- Bug triage: reviewing the 300+ bugs on ARM
- remaining 220 bugs are all still pertinent
* Release (2/10)
- Woes due to GCC ABI change may delay 3.8.0 release
- Tested on both ARM and AArch64 with old environment, all green.
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- EuroLLVM, FOSDEM preparations, ARM sync
o Teaching activity (2/10)
== Progress ==
o Linaro GCC (2/10)
* Delivered 2016.01-1 Snapshot respin with fix for Linaro PR #2001
* Gave some support on backports
o Infra/Validation (1/10)
* Compared ABE master results.
o GCC dev. (2/10)
* Identified the way testcases are uploaded on the remote target in
cross validation as the root cause of validation instabilities. Digging
into GCC .exp files and DejaGNU to fix it cleanly.
o Misc (3/10)
* Various meetings
* Start a backport/validation document
== Plan ==
o Continue backports/validation document
o Continue on the ongoing cards opened
== Progress ==
LLDB development
-- Debugging of return value related issue coming up on chromebook ARM
[TCWG-228] [2/10]
-- Setup of Arm testing on AArch64 using chroot on highkey [TCWG-231] [1/10]
-- Investigation of failures when setting watchpoint on vector
variables [TCWG-231] [4/10]
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- Travel for Thailand visa application
== Plan ==
LLDB development
-- Try a fix of return value related issue coming up on chromebook ARM
-- Submit fix for failures when setting watchpoint on vector variables
-- Mark triaged failures with xfail decorators and bug numbers.
== Progress ==
LLDB development
-- Triage testsuite failures on AArch64 highkey [TCWG-231] [5/10]
-- Triage testsuite failures on chromebook (armel) [TCWG-228] [3/10]
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Documents preparation for Thailand visa
== Plan ==
LLDB development
-- Create chroots for armhf and armel testing on AArch64 highkey board
-- Investigate ABI related issues when returning values on armel and armhf
-- Further bug triage and mark triaged failures with xfail decorators
and bug numbers.
Miscellaneous
-- Travel for Thailand visa application submission.
== This Week ==
* PR43721 (4/10)
- Patch review from Jim
- Bootstrapped and tested on x86, cross-tested with arm-linux-gnueabi
- Looking at regressions with arm-linux-gnueabi
- Wrote test-cases
* Benchmarking (2/10)
- lto spec2006 benchmarking
* Backport (1/10)
- Build successful for r232440 and r232442, failed for r232442
* PR24293 (1/10)
- Addressed comments by Marek and committed to trunk
* Misc (2/10)
- Meetings
- PR69133 - Fixed by Honza. Instead of gating on
lto_file_data as I did in my patch, gating on gimple_has_body_p()
was more suitable.
- Awaiting upstream response for tcwg-319
- Connect Slides outline, read doc on tree-ssa propagation and lto
plugin driver.
== Next Week ==
Continue ongoing tasks
== Progress ==
* Validation
- no progress in timeout issues: still didn't manage to access the logs
- 1st backport workshop successful in the team. We can increase
the difficulty for the next time :)
- initial prototype (naive) of an auto-backporter (using backflip)
when the patch are selected for inclusion
* GCC
- TCWG-485/PR68620: patch under review
- TCWG-484/target attributes testsuite fixes: committed.
- bug #1994: provided woraround to kernel team.
Related to GCC PR63304. Working on a further patch
for GCC.
* Misc (conf calls, meetings, emails, ....)
== Next ==
* Validation:
- debug timeout issues
- extended validation
* GCC:
- bug fixing
# Progress #
* Fix the arm software single step regression. [3/10]. Done.
* TCWG-503 Done.
* TCWG-491, have a patch to avoid GDB crash. Patch is pending for
review.
* TCWG-517. [2/10]
Fix fail in gdb.base/interrupt-noterm.exp. Patch is posted.
* TCWG-514. [3/10]
Fix new fails in foll-exec.exp and foll-vfork.exp. Patch is pending
for review.
* TCWG-509, GDB 7.11 release. [2/10]
GDB is in a good shape to create 7.11 branch except PR 19474. Go
through GDB test results and no ARM or AArch64 specific issues.
# Plan #
* TCWG-509, GDB 7.11 release.
* Upstream patch review.
--
Yao
The Linaro Toolchain Working Group (TCWG) announces the 2016.01-1
snapshot of the Linaro GCC 5 source package.
This package is a respin of 2016.01 source package and contains a fix
for Linaro bugzilla’s PR #2001:
* [AArch64] ICE in final_scan_insn on aarch64-linux-gnu.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/
Original release notes from 2016.01 source package can be find below:
---------------------------------------------------------------------------------------------------------------------
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.01 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.02
stable [1] quarterly release.
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn232321
* Fixes Linaro Bugzillas: #1982, #1980
* Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split
* Backport of [BugFix] [AArch32] PR target/68214: Delete
IP-reg-clobbering call-through-mem patterns
* Backport of [BugFix] [AArch32] PR target/68390
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add
compare-of-zero_extract pattern
* Backport of [BugFix] [AArch64] PR target/68696 FAIL:
gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1
* Backport of [BugFix] PR rtl-optimization/68381
* Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1
instructions
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane
and vqrdmlsh_lane
* Backport of [ARMv8.1] [AArch32] Add patterns for new instructions
* Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1
* Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1.
* Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests
* Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time
* Backport of [AArch32] Add attribute for compatibility with ARM pipeline models
* Backport of [AArch32] Fix vector TYPE_MODE in streaming-out
* Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions
* Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1
Adv.SIMD instructions
* Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD
* Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh
* Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane
* Backport of [AArch64] Documentation fix for -fpic
* Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] Fix a few failures with LSE enabled
* Backport of [AArch64] Improve add immediate expansion
* Backport of [AArch64] Improve comparison with complex immediates
followed by branch/cset
* Backport of [AArch64] Rework ARMv8.1 command line options
* Backport of [AArch64] Update patterns to support FP zero
* Backport of [AArch64] Use aarch64_sync_memory_operand in
atomic_store<mode> pattern
* Backport of [AArch64] Use vector wide add for mixed-mode adds
* Backport of [Misc] Only restrict pure simplification in mult-extend
subst case, allow other substitutions
* Backport of [Testsuite] [AArch64] Skip big-endian as well for
gcc.target/aarch64/got_mem_hoist_1.c
* Backport of [Testsuite] Make stackalign test LTO proof
* Backport of [Testsuite] Testcase for PR rtl-optimization/68381
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Folks,
I'd like to know the general opinion on this:
https://llvm.org/bugs/show_bug.cgi?id=23529
>From past experience, and my limited point of view, it seems that the
GCC community decided to change the ABI, plotted some runes, conjured
up a broken implementation (whose bugs people will exploit and GCC
will end up keeping them) and pushed distros to follow.
I don't know how much distros were involved in the original design.
Did they request the changes? Or was that an internal change? How do
you guys get to decide when to break the world?
I also don't know how will be your policy towards the bugs that people
started "using". Are you going to force them moving to a more sane
implementation (by issuing compiler/linker errors) or are you going to
support as legacy for the decades to come?
Is there a detailed document describing all the changes, and is the
GCC implementation following that to the letter, or are there still
bugs in the current version? I'm not talking about an email thread,
but an actual document on GCC's docs pages.
All I know is that people in the Clang community waited until GCC's
implementation was stable, but somehow Debian based distros started
moving as if there was something unholy about the previous ABI, and
we've been getting segmentation faults on Hello World!
I don't know much about the changes myself, nor I was involved in the
discussion, but this is now a major pain for release 3.8.0 and I
thought it would be better if I sent an email to Linaro folks and
members (which form most of the ARM GNU developers) instead of going
on the main lists.
That also gives me a bit more freedom to be more candid. I wouldn't
send those questions as they are to the GCC/binutils lists, or people
would kill me. I don't mean any of them as an offence, they are
genuine questions from someone that is not on top of that issue.
cheers,
--renato