- linaro-toolchain - lists.linaro.org

[ANNOUNCE] Linaro GCC 5 2015.12 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.12 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn231642 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn231642 * Backport of [Bugfix] [AArch32] 1/4 PR63870 Add qualifiers for NEON builtins * Backport of [Bugfix] [AArch32] 2/4 PR63870 Mark lane indices of vldN/vstN with appropriate qualifier * Backport of [Bugfix] [AArch32] 3/4 PR63870 Remove error for invalid lane numbers * Backport of [Bugfix] [AArch32] 4/4 PR63870 Remove xfails for ARM targets * Backport of [Bugfix] [AArch32] PR67305, tighten neon_vector_mem_operand on eliminable registers * Backport of [Bugfix] [AArch32] remove unused variable * Backport of [Bugfix] [AArch64] PR 63304 Fix issue with global state * Backport of [Bugfix] [AArch64] PR63304 Handle literal pools for functions > 1 MiB in size * Backport of [Bugfix] [AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check * Backport of [Bugfix] [AArch64] PR rtl-optimization/67218 * Backport of [Bugfix] PR 56036 fix typo in doc * Backport of [Bugfix] PR rtl-optimization/68236: Exit early from autoprefetcher lookahead if not in haifa sched * Backport of [Bugfix] PR tree-optimization/68234 Improve range info for loop Phi node * Backport of [AArch32] 1/4 Change GET_MODE_INNER to always return a non-void mode * Backport of [AArch32] 2/3 Make if_neg_move and if_move_neg into insn_and_split * Backport of [AArch32] 2/4 Control the FMA steering pass in tuning structures rather than as core property * Backport of [AArch32] 3/3 Expand mod by power of 2 * Backport of [AArch32] 3/4 Replace the pattern GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m) * Backport of [AArch32] 4/4 Fix - Introduce new inline functions for GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION * Backport of [AArch32] 4/4 Introduce new inline functions for GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION * Backport of [AArch32/AArch64] 2/2 Add a new Cortex-A53 scheduling model * Backport of [AArch32] Add missing v8a cpus to the t-aprofile file * Backport of [AArch32] Fix checking RTL error in cortex_a9_sched_adjust_cost * Backport of [AArch32] Fix for testcase after r228661 * Backport of [AArch32] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs * Backport of [AArch32] libgcc: include crtfastmath * Backport of [AArch32] Unified assembler in ARM state * Backport of [AArch64] 1/2 Give AArch64 ROR (Immediate) a new type attribute * Backport of [AArch64] 1/2 Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G * Backport of [AArch64] 1/2 Rename test source file for reuse * Backport of [AArch64] 1/3 Add the option -mtls-size * Backport of [AArch64] 1/3 Expand signed mod by power of 2 using CSNEG * Backport of [AArch64] 2/2 Implement -fpic for -mcmodel=small * Backport of [AArch64] 2/2 Implement TLS IE for tiny model * Backport of [AArch64] 2/3 Rename SYMBOL_TLSLE to SYMBOL_TLSLE24 * Backport of [AArch64] 3/3 Implement local executable mode for all memory model * Backport of [AArch64] Add initial qualcomm support * Backport of [AArch64] Add missing entries in iterator vwcore * Backport of [AArch64] Cleanup whitespace in aarch64.c * Backport of [AArch64] Cortex-A57 Choose some new branch costs * Backport of [AArch64] Define TARGET_UNSPEC_MAY_TRAP_P * Backport of [AArch64] Distinct costs for sign and zero extension * Backport of [AArch64] Do not ICE after apologising for -mcmodel=large -fPIC * Backport of [AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives * Backport of [AArch64] Don't transform sign and zero extends inside mults * Backport of [AArch64] Fall back to -fPIC if no support of -fpic in binutils * Backport of [AArch64] Fix for branch offsets over 1 MiB * Backport of [AArch64] Fix ICE on (const_double:HF 0.0) * Backport of [AArch64] Fix insn types * Backport of [AArch64] Fix output assembly bug under TLSIE ILP32 * Backport of [AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immediate * Backport of [AArch64] Mark GOT related MEM rtx as const to help RTL loop IV * Backport of [AArch64] Properly handle simple arith+extend ops in rtx costs * Backport of [AArch64] Rename SYMBOL_SMALL_GOTTPREL to SYMBOL_SMALL_TLSIE * Backport of [AArch64] Restrict pic-small.c by new test directive * Backport of [AArch64] Tighten direct call pattern for sibcall to repair -fno-plt * Backport of [AArch64] Tighten direct call pattern to repair -fno-plt * Backport of [Testsuite] [AArch32] Fix thumb2-slow-flash-data.c failures * Backport of [Testsuite] [AArch32] Switch ARM to unified asm * Backport of [Testsuite] [AArch64] Add more TLS local executable testcases * Backport of [Testsuite] [AArch64] Check branch types for noplt testcases * Backport of [Testsuite] [AArch64] Fix gcc.target/aarch64/vclz.c * Backport of [Testsuite] [AArch64] Fix some target attribute inlining tests for -fPIC * Backport of [Testsuite] [AArch64] Restrict got_mem_hoist_1.c with small memory model * Backport of [Testsuite] [AArch64] Skip tiny and large code model on gcc.target/aarch64/pic-small.c * Backport of [Testsuite] Add --param sra-max-scalarization-size-Ospeed to sra-12.c * Backport of [Testsuite] Fix target selector in gcc.target/i386/noplt-[1234].c testcases * Backport of [Misc] Allow sibcalls in no-PLT PIC * Backport of [Misc] Eliminate PLT stubs for specified external functions via -fno-plt * Backport of [Misc] Fix for ICE with -g on testcase with incomplete types * Backport of [Misc] Fix memory leak and wrong invariant dependence computation in IVOPT * Backport of [Misc] Improve rtl loop inv cost by checking if the inv can be propagated to address uses * Backport of [Cleanup] [AArch32/AArch64] fix ChangeLog * Backport of [cleanup] [AArch32] Remove uses of CONST_DOUBLE_HIGH/LOW * Backport of [Cleanup] [AArch64] Delete aarch64_symbol_context which is not used * Backport of [cleanup] [AArch64] Move iterators from atomics.md to iterators.md * Backport of [cleanup] [AArch64] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOW * Backport of [Doc] [AArch64] Document several AArch64-specific test directives Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 4 months

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[ACTIVITY] 7 Nov - 11 Nov 2015

by Kugan

== Progress == - LTO (8/10) * Looked at ipa-cp * Read LTO papers * Started with ipa-vrp experiment * Reproduced spec2006 issues - Misc (2/10) * gcc/bug list * LuaJIT == Plan == * LTO

10 years, 4 months

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[ACTIVITY] 7th-11th December

by Bernie Ogden

Centralised benchmark source - TCWG-354 [6/10] * Understood CoremarkPro run rules/behaviour better * Experimented with shortening runs while still giving meaningful results * Cleaned up build/run scaffolding Port to microinstance - TCWG-432 [1/10] * Got access to microinstance, learned a bit about SSL in the process Backport benchmarking - TCWG-352 [2/10] * Fixed 'build with sysroot' code for current deliverable shape * Fixed a problem with multiple manifests =Plan= Review, test, debug build-triggers-benchmark job Finish off Coremark Pro integration Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) More support for SPEC-on-Android? =Absence= Holiday 22nd December - 1st January

10 years, 4 months

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[ACTIVITY] 7 Nov - 11 Nov 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (2/10) - Another iteration. * LTO (4/10) - Building spec with different combinations of -flto -flto-partition -flto-compression-level - Builds cleanly on AArch64, ICE's on ARM for 447.dealII with -flto - Looked at segfault with 483.xalanpack * TCWG-319 benchmarking (1/10) - fp benchmark results on: r1-a12: -0.04 % cortex-a53: -0.09 % cortex-a57: -0.14% - int benchmarks completed running for reference revision on cortex-a15 - int benchmarks with-patch runnning on cortex-a15 * TCWG-310 benchmarking (1/10) - r1-a12: 0.11% - Benchmark jobs failed on a53, a57. * Misc (2/10) - Submitted patch to fix building 450.soplex - Looked at how to write ipa pass, ipa-pure-const and ipa-cp. - Meetings == Next Week == - tcwg-319, tcwg-310 benchmarking - tcwg-72 - LTO

10 years, 4 months

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[Weekly] 07-11 December 2015

by Michael Collison

== This week == * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (7/10) - Implemented signed and unsigned add, subtract, and multiply overflow standard patterns - Investigated testing of overflow patterns * Misc (3/10) - Conference calls - Misc ARM Housekeeping - Lost connectivity due to old ARM Unix VPN Client == Next week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 - Minor code update to address upstream comment * Vacation until rest of year

10 years, 4 months

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[ACTIVITY] 7-11 December 2015

by Christophe Lyon

== Progress == * GCC (4/10) - pr68620 (fp16 transfers in big-endian mode) - checking regressions observed on trunk - had to revert my cleanup patch for target attributes tests, not sure how to handle all possible combinations of options/defaults * Validation (1/10) - small improvements in reporting * Misc (conf calls, meetings, emails, ...) (3/10) * Internal training (2/10) == Next == * Validation * GCC: bug fixes/cleanup

10 years, 4 months

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[ACTIVITY] Dec 7 - 11, 2015

by Yao Qi

* One day off on Wed. [2/10] # Progress # * Enable gdb core file tests when testing remotely, TCWG-171. I've almost had the conclusion that corefile remote testing can't be done due to limitations in dejagnu and nfs mount testing infrastructure. Need to write them down. [2/10] * Mutli-arch follow-up work, teach AArch64 GDBserver understand ARM breakpoint instructions. TCWG-460. Done. [3/10] * Review ARM GDBserver software single step patch V7. Almost OK, except some small things. [2/10] * Misc, meeting, email, [1/10] # Plan # * TCWG-424, Draft a fix for the fail in random-signal.exp. * TCWG-156, GDB test parity between AArch64 and X86_64. * One day off on Wed. or Fri. Planned absence: * Dec 24-Jan 3. -- Yao

10 years, 4 months

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[ACTIVITY]

by Renato Golin

== Progress == * Holiday (2/10) * Release (1/20) - 3.7.1 Final, all green * Maintenance (5/10) - Fixing PR25720 - Bug cleaning: PR18921, PR13259, PR13138, PR12926, PR17963, PR18187, PR22692 - Checked strided vectorizer on ToT, EEMBC 2x geomean! * Background (2/10) - Code review, meetings, discussions, general support, etc. - Power cut, restarting bots, testing TK1, plans, etc. == Holidays == I'll be back on the 5th Jan.

10 years, 4 months

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[ACTIVITY] Nov 30 - Dec 4, 2015

by Kugan

== Progress == - PR66726 (2/10) * Testing a patch - PR63586 (2/10) * Posted a patch * Revised the patch based on testing - LuaJIT (2/10) * Setup nginx * Still haven't figured out how to use mongodb with nginx (config required). - Misc (2/10) * gcc/bug list * LTO - sick (2/10) == Plan == * bug reports * LTO

10 years, 4 months

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incomplete .arch specifiers with latest Linaro gcc5 patches on armv8?

by Robert Schiele

Hi, when working with the Linaro patches I found that a particular commit breaks our aarch64 kernel build. The patch in question is that one: commit be09330da9d0777c4a58568d137e3f8a3dbe0a0b Author: Yvan Roux <yvan.roux(a)linaro.org> Date: Tue Oct 27 21:18:19 2015 +0100 One of the things it attempts to change apparently is moving the .arch specifiers in the assembler file from a global scope to individual functions. What also happens though is that they seem to lose some information after that transformation. I observed that when building arch/arm64/crypto/aes-ce-cipher.c from the Linux kernel. This code contains inline assembly like this: static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[]) { struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm); struct aes_block *out = (struct aes_block *)dst; struct aes_block const *in = (struct aes_block *)src; void *dummy0; int dummy1; kernel_neon_begin_partial(4); __asm__(" ld1 {v0.16b}, %[in] ;" " ld1 {v1.2d}, [%[key]], #16 ;" " cmp %w[rounds], #10 ;" " bmi 0f ;" " bne 3f ;" " mov v3.16b, v1.16b ;" " b 2f ;" "0: mov v2.16b, v1.16b ;" " ld1 {v3.2d}, [%[key]], #16 ;" "1: aesd v0.16b, v2.16b ;" " aesimc v0.16b, v0.16b ;" "2: ld1 {v1.2d}, [%[key]], #16 ;" " aesd v0.16b, v3.16b ;" " aesimc v0.16b, v0.16b ;" "3: ld1 {v2.2d}, [%[key]], #16 ;" " subs %w[rounds], %w[rounds], #3 ;" " aesd v0.16b, v1.16b ;" " aesimc v0.16b, v0.16b ;" " ld1 {v3.2d}, [%[key]], #16 ;" " bpl 1b ;" " aesd v0.16b, v2.16b ;" " eor v0.16b, v0.16b, v3.16b ;" " st1 {v0.16b}, %[out] ;" : [out] "=Q"(*out), [key] "=r"(dummy0), [rounds] "=r"(dummy1) : [in] "Q"(*in), "1"(ctx->key_dec), "2"(num_rounds(ctx) - 2) : "cc"); kernel_neon_end(); } Now without this patch the compiler behaved like the following. It was invoked with: aarch64-linux-gnu-gcc -Wp,-MD,arch/arm64/crypto/.aes-ce-cipher.o.d -nostdinc -isystem /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/bin/../lib/gcc/aarch64-linux-gnu/5.2.1/include -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/include -Iarch/arm64/include/generated/uapi -Iarch/arm64/include/generated -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include -Iinclude -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/include/uapi -Iarch/arm64/include/generated/uapi -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include/uapi -Iinclude/generated/uapi -include /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/include/linux/kconfig.h -I/var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/crypto -Iarch/arm64/crypto -D__KERNEL__ -mlittle-endian -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -std=gnu89 -mgeneral-regs-only -fno-delete-null-pointer-checks -O2 --param=allow-store-data-races=0 -Wframe-larger-than=2048 -fno-stack-protector -Wno-unused-but-set-variable -fno-omit-frame-pointer -fno-optimize-sibling-calls -fno-var-tracking-assignments -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -Werror=strict-prototypes -Werror=date-time -DCC_HAVE_ASM_GOTO -Werror -march=armv8-a+crypto -D"KBUILD_STR(s)=#s" -D"KBUILD_BASENAME=KBUILD_STR(aes_ce_cipher)" -D"KBUILD_MODNAME=KBUILD_STR(aes_ce_cipher)" -c -o arch/arm64/crypto/aes-ce-cipher.o /var/fpwork/rschiele/crossbuild/builds/aarch64-linux-gnu/linux-next/srcdir/src/linux/arch/arm64/crypto/aes-ce-cipher.c As a result it created a file for the assembler with the global .arch armv8-a+fp+simd+crypto at the beginning of the file. After the patch it created individual .arch armv8-a at individual places. It is not clear to me, why the extensions (fp+simd+crypto) got lost. Is that intended, such that the code needs special adaption for inline assembly using those extensions or is that loss of extensions a bug of that patch? Greetings! Robert

10 years, 4 months

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[ACTIVITY] Week 48

by Yvan Roux

== Progress == o Linaro GCC (6/10) * More backports * Compared our various flavor of validation results * Looked at bug reports and mailing list questions on our last snapshot. o Upstream work (2/10) * Continue on sanitizing gfortran testsuite o Misc (2/10) * Various meetings * Discussed benchmarking infra with Bernie == Plan == o GCC 5.3 branch merge o Continue on-going tasks o Tuesday Off

10 years, 4 months

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[ACTIVITY] 30th November - 4th December

by Bernie Ogden

Holiday [2/10] Port to microinstance - TCWG-432 [1/10] * Set up reporting for CPU2006 * Learned how to generate metadata, but not how to use it Trigger benchmarks on backports - TCWG-352 [2/10] * Figured out the rough shape * Created, didn't test, rough implementation TCWG-354 [3/10] * Build/run scaffolding for CoreMark Pro * Working for manual runs Misc [2/10] * Input validation for dispatcher script * Meeting with Ade on LAVA benchmarking * Meetings/mail/etc =Plan= Review, test, debug build-triggers-benchmark job Check CoreMark Pro run configuration, enable for automatic runs Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) More support for SPEC-on-Android?

10 years, 4 months

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[ACTIVITY] 30 Nov to 4 Dec 2015

by Prathamesh Kulkarni

* TCWG-72 (2/10) - Added new target hook to generate target-specific divmod libfunc - Builds cleanly now on x86_64, arm and arm-linux-gnueabihf - Sent to tcwg list for review * LTO spec2k6 build (2/10) - Built speck26 with LTO * Target hook (4/10) - Completed with ASM_OUTPUT_LABEL_REF - In progress - SIZE_ASM_OP to data hook, ASM_OUTPUT_SIZE_DIRECTIVE, ASM_OUTPUT_MEASURED_SIZE * Benchmarking (1/10) - tcwg-319: Job in progress for fp benchmarks with patch - tcwg-310 (loop peeling): Submitted job for running 252.eon - Both the jobs failed due to lab downtime, need to be re-run. - Received job template from Bernie for running benchmarks on cortex-a15. * Misc (1/10) - Meetings == Next Week == - Continue benchmarking spec2k6 with LTO - Look at bugs exposed by speck2k6 LTO build - Benchmarking tcwg-319, tcwg-310

10 years, 4 months

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[Weekly] 30 November - 4 December 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (0/10) - No comments/review upstream will ping for update * TCWG-316 - Exploit vector multiply by scalar instructions (4/10) - Code improvements will require standard name for vectorizer and new patterns - On hold until GCC 6 is released * Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard names (3/10) - Initial investigation * Bugzilla 68532 - [ARM] Incorrect code result on arm big endian (2/10) - Investigation into understanding how vectorizer represents lanes vs arm big endian back end - Solution suspended until I can coordinate with Charlie * Misc (1/10) - Conference calls == Next week == * Bugzilla 68543 - Implement add and subtract overflow operations and test * TCWG-317 - Ping upstream and respond to upstream feedback * Bugzilla 68532 - Coordinate with Charlie

10 years, 4 months

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[ACTIVITY]

by Renato Golin

== Progress == * Ill (4/10) * Support (1/10) - Bugzilla issues (PR20490, PR24635, PR24350, PR20025, PR25720, PR25722) * Benchmarks (1/10) - Checking some previous benchmark results on A57 * Buildbots (2/10) - Getting AArch64 full bot back to rotation, since it's stable now - Re-enabling libc++ prototypes on local master - Bisecting broken test-suite - Another power cut in the office sent all the bots down... :( * Background (2/10) - Code review, meetings, discussions, general support, etc. - Validating some old sanitizer bugs - FOSDEM admin

10 years, 5 months

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[ACTIVITY] 30th Nov - 04th Dec

by Yao Qi

* One day off on Monday. # Progress # * Answer ST questions about supporting multi-arch with ST jtag probe. [1/10] * TCWG-171, Enable gdb core file tests when testing remotely, [3/10]. Ongoing. * Run gdb.base/sizeof.exp with board having gdb,noinferiorio. Done. [1/10] * TCWG-460, mutli-arch follow-up work, teach AArch64 GDBserver understand ARM breakpoint instructions. Patch is approved. [2/10]. * TCWG-424, fail in gdb.base/random-signal.exp. [1/10] Root cause is identified, need to figure out how to fix it in next step. * Review ARM GDBserver software single step patch V4. # Plan # * TCWG-171, TCWG-156, TCWG-424. * Review ARM GDBserver software single step patch V5, which should be the final version, I hope. -- Yao

10 years, 5 months

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[ACTIVITY] Nov 30- Dec 4, 2015

by Christophe Lyon

== Progress == * Validation - a few cleanup patches in the comparison scripts - contribute to debug of ptys allocation problems: the tests pass when executed outside of our schroots. - improvements in the reports from the validation done in the ST Compute Farm - reported a few regressions * GCC - cleanup patch for target attributes tests, - pr68620 (fp16 transfers in big-endian mode) * Misc (conf calls, meetings, emails, ....) == Next == * Validation: monitoring, improvements * GCC: bug fixes, cleanup

10 years, 5 months

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GNU GCC development plan and its interaction with Linaro

by Virendra Kumar Pathak

Hi Linaro Toolchian Group, I am new to GCC development and have some basic question on its development process. Could you please give some insight on below questions. (Apology if they are very trivial). I have read https://gcc.gnu.org/develop.html If I am correct, gcc trunk is on gcc 6.0.0 (stage 3) at present and will becomes 6.0.1 (regression fix only) in January 2016. gcc 6.0.1 will be released as gcc 6.1.0 in April, 2016 and from there onwards gcc 6 release branch will start. However, There is also a gcc 5 branch in parallel whose current version is 5.2.1 and will be released as gcc 5.3 soon. Hopefully gcc 5.3 would be the last release in gcc 5 series. (Please correct me if I am wrong). [Questions] 1. What is the difference between experimental(gcc 6.0.0 stage 3) & gcc release branch (gcc 5.2.1)? Is there any rule which decides which changes will go where? In case, I have some patches for new aarch64 processor at present, in which branch these changes would be merged (assuming they passes reviews)? 2. How is the subversion of release branches are decided? Is it correct to say that there will be always 3 subversion of any release branch (e.g. gcc 5.1, gcc 5.2 & gcc 5.3)? 3. What is the working model between GNU GCC and Linaro GCC? Does Linaro directly accept patches? or they need to go to GNU GCC first? Thanks in advance for your time. with regards, Virendra Kumar Pathak -- with regards, Virendra Kumar Pathak

10 years, 5 months

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Fwd: Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch

by Robert Schiele

Keeping linaro-toolchain in the loop. Robert ---------- Forwarded message ---------- From: Robert Schiele <rschiele(a)gmail.com> Date: Thu, Dec 3, 2015 at 4:44 PM Subject: Re: Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch To: Yvan Roux <yvan.roux(a)linaro.org> Hi Yvan, On Thu, Dec 3, 2015 at 1:25 PM, Yvan Roux <yvan.roux(a)linaro.org> wrote: > This fix on gcc-5-branch doesn't apply on Linaro 5 branch, because we > have backported trunk revision 222624 (which renames maybe_fma to > coumpound_p) into it. So, our branch as the same code as trunk one > regarding aarch64_rtx_costs. Do you experiment any issues related to > this change ? No issues. This was just a theoretical thought and through our CI build I learned exactly what you just told me the hard way now. Sorry for the noise. Robert

10 years, 5 months

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Bug: Linaro ABE abe.sh doesn't allow timeout > 10 seconds

by Christopher Roberts

abe.sh in the ABE framework accepts a parameter to set the wget timeout when it fetches snapshots (default 10s); however that parameter has an upper threshold of 10 seconds (condition at line 996 only sets timeout to specified value if < 11). Is this intentional? It seems like it would make more sense to give it a floor instead of a ceiling or perhaps not limit the range of potential values at all. Best regards, Chris Roberts

10 years, 5 months

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why ld.so in arm-linux-gnueabihf- toolchains search so many paths ?

by Barry Song

hi guys, sorry maybe my question is stupid as i am not a toolchain guy. i have no idea why ld.so search so many paths. for example, put "-rpath" with /home/cnb1szh/test in a simple test program. then during dynamic linking at runtime, we get the below linking debug information: 30693: find library=libmytest.so [0]; searching 30693: search path=/home/cnb1szh/test/tls/v7l/neon/vfp:/home/cnb1szh/test/tls/v7l/neon:/home/cnb1szh/test/tls/v7l/vfp:/home/cnb1szh/test/tls/v7l:/home/cnb1szh/test/tls/neon/vfp:/home/cnb1szh/test/tls/neon:/home/cnb1szh/test/tls/vfp:/home/cnb1szh/test/tls:/home/cnb1szh/test/v7l/neon/vfp:/home/cnb1szh/test/v7l/neon:/home/cnb1szh/test/v7l/vfp:/home/cnb1szh/test/v7l:/home/cnb1szh/test/neon/vfp:/home/cnb1szh/test/neon:/home/cnb1szh/test/vfp:/home/cnb1szh/test (RPATH from file ./hello) 30693: trying file=/home/cnb1szh/test/tls/v7l/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/v7l/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/tls/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/v7l/libmytest.so 30693: trying file=/home/cnb1szh/test/neon/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/neon/libmytest.so 30693: trying file=/home/cnb1szh/test/vfp/libmytest.so 30693: trying file=/home/cnb1szh/test/libmytest.so but we don't have /home/cnb1szh/test/tls/, /home/cnb1szh/test/v7l/, /home/cnb1szh/test/vfp/, /home/cnb1szh/test/neon/, why does the ld.so search so many paths? -barry

10 years, 5 months

3
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Lost upstream patch in merge from gcc-5-branch to linaro/gcc-5-branch

by Robert Schiele

Hi, I found that with the merge commit ac19ac6481a3f326d9f41403f5dadab548b2c8a6 Author: Yvan Roux <yvan.roux(a)linaro.org> Date: Wed Sep 16 10:57:42 2015 +0200 Merge branches/gcc-5-branch rev 227732. Change-Id: I2f59904b28323b1c72a8cf1bd62c9e460d95bcea the following branch that was within merge range on gcc-5-branch was lost on the linaro branch: commit b45a5cf7c1544f95578e823e25402b58fb3fbedd Author: nsz <nsz@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Tue Aug 4 16:49:54 2015 +0000 Fix broken backport patch. gcc: Backport from mainline: 2015-08-04 Szabolcs Nagy <szabolcs.nagy(a)arm.com> PR target/66731 * config/aarch64/aarch64.c (aarch64_rtx_costs): Fix NEG cost for FNMUL. (aarch64_rtx_mult_cost): Fix MULT cost with -frounding-math. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@226588 138bc75d-0d04-0410-961f-82ee72b054a4 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 691874b..eebc9c3 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5250,7 +5250,7 @@ aarch64_rtx_mult_cost (rtx x, int code, int outer, bool speed) which case FNMUL is different than FMUL with operand negation. */ bool neg0 = GET_CODE (op0) == NEG; bool neg1 = GET_CODE (op1) == NEG; - if (compound_p || !flag_rounding_math || (neg0 && neg1)) + if (maybe_fma || !flag_rounding_math || (neg0 && neg1)) { if (neg0) op0 = XEXP (op0, 0); Since this was a fix to the patch one commit ahead and also merged in the same operation and there is no further comment on why this fix was skipped, may I assume that this happened by accident and you probably want to fix that merge flaw by reapplying the missing patch? Or is there an information detail I don't have that requires this fix to be skipped on the Linaro branch? Robert

10 years, 5 months

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[ACTIVITY] 23rd - 27th November

by Bernie Ogden

Controlled image builds - TCWG-360 [1/10] * Tried, failed to generate bootable images Jenkins benchmarking job - TCWG-348 [5/10] * Jenkins job functional on kvms in main instance * Wrote job-dispatch script for non-Jenkins use cases Juno crashdump [1/10] * Struggled with, worked around network problems * Juno running, waiting for it to crash SPEC-on-Android [1/10] * Helped Qian to find root cause of a problem Misc [2/10] =Plan= Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Debug/test Jenkins job in microinstance Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) Probably more support for SPEC-on-Android

10 years, 5 months

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[ACTIVITY] 23 - 27 November 2015

by Yao Qi

# Progress # * Fix timeout in random-signal.exp. TCWG-424. Ongoing. [4/10] I know the cause of the problem but can't figure out why it can happen. Can only reproduce the fail in every 20~30 runs. * TCWG-423, support gnu vector in inferior call in AArch64 GDB. Done. [1/10] * Build native ARM and AArch64 GDB in C++. No regression in test. Done. TCWG-446. Done. [1/10]. * Fix GDB internal error in gdb.thread/watchpoint-fork.exp on AArch64. [2/10] * Upstream patches review [2/10] ** Review patches on arm gdbserver software single step V3. Some patches are approved, but V4 is also needed for the rest. ** Review all-stop on non-stop patches. ** Discuss whether we need single step in fast tracepoint. Ongoing. # Plan # * One day off on Monday. * Understand ST's jtag probe and help them to make use of multi-arch in GDB. * Look into timeout in random-signal.exp. * TCWG-156, GDB test parity between AArch64 and X86_64. * TCWG-460, follow up on the AArch64 GDBserver multi-arch work. -- Yao

10 years, 5 months

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[ACTIVITY] 23 - 27 November 2015

by Kugan

== Progress == - tree re-assoc regression (2/10) - Found a test-case to reproduce it. - working on a patch - LuaJIT issue (6/10) * Setup luajit on aarch64 and tried it * tried to reproduce nginx issue with various configs without success - LTO (1/10) * aarch64 bootstrap * ran into an uninit warning issues looking into it - Misc (1/10) * gcc/bug list == Plan == * tree re-assoc * LTO

10 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (6/10) - Trying to add ADRL support in the assembler: http://llvm.org/PR24350 * Buildbots (1/10) - Some breakages, nothing serious * Background (3/10) - Code review, meetings, discussions, general support, etc. - Working on 2016's plan

10 years, 5 months

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[ACTIVITY] Week 47

by Yvan Roux

== Progress == o Linaro GCC (4/10) * Found and backported missing dependencies * More backports o Upstream work (4/10) * Reviewed some patches * Tried to reproduced an LRA issue (fixed in the meantime) * Continue on sanitizing gfortran testsuite o Misc (2/10) * Various meetings == Plan == o Continue on-going tasks

10 years, 5 months

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[ACTIVITY] 23 - 27 November 2015

by Prathamesh Kulkarni

== This Week == * Target conversion to hook (2/10) - Completed build and test for ASM_FORMAT_PRIVATE_NAME, ASM_LABEL_OUTPUT_LABEL to hook - Converted ASM_OUTPUT_LABEL_REF to hook * Holidays (8/10) - 3 days leave and public holiday (Guru nanak Jayanti) == Next Week == - Send updated patch upstream for tcwg-72 - LTO benchmarking with SPEC for correctness on arm and aarch64 - Target hook conversion

10 years, 5 months

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[Weekly] 23-27 November 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (4/10) - Determined that big endian failure is unrelated to vaddw. - Bug filed upstream: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68532 - Sent modified patch upstream for approval with caveat related to bugzilla 68532 * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (1/10) - Code checked in upstream. TCWG-369 is complete * Misc (1/10) - Conference calls * USA Thanksgiving Holiday (4/10) == Next week == * TCWG-316 - Additional investigation * TCWG-317 - Respond to upstream feedback * Bugzilla 68532 - Investigation

10 years, 5 months

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 5.2 2015.11

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11 Release Archives. http://releases.linaro.org/components/toolchain/binaries/5.2-2015.11/ http://releases.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11 The Linaro GCC 5.2 2015.11 binary toolchain release is built from the Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 5 months

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problems in ABE's support for manifest files and multilibs

by Fred Peterson

Hello, I am trying to create gcc 4.9.x toolchains for ARM v7 and v8 based on Linaro's sources. At first Linaro's 4.9-2015.05 binary release looked suitable, but then one of my colleagues noticed that that it had an incompatibility with Red Hat Enterprise Linux 6. Linaro has decided not to fix this incompatibility (see https://bugs.linaro.org/show_bug.cgi?id=1869 ). So, I tried to work around that bug by rebuilding the toolchains myself on RHEL6 using Linaro's new ABE script. I initially tried to recreate the builds by using ABE's --manifest <manifest_file> command line option. I experienced problems with that, though, including it building gcc version 6.x instead of 4.9.x. I eventually gave up on that approach. Instead, I extracted the required branches and revisions from the manifest files and put them into ABE command line options, like this: abe.sh --target aarch64-elf --build all --parallel --dump --tarball --release fsl-2015.11.16 --set libc=newlib binutils=binutils-gdb.git~linaro_binutils-2_24-branch@a93e252ee5250dba831e54f98336b40c7210dac7 gcc=gcc-linaro-4.9-2015.05 gmp=5.1.3 gdb=binutils-gdb.git~gdb-7.10-branch@ef5fa52ac9ab68b505b52acb2d2068b366ba8bf2 mpfr=3.1.2 mpc=1.0.1 newlib=newlib.git~linaro_newlib-branch@136b66e404df41435bdec4630c0787b0bc7e7580 abe.sh --target aarch64-linux-gnu --build all --parallel --dump --tarball --release fsl-2015.11.16 --set libc=glibc binutils=binutils-gdb.git~linaro_binutils-2_24-branch@a93e252ee5250dba831e54f98336b40c7210dac7 gcc=gcc-linaro-4.9-2015.05 gmp=5.1.3 gdb=binutils-gdb.git~gdb-7.10-branch@ef5fa52ac9ab68b505b52acb2d2068b366ba8bf2 mpfr=3.1.2 mpc=1.0.1 glibc=glibc-linaro-2.20-2014.11.tar.xz abe.sh --target arm-eabi --build all --parallel --dump --tarball --release fsl-2015.11.16 --set libc=newlib binutils=binutils-gdb.git~linaro_binutils-2_24-branch@a93e252ee5250dba831e54f98336b40c7210dac7 gcc=gcc-linaro-4.9-2015.05 gmp=5.1.3 gdb=binutils-gdb.git~gdb-7.10-branch@ef5fa52ac9ab68b505b52acb2d2068b366ba8bf2 mpfr=3.1.2 mpc=1.0.1 newlib=newlib.git~linaro_newlib-branch@136b66e404df41435bdec4630c0787b0bc7e7580 abe.sh --target arm-linux-gnueabihf --build all --parallel --dump --tarball --release fsl-2015.11.16 --set libc=glibc binutils=binutils-gdb.git~linaro_binutils-2_24-branch@a93e252ee5250dba831e54f98336b40c7210dac7 gcc=gcc-linaro-4.9-2015.05 gmp=5.1.3 gdb=binutils-gdb.git~gdb-7.10-branch@ef5fa52ac9ab68b505b52acb2d2068b366ba8bf2 mpfr=3.1.2 mpc=1.0.1 glibc=glibc-linaro-2.20-2014.11.tar.xz That worked, and the resulting toolchains ran without error under RHEL6. Note that I deliberately chose to switch to glibc in the *-linux-* toolchains, whereas the manifest files had them using eglibc. At least one serious problem remained. The toolchains supported different multilibs than previous releases. For example, arm-eabi-gcc reported that it supported only three sets of libraries: $ arm-eabi-gcc -print-multi-lib .; thumb;@mthumb fpu;@mfloat-abi=hard Linaro's 2015.05 build of the toolchain gives the same output. However, previous releases of this toolchain supported a much larger set of multilibs. A build from 2014.08 reports: $ arm-none-eabi-gcc --print-multi-lib .; thumb;@mthumb v7-a;@march=armv7-a v7ve;@march=armv7ve v8-a;@march=armv8-a v7-a/fpv3/softfp;@march=armv7-a@mfpu=vfpv3-d16@mfloat-abi=softfp v7-a/fpv3/hard;@march=armv7-a@mfpu=vfpv3-d16@mfloat-abi=hard v7-a/simdv1/softfp;@march=armv7-a@mfpu=neon@mfloat-abi=softfp v7-a/simdv1/hard;@march=armv7-a@mfpu=neon@mfloat-abi=hard v7ve/fpv4/softfp;@march=armv7ve@mfpu=vfpv4-d16@mfloat-abi=softfp v7ve/fpv4/hard;@march=armv7ve@mfpu=vfpv4-d16@mfloat-abi=hard v7ve/simdvfpv4/softfp;@march=armv7ve@mfpu=neon-vfpv4@mfloat-abi=softfp v7ve/simdvfpv4/hard;@march=armv7ve@mfpu=neon-vfpv4@mfloat-abi=hard v8-a/simdv8/softfp;@march=armv8-a@mfpu=neon-fp-armv8@mfloat-abi=softfp v8-a/simdv8/hard;@march=armv8-a@mfpu=neon-fp-armv8@mfloat-abi=hard thumb/v7-a;@mthumb@march=armv7-a thumb/v7ve;@mthumb@march=armv7ve thumb/v8-a;@mthumb@march=armv8-a thumb/v7-a/fpv3/softfp;@mthumb@march=armv7-a@mfpu=vfpv3-d16@mfloat-abi=softfp thumb/v7-a/fpv3/hard;@mthumb@march=armv7-a@mfpu=vfpv3-d16@mfloat-abi=hard thumb/v7-a/simdv1/softfp;@mthumb@march=armv7-a@mfpu=neon@mfloat-abi=softfp thumb/v7-a/simdv1/hard;@mthumb@march=armv7-a@mfpu=neon@mfloat-abi=hard thumb/v7ve/fpv4/softfp;@mthumb@march=armv7ve@mfpu=vfpv4-d16@mfloat-abi=softfp thumb/v7ve/fpv4/hard;@mthumb@march=armv7ve@mfpu=vfpv4-d16@mfloat-abi=hard thumb/v7ve/simdvfpv4/softfp;@mthumb@march=armv7ve@mfpu=neon-vfpv4@mfloat-abi=softfp thumb/v7ve/simdvfpv4/hard;@mthumb@march=armv7ve@mfpu=neon-vfpv4@mfloat-abi=hard thumb/v8-a/simdv8/softfp;@mthumb@march=armv8-a@mfpu=neon-fp-armv8@mfloat-abi=softfp thumb/v8-a/simdv8/hard;@mthumb@march=armv8-a@mfpu=neon-fp-armv8@mfloat-abi=hard I found that the file that encodes this older set of multilib mappings is gcc-linaro-4.9-2015.05/gcc/config/arm/t-aprofile. Based on some comments in gcc-linaro-4.9-2015.05/gcc/config.gcc, I guessed that ABE should have configured gcc with "--with-multilib-list=aprofile", and without "--with-arch=armv7-a" or "--with-fpu=vfpv3-d16". I quickly hacked these changes into abe/config/gcc.conf like this: diff --git a/config/gcc.conf b/config/gcc.conf index 19c44ca..4cc5eaf --- a/config/gcc.conf +++ b/config/gcc.conf @@ -111,9 +111,9 @@ if test x"${build}" != x"${target}"; then default_configure_flags="${default_configure_flags} --with-tune=cortex-a9" fi if test x"${override_arch}" = x -a x"${override_cpu}" = x; then - default_configure_flags="${default_configure_flags} --with-arch=armv7-a" + default_configure_flags="${default_configure_flags}" fi - default_configure_flags="${default_configure_flags} --enable-threads=no --with-fpu=vfpv3-d16 --enable-multilib --disable-multiarch" + default_configure_flags="${default_configure_flags} --enable-threads=no --with-multilib-list=aprofile --enable-multilib --disable-multiarch" languages="c,c++,lto" ;; aarch64*-*elf) After rebuilding the toolchain, I found it had the desired older set of multilibs. I hope that this mail will help anyone who experiences similar problems. I have filed a bug report for the multilib issue. See https://bugs.linaro.org/show_bug.cgi?id=1920 . While validating the toolchains, dejagnu reports a few unexpected failures. Does the TCWG publish their validation results anywhere for comparison? That would be very helpful. Thanks, Fred Peterson Freescale Developer Tools

10 years, 5 months

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[ACTIVITY] 16-20 November 2015

by Kugan

== Progress == - Linaro bug 1900 (4/10) * Committed fix to trunk * Will propose back-port to branches after a week - Widening pass (TCWG-547) - 4/10 * Address latest review comments * Posted updated patch to the list - Misc (2/10) * Looked at LuaJIT issue * gcc/bug list == Plan == * LuaJIT * LTO

10 years, 5 months

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[ACTIVITY] Week 46

by Yvan Roux

== Progress == o Valfidation and Infra (2/10) * Some fixes in our release script * look at refactoring our publishing snapshot job o Linaro GCC (4/10) * Start backports for 2015.12 * Tracking dependencies o Upstream work (1/10) * Continue on sanitizing gfortran testsuite o Misc (3/10) * Various meetings * Internal support == Plan == o Continue on-going tasks

10 years, 5 months

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[ACTIVITY] 16th - 20th November

by Bernie Ogden

Controlled image builds - TCWG-360 [2/10] * A few more test/debug cycles with ci-loop-built image Jenkins benchmarking job - TCWG-348 [3/10] * YAML-ised Jenkins job, more test/debug cycles Juno crashdump [1/10] * Got a usable dump (via alt-sysrq-c) with latest patches plus some fiddling SPEC-on-Android [1/10] * Looked at Qian's work to date, didn't come up with any bright ideas Misc [3/10] =Plan= Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Continue debug/test of Jenkins job Create bootable image for at least 1 target, or know what the problems are Write up noise control report (if time) Set Juno off, try to get a dump of my crash Probably more support for SPEC-on-Android =Absences= 'ARM Day' next Monday (30th)

10 years, 5 months

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[Weekly] 16-20 November 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (5/10) - Blocked as I have not yet determined why the pattern fails on big endian targets * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (1/10) - Modified code based on minor code style comments * TCWG-316 - Exploit vector multiply by scalar instructions (3/10) - Discovered relevant previous RFC: https://gcc.gnu.org/ml/gcc/2013-09/msg00061.html - Coded subset of vector patterns - Debugging combine phase to determine why patterns are not being utilized * Misc (1/10) - Conference calls == Next week == - TCWG-369 - Submit modified patch upstream for final approval - TCWG-316 - Determine if rtl patterns can be used by combine - TCWG-317 - Need feedback - USA Thanksgiving Holidays (November 26-27)

10 years, 5 months

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[ACTIVITY] 16th-20th November 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (2/10) - Rebased patch - Fixed ICE for x86-gcc with -m32 following Jim's suggestions. * Target hook conversion (6/10) - Converted ASM_FORMAT_PRIVATE_NAME, ASM_LABEL_OUTPUT_LABEL, ASM_OUTPUT_LABELREF to hook * TCWG-319 (1/10) - Benchmark jobs for fp in progress on a53, a57. * Misc (1/10) - Meetings == Next Week == - Test and send updated patch upstream for tcwg-72 - TCWG-319 benchmarking on cortex-a15 - Holidays from 23-25th November (Mon-Wed).

10 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (1/10) - Bisecting breakages, testing ASAN patches * Release (1/10) - Testing 3.7.1-RC1, all green * Benchmarks (3/10) - Updating some benchmarks results, running EEMBC on HiKey - Investigating old performance reports * Background (5/10) - Code review, meetings, discussions, general support, etc. - Bootstrapping laptop - EuroLLVM, AOSP meetings - Jira farming

10 years, 5 months

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[ACTIVITY] 16-20 November 2015

by Yao Qi

# Progress # * TCWG-332, done. [1/10] Fix GDB bug on stepping over breakpoint on ARM. Patch is pushed in. * TCWG-423, patches are posted. [5/10]. Support gnu vector in inferior call in AArch64 GDB. Also correctly handle HVA (homogeneous vector aggregate) in inferior call. * TCWG-433, done. [2/10] All memory issues found by -fsanitize=address in GDB are fixed. * TCWG-447, done. [1/10] Fix GDB mainline build warnings and errors in C++ mode on ARM and AArch64. * Discussion on the approach of building GDB in C++. Need to test GDB built in C++ on both ARM and AArch64, from my side. [1/10] # Plan # * Understand ST's jtag probe and help them to make use of multi-arch in GDB. * Fix GDB internal error in gdb.thread/watchpoint-fork.exp on AArch64. * TCWG-156, GDB test parity between AArch64 and X86_64. -- Yao

10 years, 5 months

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[ACTIVITY] 16-20 November 2015

by Christophe Lyon

== Progress == * Validation (6/10) - a few improvements in the validations using the ST compute farm - thinking about appropriate ways of sharing validation reports with the GCC community without flooding gcc-testresults - moved results comparison scripts to a dedicated repo and updated Jenkins jobs accordingly * GCC (1/10) - bug #1869 / glibc dependency on RHEL6 proof of concept to force use of old memcpy but it will be much safer to build the toolchain in a suitable container with the right distro * Misc (conf calls, meetings, emails, ...) (3/10) - patches and backports reviews == Next == * Validation - continue preparation of switch, as dev-01 is now back - improve reporting * GCC: - check Neon tests cleanup - bug #1869 - look at how to send valuable reports to gcc-regression

10 years, 5 months

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ETA for glibc-linaro 2.22 ?

by Koen Kooi

Hi, We're currently running into issues with the OE builds due to OE-core having moved to 2.22. So what's the plan for glibc-linaro 2.22? -- Koen Kooi Builds and Baselines | Release Manager Linaro.org | Open source software for ARM SoCs

10 years, 5 months

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Configuration question

by Bill Fischofer

Hi, This question has arisen in the ODP project and the thought is that a 'best practices' answer would be more likely to be found on this list. We have a component that wants to make use of specialized instructions for performing CRC and/or AES computations and was wondering what is the recommended way for an application to determine whether such instructions are available in the toolchain and whether the user has overruled their use? Thanks for any insight you can provide. Bill

10 years, 5 months

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Re: [lng-odp] Runtime inlining

by Ola Liljedahl

I think there are many issues with binary compatibility beyond function inlining. An ODP application cannot expect all ODP implementations to support the same number of ODP queues or classification rules or even which classification terms (fields) are supported (efficiently/in HW) etc. Is there some kind of lowest common denominator an application should expect? Do we want to make guarantees of an ODP implementation stricter? What are the consequences of such strict functional guarantees? I think an application that requires binary compatibility over ARMv8.1 platforms should compile and link against a specific ODP SW implementation (possibly with some well-defined HW offloads where the underlying platform can provide the relevant drivers). I.e. more of a (user-space) Linux architecture than standard ODP (as influenced by OpenGL). The important binary interfaces then becomes the interfaces to these offloads/drivers. On 16 November 2015 at 14:23, Nicolas Morey-Chaisemartin <nmorey(a)kalray.eu> wrote: > > > On 11/11/2015 09:45 AM, Savolainen, Petri (Nokia - FI/Espoo) wrote: >> >>> -----Original Message----- >>> From: lng-odp [mailto:lng-odp-bounces@lists.linaro.org] On Behalf Of >>> EXT Nicolas Morey-Chaisemartin >>> Sent: Tuesday, November 10, 2015 5:13 PM >>> To: Zoltan Kiss; linaro-toolchain(a)lists.linaro.org >>> Cc: lng-odp >>> Subject: Re: [lng-odp] Runtime inlining >>> >>> As I said in the call last week, the problem is wider than that. >>> >>> ODP specifies a lot of types but not their sizes, a lot of >>> enums/defines (things like ODP_PKTIO_INVALID) but not their value >>> either. >>> For our port a lot of those values were changed for >>> performance/implementation reason. So I'm not even compatible between >>> one version of our ODP port and another one. >>> >>> The only way I can see to solve this is for ODP to fix the size of all >>> these types. >>> Default/Invalid values are not that easy, as a pointer would have a >>> completely different behaviour from structs/bitfields >>> >>> Nicolas >>> >> Type sizes do not need to be fixed in general, but only when an application is build for binary compatibility (the use case we are talking here). Binary compatibility and thus the fixed type sizes are defined per ISA. >> >> We can e.g. define a configure target (for our reference implementation == linux-generic) "--binary-compatible=armv8.x" or "--binary-compatible=x86_64". When you build your application with that option, "platform dependent" types and constants would be fixed to pre-defined values specified in (new) ODP API arch files. >> >> So instead of building against odp/platform/linux-generic/include/odp/plat/queue_types.h ... >> >> typedef ODP_HANDLE_T(odp_queue_t); >> #define ODP_QUEUE_INVALID _odp_cast_scalar(odp_queue_t, 0) >> #define ODP_QUEUE_NAME_LEN 32 >> >> >> ... you'd build against odp/arch/armv8.x/include/odp/queue_types.h ... >> >> typedef uintptr_t odp_queue_t; >> #define ODP_QUEUE_INVALID ((uintptr_t)0) >> #define ODP_QUEUE_NAME_LEN 64 >> >> >> ... or odp/arch/x86_64/include/odp/queue_types.h >> >> typedef uint64_t odp_queue_t; >> #define ODP_QUEUE_INVALID ((uint64_t)0xffffffffffffffff) >> #define ODP_QUEUE_NAME_LEN 32 >> >> >> For highest performance on a fixed target platform, you'd still build against the platform directly >> >> odp/platform/<soc_vendor_xyz>/include/odp/plat/queue_types.h >> >> typedef xyz_queue_desc_t * odp_queue_t; >> #define ODP_QUEUE_INVALID ((xyz_queue_desc_t *)0xdeadbeef) >> #define ODP_QUEUE_NAME_LEN 20 >> >> >> -Petri >> > > It still means that you need to enforce a type for all ODP implementation on a given arch. Which could be problematic. > As a precise example: the way handles are used now for odp_packet_t brings some useful features for checks and memory savings, but performance wise, they are a "disaster". One of the first thing I did was to switch them to pointers. And if I wanted a high perf linux x86_64 implementation, I'd probably do the same. > > Nicolas > _______________________________________________ > lng-odp mailing list > lng-odp(a)lists.linaro.org > https://lists.linaro.org/mailman/listinfo/lng-odp

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[ACTIVITY] 9 - 13 November 2015

by Omair Javaid

== Progress == LLDB development -- Root Google Nexus devices and read debug module configuration with kernel module [TCWG-429] [7/10] -- Figure out steps to unlock and root Nexus S -- Figure out steps to build kernel and kernel module for Nexus S -- Tried out lldb watchpoints with custom kernel on Nexus S -- Tried out reaching debug co processors without ptrace using kernel module. -- Identify mix-mode debugging problems (ARM & Thumb) [TCWG-229] [2/10] -- Ongoing Initial investigation and indentifying code areas needing changes Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == -- Root Google Nexus devices and read debug module configuration with kernel module [TCWG-429] -- Complete app and kernel module to read debug coprocessor registers. -- Try them out on remaining Android devices. -- Identify mix-mode debugging problems (ARM & Thumb) [TCWG-229] -- Further investigation and testing a mix mode application.

10 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (4/10) - Found culprit for self-hosting breakages - Bot didn't get right because of dirty builds - Moving all self-hosting bots to clean builds (~3h) - More work on MIPS patch breaking self-hosting - Several breakages and bisections - Adding first cloud (Scaleway) buildbot to local master - No NEON, so we can't replace the Chromebooks * Infrastructure (4/10) - Power cut in Cambridge Lab, no generator yet - Chromebooks fail at the time of the cut, even with the UPS batteries still holding. I'm guessing the power regulator depends on the internal battery to work (and we removed them) - Bringing all bots up, etc. - Setting up an HiKey/AMD for benchmarks (APMs are too different) - Running EEMBC and SPEC on AMD * Background (2/10) - Code review, meetings, discussions, general support, etc. - Upstreaming -meabi, which may fix builds of kernel, android, bsd - Compiling aarch64-linux-gnu-gcc by hand because Arch pkg didn't work

10 years, 5 months

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[ACTIVITY] Week 45

by Yvan Roux

o 1 day off (2/10) == Progress == o Linaro GCC (6/10) * FSF branch merge into linaro GCC 5 branch * Troubleshot various regression after the merge * Delivered GCC 5.2 2015.11 snapshot o Upstream work (1/10) * Sanitizing gfortran testsuite o Misc (1/10) * Various meetings == Plan == o Continue on sanitizing testsuite o Backports, infra, ...

10 years, 5 months

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[ACTIVITY] 9th-13th November

by Bernie Ogden

Implement LAVA jobs for microinstance - TCWG-432 [6/10] * Refactoring to permit sharing of code between uinstance & main instance, as far as possible * Further refactoring for sane submission of bundles without inserting LAVA assumptions in the wrong places * Tested as far as possible in main instance, using light hacks and fakebench Jenkins benchmarking job - TCWG-348 [1/10] * Converted pbl hacks into a sane patch for yaml-to-json.py Controlled image builds - TCWG-360 [1/10] * Submitted aarch64 filesystem build for review * Generated armhf and amd64 filesystems * Started learning how to generate hwpack Misc [2/10] =Plan= Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Create YAML definition for Jenkins benchmarking job Generate (controlled) hwpack for at least one target, or know what the problems are Write up noise control report (if time) Have another at crashdump (if time, if new kexec patches)

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[ACTIVITY] 9 - 13 November 2015

by Prathamesh Kulkarni

* TCWG-72 (3/10) - divmod transform approved by Richard - builds cleanly on arm-linux-gnueabihf, aarch64-linux-gnu - Investigating segfault with __bdi64_div.c happens when mode == DImode and libval_mode == TImode - Found another segfault on x86 with TImode, on arm TImode is not supported and compiler aborts. Perhaps we should not do the transform when mode is TImode ? - Had a look at expand_binop_twoval_libfunc(). Wrote a similar function to obtain both results but this resulted in infinite loop in emit_libcall_block_1 - Strangely the bug is reproducible only during the build and doesn't trigger when compiled with preprocessed version of bid64_div.c (passing the same set of options). - waiting for upstream comments * TCWG-319 (1/10) - Submitted jobs for fp benchmark on a53, a57 * Misc: - PR66214 appears to have gone (fixed or became latent), that was blocking firefox LTO build with trunk - PR65837 still appears to be present after r230327 * Public Holidays (6/10) - Diwali festival == Next Week == - Continue with TCWG-72, TCWG-319 benchmarking, target hook conversion - Run SPEC2k6 with LTO

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[ACTIVITY] 9-13 November 2015

by Kugan

== Progress == - Widening pass (TCWG-547) - 6/10 * Bootstrapped latest patch on ppc64-linux-gnu, aarch64-linux-gnu and x64-64-linux-gnu. * Regression testing on ppc64-linux-gnu, aarch64-linux-gnu arm64-linux-gnu and x64-64-linux-gnu. * Fixed all of the execution issues * Posted updated patch to the list - Misc (4/10) * Linaro bug 1900 * Continued Looking at LuaJIT code-base * gcc/bug list == Plan == * bug 1900 * Look at implementing LuaJIT for aarch64 * LTO

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Runtime inlining

by Zoltan Kiss

Hi, We have a packaging/linking/optimization problem at LNG, I hope you guys can give us some advice on that. (Cc'ing ODP list in case someone want to add something) We have OpenDataPlane (ODP), an API stretching between userspace applications and hardware SDKs. It's defined in the form of C headers, and we already have several implementations to face SDKs (or whathever is actually controlling the hardware), e.g. linux-generic, a DPDK one etc. And we have applications, like Open vSwitch (OVS), which now is able to work with any ODP platform implementation which implements this API When it comes to packaging, the ideal scenario would be to create one package for the application, e.g. openvswitch.deb, and one for each platform, e.g odp-generic.deb, odp-dpdk.deb. The latter would contain the implementations in the form of a libodp.so file, so the application can dynamically load the actually installed platform's library runtime, with all the benefits of dynamic linking. The trouble is that we have several accessor functions in the API which are very short and __very__ frequently used. The best example is "uint32_t odp_packet_len(odp_packet_t pkt)", which returns the length of the packet. odp_packet_t is an opaque type defined by the implementation, often a pointer to the packet's actual metadata, so the actual function call yields to a simple load from that metadata pointer (+offset). Having it wrapped into a function call brings a significant performance decrease: when forwarding 64 byte packets at 10 Gbps, I got 13.2 Mpps with function calls. When I've inlined that function it brought 13.8 Mpps, that's ~5% difference. And there are a lot of other frequently used short accessor functions with the same problem. But obviously if I inline these functions I break the ABI, and I need to compile the application for each platform (and create packages like openvswitch-odp-dpdk.deb, containing the platform statically linked). I've tried to look around on Google and in gcc manual, but I couldn't find a good solution for this kind of problem. I've checked link time optimization (-flto), but it only helps with static linking. Is there any way to keep the ODP application and platform implementation binaries in separate files while having the performance benefit of inlining? Regards, Zoltan

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[ANNOUNCE] Linaro GCC 5 2015.11 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.11 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn230068 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn230068 * Backport of [Bugfix] [AArch32] fp16 Fix PR 67624 - Incorrect conversion of float Infinity to __fp16 * Backport of [Bugfix] [AArch64] PR 66776 Add cmovdi_insn_uxtw pattern * Backport of [Bugfix] [AArch64] PR rtl-optimization/68106 LRA * Backport of [Bugfix] PR48052 fix testcase * Backport of [Bugfix] PR other/57195 * Backport of [Bugfix] PR rtl-optim/67421 Cost instruction sequences when doing left wide shift * Backport of [Bugfix] PR rtl-optimization/67103 Improve conditional select ops on immediates * Backport of [Bugfix] PR rtl-optimization/67756 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR tree-optimization/48052 IVOPTS * Backport of [Bugfix] PR tree-optimization/52563 and 62173 IVOPTS * Backport of [Bugfix] PR tree-optimization/64454 * Backport of [Bugfix] PR tree-optimization/66449 * Backport of [AArch32] 1/2 Record FPU features as a bit-set * Backport of [AArch32] 2/2 Use new FPU features representation * Backport of [AArch32] 1/5 Make room for more CPU feature flags * Backport of [AArch32] 2/5 Add feature set definitions * Backport of [AArch32] 3/5 Use new feature set representation * Backport of [AArch32] 4/5 Use features sets for builtins * Backport of [AArch32] 5/5 Move initializer into arm-cores.def and arm-arches.def * Backport of [AArch32] Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtx pattern * Backport of [AArch32] Add missing is_neon_type types * Backport of [AArch32] arm memcpy of aligned data * Backport of [AArch32] Fix arm bootstrap failure due to -Werror=shift-negative-value * Backport of [AArch32] fix vget_lane on big-endian * Backport of [AArch32] Use %wd format for lane printing in bounds_check * Backport of [AArch32/AArch64] 1/15 [FP16] Hide existing float16 intrinsics unless we have a scalar __fp16 type * Backport of [AArch32/AArch64] 2/15 [fp16] float16x4_t intrinsics in arm_neon.h * Backport of [AArch32/AArch64] 3/15 Add V8HFmode and float16x8_t type * Backport of [AArch32/AArch64] 4/15 float16x8_t intrinsics in arm_neon.h * Backport of [AArch32/AArch64] 5/15 Remaining intrinsics * Backport of [AArch32/AArch64] 6/15 Add basic FP16 support * Backport of [AArch32/AArch64] 8/15 Add support for float16x{4,8}_t vectors/builtins * Backport of [AArch32/AArch64] 9/15 vld{2,3,4}{,_lane,_dup}, vcombine, vcreate * Backport of [AArch32/AArch64] 10/15 Implement vcvt_{,high_}f16_f32 * Backport of [AArch32/AArch64] 11/15 vreinterpret(q?), vget_(low|high), vld1(q?)_dup * Backport of [AArch32/AArch64] 12/15 Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix * Backport of [AArch32/AArch64] 13/15 Add float16 tests to advsimd-intrinsics testsuite * Backport of [AArch32/AArch64] 14/15 Add test of vcvt{,_high}_i{f32_f16,f16_f32} * Backport of [AArch32/AArch64] 15/15 Update sourcebuild.texi with testsuite/effective-target hooks * Backport of [AArch64] 1/5 Reimplement aarch64_bitmask_imm * Backport of [AArch64] 2/5 Improve aarch64_internal_mov_immediate by using faster algorithm * Backport of [AArch64] 3/5 Remove dead code * Backport of [AArch64] 4/5 Remove redundant code * Backport of [AArch64] 5/5 Cleanup immediate generation code in aarch64_internal_mov_immediate * Backport of [AArch64] 1/14 Add ident field to struct processor * Backport of [AArch64] 2/14 Refactor arches handling, add arch enum identifier * Backport of [AArch64] 3/14 Refactor option override code * Backport of [AArch64] 4/14 Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769 * Backport of [AArch64] 5/14 Make flag_omit_leaf_frame_pointer intialize to 2. Define and use TARGET_OMIT_LEAF_FRAME * Backport of [AArch64] 6/14 Implement TARGET_OPTION_SAVE/TARGET_OPTION_RESTORE * Backport of [AArch64] 7/14 Implement TARGET_SET_CURRENT_FUNCTION * Backport of [AArch64] 8/14 Implement TARGET_OPTION_VALID_ATTRIBUTE_P * Backport of [AArch64] 9/14 Implement TARGET_CAN_INLINE_P * Backport of [AArch64] 10/14 Implement target pragmas * Backport of [AArch64] 11/14 Re-layout SIMD builtin types on builtin expansion * Backport of [AArch64] 12/14 Target attributes and target pragmas tests * Backport of [AArch64] 13/14 Document AArch64 target attributes and pragmas * Backport of [AArch64] 14/14 Reuse target_option_current_node when passing pragma string to target attribute * Backport of [AArch64] vtbl[34] and vtbx4 * Backport of [AArch64] Add backend aarch64_bfi pattern * Backport of [AArch64] Add csneg3_uxtw_insn pattern * Backport of [AArch64] Add support for 64-bit vector-mode ldp/stp * Backport of [AArch64] Adjust tests to take LSE extension into account * Backport of [AArch64] [array_mode 1/8] Rename vec_store_lanes<mode>_lane to aarch64_vec_store_lanes<mode>_lane * Backport of [AArch64] [array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands * Backport of [AArch64] [array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md * Backport of [AArch64] [array_mode 4/8] Remove EImode * Backport of [AArch64] [array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. * Backport of [AArch64] [array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. * Backport of [AArch64] [array_mode 7/8] Combine the expanders using VSTRUCT:nregs * Backport of [AArch64] [array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P * Backport of [AArch64] Break -mcpu tie between the compiler and assembler * Backport of [AArch64] [expand] Check gimple statement to improve LSHIFT_EXP expand * Backport of [AArch64] Fix FAIL: gcc.target/aarch64/target_attr_crypto_ice_1.c (internal compiler error) * Backport of [AArch64] Fix vcvt_high_f64_f32 and vcvt_figh_f32_f64 intrinsics * Backport of [AArch64] Fix vldX/vstX AdvSIMD intrinsics * Backport of [AArch64] Followup to [AArch64_be] Fix vtbl[34] and vtbx4 * Backport of [AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG * Backport of [AArch64] Handle const address in aarch64_print_operand * Backport of [AArch64] Implement copysign[ds]f3 * Backport of [AArch64] Improve code generation for float16 vector code * Backport of [AArch64] Improve SIMD concatenation with zeroes * Backport of [AArch64] Remove index from AARCH64_FUSION_PAIR * Backport of [AArch64] Remove obsolete comment in aarch64-option-extensions.def * Backport of [AArch64] Remove separate movtf pattern - Use an iterator for all FP modes * Backport of [AArch64] Remove the hack for AARCH64_EXTRA_TUNE_ALL * Backport of [AArch64] TLSLE 1,2 and 3/N * Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook * Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook * Backport of [AArch64] Use logics_imm type for 2nd alternative of *and<mode>3nr_compare0 * Backport of [AArch64] Use popcount_hwi instead of homebrew version * Backport of [Testsuite] Fix race on temp file in gfortran streamio_*.f90 tests * Backport of [Testsuite] Fix race on temp file in gfortran tests * Backport of [Testsuite] Fix typo in vcvt_f16.c testcase * Backport of [Testsuite] Adjust compiling options for gcc.target/arm/unsigned-float.c * Backport of [Testsuite] [AArch32] gcc.target/arm/pr67756.c: Fixed warnings * Backport of [Testsuite] [AArch64] 7/15 Add basic fp16 tests * Backport of [Testsuite] [AArch64] Adjust some arith+compare tests for potentially more aggressive if-conversion * Backport of [Testsuite] [AArch64] Make arm_align_max_stack_pwr.c and arm_align_max_pwr.c compile testcase, instead of execution * Backport of [Testsuite] [AArch64] Mark target_attr_1.c as compile-only * Backport of [testsuite] [AArch64] Remove divisions-to-produce-NaN from vdiv_f.c * Backport of [Testsuite] Add float16 lane_f16_indices tests * Backport of [Testsuite] auto-wipe dump files * Backport of [Testsuite] Clean up effective_target cache * Backport of [Testsuite] Clean up effective_target cache * Backport of [Testsuite] Fix order of dg-do and dg-require-effective-target directives * Backport of [testsuite] gcc.dg/builtins-20.c: Remove undefined behavior * Backport of [Testsuite] gcc.dg/tree-ssa/pr65447.c: Increase searching number * Backport of [Misc] add separate insn sched class for vector LDP & STP * Backport of [Misc] ccorrect ChangeLog dates+address * Backport of [Misc] fix typo in 223858 1/2 * Backport of [Misc] fix typo in 223858 2/2 * Backport of [Misc] Fix bigendian HFmode in native_interpret_real * Backport of [Misc] model load/store multiples properly in autoprefetcher scheduling * Backport of [Misc] Improve auto-increment addressing mode support in IVO by refactoring add candiate logic * Backport of [Misc] Improve bound information in loop niter analysis * Backport of [Misc] Improve conditional select ops on immediates * Backport of [Misc] Improve loop bound info by simplifying conversions in iv base * Backport of [Misc] IVOPS * Backport of [Misc] Look into unnecessary conversion when checking mult_op in get_shiftadd_cost * Backport of [Misc] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] mark libstdc++ tests unsupported if they fail with relocation truncated * Backport of [Misc] Rerun loop-header-copying just before vectorization * Backport of [Misc] Allow PLUS+immediate expression in noce_try_store_flag_constants * Backport of [Doc] Clarify feature modifiers {no,}{fp,simd,crypto} Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 5 months

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[ACTIVITY] 9-13 November 2015

by Christophe Lyon

1 day off (Wednesday) (2/10) == Progress == * Validation - Jenkins jobs maintenance & cleanup - comparison of build times between old & new lab - dedicated slave for results comparison works well * GCC - trunk monitoring, reported a few new failures. - high rate of commits before e/o stage1 means lots of patches to check - infrastructure problems in the ST compute farm mean a few false errors needed analysis - looked at bug #1869, (problem with binary toolsets on RHEL6). Made some progress == Next == * Validation: - continue preparation of switch, as dev-01 is now back - improve reporting * GCC: - check Neon tests cleanup - bug #1869 - look at how to send valuable reports to gcc-regression

10 years, 5 months

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[ACTIVITY] 9th -- 13th November

by Yao Qi

* Off on Wed afternoon [1/10]. # Progress # * Fails in gdb.threads/multiple-step-overs.exp, (TCWG-332) [1/10] Patch V2 is posted, pending for review. * TCWG-422, patch is committed. Done. [2/10]. * TCWG-423, patches are ready, being regression tested. [2/10] * TCWG-433, build GDB with -fsanitize=address, and exposes many memory issues. Some of them are fixed. [2/10]. * Upstream patch review, [1/10] * Misc, meeting, [1/10] # Plan # * TCWG-423, Post patches upstream. * Understand ST's jtag probe and help them to make use of multi-arch with GDB. * TCWG-433, Continue fixing memory issues exposed by -fsanitize=address. -- Yao

10 years, 5 months

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Re: [U-Boot] aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi Albert, On Thu, Nov 12, 2015 at 08:20:18AM +0100, Albert ARIBAUD wrote: > Can you provide the target name and commit ID that you are building, > s well as the version of the toolchain that you are building with? > Without being able to reproduce your issue, it's kind of hard to > diagnose it. With the explanation from Ard, I understand the thing now. But thanks for the reply anyway. Shawn

10 years, 5 months

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aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi, I need some help to understand aarch64-linux-gnu-objdump output in .data section as below. It's part of the dump of u-boot image with command 'aarch64-linux-gnu-objdump -D -z u-boot'. Disassembly of section .data: 0000000035039898 <reserved_list>: <snip> 0000000035039948 <init_sequence_f>: 35039948: 00000000 .word 0x00000000 3503994c: 00000000 .word 0x00000000 35039950: 00000000 .word 0x00000000 35039954: 00000000 .word 0x00000000 35039958: 00000000 .word 0x00000000 3503995c: 00000000 .word 0x00000000 35039960: 00000000 .word 0x00000000 35039964: 00000000 .word 0x00000000 35039968: 00000000 .word 0x00000000 3503996c: 00000000 .word 0x00000000 35039970: 00000000 .word 0x00000000 35039974: 00000000 .word 0x00000000 35039978: 00000000 .word 0x00000000 3503997c: 00000000 .word 0x00000000 35039980: 00000000 .word 0x00000000 35039984: 00000000 .word 0x00000000 35039988: 00000000 .word 0x00000000 3503998c: 00000000 .word 0x00000000 35039990: 00000000 .word 0x00000000 35039994: 00000000 .word 0x00000000 35039998: 00000000 .word 0x00000000 3503999c: 00000000 .word 0x00000000 350399a0: 00000000 .word 0x00000000 350399a4: 00000000 .word 0x00000000 350399a8: 00000000 .word 0x00000000 350399ac: 00000000 .word 0x00000000 350399b0: 00000000 .word 0x00000000 350399b4: 00000000 .word 0x00000000 350399b8: 00000000 .word 0x00000000 350399bc: 00000000 .word 0x00000000 350399c0: 00000000 .word 0x00000000 350399c4: 00000000 .word 0x00000000 350399c8: 00000000 .word 0x00000000 350399cc: 00000000 .word 0x00000000 350399d0: 00000000 .word 0x00000000 350399d4: 00000000 .word 0x00000000 350399d8: 00000000 .word 0x00000000 350399dc: 00000000 .word 0x00000000 350399e0: 00000000 .word 0x00000000 350399e4: 00000000 .word 0x00000000 350399e8: 00000000 .word 0x00000000 350399ec: 00000000 .word 0x00000000 350399f0: 00000000 .word 0x00000000 350399f4: 00000000 .word 0x00000000 350399f8: 00000000 .word 0x00000000 350399fc: 00000000 .word 0x00000000 35039a00: 00000000 .word 0x00000000 35039a04: 00000000 .word 0x00000000 35039a08: 00000000 .word 0x00000000 35039a0c: 00000000 .word 0x00000000 35039a10: 00000000 .word 0x00000000 35039a14: 00000000 .word 0x00000000 35039a18: 00000000 .word 0x00000000 35039a1c: 00000000 .word 0x00000000 35039a20: 00000000 .word 0x00000000 35039a24: 00000000 .word 0x00000000 35039a28: 00000000 .word 0x00000000 35039a2c: 00000000 .word 0x00000000 35039a30: 00000000 .word 0x00000000 35039a34: 00000000 .word 0x00000000 35039a38: 00000000 .word 0x00000000 35039a3c: 00000000 .word 0x00000000 35039a40: 00000000 .word 0x00000000 35039a44: 00000000 .word 0x00000000 35039a48: 00000000 .word 0x00000000 35039a4c: 00000000 .word 0x00000000 The init_sequence_f[] is an array defined in U-Boot v2015.04 source common/board_f.c, which holds a bunch of pointers to critical initialization functions that have to be called during boot. Obviously, the array cannot be all zeros like what objdump tells. And I confirmed that by printing the pointers at run-time as below. init_sequence_f[0]: 0000000035004280 init_sequence_f[1]: 00000000350042a8 init_sequence_f[2]: 0000000035004380 init_sequence_f[3]: 00000000350042a0 init_sequence_f[4]: 00000000350044b8 init_sequence_f[5]: 0000000035004388 init_sequence_f[6]: 0000000035029538 init_sequence_f[7]: 000000003500675c init_sequence_f[8]: 000000003500447c init_sequence_f[9]: 000000003501d864 init_sequence_f[10]: 0000000035013778 init_sequence_f[11]: 0000000035004398 init_sequence_f[12]: 0000000035028ab8 init_sequence_f[13]: 0000000035004278 init_sequence_f[14]: 0000000035004270 init_sequence_f[15]: 000000003500445c init_sequence_f[16]: 0000000035001f20 init_sequence_f[17]: 0000000035004574 init_sequence_f[18]: 00000000350042b0 init_sequence_f[19]: 00000000350042c4 init_sequence_f[20]: 00000000350042cc init_sequence_f[21]: 00000000350042f8 init_sequence_f[22]: 00000000350044d4 init_sequence_f[23]: 000000003500430c init_sequence_f[24]: 0000000035004314 init_sequence_f[25]: 0000000035004330 init_sequence_f[26]: 0000000035004390 init_sequence_f[27]: 00000000350045bc init_sequence_f[28]: 0000000035004550 init_sequence_f[29]: 0000000035004518 init_sequence_f[30]: 0000000035004378 init_sequence_f[31]: 0000000035004428 init_sequence_f[32]: 00000000350043f0 Dumping an u-boot image built for 32-bit platform with arm-linux-gnueabi-objdump gives correct pointer values for the same array. 17853c7c <init_sequence_f>: 17853c7c: 17805600 strne r5, [r0, r0, lsl #12] 17853c80: 17805620 strne r5, [r0, r0, lsr #12] 17853c84: 1780574c strne r5, [r0, ip, asr #14] 17853c88: 178007ec strne r0, [r0, ip, ror #15] 17853c8c: 1780583c ; <UNDEFINED> instruction: 0x1780583c 17853c90: 17805834 ; <UNDEFINED> instruction: 0x17805834 17853c94: 1780315c ; <UNDEFINED> instruction: 0x1780315c 17853c98: 178015f4 ; <UNDEFINED> instruction: 0x178015f4 17853c9c: 17800890 ; <UNDEFINED> instruction: 0x17800890 17853ca0: 17801c0c strne r1, [r0, ip, lsl #24] 17853ca4: 178078f8 ; <UNDEFINED> instruction: 0x178078f8 17853ca8: 17805808 strne r5, [r0, r8, lsl #16] 17853cac: 17829564 strne r9, [r2, r4, ror #10] 17853cb0: 17816104 strne r6, [r1, r4, lsl #2] 17853cb4: 1783dea4 strne sp, [r3, r4, lsr #29] 17853cb8: 178055f8 ; <UNDEFINED> instruction: 0x178055f8 17853cbc: 17801a54 ; <UNDEFINED> instruction: 0x17801a54 17853cc0: 17805b4c strne r5, [r0, ip, asr #22] 17853cc4: 178057e0 strne r5, [r0, r0, ror #15] 17853cc8: 178057c8 strne r5, [r0, r8, asr #15] 17853ccc: 17802e20 strne r2, [r0, r0, lsr #28] 17853cd0: 17805910 usada8ne r0, r0, r9, r5 17853cd4: 17805628 strne r5, [r0, r8, lsr #12] 17853cd8: 17805640 strne r5, [r0, r0, asr #12] 17853cdc: 17805678 ; <UNDEFINED> instruction: 0x17805678 17853ce0: 17805680 strne r5, [r0, r0, lsl #13] 17853ce4: 178056b0 ; <UNDEFINED> instruction: 0x178056b0 17853ce8: 17805850 ; <UNDEFINED> instruction: 0x17805850 17853cec: 178056c8 strne r5, [r0, r8, asr #13] 17853cf0: 178056dc ; <UNDEFINED> instruction: 0x178056dc 17853cf4: 178056f8 ; <UNDEFINED> instruction: 0x178056f8 17853cf8: 17805768 strne r5, [r0, r8, ror #14] 17853cfc: 17805950 ; <UNDEFINED> instruction: 0x17805950 17853d00: 178058ec strne r5, [r0, ip, ror #17] 17853d04: 17805894 ; <UNDEFINED> instruction: 0x17805894 17853d08: 17805744 strne r5, [r0, r4, asr #14] 17853d0c: 17805798 ; <UNDEFINED> instruction: 0x17805798 17853d10: 17805770 ; <UNDEFINED> instruction: 0x17805770 17853d14: 00000000 andeq r0, r0, r0 Here are my questions: - Is this only because that ARM 64-bit toolchain doesn't show the real value of the pointers, or there are some linking or run-time magics to get these pointers correct when the binary is actually running? - Is this different behavior between ARM 32-bit and 64-bit toolchain expected? Or did I miss anything on 64-bit toolchain usage? Any hints or comments are much appreciated. Thanks, Shawn

10 years, 5 months

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Re: [lng-odp] Runtime inlining

by Mike Holmes

On 11 November 2015 at 00:45, Savolainen, Petri (Nokia - FI/Espoo) < petri.savolainen(a)nokia.com> wrote: > > > > -----Original Message----- > > From: lng-odp [mailto:lng-odp-bounces@lists.linaro.org] On Behalf Of > > EXT Nicolas Morey-Chaisemartin > > Sent: Tuesday, November 10, 2015 5:13 PM > > To: Zoltan Kiss; linaro-toolchain(a)lists.linaro.org > > Cc: lng-odp > > Subject: Re: [lng-odp] Runtime inlining > > > > As I said in the call last week, the problem is wider than that. > > > > ODP specifies a lot of types but not their sizes, a lot of > > enums/defines (things like ODP_PKTIO_INVALID) but not their value > > either. > > For our port a lot of those values were changed for > > performance/implementation reason. So I'm not even compatible between > > one version of our ODP port and another one. > > > > The only way I can see to solve this is for ODP to fix the size of all > > these types. > > Default/Invalid values are not that easy, as a pointer would have a > > completely different behaviour from structs/bitfields > > > > Nicolas > > > > Type sizes do not need to be fixed in general, but only when an > application is build for binary compatibility (the use case we are talking > here). Binary compatibility and thus the fixed type sizes are defined per > ISA. > > We can e.g. define a configure target (for our reference implementation == > linux-generic) "--binary-compatible=armv8.x" or > "--binary-compatible=x86_64". When you build your application with that > option, "platform dependent" types and constants would be fixed to > pre-defined values specified in (new) ODP API arch files. > > So instead of building against > odp/platform/linux-generic/include/odp/plat/queue_types.h ... > > typedef ODP_HANDLE_T(odp_queue_t); > #define ODP_QUEUE_INVALID _odp_cast_scalar(odp_queue_t, 0) > #define ODP_QUEUE_NAME_LEN 32 > > > ... you'd build against odp/arch/armv8.x/include/odp/queue_types.h ... > With the introduction of odp/arch at the top level I think we should also move platform/linux-generic/arch to the same location > typedef uintptr_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uintptr_t)0) > #define ODP_QUEUE_NAME_LEN 64 > > > ... or odp/arch/x86_64/include/odp/queue_types.h > > typedef uint64_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uint64_t)0xffffffffffffffff) > #define ODP_QUEUE_NAME_LEN 32 > > > For highest performance on a fixed target platform, you'd still build > against the platform directly > > odp/platform/<soc_vendor_xyz>/include/odp/plat/queue_types.h > > typedef xyz_queue_desc_t * odp_queue_t; > #define ODP_QUEUE_INVALID ((xyz_queue_desc_t *)0xdeadbeef) > #define ODP_QUEUE_NAME_LEN 20 > > > -Petri > > > > > _______________________________________________ > lng-odp mailing list > lng-odp(a)lists.linaro.org > https://lists.linaro.org/mailman/listinfo/lng-odp > -- Mike Holmes Technical Manager - Linaro Networking Group Linaro.org <http://www.linaro.org/> *│ *Open source software for ARM SoCs

10 years, 5 months

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[ACTIVITY] 2nd - 6th November

by Bernie Ogden

Holiday [2/10] Juno crash analysis [2/10] * Spent some time fiddling with kexec on AArch64 * Worked in one very specific case * Another patch series is (apparently) coming, will look out for it and try again SPEC-on-Android [2/10] * Supporting Qian on getting this working * Wrote a readme for the repository, fixed a Makefile bug that Qian's cross-compiler happened to tickle Jenkins benchmarking job - TCWG-348 [1/10] * Tested, tidied up pbl hacks to generate JSON * Tested my pbl with Jenkins prototype jobs * A few minor bug fixes/enhancements for pbl LAVA jobs for uinstance - TCWG-432 [1/10] * Reworked jobs to support uinstance, maintaining backward compatibility as far as possible * Started adding support to submit results to bundle stream Misc [2/10] * Debian FS ready to submit * Usual meetings/mail/etc background =Plan= Look at doing pbl hacks properly in Fathi's in-development refactored p-b-l Pull together Jenkins/LAVA/pbl, ready to test when uinstance is available Write up noise control report (If time, if patches land) have another go at crashdump

10 years, 5 months

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[ACTIVITY] Week 44

by Yvan Roux

== Progress == o Linaro GCC (4/10) * Delivered GCC 4.9 2015.10 snapshot * More backports forGCC 5 2015.11 * Many instabilities on Hetzner this week o Upstream work (2/10) * Sanitizing gfortran testsuite o Release tools (2/10) * Added RCs and binaries support to our snapshot.linaro.org publishing job o Misc (2/10) * Various meetings * Some support == Plan == o Track missing backports dependencies o Continue ongoing tasks.

10 years, 5 months

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[Weekly] 02-06 November 2015

by Michael Collison

== This week == * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Determined that vectorizer is failing for all targets that have widening adds with V8HI to V4SI support (aarch64, ia64, powerPC). - Modified test cases to indicate expected failure with wide add V8HI to V4SI support - Patch sent upstream for approval * Bugzilla 68223 - arm_[su]min_cmp pattern fails - Resolved by reverting patch for tcwg-146 as pattern fail in some corner cases. (3/10) - Reverted patch checked in upstream * Misc (1/10) - Conference calls * Illness, November 2nd (2/10) == Next week == - TCWG-317 - Resolve lto big endian failures

10 years, 5 months

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[ACTIVITY] 2-6 November 2015

by Kugan

== Progress == - Leave (2/10) - Widening pass (TCWG-547) - 5/10 * Made the latest changes requested in the review * Fixed bootstrap and bootstrap mis-compare for ppc64-linux-gnu * Making uninitialized variable as anonymous ssa (as asked in review) results in few ICEs. * Posted updated patch for feedback - Misc (3/10) * started looking into LTO status * Looked at LuaJIT for arm * gcc/bug list == Plan == * continue with widening pass based on feedback * Look at implementing LuaJIT for aarch64 * LTO

10 years, 5 months

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[ACTIVITY] 2 - 6 November 2015

by Prathamesh Kulkarni

== This week == * TCWG-72 (6/10) - 5 iterations since the original patch. Changes include: a) Integration into widening_mul patch b) Rewriting the divmod transform so DIVMOD() is placed before the topmost div/mod stmt c) Removed check for widening mode and optab handler check in expand_DIVMOD d) Fixed ICE when constant is one of the operands to div/mod stmt. e) Fixed mis-compilation with a test-case when operands matched but in opposite order. f) Formatting nits and fixed test-cases. - Richard suggested no need to check for post-domination conditions. - Not sure on what condition to gate the transform. Checking for availability of divmod/div/mod is not sufficient because arm defines optab handler for mod which only matches r0 % n where n is constant and power of 2 for other cases it's expanded via divmod libcall thru expand_divmod. We would rather need to check if the template for mod/div gets matched than just to check if optab handler exists. AFAIK this cannot be done during tree-ssa passes. I can think of two approaches: a) Do the transform to DIVMOD representation unconditionally in widening_mul pass. And then in expand_DIVMOD check if the template for mod can be matched. If it does match then undo the transform from DIVMOD to original representation and expand. I am not sure how feasible it is to undo the transform at expansion time, and start expanding the modified cfg. b) Define a new target hook combine_divmod. Default implementation could check for optab handler for div/mod/divmod. and I could override it for arm-backend to additionally check if the second operand is a constant and power of 2 and fail for this case (since we want this to be expanded from modsi3 pattern). Not sure if this is a good idea, I am replicating the information from the modsi3 pattern. If the pattern changes, the hook would also need to be changed. * Convert ASM_FORMAT_PRIVATE_NAME to hook (2/10) * TCWG-319 (1/10) - Bencharmking for patch in progress * Misc (1/10) - Meetings - Sync with Kugan == Next Week == - Continue with TCWG-72 - Complete the patch with build, test and config-builds for ASM_FROMAT_PRIVATE_NAME and submit upstream - Continue benchmarking TCWG-319, TCWG-310

10 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (5/10) - Some broken bots, bisecting, etc - Helping a MIPS patch pass on ARM bot * Maintenance (2/10) - SciMark2 seems not to be unstable or slow any more in ARM64 - Some more investigations on Loop Load Elimination - Profiling bigfib on APM and HiKey * Background (3/10) - Code review, meetings, discussions, general support, etc. - Some FOSDEM fiddling - Some power issues

10 years, 5 months

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[ACTIVITY] 2-6 November 2015

by Christophe Lyon

== Progress == * Validation - moved list of unstable tests to a separate repo, to make maintenance easier (TCWG-425) - Jenkins jobs maintenance & cleanup - a few ABE reporting patches - comparison of results between old & new lab * GCC - trunk monitoring, reported a few new failures. - Send patch to fix vqtb[lx][34] intrinsics on aarch64_be * Binutils - Added a Jenkins job to build+check binutils on a variety of configurations: https://ci.linaro.org/view/tcwg-ci/job/tcwg-binutils/ - sent a small patch to fix a bug in the recent STM32L4XX erratum patch == Next == * Validation: - work on the switch to the new lab, once dev-01 is back online - more tuning to avoid deadlocks - re-measure build time on dev-01, to better tune other build jobs

10 years, 5 months

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[ACTIVITY] 2nd - 6th Nov

by Yao Qi

* Two half day off. [2/10] # Progress # * TCWG-332, fails in gdb.threads/multiple-step-overs.exp. [1/10] Testing the simpler approach suggested during the review. * TCWG-387, done. [1/10] GDB patches are pushed in. * TCWG-422, GNU vector extension support in ARM GDB. [2/10] Patches are done, and being tested. * TCWG-423, GNU vector extension support in AArch64 GDB. [2/10] Writing patches. Find more issues for AArch64 that GDB doesn't fully understand the AArch64 calling convention. Need more work here. * Review ARM GDBserver software single step patch. [1/10] * Misc, meeting, email, [1/10] # Plan # * Off on Wed afternoon. * TCWG-422, post patches * TCWG-423, continue. -- Yao

10 years, 5 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.2 2015.11-rc1

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-rc1 Release-Candidate Archives. http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-rc1/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-rc1/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 6 months

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GCC performance questions

by Gunnar von Boehn

Dear List, I'm new to this list and have some questions. Looking at the created code of GCC on ARMv8, we noticed some areas where there is room for performance improvements. I assume that these items might already be noticed by you guys. For example: 1) We noticed that when writing typical DGEMM like code, GCC includes unnecessary DUP instruction 2) GCC seems unwilling to use LDP loads 3) For optimal FPU performance on some A57 its needed to interleave instruction working on ODD and EVEN registers GCC seem not properly support this. Here sometimes 100% performance increase could be reached by different instruction interleaving. 4) Some work loops highly benefit of interleaving of FPU instructinons and loads. GCC seems to likes to re-arrange the code so that most or all loads are put on top of the loop. This can reduce the performance of a well written workloop significantly. I have no patches to fix this. But I can produce C- code and ASM output which will show these performance issues. Please tell me what the next recommended step will be now. Are all these items known already, or shall I provide code examples to further explain them? Kind regards Gunnar von Boehn

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Christophe Lyon

== Progress == * Validation - comparing results and build times between the 2 labs - tuning jobs scheduling to avoid deadlocks * GCC trunk monitoring - lots of validation results to check after 1 week of holidays :-) - a few regressions/new failures/wrong tests reported * Backports - a few reviews == Next == * Infrastructure/Validation * GCC dev: try to fix vqtbl intrinsics for aarch64_be before e/o stage1

10 years, 6 months

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[ANNOUNCE] Linaro GCC 4.9 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 4.9 source package. This snapshot[1] is based on FSF GCC 4.9.4-pre+svn229467 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 4.9.4-pre+svn229467 * Backport of [Bugfix] PR tree-optimization/65735 * Backport of [Bugfix] PR tree-optimization/65177 * Backport of [Bugfix] PR tree-optimization/65048 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Infrastructure (4/10) - Installing Ubuntu on APM (perf works!) - Setting up a HiKey for in-order perf - Helping Milosz with crashing HiKeys * Maintenance (4/10) - Helping ARM with test-suite patches (D14061) - Investigating read-after-read dependency (D13259) * Background (2/10) - Code review, meetings, discussions, general support, etc.

10 years, 6 months

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[ACTIVITY] Week 43

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and reviews for our GCC 5 2015.11 snapshot * FSF branch merge and needed backports for our GCC 4.9 2015.10 snapshot o Misc (1/10) * Various meetings == Plan == o Complete 4.9 snapshot

10 years, 6 months

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[ACTIVITY] 26th - 30th October

by Bernie Ogden

Noise control experiments - TCWG-358 [3/10] * Some analysis of data to date Debian filesystem - TCWG-360 [3/10] * Got stuck on LAVA interactions * Now booting-to-LAVA-usability, needs some cleanup and testing with real benchmark runs Benchmarking-via-Jenkins - TCWG-348 [1/10] * Picked back up on understanding that LAVA uinstance is a-coming * Hacked pbl.py (post-build-lava) to generate suitable JSON ** As a bonus, this can work as a CLI job-submission tool =Plan= Holiday Friday (pending approval) Set up crashdumping on my Juno, try to learn why it crashes Finish Debian filesystem Get Jenkins generating and submitting jobs suitable for uinstance Write up noise control report (probably will get bumped to next week)

10 years, 6 months

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[Weekly] 26-30 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (3/10) - Could not reproduce test failure in qemu - Waiting on feedback from Maxim who is running patch on Linaro validation * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Debugging tree vectorizer to determine why loops with no wide add operations are no longer being vectorized * TCWG 146 - Debugging regression on arm big endian with Linaro 5 branch (2/10) * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures - TCWG-369 - Identify why loops are not being vectorized - TCWG-146 - Resolve big endian failures

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 / PR43721 (8/10) - Completed writing expand_DIVMOD() and submitted patch upstream - Reworked patch according to Richard Biener's comments. (http://people.linaro.org/~prathamesh.kulkarni/pr43721-patch-v2.diff) - Wrote test-cases. * TCWG-319 (1/10) - Benchmark run without patch complete for "int" benchmarks on a53, a57 - Benchmark run with patch in progress for "int" benchmarks on a53, a57 * Misc (1/10) - Meetings == Next Week == - Continue with TCWG-72, TCWG-310li, TCWG-319 benchmarking

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Yao Qi

# Progress # * TCWG-332, [1/10], patch is posted for review. * TCWG-187, [1/10], looks like a kernel (~3.4) bug on setting VFP registers through ptrace. Fails go away after I upgrade the kernel. * TCWG-387, [2/10], binutils patch is committed, while GDB patches are being reviewed. * TCWG-422, [3/10], Read AAPCS and gcc source code to understand the calling convention. On going. * FSF patch review, [2/10] ** Review patch set "all-stop on top of non-stop for remote". ** Review ARM fast tracepoint patches. ** Reopen PR 15564, as the fail isn't fixed. * Misc, meeting, [1/10] # Plan # * TCWG-422 * Support ST on using AArch64 multi-arch GDB if needed. * Review ARM GDBserver software single step patch. -- Yao

10 years, 6 months

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[Weekly] 19-23 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (5/10) - Continued to debug big endian/lto failure of four torture tests - Differences in lto vs. non-lto executables showed no significant differences * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Resolved three of six test suite failures * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures by debugging test cases with qemu - TCWG-369 - Resolve remaining test suite failures -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

10 years, 6 months

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linux ipv4 forward performance issue

by Liu Ting

Hello all, When upgrading meta-linaro/meta-linaro-toolchain from daisy to fido, we faced drastic performance downgrade (-34.06%) on linux ipv4 forwarding. The board is ls1021atwr (ARM Cortex-A7 MPCore compliant with ARMv7-A architecture). We did some investigation, and suspected that it is caused by the toolchain upgrade. Did someone meet similar issue? The detailed toolchain info: https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/fido gcc-linaro-4.9.3-2015.03, glibc-linaro-2.20-2014.11, binutils-linaro-2.25-2015.01 https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/dai… gcc-linaro-4.8.3-2014.04, eglibc-linaro-2.19-r2014.04, binutils-linaro-2.24-r2014.03 thanks. -Ting

10 years, 6 months

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[ACTIVITY] Week 41 - 42

by Yvan Roux

o Week 42 off (10/10) == Progress == o Linaro GCC (9/10) * Completed backports and reviews * Delivered GCC 5 2015.10 snapshot * Completed TCWG 389 (deploy snapshot job) o Misc (1/10) * Various meetings == Plan == o Back to work

10 years, 6 months

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[ACTIVITY] 19th - 23rd October

by Bernie Ogden

Mustang benchmarking bringup - (no ticket) [2/10] Controlled Debian build - TCWG-360 [1/10] * Constructed filesystem, works OK as chroot * Next step is to boot it Investigate Workload Automation framework - TCWG-361 [1/10] * Seems to basically work * SPEC support dubious Misc * LAVA uinstance background (TCWG-396, < 1/10) * Noise control experiments (TCWG-358, < 1/10) * ARM management duties [2/10]

10 years, 6 months

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[ACTIVITY] 19 - 23 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (4/10) - wrote new pass to generate "divmod" internal fn. - investigating segfault during expansion of divmod. * TCWG-319 (2/10) - Benchmarking setup - Running INT benchmarks for a53, a57. * TCWG-310 (1/10) - Looked at how peeling occurs - Email discussions * Public Holiday (2/10) * Misc (1/10) - Meetings == Next week == - Submit patch for TCWG-72 upstream - TCWG-319 benchmarking - Convert ASM_FORMAT_PRIVATE_NAME macro to hook. - Continue with TCWG-310

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (5/10) - Investigating some LivermoreLoops that don't vectorise - Reducing cases to single specific causes * Background (5/10) - Code review, meetings, discussions, general support, etc. - More code of conduct stuff, license change to Apache 2 - Following up on sanitizers VMA discussion

10 years, 6 months

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[ACTIVITY] 19 - 23 October 2015

by Yao Qi

* Two days (Tue and Thu) off. [4/10] # Progress # * TCWG-180, patch is committed by Andrew Stubs. [1/10] I review and approve it. * Review patch set "all-stop on top of non-stop for remote". [3/10] Test them on aarch64 and arm. Triage and fix one regression. Review is still on going. * Review patch set "ARM gdbserver software breakpoint". [2/10] Review and approve them. They are preparatory to ARM tracepoint. # Plan # * Patch review. * TCWG-387, Move GDB using libopcodes to decode instructions. -- Yao

10 years, 6 months

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 5.1 2015.08

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.1-2015.08 Archives. http://releases.linaro.org/components/toolchain/binaries/5.1-2015.08/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. For bugs related to this release please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * 2015.08 * The Linaro GCC 5.1 2015.08 binary toolchain release is based on the Linaro GCC-5.1-2015.08 source archive release <http://releases.linaro.org/components/toolchain/gcc-linaro/5.1-2015.08/>. The major changes contained in 2015.08 over 2015.05 are described in the sections below on 2015.08-rc1 and 2015.08-rc2 . * 2015.08-rc2 * The Linaro 2015.08-rc2 release-candidate binary toolchain is based on the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in how the binary toolchains were built. The compiler itself was not changed. * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are now correctly configured. This was broken in 2015.08-rc1. The cross-compiler targetting armv8l-linux-gnueabihf is now correctly configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8 --with-float=hard --disable-multilib --enable-multiarch. * Glibc’s slibdir and libdir were once again modified to address Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. The following are now the correct locations: libdir=lib/ (linker-scripts and static archives) slibdir=usr/lib/ (shared objects) rtlddir=lib/ (dynamic linker) * 2015.08-rc1 * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now provided. Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A) cross binary toolchain product release and CARD-1637 – Enable Aarch32 (32-bit ARMv8-A) cross binary toolchain product releases , armv8l-linux-gnueabihf targetted toolchains are now available as part of this release-candidate. * Python support in GDB for both Linux and Mingw32 (32-bit windows). Delivered as requested in the linaro-toolchain mailing list post title – windows binary builds with gdb-python enabled?. * Added missing expat support to GDB. This addresses the following linaro-toolchain mailing list post – "Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal targets." * A fix for multilib enablement in baremetal toolchains (as described in ABE Review 6862). * Library Paths are now congruent with older Linaro Toolchain path layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. libdir=lib/ (shared objects) slibdir=usr/lib/ (static libraries) rtlddir=lib/ (dynamic linker) -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 6 months

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Question about the Linaro toolchain version

by Luo Zhenhua

Hi, The default gcc version of Yocto 2.0(Jethro) is 5.2.0, the gcc version in meta-linaro is gcc-4.9.4, may I know if gcc-linaro-4.9.4 will be used for Yocto 2.0 release? when will the linaro gcc be upgraded to gcc-5.x? BTW, can someone please help point out where the Linaro toolchain roadmap can be got? Best Regards, Zhenhua

10 years, 6 months

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[ACTIVITY] 12 - 16 October 2015

by Omair Javaid

== Progress == LLDB development -- Verify LLDB watchpoints on Android Arm and AArch64 targets. [TCWG-405] [4/10] - Ran LLDB testsuite on Nexus5, Nexus 7, Nexus S and Nexus 9 devices. - Started into failing watchpoint tests on all devices. -- Investigate and fix LLDB watchpoints tests that are failing on Android Nexus 9 AArch64 target. [TCWG-405] [5/10] - Debugging of ptrace watchpoint installation code. - Prepared a fix and tested on Nexus 9. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == Further progress on investigating LLDB watchpoint issues on Android Nexus devices. Local testbots setup using new Android Nexus and Arm linux devices.

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Libraries (3/10) - Back investigating libc++ issues in AArch64 buildbot - http://buildmaster.tcwglab.linaro.org/builders/clang-cmake-aarch64-prototype - Trying to solve the rt/unw/c++ library entanglement in the driver * Buildbots (1/10) - Trying to perf an application on APM, but it crashed while - Rebooted it for now, but on the list to migrate to a newer kernel * Background (6/10) - Code review, meetings, discussions, general support, etc. - Laptop playing stupid again, lost a day trying to fix things - New LLVM "code of conduct" sparked a huge discussion

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [4/10] * Recovered from a couple more crashes, existing logging sheds no light * Explored the existing data a bit, need more to draw any conclusions Controlled image builds - TCWG-360 [2/10] * Looked into controlled, repeatable debian builds, B&B-style * Got the general shape of it, checking my understanding with Fathi LAVA microinstance - TCWG-396 [1/10] * Sent doc for review, revised it a bit Misc [3/10] * Exported benchmark/results handling rules to a place other Linaro-ans can read them * Updated example LAVA jobs to use tcwg tag (for load balancing purposes) * Meetings, mail, etc =Plan= Generate more noise data, watching out for crashes Produce a candidate Debian image, document how I did it If time, learn about Workload Automation

10 years, 6 months

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[Weekly] 12 - 16 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (6/10) - Debugging failures on -flto/big endian combination - Wrote code for big endian lane support; failures still exist - Debugging lto to see if optimization is causing failures * TCWG-77 - Transform end of loop conditions to min_expr (1/10) - patch approved, checked in upstream * Misc (1/10) - Conference calls * US Holiday, Monday October 12th (2/10) == Next week == - TCWG-317 - Debug to determine if lto is causing failures

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Kugan

== Progress == - Run spec2006 with DS5/Streamline Performance Analyzer (3/10) - Setup DS5 - Setting up client for chromebook which requires kernel rebuild - Widening pass (TCWG-547) - 5/10 * iterated based on review comments * re-wrote GIMPLE_DEBUG handling - Misc (2/10) * gcc/bug list == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [1/10] Patches are committed. * TCWG-335, HW breakpoint on 2-byte aligned address, [3/10] patch is tested against most recent kernel. Everything works. Patch is committed. * TCWG-166, Review ARM software breakpoint in GDBserver patches. [1/10] Almost done. * Review various upstream patches. [2/10]. * Misc, [3/10] ** Meeting, ** Write up some slides about recent GDB development, and present them in ARM. # Plan # * TCWG-387, Move GDB using libopcodes to decode instructions. * More upstream patches review. * Two days off on Tue and Thu. Maybe off on Friday too. -- Yao

10 years, 6 months

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[ANNOUNCE] Linaro GCC 5 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn228499 * Backport of [Bugfix] [AArch32] Fix PR target/29693 * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check * Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane bounds in expand * Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target * Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404 * Backport of [Bugfix] [AArch32] PR target/52144 attribute target (thumb,arm) [2.2/6] * Backport of [Bugfix] [AArch32] PR target/52144 target attributes Clean up arm_option_params_internals macro settings for attribute/pragma targets * Backport of [Bugfix] [AArch32] PR target/65768 * Backport of [Bugfix] [AArch64] PR63870 Neon error messages for vldN_lane/vstN_lane * Backport of [Bugfix] Fix PR66168 * Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765 * Backport of [Bugfix] PR c/49551 * Backport of [Bugfix] PR middle-end/64130 * Backport of [Bugfix] PR middle-end/66726 * Backport of [Bugfix] PR target/65768 Check cost of constants before propagating * Backport of [Bugfix] PR tree-optimization/67043 * Backport of [AArch32] 1-ARM/Thumb target attributes * Backport of [AArch32] 2-ARM/Thumb target attributes * Backport of [AArch32] 3-ARM/Thumb target attributes * Backport of [AArch32] Add ARM/thumb attribute target * Backport of [AArch32] Add ARM/thumb pragma target * Backport of [AArch32] Add TARGET_OPTION_PRINT * Backport of [AArch32] attribute target (thumb,arm) [2.1/6] * Backport of [AArch32] Correct spelling of references to ARMv6KZ * Backport of [AArch32] Fix ChangeLog * Backport of [AArch32] fix date * Backport of [AArch32] Fix static interworking call * Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM * Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT * Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when -mrestrict-it is in place * Backport of [AArch32] Use dmb ish instead of dmb sy for ARM * Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap instructions when available * Backport of [AArch64] [1/4] Define candidates for instruction fusion in a .def file * Backport of [AArch64] 1/5 Use atomic instructions for swap and fetch-update operations * Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [2/4] Control the FMA steering pass in tuning structures rather than as core property * Backport of [AArch64] 2/5 Make BIC, other logical instructions, available * Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [3/4] De-const-ify struct tune_params * Backport of [AArch64] 3/5 Add atomic load-operate instructions * Backport of [AArch64] [4/4] Add -moverride tuning command, and wire it up for control of fusion and fma-steering * Backport of [AArch64] 4/5 Use atomic load-operate instructions for fetch-update patterns * Backport of [AArch64] 5/5 Use atomic load-operate instructions for update-fetch patterns * Backport of [AArch64] Add ACLE predefined marcos: __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR * Backport of [AArch64] Add support for ARMv8.1 command line options * Backport of [AArch64] Always register fma_steering pass but gate it on the target option instead * Backport of [AArch64] [armv8.1] Expand +rdma documentation, small changes to march and mcpu text * Backport of [AArch64] --with-arch in config.gcc support "." * Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter * Backport of [AArch64] Fix another ICE with -mgeneral-regs-only * Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp * Backport of [AArch64] fix regrename pass to ensure renamings produce valid insns * Backport of [AArch64] Fix type of *<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern * Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch64] Improve spill code - swap order in shl pattern * Backport of [AArch64] Improve spill code - swap order in shr patterns * Backport of [AArch64] movi type attribute confusion * Backport of [AArch64] Removed unused SLOWMUL target flags * Backport of [AArch64] typo fix in attribute for vst2_lane * Backport of [AArch64] Use conditional negate for abs * Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests * Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when Thumb mode is not supported * Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c * Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should not add -mfloat-abi=soft * Backport of [Testsuite] [AArch32] target attribute cleanup directives * Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn * Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case * Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values * Backport of [Testsuite] Don't specify "dg-do run" explicitly for vect test cases * Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove movw and movt * Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the testsuite is explicitly passing -mfloat-abi=hard * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] Skip tests for inappropriate multilibs * Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Set REG_EQUAL * Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Fix ChangeLog * Backport of [Misc] fix segfault in verify_flow_info() with -dx option * Backport of [Misc] fix typo * Backport of [Misc] Fix typo: Rename insn_reservation cortex_53_advsimd to cortex_a53_advsimd * Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [Misc] [ifcvt Fix typo in comment * Backport of [Misc] [match-and-simplify] fix incorrect code-gen in 'for' pattern * Backport of [Misc] [match-and-simplify] reject expanding operator-list to implicit 'for' * Backport of [Misc] [match-and-simplify] report error for invalid operator-lists * Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) -> (!y ? -x : x) * Backport of [Misc] The comparison in a compare exchange should not take place in VOIDmode * Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn * Backport of [Misc] warn for empty struct -Wc++-compat * Backport of [Misc] [Driver] Wrong C++ paths when configuring with "--with-sysroot=/" * Backport of [Misc] [combine][1/2] Try to simplify before substituting * Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto} * Backport of [Doc] [AArch64] Fix position of -moverride documentation * Backport of [Doc] move (Variable Attributes, Type Attributes) up Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 6 months

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[ACTIVITY] Week 40 #2

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and Reviews - FSF branch merge - AArch64 armv8-1 support backported - Attribute target almost done * Long discussion on infra and stability o Misc (1/10) * Various meetings == Plan == o Complete backports o 2015.10 Snapshot

10 years, 6 months

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[ACTIVITY] 4th - 9th October

by Bernie Ogden

LAVA uinstance for benchmarking - TCWG-396 [3/10] * Long meeting with Renato + LAVA/lab people * Much thinking about the security side * Wrote up rough draft of what I understand the design to be Investigate effectiveness of noise control measures - TCWG-358 [3/10] * Set up new host node * Dealt with one host node crash, one target crash ** Noticed that target was writing logs to tmpfs, changed that so I can investigate next crash * Both sides stayed up through the weekend, hurrah * Some work on data-massaging scripts Misc [4/10] Heavier than usual week mail-wise, plus performance review prep =Plan= Clean up uinstance design, circulate to make sure we're all on same page Look at data from experiments so far Investigate B&B's Debian-building tools

10 years, 6 months

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[ACTIVITY] 5 - 9 October 2015

by Kugan

== Progress == - 1 day off public holiday (2/10) - Upstream patch follow-ups (2/10) * https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html Trying to reproduce 1.cc failure found with Christophe's testing * https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html Committed it and verified this will not happen with linaro-5 branch - Widening pass (TCWG-547) - 4/10 * iterated based on review comments - Misc (2/10) * gcc/bug list * setup vpn to lab == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (1/10) - Removed redundant DefaultCPU in ARMTargetInfo * Buildbots (4/10) - Looong discussions upstream about stability of buildbots - Trial with IFC6410 marginally successfull, still not good enough, aborting - Moved benchmark buildbot to silent (avoid unnecessary spam) - Writing up some docs on current infra and plan * Infrastructure (3/10) - Long internal discussions about stability of TCWG validation - Agreeing on a LAVA micro-instance in TCWG for benchmarks * Background (2/10) - Code review, meetings, discussions, general support, etc. - Checking status of OpenMP on AArch64 (~10 failures out of ~240 tests) == Plan == More stuff...

10 years, 6 months

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[ACTIVITY] 5-9 October 2015

by Christophe Lyon

== Progress == * Infrastructure/validation (3/10) - prototyping a new Jenkins to job properly allocate testers. This raises more questions.... * Backports (1/10) - a few reviews * GCC (3/10) - sent updated patch for vtbX34 AdvSIMD intrinsics - discussed a few regressions * Misc (conf calls, meetings, emails, ...) (3/10) == Next == * Backports reviews * Infrastructure * GCC devs

10 years, 6 months

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[ACTIVITY] 5th October -- 9th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [4/10] After testing, patches are posted upstream. * In order to review one c++ debugging patch, learn some C++ abi, vtable and VTT, etc. Understand gcc dump by -fdump-class-hierarchy. [3/10] * Fix GDB cxx build breakage caused by my patch. [1/10] * Ask the effect of -fstack-check=specific to AArch64 prologue. GDB needs update. [1/10] * Misc, email, meeting. [1/10]. # Plan # * TCWG-162, commit patches if no objections. * TCWG-387, use libopcodes to decode instructions in GDB. -- Yao

10 years, 6 months

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ILP32 is a parity feature to x86_64 (x32)

by Pinski, Andrew

10 years, 6 months

2
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Fw: [Bug target/67877] New: Split stack needs to be support for AARCH64

by Pinski, Andrew

FYI. This is a parity feature with both PowerPC64 and x86_64. Needed to support GCCgo. Note full gold support is needed too. ---------- Forwarded message ---------- From: pinskia at gcc dot gnu.org <gcc-bugzilla(a)gcc.gnu.org> Date: Tue, Oct 6, 2015 at 3:30 PM Subject: [Bug target/67877] New: Split stack needs to be support for AARCH64 To: gcc-bugs(a)gcc.gnu.org https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67877 Bug ID: 67877 Summary: Split stack needs to be support for AARCH64 Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pinskia at gcc dot gnu.org Target Milestone: --- Target: aarch64-linux-gnu* To support gccgo better split stack should be implemented.

10 years, 6 months

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[ACTIVITY] 28th August - 2nd October

by Bernie Ogden

Connect recovery - [2/10] Investigate effectiveness of noise-control measures - TCWG-358 [3/10] * Host node crashed, tried to recover it, failed, started building a new one Jenkins automation - TCWG-348 [3/10] * Everything in place up to first interaction with LAVA kvm * Considered LAVA team's micro-instance proposal Misc [2/10] =Plan= Discuss micro-instance proposal Work on whatever comes out of discussion Finish building new host node, get experiments running again

10 years, 7 months

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[ACTIVITY] 14th - 18th September

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [6/10] * Finished setup, started running experiments * Initial data pretty noisy, more runs needed * Kicked off more runs for week of Connect Ensure that all critical data is logged - TCWG-349 [1/10] * Logged a few more variables, tested, merged * Put down until we have a controlled image build Misc - [3/10]

10 years, 7 months

1
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[ACTIVITY] Week 40

by Yvan Roux

* 2 post-connect days off (4/10) == Progress == o Linaro GCC (3/10) * Backporting armv8-1 support * Dealing with conflicts o Misc (3/10) * Various meetings * Internal report on Connect == Plan == o Backports o Releases process tasks

10 years, 7 months

1
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