- linaro-toolchain - lists.linaro.org

by Bernie Ogden

Implement LAVA jobs for microinstance - TCWG-432 [6/10] * Refactoring to permit sharing of code between uinstance & main instance, as far as possible * Further refactoring for sane submission of bundles without inserting LAVA assumptions in the wrong places * Tested as far as possible in main instance, using light hacks and fakebench Jenkins benchmarking job - TCWG-348 [1/10] * Converted pbl hacks into a sane patch for yaml-to-json.py Controlled image builds - TCWG-360 [1/10] * Submitted aarch64 filesystem build for review * Generated armhf and amd64 filesystems * Started learning how to generate hwpack Misc [2/10] =Plan= Review security with shared uinstance/main instance code Expose more data, benchmarks to bundles Create YAML definition for Jenkins benchmarking job Generate (controlled) hwpack for at least one target, or know what the problems are Write up noise control report (if time) Have another at crashdump (if time, if new kexec patches)

9 years, 11 months

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[ACTIVITY] 9 - 13 November 2015

by Prathamesh Kulkarni

* TCWG-72 (3/10) - divmod transform approved by Richard - builds cleanly on arm-linux-gnueabihf, aarch64-linux-gnu - Investigating segfault with __bdi64_div.c happens when mode == DImode and libval_mode == TImode - Found another segfault on x86 with TImode, on arm TImode is not supported and compiler aborts. Perhaps we should not do the transform when mode is TImode ? - Had a look at expand_binop_twoval_libfunc(). Wrote a similar function to obtain both results but this resulted in infinite loop in emit_libcall_block_1 - Strangely the bug is reproducible only during the build and doesn't trigger when compiled with preprocessed version of bid64_div.c (passing the same set of options). - waiting for upstream comments * TCWG-319 (1/10) - Submitted jobs for fp benchmark on a53, a57 * Misc: - PR66214 appears to have gone (fixed or became latent), that was blocking firefox LTO build with trunk - PR65837 still appears to be present after r230327 * Public Holidays (6/10) - Diwali festival == Next Week == - Continue with TCWG-72, TCWG-319 benchmarking, target hook conversion - Run SPEC2k6 with LTO

9 years, 11 months

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[ACTIVITY] 9-13 November 2015

by Kugan

== Progress == - Widening pass (TCWG-547) - 6/10 * Bootstrapped latest patch on ppc64-linux-gnu, aarch64-linux-gnu and x64-64-linux-gnu. * Regression testing on ppc64-linux-gnu, aarch64-linux-gnu arm64-linux-gnu and x64-64-linux-gnu. * Fixed all of the execution issues * Posted updated patch to the list - Misc (4/10) * Linaro bug 1900 * Continued Looking at LuaJIT code-base * gcc/bug list == Plan == * bug 1900 * Look at implementing LuaJIT for aarch64 * LTO

9 years, 11 months

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Runtime inlining

by Zoltan Kiss

Hi, We have a packaging/linking/optimization problem at LNG, I hope you guys can give us some advice on that. (Cc'ing ODP list in case someone want to add something) We have OpenDataPlane (ODP), an API stretching between userspace applications and hardware SDKs. It's defined in the form of C headers, and we already have several implementations to face SDKs (or whathever is actually controlling the hardware), e.g. linux-generic, a DPDK one etc. And we have applications, like Open vSwitch (OVS), which now is able to work with any ODP platform implementation which implements this API When it comes to packaging, the ideal scenario would be to create one package for the application, e.g. openvswitch.deb, and one for each platform, e.g odp-generic.deb, odp-dpdk.deb. The latter would contain the implementations in the form of a libodp.so file, so the application can dynamically load the actually installed platform's library runtime, with all the benefits of dynamic linking. The trouble is that we have several accessor functions in the API which are very short and __very__ frequently used. The best example is "uint32_t odp_packet_len(odp_packet_t pkt)", which returns the length of the packet. odp_packet_t is an opaque type defined by the implementation, often a pointer to the packet's actual metadata, so the actual function call yields to a simple load from that metadata pointer (+offset). Having it wrapped into a function call brings a significant performance decrease: when forwarding 64 byte packets at 10 Gbps, I got 13.2 Mpps with function calls. When I've inlined that function it brought 13.8 Mpps, that's ~5% difference. And there are a lot of other frequently used short accessor functions with the same problem. But obviously if I inline these functions I break the ABI, and I need to compile the application for each platform (and create packages like openvswitch-odp-dpdk.deb, containing the platform statically linked). I've tried to look around on Google and in gcc manual, but I couldn't find a good solution for this kind of problem. I've checked link time optimization (-flto), but it only helps with static linking. Is there any way to keep the ODP application and platform implementation binaries in separate files while having the performance benefit of inlining? Regards, Zoltan

9 years, 11 months

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[ANNOUNCE] Linaro GCC 5 2015.11 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.11 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn230068 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn230068 * Backport of [Bugfix] [AArch32] fp16 Fix PR 67624 - Incorrect conversion of float Infinity to __fp16 * Backport of [Bugfix] [AArch64] PR 66776 Add cmovdi_insn_uxtw pattern * Backport of [Bugfix] [AArch64] PR rtl-optimization/68106 LRA * Backport of [Bugfix] PR48052 fix testcase * Backport of [Bugfix] PR other/57195 * Backport of [Bugfix] PR rtl-optim/67421 Cost instruction sequences when doing left wide shift * Backport of [Bugfix] PR rtl-optimization/67103 Improve conditional select ops on immediates * Backport of [Bugfix] PR rtl-optimization/67756 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR target/61578 * Backport of [Bugfix] PR tree-optimization/48052 IVOPTS * Backport of [Bugfix] PR tree-optimization/52563 and 62173 IVOPTS * Backport of [Bugfix] PR tree-optimization/64454 * Backport of [Bugfix] PR tree-optimization/66449 * Backport of [AArch32] 1/2 Record FPU features as a bit-set * Backport of [AArch32] 2/2 Use new FPU features representation * Backport of [AArch32] 1/5 Make room for more CPU feature flags * Backport of [AArch32] 2/5 Add feature set definitions * Backport of [AArch32] 3/5 Use new feature set representation * Backport of [AArch32] 4/5 Use features sets for builtins * Backport of [AArch32] 5/5 Move initializer into arm-cores.def and arm-arches.def * Backport of [AArch32] Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtx pattern * Backport of [AArch32] Add missing is_neon_type types * Backport of [AArch32] arm memcpy of aligned data * Backport of [AArch32] Fix arm bootstrap failure due to -Werror=shift-negative-value * Backport of [AArch32] fix vget_lane on big-endian * Backport of [AArch32] Use %wd format for lane printing in bounds_check * Backport of [AArch32/AArch64] 1/15 [FP16] Hide existing float16 intrinsics unless we have a scalar __fp16 type * Backport of [AArch32/AArch64] 2/15 [fp16] float16x4_t intrinsics in arm_neon.h * Backport of [AArch32/AArch64] 3/15 Add V8HFmode and float16x8_t type * Backport of [AArch32/AArch64] 4/15 float16x8_t intrinsics in arm_neon.h * Backport of [AArch32/AArch64] 5/15 Remaining intrinsics * Backport of [AArch32/AArch64] 6/15 Add basic FP16 support * Backport of [AArch32/AArch64] 8/15 Add support for float16x{4,8}_t vectors/builtins * Backport of [AArch32/AArch64] 9/15 vld{2,3,4}{,_lane,_dup}, vcombine, vcreate * Backport of [AArch32/AArch64] 10/15 Implement vcvt_{,high_}f16_f32 * Backport of [AArch32/AArch64] 11/15 vreinterpret(q?), vget_(low|high), vld1(q?)_dup * Backport of [AArch32/AArch64] 12/15 Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix * Backport of [AArch32/AArch64] 13/15 Add float16 tests to advsimd-intrinsics testsuite * Backport of [AArch32/AArch64] 14/15 Add test of vcvt{,_high}_i{f32_f16,f16_f32} * Backport of [AArch32/AArch64] 15/15 Update sourcebuild.texi with testsuite/effective-target hooks * Backport of [AArch64] 1/5 Reimplement aarch64_bitmask_imm * Backport of [AArch64] 2/5 Improve aarch64_internal_mov_immediate by using faster algorithm * Backport of [AArch64] 3/5 Remove dead code * Backport of [AArch64] 4/5 Remove redundant code * Backport of [AArch64] 5/5 Cleanup immediate generation code in aarch64_internal_mov_immediate * Backport of [AArch64] 1/14 Add ident field to struct processor * Backport of [AArch64] 2/14 Refactor arches handling, add arch enum identifier * Backport of [AArch64] 3/14 Refactor option override code * Backport of [AArch64] 4/14 Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769 * Backport of [AArch64] 5/14 Make flag_omit_leaf_frame_pointer intialize to 2. Define and use TARGET_OMIT_LEAF_FRAME * Backport of [AArch64] 6/14 Implement TARGET_OPTION_SAVE/TARGET_OPTION_RESTORE * Backport of [AArch64] 7/14 Implement TARGET_SET_CURRENT_FUNCTION * Backport of [AArch64] 8/14 Implement TARGET_OPTION_VALID_ATTRIBUTE_P * Backport of [AArch64] 9/14 Implement TARGET_CAN_INLINE_P * Backport of [AArch64] 10/14 Implement target pragmas * Backport of [AArch64] 11/14 Re-layout SIMD builtin types on builtin expansion * Backport of [AArch64] 12/14 Target attributes and target pragmas tests * Backport of [AArch64] 13/14 Document AArch64 target attributes and pragmas * Backport of [AArch64] 14/14 Reuse target_option_current_node when passing pragma string to target attribute * Backport of [AArch64] vtbl[34] and vtbx4 * Backport of [AArch64] Add backend aarch64_bfi pattern * Backport of [AArch64] Add csneg3_uxtw_insn pattern * Backport of [AArch64] Add support for 64-bit vector-mode ldp/stp * Backport of [AArch64] Adjust tests to take LSE extension into account * Backport of [AArch64] [array_mode 1/8] Rename vec_store_lanes<mode>_lane to aarch64_vec_store_lanes<mode>_lane * Backport of [AArch64] [array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands * Backport of [AArch64] [array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md * Backport of [AArch64] [array_mode 4/8] Remove EImode * Backport of [AArch64] [array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. * Backport of [AArch64] [array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. * Backport of [AArch64] [array_mode 7/8] Combine the expanders using VSTRUCT:nregs * Backport of [AArch64] [array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P * Backport of [AArch64] Break -mcpu tie between the compiler and assembler * Backport of [AArch64] [expand] Check gimple statement to improve LSHIFT_EXP expand * Backport of [AArch64] Fix FAIL: gcc.target/aarch64/target_attr_crypto_ice_1.c (internal compiler error) * Backport of [AArch64] Fix vcvt_high_f64_f32 and vcvt_figh_f32_f64 intrinsics * Backport of [AArch64] Fix vldX/vstX AdvSIMD intrinsics * Backport of [AArch64] Followup to [AArch64_be] Fix vtbl[34] and vtbx4 * Backport of [AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG * Backport of [AArch64] Handle const address in aarch64_print_operand * Backport of [AArch64] Implement copysign[ds]f3 * Backport of [AArch64] Improve code generation for float16 vector code * Backport of [AArch64] Improve SIMD concatenation with zeroes * Backport of [AArch64] Remove index from AARCH64_FUSION_PAIR * Backport of [AArch64] Remove obsolete comment in aarch64-option-extensions.def * Backport of [AArch64] Remove separate movtf pattern - Use an iterator for all FP modes * Backport of [AArch64] Remove the hack for AARCH64_EXTRA_TUNE_ALL * Backport of [AArch64] TLSLE 1,2 and 3/N * Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook * Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook * Backport of [AArch64] Use logics_imm type for 2nd alternative of *and<mode>3nr_compare0 * Backport of [AArch64] Use popcount_hwi instead of homebrew version * Backport of [Testsuite] Fix race on temp file in gfortran streamio_*.f90 tests * Backport of [Testsuite] Fix race on temp file in gfortran tests * Backport of [Testsuite] Fix typo in vcvt_f16.c testcase * Backport of [Testsuite] Adjust compiling options for gcc.target/arm/unsigned-float.c * Backport of [Testsuite] [AArch32] gcc.target/arm/pr67756.c: Fixed warnings * Backport of [Testsuite] [AArch64] 7/15 Add basic fp16 tests * Backport of [Testsuite] [AArch64] Adjust some arith+compare tests for potentially more aggressive if-conversion * Backport of [Testsuite] [AArch64] Make arm_align_max_stack_pwr.c and arm_align_max_pwr.c compile testcase, instead of execution * Backport of [Testsuite] [AArch64] Mark target_attr_1.c as compile-only * Backport of [testsuite] [AArch64] Remove divisions-to-produce-NaN from vdiv_f.c * Backport of [Testsuite] Add float16 lane_f16_indices tests * Backport of [Testsuite] auto-wipe dump files * Backport of [Testsuite] Clean up effective_target cache * Backport of [Testsuite] Clean up effective_target cache * Backport of [Testsuite] Fix order of dg-do and dg-require-effective-target directives * Backport of [testsuite] gcc.dg/builtins-20.c: Remove undefined behavior * Backport of [Testsuite] gcc.dg/tree-ssa/pr65447.c: Increase searching number * Backport of [Misc] add separate insn sched class for vector LDP & STP * Backport of [Misc] ccorrect ChangeLog dates+address * Backport of [Misc] fix typo in 223858 1/2 * Backport of [Misc] fix typo in 223858 2/2 * Backport of [Misc] Fix bigendian HFmode in native_interpret_real * Backport of [Misc] model load/store multiples properly in autoprefetcher scheduling * Backport of [Misc] Improve auto-increment addressing mode support in IVO by refactoring add candiate logic * Backport of [Misc] Improve bound information in loop niter analysis * Backport of [Misc] Improve conditional select ops on immediates * Backport of [Misc] Improve loop bound info by simplifying conversions in iv base * Backport of [Misc] IVOPS * Backport of [Misc] Look into unnecessary conversion when checking mult_op in get_shiftadd_cost * Backport of [Misc] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] mark libstdc++ tests unsupported if they fail with relocation truncated * Backport of [Misc] Rerun loop-header-copying just before vectorization * Backport of [Misc] Allow PLUS+immediate expression in noce_try_store_flag_constants * Backport of [Doc] Clarify feature modifiers {no,}{fp,simd,crypto} Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

9 years, 11 months

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[ACTIVITY] 9-13 November 2015

by Christophe Lyon

1 day off (Wednesday) (2/10) == Progress == * Validation - Jenkins jobs maintenance & cleanup - comparison of build times between old & new lab - dedicated slave for results comparison works well * GCC - trunk monitoring, reported a few new failures. - high rate of commits before e/o stage1 means lots of patches to check - infrastructure problems in the ST compute farm mean a few false errors needed analysis - looked at bug #1869, (problem with binary toolsets on RHEL6). Made some progress == Next == * Validation: - continue preparation of switch, as dev-01 is now back - improve reporting * GCC: - check Neon tests cleanup - bug #1869 - look at how to send valuable reports to gcc-regression

9 years, 11 months

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[ACTIVITY] 9th -- 13th November

by Yao Qi

* Off on Wed afternoon [1/10]. # Progress # * Fails in gdb.threads/multiple-step-overs.exp, (TCWG-332) [1/10] Patch V2 is posted, pending for review. * TCWG-422, patch is committed. Done. [2/10]. * TCWG-423, patches are ready, being regression tested. [2/10] * TCWG-433, build GDB with -fsanitize=address, and exposes many memory issues. Some of them are fixed. [2/10]. * Upstream patch review, [1/10] * Misc, meeting, [1/10] # Plan # * TCWG-423, Post patches upstream. * Understand ST's jtag probe and help them to make use of multi-arch with GDB. * TCWG-433, Continue fixing memory issues exposed by -fsanitize=address. -- Yao

9 years, 11 months

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Re: [U-Boot] aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi Albert, On Thu, Nov 12, 2015 at 08:20:18AM +0100, Albert ARIBAUD wrote: > Can you provide the target name and commit ID that you are building, > s well as the version of the toolchain that you are building with? > Without being able to reproduce your issue, it's kind of hard to > diagnose it. With the explanation from Ard, I understand the thing now. But thanks for the reply anyway. Shawn

9 years, 11 months

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aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi, I need some help to understand aarch64-linux-gnu-objdump output in .data section as below. It's part of the dump of u-boot image with command 'aarch64-linux-gnu-objdump -D -z u-boot'. Disassembly of section .data: 0000000035039898 <reserved_list>: <snip> 0000000035039948 <init_sequence_f>: 35039948: 00000000 .word 0x00000000 3503994c: 00000000 .word 0x00000000 35039950: 00000000 .word 0x00000000 35039954: 00000000 .word 0x00000000 35039958: 00000000 .word 0x00000000 3503995c: 00000000 .word 0x00000000 35039960: 00000000 .word 0x00000000 35039964: 00000000 .word 0x00000000 35039968: 00000000 .word 0x00000000 3503996c: 00000000 .word 0x00000000 35039970: 00000000 .word 0x00000000 35039974: 00000000 .word 0x00000000 35039978: 00000000 .word 0x00000000 3503997c: 00000000 .word 0x00000000 35039980: 00000000 .word 0x00000000 35039984: 00000000 .word 0x00000000 35039988: 00000000 .word 0x00000000 3503998c: 00000000 .word 0x00000000 35039990: 00000000 .word 0x00000000 35039994: 00000000 .word 0x00000000 35039998: 00000000 .word 0x00000000 3503999c: 00000000 .word 0x00000000 350399a0: 00000000 .word 0x00000000 350399a4: 00000000 .word 0x00000000 350399a8: 00000000 .word 0x00000000 350399ac: 00000000 .word 0x00000000 350399b0: 00000000 .word 0x00000000 350399b4: 00000000 .word 0x00000000 350399b8: 00000000 .word 0x00000000 350399bc: 00000000 .word 0x00000000 350399c0: 00000000 .word 0x00000000 350399c4: 00000000 .word 0x00000000 350399c8: 00000000 .word 0x00000000 350399cc: 00000000 .word 0x00000000 350399d0: 00000000 .word 0x00000000 350399d4: 00000000 .word 0x00000000 350399d8: 00000000 .word 0x00000000 350399dc: 00000000 .word 0x00000000 350399e0: 00000000 .word 0x00000000 350399e4: 00000000 .word 0x00000000 350399e8: 00000000 .word 0x00000000 350399ec: 00000000 .word 0x00000000 350399f0: 00000000 .word 0x00000000 350399f4: 00000000 .word 0x00000000 350399f8: 00000000 .word 0x00000000 350399fc: 00000000 .word 0x00000000 35039a00: 00000000 .word 0x00000000 35039a04: 00000000 .word 0x00000000 35039a08: 00000000 .word 0x00000000 35039a0c: 00000000 .word 0x00000000 35039a10: 00000000 .word 0x00000000 35039a14: 00000000 .word 0x00000000 35039a18: 00000000 .word 0x00000000 35039a1c: 00000000 .word 0x00000000 35039a20: 00000000 .word 0x00000000 35039a24: 00000000 .word 0x00000000 35039a28: 00000000 .word 0x00000000 35039a2c: 00000000 .word 0x00000000 35039a30: 00000000 .word 0x00000000 35039a34: 00000000 .word 0x00000000 35039a38: 00000000 .word 0x00000000 35039a3c: 00000000 .word 0x00000000 35039a40: 00000000 .word 0x00000000 35039a44: 00000000 .word 0x00000000 35039a48: 00000000 .word 0x00000000 35039a4c: 00000000 .word 0x00000000 The init_sequence_f[] is an array defined in U-Boot v2015.04 source common/board_f.c, which holds a bunch of pointers to critical initialization functions that have to be called during boot. Obviously, the array cannot be all zeros like what objdump tells. And I confirmed that by printing the pointers at run-time as below. init_sequence_f[0]: 0000000035004280 init_sequence_f[1]: 00000000350042a8 init_sequence_f[2]: 0000000035004380 init_sequence_f[3]: 00000000350042a0 init_sequence_f[4]: 00000000350044b8 init_sequence_f[5]: 0000000035004388 init_sequence_f[6]: 0000000035029538 init_sequence_f[7]: 000000003500675c init_sequence_f[8]: 000000003500447c init_sequence_f[9]: 000000003501d864 init_sequence_f[10]: 0000000035013778 init_sequence_f[11]: 0000000035004398 init_sequence_f[12]: 0000000035028ab8 init_sequence_f[13]: 0000000035004278 init_sequence_f[14]: 0000000035004270 init_sequence_f[15]: 000000003500445c init_sequence_f[16]: 0000000035001f20 init_sequence_f[17]: 0000000035004574 init_sequence_f[18]: 00000000350042b0 init_sequence_f[19]: 00000000350042c4 init_sequence_f[20]: 00000000350042cc init_sequence_f[21]: 00000000350042f8 init_sequence_f[22]: 00000000350044d4 init_sequence_f[23]: 000000003500430c init_sequence_f[24]: 0000000035004314 init_sequence_f[25]: 0000000035004330 init_sequence_f[26]: 0000000035004390 init_sequence_f[27]: 00000000350045bc init_sequence_f[28]: 0000000035004550 init_sequence_f[29]: 0000000035004518 init_sequence_f[30]: 0000000035004378 init_sequence_f[31]: 0000000035004428 init_sequence_f[32]: 00000000350043f0 Dumping an u-boot image built for 32-bit platform with arm-linux-gnueabi-objdump gives correct pointer values for the same array. 17853c7c <init_sequence_f>: 17853c7c: 17805600 strne r5, [r0, r0, lsl #12] 17853c80: 17805620 strne r5, [r0, r0, lsr #12] 17853c84: 1780574c strne r5, [r0, ip, asr #14] 17853c88: 178007ec strne r0, [r0, ip, ror #15] 17853c8c: 1780583c ; <UNDEFINED> instruction: 0x1780583c 17853c90: 17805834 ; <UNDEFINED> instruction: 0x17805834 17853c94: 1780315c ; <UNDEFINED> instruction: 0x1780315c 17853c98: 178015f4 ; <UNDEFINED> instruction: 0x178015f4 17853c9c: 17800890 ; <UNDEFINED> instruction: 0x17800890 17853ca0: 17801c0c strne r1, [r0, ip, lsl #24] 17853ca4: 178078f8 ; <UNDEFINED> instruction: 0x178078f8 17853ca8: 17805808 strne r5, [r0, r8, lsl #16] 17853cac: 17829564 strne r9, [r2, r4, ror #10] 17853cb0: 17816104 strne r6, [r1, r4, lsl #2] 17853cb4: 1783dea4 strne sp, [r3, r4, lsr #29] 17853cb8: 178055f8 ; <UNDEFINED> instruction: 0x178055f8 17853cbc: 17801a54 ; <UNDEFINED> instruction: 0x17801a54 17853cc0: 17805b4c strne r5, [r0, ip, asr #22] 17853cc4: 178057e0 strne r5, [r0, r0, ror #15] 17853cc8: 178057c8 strne r5, [r0, r8, asr #15] 17853ccc: 17802e20 strne r2, [r0, r0, lsr #28] 17853cd0: 17805910 usada8ne r0, r0, r9, r5 17853cd4: 17805628 strne r5, [r0, r8, lsr #12] 17853cd8: 17805640 strne r5, [r0, r0, asr #12] 17853cdc: 17805678 ; <UNDEFINED> instruction: 0x17805678 17853ce0: 17805680 strne r5, [r0, r0, lsl #13] 17853ce4: 178056b0 ; <UNDEFINED> instruction: 0x178056b0 17853ce8: 17805850 ; <UNDEFINED> instruction: 0x17805850 17853cec: 178056c8 strne r5, [r0, r8, asr #13] 17853cf0: 178056dc ; <UNDEFINED> instruction: 0x178056dc 17853cf4: 178056f8 ; <UNDEFINED> instruction: 0x178056f8 17853cf8: 17805768 strne r5, [r0, r8, ror #14] 17853cfc: 17805950 ; <UNDEFINED> instruction: 0x17805950 17853d00: 178058ec strne r5, [r0, ip, ror #17] 17853d04: 17805894 ; <UNDEFINED> instruction: 0x17805894 17853d08: 17805744 strne r5, [r0, r4, asr #14] 17853d0c: 17805798 ; <UNDEFINED> instruction: 0x17805798 17853d10: 17805770 ; <UNDEFINED> instruction: 0x17805770 17853d14: 00000000 andeq r0, r0, r0 Here are my questions: - Is this only because that ARM 64-bit toolchain doesn't show the real value of the pointers, or there are some linking or run-time magics to get these pointers correct when the binary is actually running? - Is this different behavior between ARM 32-bit and 64-bit toolchain expected? Or did I miss anything on 64-bit toolchain usage? Any hints or comments are much appreciated. Thanks, Shawn

9 years, 11 months

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Re: [lng-odp] Runtime inlining

by Mike Holmes

On 11 November 2015 at 00:45, Savolainen, Petri (Nokia - FI/Espoo) < petri.savolainen(a)nokia.com> wrote: > > > > -----Original Message----- > > From: lng-odp [mailto:lng-odp-bounces@lists.linaro.org] On Behalf Of > > EXT Nicolas Morey-Chaisemartin > > Sent: Tuesday, November 10, 2015 5:13 PM > > To: Zoltan Kiss; linaro-toolchain(a)lists.linaro.org > > Cc: lng-odp > > Subject: Re: [lng-odp] Runtime inlining > > > > As I said in the call last week, the problem is wider than that. > > > > ODP specifies a lot of types but not their sizes, a lot of > > enums/defines (things like ODP_PKTIO_INVALID) but not their value > > either. > > For our port a lot of those values were changed for > > performance/implementation reason. So I'm not even compatible between > > one version of our ODP port and another one. > > > > The only way I can see to solve this is for ODP to fix the size of all > > these types. > > Default/Invalid values are not that easy, as a pointer would have a > > completely different behaviour from structs/bitfields > > > > Nicolas > > > > Type sizes do not need to be fixed in general, but only when an > application is build for binary compatibility (the use case we are talking > here). Binary compatibility and thus the fixed type sizes are defined per > ISA. > > We can e.g. define a configure target (for our reference implementation == > linux-generic) "--binary-compatible=armv8.x" or > "--binary-compatible=x86_64". When you build your application with that > option, "platform dependent" types and constants would be fixed to > pre-defined values specified in (new) ODP API arch files. > > So instead of building against > odp/platform/linux-generic/include/odp/plat/queue_types.h ... > > typedef ODP_HANDLE_T(odp_queue_t); > #define ODP_QUEUE_INVALID _odp_cast_scalar(odp_queue_t, 0) > #define ODP_QUEUE_NAME_LEN 32 > > > ... you'd build against odp/arch/armv8.x/include/odp/queue_types.h ... > With the introduction of odp/arch at the top level I think we should also move platform/linux-generic/arch to the same location > typedef uintptr_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uintptr_t)0) > #define ODP_QUEUE_NAME_LEN 64 > > > ... or odp/arch/x86_64/include/odp/queue_types.h > > typedef uint64_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uint64_t)0xffffffffffffffff) > #define ODP_QUEUE_NAME_LEN 32 > > > For highest performance on a fixed target platform, you'd still build > against the platform directly > > odp/platform/<soc_vendor_xyz>/include/odp/plat/queue_types.h > > typedef xyz_queue_desc_t * odp_queue_t; > #define ODP_QUEUE_INVALID ((xyz_queue_desc_t *)0xdeadbeef) > #define ODP_QUEUE_NAME_LEN 20 > > > -Petri > > > > > _______________________________________________ > lng-odp mailing list > lng-odp(a)lists.linaro.org > https://lists.linaro.org/mailman/listinfo/lng-odp > -- Mike Holmes Technical Manager - Linaro Networking Group Linaro.org <http://www.linaro.org/> *│ *Open source software for ARM SoCs

9 years, 11 months

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[ACTIVITY] 2nd - 6th November

by Bernie Ogden

Holiday [2/10] Juno crash analysis [2/10] * Spent some time fiddling with kexec on AArch64 * Worked in one very specific case * Another patch series is (apparently) coming, will look out for it and try again SPEC-on-Android [2/10] * Supporting Qian on getting this working * Wrote a readme for the repository, fixed a Makefile bug that Qian's cross-compiler happened to tickle Jenkins benchmarking job - TCWG-348 [1/10] * Tested, tidied up pbl hacks to generate JSON * Tested my pbl with Jenkins prototype jobs * A few minor bug fixes/enhancements for pbl LAVA jobs for uinstance - TCWG-432 [1/10] * Reworked jobs to support uinstance, maintaining backward compatibility as far as possible * Started adding support to submit results to bundle stream Misc [2/10] * Debian FS ready to submit * Usual meetings/mail/etc background =Plan= Look at doing pbl hacks properly in Fathi's in-development refactored p-b-l Pull together Jenkins/LAVA/pbl, ready to test when uinstance is available Write up noise control report (If time, if patches land) have another go at crashdump

9 years, 12 months

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[ACTIVITY] Week 44

by Yvan Roux

== Progress == o Linaro GCC (4/10) * Delivered GCC 4.9 2015.10 snapshot * More backports forGCC 5 2015.11 * Many instabilities on Hetzner this week o Upstream work (2/10) * Sanitizing gfortran testsuite o Release tools (2/10) * Added RCs and binaries support to our snapshot.linaro.org publishing job o Misc (2/10) * Various meetings * Some support == Plan == o Track missing backports dependencies o Continue ongoing tasks.

9 years, 12 months

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[Weekly] 02-06 November 2015

by Michael Collison

== This week == * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Determined that vectorizer is failing for all targets that have widening adds with V8HI to V4SI support (aarch64, ia64, powerPC). - Modified test cases to indicate expected failure with wide add V8HI to V4SI support - Patch sent upstream for approval * Bugzilla 68223 - arm_[su]min_cmp pattern fails - Resolved by reverting patch for tcwg-146 as pattern fail in some corner cases. (3/10) - Reverted patch checked in upstream * Misc (1/10) - Conference calls * Illness, November 2nd (2/10) == Next week == - TCWG-317 - Resolve lto big endian failures

9 years, 12 months

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[ACTIVITY] 2-6 November 2015

by Kugan

== Progress == - Leave (2/10) - Widening pass (TCWG-547) - 5/10 * Made the latest changes requested in the review * Fixed bootstrap and bootstrap mis-compare for ppc64-linux-gnu * Making uninitialized variable as anonymous ssa (as asked in review) results in few ICEs. * Posted updated patch for feedback - Misc (3/10) * started looking into LTO status * Looked at LuaJIT for arm * gcc/bug list == Plan == * continue with widening pass based on feedback * Look at implementing LuaJIT for aarch64 * LTO

9 years, 12 months

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[ACTIVITY] 2 - 6 November 2015

by Prathamesh Kulkarni

== This week == * TCWG-72 (6/10) - 5 iterations since the original patch. Changes include: a) Integration into widening_mul patch b) Rewriting the divmod transform so DIVMOD() is placed before the topmost div/mod stmt c) Removed check for widening mode and optab handler check in expand_DIVMOD d) Fixed ICE when constant is one of the operands to div/mod stmt. e) Fixed mis-compilation with a test-case when operands matched but in opposite order. f) Formatting nits and fixed test-cases. - Richard suggested no need to check for post-domination conditions. - Not sure on what condition to gate the transform. Checking for availability of divmod/div/mod is not sufficient because arm defines optab handler for mod which only matches r0 % n where n is constant and power of 2 for other cases it's expanded via divmod libcall thru expand_divmod. We would rather need to check if the template for mod/div gets matched than just to check if optab handler exists. AFAIK this cannot be done during tree-ssa passes. I can think of two approaches: a) Do the transform to DIVMOD representation unconditionally in widening_mul pass. And then in expand_DIVMOD check if the template for mod can be matched. If it does match then undo the transform from DIVMOD to original representation and expand. I am not sure how feasible it is to undo the transform at expansion time, and start expanding the modified cfg. b) Define a new target hook combine_divmod. Default implementation could check for optab handler for div/mod/divmod. and I could override it for arm-backend to additionally check if the second operand is a constant and power of 2 and fail for this case (since we want this to be expanded from modsi3 pattern). Not sure if this is a good idea, I am replicating the information from the modsi3 pattern. If the pattern changes, the hook would also need to be changed. * Convert ASM_FORMAT_PRIVATE_NAME to hook (2/10) * TCWG-319 (1/10) - Bencharmking for patch in progress * Misc (1/10) - Meetings - Sync with Kugan == Next Week == - Continue with TCWG-72 - Complete the patch with build, test and config-builds for ASM_FROMAT_PRIVATE_NAME and submit upstream - Continue benchmarking TCWG-319, TCWG-310

9 years, 12 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (5/10) - Some broken bots, bisecting, etc - Helping a MIPS patch pass on ARM bot * Maintenance (2/10) - SciMark2 seems not to be unstable or slow any more in ARM64 - Some more investigations on Loop Load Elimination - Profiling bigfib on APM and HiKey * Background (3/10) - Code review, meetings, discussions, general support, etc. - Some FOSDEM fiddling - Some power issues

9 years, 12 months

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[ACTIVITY] 2-6 November 2015

by Christophe Lyon

== Progress == * Validation - moved list of unstable tests to a separate repo, to make maintenance easier (TCWG-425) - Jenkins jobs maintenance & cleanup - a few ABE reporting patches - comparison of results between old & new lab * GCC - trunk monitoring, reported a few new failures. - Send patch to fix vqtb[lx][34] intrinsics on aarch64_be * Binutils - Added a Jenkins job to build+check binutils on a variety of configurations: https://ci.linaro.org/view/tcwg-ci/job/tcwg-binutils/ - sent a small patch to fix a bug in the recent STM32L4XX erratum patch == Next == * Validation: - work on the switch to the new lab, once dev-01 is back online - more tuning to avoid deadlocks - re-measure build time on dev-01, to better tune other build jobs

9 years, 12 months

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[ACTIVITY] 2nd - 6th Nov

by Yao Qi

* Two half day off. [2/10] # Progress # * TCWG-332, fails in gdb.threads/multiple-step-overs.exp. [1/10] Testing the simpler approach suggested during the review. * TCWG-387, done. [1/10] GDB patches are pushed in. * TCWG-422, GNU vector extension support in ARM GDB. [2/10] Patches are done, and being tested. * TCWG-423, GNU vector extension support in AArch64 GDB. [2/10] Writing patches. Find more issues for AArch64 that GDB doesn't fully understand the AArch64 calling convention. Need more work here. * Review ARM GDBserver software single step patch. [1/10] * Misc, meeting, email, [1/10] # Plan # * Off on Wed afternoon. * TCWG-422, post patches * TCWG-423, continue. -- Yao

9 years, 12 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.2 2015.11-rc1

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-rc1 Release-Candidate Archives. http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-rc1/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-rc1/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

9 years, 12 months

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GCC performance questions

by Gunnar von Boehn

Dear List, I'm new to this list and have some questions. Looking at the created code of GCC on ARMv8, we noticed some areas where there is room for performance improvements. I assume that these items might already be noticed by you guys. For example: 1) We noticed that when writing typical DGEMM like code, GCC includes unnecessary DUP instruction 2) GCC seems unwilling to use LDP loads 3) For optimal FPU performance on some A57 its needed to interleave instruction working on ODD and EVEN registers GCC seem not properly support this. Here sometimes 100% performance increase could be reached by different instruction interleaving. 4) Some work loops highly benefit of interleaving of FPU instructinons and loads. GCC seems to likes to re-arrange the code so that most or all loads are put on top of the loop. This can reduce the performance of a well written workloop significantly. I have no patches to fix this. But I can produce C- code and ASM output which will show these performance issues. Please tell me what the next recommended step will be now. Are all these items known already, or shall I provide code examples to further explain them? Kind regards Gunnar von Boehn

10 years

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[ACTIVITY] 26-30 October 2015

by Christophe Lyon

== Progress == * Validation - comparing results and build times between the 2 labs - tuning jobs scheduling to avoid deadlocks * GCC trunk monitoring - lots of validation results to check after 1 week of holidays :-) - a few regressions/new failures/wrong tests reported * Backports - a few reviews == Next == * Infrastructure/Validation * GCC dev: try to fix vqtbl intrinsics for aarch64_be before e/o stage1

10 years

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[ANNOUNCE] Linaro GCC 4.9 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 4.9 source package. This snapshot[1] is based on FSF GCC 4.9.4-pre+svn229467 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 4.9.4-pre+svn229467 * Backport of [Bugfix] PR tree-optimization/65735 * Backport of [Bugfix] PR tree-optimization/65177 * Backport of [Bugfix] PR tree-optimization/65048 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years

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[ACTIVITY]

by Renato Golin

== Progress == * Infrastructure (4/10) - Installing Ubuntu on APM (perf works!) - Setting up a HiKey for in-order perf - Helping Milosz with crashing HiKeys * Maintenance (4/10) - Helping ARM with test-suite patches (D14061) - Investigating read-after-read dependency (D13259) * Background (2/10) - Code review, meetings, discussions, general support, etc.

10 years

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[ACTIVITY] Week 43

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and reviews for our GCC 5 2015.11 snapshot * FSF branch merge and needed backports for our GCC 4.9 2015.10 snapshot o Misc (1/10) * Various meetings == Plan == o Complete 4.9 snapshot

10 years

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[ACTIVITY] 26th - 30th October

by Bernie Ogden

Noise control experiments - TCWG-358 [3/10] * Some analysis of data to date Debian filesystem - TCWG-360 [3/10] * Got stuck on LAVA interactions * Now booting-to-LAVA-usability, needs some cleanup and testing with real benchmark runs Benchmarking-via-Jenkins - TCWG-348 [1/10] * Picked back up on understanding that LAVA uinstance is a-coming * Hacked pbl.py (post-build-lava) to generate suitable JSON ** As a bonus, this can work as a CLI job-submission tool =Plan= Holiday Friday (pending approval) Set up crashdumping on my Juno, try to learn why it crashes Finish Debian filesystem Get Jenkins generating and submitting jobs suitable for uinstance Write up noise control report (probably will get bumped to next week)

10 years

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[Weekly] 26-30 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (3/10) - Could not reproduce test failure in qemu - Waiting on feedback from Maxim who is running patch on Linaro validation * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Debugging tree vectorizer to determine why loops with no wide add operations are no longer being vectorized * TCWG 146 - Debugging regression on arm big endian with Linaro 5 branch (2/10) * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures - TCWG-369 - Identify why loops are not being vectorized - TCWG-146 - Resolve big endian failures

10 years

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[ACTIVITY] 26-30 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 / PR43721 (8/10) - Completed writing expand_DIVMOD() and submitted patch upstream - Reworked patch according to Richard Biener's comments. (http://people.linaro.org/~prathamesh.kulkarni/pr43721-patch-v2.diff) - Wrote test-cases. * TCWG-319 (1/10) - Benchmark run without patch complete for "int" benchmarks on a53, a57 - Benchmark run with patch in progress for "int" benchmarks on a53, a57 * Misc (1/10) - Meetings == Next Week == - Continue with TCWG-72, TCWG-310li, TCWG-319 benchmarking

10 years

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[ACTIVITY] 26-30 October 2015

by Yao Qi

# Progress # * TCWG-332, [1/10], patch is posted for review. * TCWG-187, [1/10], looks like a kernel (~3.4) bug on setting VFP registers through ptrace. Fails go away after I upgrade the kernel. * TCWG-387, [2/10], binutils patch is committed, while GDB patches are being reviewed. * TCWG-422, [3/10], Read AAPCS and gcc source code to understand the calling convention. On going. * FSF patch review, [2/10] ** Review patch set "all-stop on top of non-stop for remote". ** Review ARM fast tracepoint patches. ** Reopen PR 15564, as the fail isn't fixed. * Misc, meeting, [1/10] # Plan # * TCWG-422 * Support ST on using AArch64 multi-arch GDB if needed. * Review ARM GDBserver software single step patch. -- Yao

10 years

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[Weekly] 19-23 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (5/10) - Continued to debug big endian/lto failure of four torture tests - Differences in lto vs. non-lto executables showed no significant differences * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Resolved three of six test suite failures * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures by debugging test cases with qemu - TCWG-369 - Resolve remaining test suite failures -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

10 years

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linux ipv4 forward performance issue

by Liu Ting

Hello all, When upgrading meta-linaro/meta-linaro-toolchain from daisy to fido, we faced drastic performance downgrade (-34.06%) on linux ipv4 forwarding. The board is ls1021atwr (ARM Cortex-A7 MPCore compliant with ARMv7-A architecture). We did some investigation, and suspected that it is caused by the toolchain upgrade. Did someone meet similar issue? The detailed toolchain info: https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/fido gcc-linaro-4.9.3-2015.03, glibc-linaro-2.20-2014.11, binutils-linaro-2.25-2015.01 https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/dai… gcc-linaro-4.8.3-2014.04, eglibc-linaro-2.19-r2014.04, binutils-linaro-2.24-r2014.03 thanks. -Ting

10 years

3
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[ACTIVITY] Week 41 - 42

by Yvan Roux

o Week 42 off (10/10) == Progress == o Linaro GCC (9/10) * Completed backports and reviews * Delivered GCC 5 2015.10 snapshot * Completed TCWG 389 (deploy snapshot job) o Misc (1/10) * Various meetings == Plan == o Back to work

10 years

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[ACTIVITY] 19th - 23rd October

by Bernie Ogden

Mustang benchmarking bringup - (no ticket) [2/10] Controlled Debian build - TCWG-360 [1/10] * Constructed filesystem, works OK as chroot * Next step is to boot it Investigate Workload Automation framework - TCWG-361 [1/10] * Seems to basically work * SPEC support dubious Misc * LAVA uinstance background (TCWG-396, < 1/10) * Noise control experiments (TCWG-358, < 1/10) * ARM management duties [2/10]

10 years

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[ACTIVITY] 19 - 23 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (4/10) - wrote new pass to generate "divmod" internal fn. - investigating segfault during expansion of divmod. * TCWG-319 (2/10) - Benchmarking setup - Running INT benchmarks for a53, a57. * TCWG-310 (1/10) - Looked at how peeling occurs - Email discussions * Public Holiday (2/10) * Misc (1/10) - Meetings == Next week == - Submit patch for TCWG-72 upstream - TCWG-319 benchmarking - Convert ASM_FORMAT_PRIVATE_NAME macro to hook. - Continue with TCWG-310

10 years

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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (5/10) - Investigating some LivermoreLoops that don't vectorise - Reducing cases to single specific causes * Background (5/10) - Code review, meetings, discussions, general support, etc. - More code of conduct stuff, license change to Apache 2 - Following up on sanitizers VMA discussion

10 years

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[ACTIVITY] 19 - 23 October 2015

by Yao Qi

* Two days (Tue and Thu) off. [4/10] # Progress # * TCWG-180, patch is committed by Andrew Stubs. [1/10] I review and approve it. * Review patch set "all-stop on top of non-stop for remote". [3/10] Test them on aarch64 and arm. Triage and fix one regression. Review is still on going. * Review patch set "ARM gdbserver software breakpoint". [2/10] Review and approve them. They are preparatory to ARM tracepoint. # Plan # * Patch review. * TCWG-387, Move GDB using libopcodes to decode instructions. -- Yao

10 years

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 5.1 2015.08

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.1-2015.08 Archives. http://releases.linaro.org/components/toolchain/binaries/5.1-2015.08/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. For bugs related to this release please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * 2015.08 * The Linaro GCC 5.1 2015.08 binary toolchain release is based on the Linaro GCC-5.1-2015.08 source archive release <http://releases.linaro.org/components/toolchain/gcc-linaro/5.1-2015.08/>. The major changes contained in 2015.08 over 2015.05 are described in the sections below on 2015.08-rc1 and 2015.08-rc2 . * 2015.08-rc2 * The Linaro 2015.08-rc2 release-candidate binary toolchain is based on the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in how the binary toolchains were built. The compiler itself was not changed. * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are now correctly configured. This was broken in 2015.08-rc1. The cross-compiler targetting armv8l-linux-gnueabihf is now correctly configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8 --with-float=hard --disable-multilib --enable-multiarch. * Glibc’s slibdir and libdir were once again modified to address Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. The following are now the correct locations: libdir=lib/ (linker-scripts and static archives) slibdir=usr/lib/ (shared objects) rtlddir=lib/ (dynamic linker) * 2015.08-rc1 * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now provided. Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A) cross binary toolchain product release and CARD-1637 – Enable Aarch32 (32-bit ARMv8-A) cross binary toolchain product releases , armv8l-linux-gnueabihf targetted toolchains are now available as part of this release-candidate. * Python support in GDB for both Linux and Mingw32 (32-bit windows). Delivered as requested in the linaro-toolchain mailing list post title – windows binary builds with gdb-python enabled?. * Added missing expat support to GDB. This addresses the following linaro-toolchain mailing list post – "Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal targets." * A fix for multilib enablement in baremetal toolchains (as described in ABE Review 6862). * Library Paths are now congruent with older Linaro Toolchain path layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. libdir=lib/ (shared objects) slibdir=usr/lib/ (static libraries) rtlddir=lib/ (dynamic linker) -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years

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Question about the Linaro toolchain version

by Luo Zhenhua

Hi, The default gcc version of Yocto 2.0(Jethro) is 5.2.0, the gcc version in meta-linaro is gcc-4.9.4, may I know if gcc-linaro-4.9.4 will be used for Yocto 2.0 release? when will the linaro gcc be upgraded to gcc-5.x? BTW, can someone please help point out where the Linaro toolchain roadmap can be got? Best Regards, Zhenhua

10 years

3
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[ACTIVITY] 12 - 16 October 2015

by Omair Javaid

== Progress == LLDB development -- Verify LLDB watchpoints on Android Arm and AArch64 targets. [TCWG-405] [4/10] - Ran LLDB testsuite on Nexus5, Nexus 7, Nexus S and Nexus 9 devices. - Started into failing watchpoint tests on all devices. -- Investigate and fix LLDB watchpoints tests that are failing on Android Nexus 9 AArch64 target. [TCWG-405] [5/10] - Debugging of ptrace watchpoint installation code. - Prepared a fix and tested on Nexus 9. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == Further progress on investigating LLDB watchpoint issues on Android Nexus devices. Local testbots setup using new Android Nexus and Arm linux devices.

10 years

1
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[ACTIVITY]

by Renato Golin

== Progress == * Libraries (3/10) - Back investigating libc++ issues in AArch64 buildbot - http://buildmaster.tcwglab.linaro.org/builders/clang-cmake-aarch64-prototype - Trying to solve the rt/unw/c++ library entanglement in the driver * Buildbots (1/10) - Trying to perf an application on APM, but it crashed while - Rebooted it for now, but on the list to migrate to a newer kernel * Background (6/10) - Code review, meetings, discussions, general support, etc. - Laptop playing stupid again, lost a day trying to fix things - New LLVM "code of conduct" sparked a huge discussion

10 years

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[ACTIVITY] 12th - 16th October

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [4/10] * Recovered from a couple more crashes, existing logging sheds no light * Explored the existing data a bit, need more to draw any conclusions Controlled image builds - TCWG-360 [2/10] * Looked into controlled, repeatable debian builds, B&B-style * Got the general shape of it, checking my understanding with Fathi LAVA microinstance - TCWG-396 [1/10] * Sent doc for review, revised it a bit Misc [3/10] * Exported benchmark/results handling rules to a place other Linaro-ans can read them * Updated example LAVA jobs to use tcwg tag (for load balancing purposes) * Meetings, mail, etc =Plan= Generate more noise data, watching out for crashes Produce a candidate Debian image, document how I did it If time, learn about Workload Automation

10 years

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[Weekly] 12 - 16 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (6/10) - Debugging failures on -flto/big endian combination - Wrote code for big endian lane support; failures still exist - Debugging lto to see if optimization is causing failures * TCWG-77 - Transform end of loop conditions to min_expr (1/10) - patch approved, checked in upstream * Misc (1/10) - Conference calls * US Holiday, Monday October 12th (2/10) == Next week == - TCWG-317 - Debug to determine if lto is causing failures

10 years

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[ACTIVITY] 12th - 16th October

by Kugan

== Progress == - Run spec2006 with DS5/Streamline Performance Analyzer (3/10) - Setup DS5 - Setting up client for chromebook which requires kernel rebuild - Widening pass (TCWG-547) - 5/10 * iterated based on review comments * re-wrote GIMPLE_DEBUG handling - Misc (2/10) * gcc/bug list == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years

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[ACTIVITY] 12th - 16th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [1/10] Patches are committed. * TCWG-335, HW breakpoint on 2-byte aligned address, [3/10] patch is tested against most recent kernel. Everything works. Patch is committed. * TCWG-166, Review ARM software breakpoint in GDBserver patches. [1/10] Almost done. * Review various upstream patches. [2/10]. * Misc, [3/10] ** Meeting, ** Write up some slides about recent GDB development, and present them in ARM. # Plan # * TCWG-387, Move GDB using libopcodes to decode instructions. * More upstream patches review. * Two days off on Tue and Thu. Maybe off on Friday too. -- Yao

10 years

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[ANNOUNCE] Linaro GCC 5 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn228499 * Backport of [Bugfix] [AArch32] Fix PR target/29693 * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check * Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane bounds in expand * Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target * Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404 * Backport of [Bugfix] [AArch32] PR target/52144 attribute target (thumb,arm) [2.2/6] * Backport of [Bugfix] [AArch32] PR target/52144 target attributes Clean up arm_option_params_internals macro settings for attribute/pragma targets * Backport of [Bugfix] [AArch32] PR target/65768 * Backport of [Bugfix] [AArch64] PR63870 Neon error messages for vldN_lane/vstN_lane * Backport of [Bugfix] Fix PR66168 * Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765 * Backport of [Bugfix] PR c/49551 * Backport of [Bugfix] PR middle-end/64130 * Backport of [Bugfix] PR middle-end/66726 * Backport of [Bugfix] PR target/65768 Check cost of constants before propagating * Backport of [Bugfix] PR tree-optimization/67043 * Backport of [AArch32] 1-ARM/Thumb target attributes * Backport of [AArch32] 2-ARM/Thumb target attributes * Backport of [AArch32] 3-ARM/Thumb target attributes * Backport of [AArch32] Add ARM/thumb attribute target * Backport of [AArch32] Add ARM/thumb pragma target * Backport of [AArch32] Add TARGET_OPTION_PRINT * Backport of [AArch32] attribute target (thumb,arm) [2.1/6] * Backport of [AArch32] Correct spelling of references to ARMv6KZ * Backport of [AArch32] Fix ChangeLog * Backport of [AArch32] fix date * Backport of [AArch32] Fix static interworking call * Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM * Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT * Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when -mrestrict-it is in place * Backport of [AArch32] Use dmb ish instead of dmb sy for ARM * Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap instructions when available * Backport of [AArch64] [1/4] Define candidates for instruction fusion in a .def file * Backport of [AArch64] 1/5 Use atomic instructions for swap and fetch-update operations * Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [2/4] Control the FMA steering pass in tuning structures rather than as core property * Backport of [AArch64] 2/5 Make BIC, other logical instructions, available * Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [3/4] De-const-ify struct tune_params * Backport of [AArch64] 3/5 Add atomic load-operate instructions * Backport of [AArch64] [4/4] Add -moverride tuning command, and wire it up for control of fusion and fma-steering * Backport of [AArch64] 4/5 Use atomic load-operate instructions for fetch-update patterns * Backport of [AArch64] 5/5 Use atomic load-operate instructions for update-fetch patterns * Backport of [AArch64] Add ACLE predefined marcos: __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR * Backport of [AArch64] Add support for ARMv8.1 command line options * Backport of [AArch64] Always register fma_steering pass but gate it on the target option instead * Backport of [AArch64] [armv8.1] Expand +rdma documentation, small changes to march and mcpu text * Backport of [AArch64] --with-arch in config.gcc support "." * Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter * Backport of [AArch64] Fix another ICE with -mgeneral-regs-only * Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp * Backport of [AArch64] fix regrename pass to ensure renamings produce valid insns * Backport of [AArch64] Fix type of *<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern * Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch64] Improve spill code - swap order in shl pattern * Backport of [AArch64] Improve spill code - swap order in shr patterns * Backport of [AArch64] movi type attribute confusion * Backport of [AArch64] Removed unused SLOWMUL target flags * Backport of [AArch64] typo fix in attribute for vst2_lane * Backport of [AArch64] Use conditional negate for abs * Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests * Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when Thumb mode is not supported * Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c * Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should not add -mfloat-abi=soft * Backport of [Testsuite] [AArch32] target attribute cleanup directives * Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn * Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case * Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values * Backport of [Testsuite] Don't specify "dg-do run" explicitly for vect test cases * Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove movw and movt * Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the testsuite is explicitly passing -mfloat-abi=hard * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] Skip tests for inappropriate multilibs * Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Set REG_EQUAL * Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Fix ChangeLog * Backport of [Misc] fix segfault in verify_flow_info() with -dx option * Backport of [Misc] fix typo * Backport of [Misc] Fix typo: Rename insn_reservation cortex_53_advsimd to cortex_a53_advsimd * Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [Misc] [ifcvt Fix typo in comment * Backport of [Misc] [match-and-simplify] fix incorrect code-gen in 'for' pattern * Backport of [Misc] [match-and-simplify] reject expanding operator-list to implicit 'for' * Backport of [Misc] [match-and-simplify] report error for invalid operator-lists * Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) -> (!y ? -x : x) * Backport of [Misc] The comparison in a compare exchange should not take place in VOIDmode * Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn * Backport of [Misc] warn for empty struct -Wc++-compat * Backport of [Misc] [Driver] Wrong C++ paths when configuring with "--with-sysroot=/" * Backport of [Misc] [combine][1/2] Try to simplify before substituting * Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto} * Backport of [Doc] [AArch64] Fix position of -moverride documentation * Backport of [Doc] move (Variable Attributes, Type Attributes) up Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years

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[ACTIVITY] Week 40 #2

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and Reviews - FSF branch merge - AArch64 armv8-1 support backported - Attribute target almost done * Long discussion on infra and stability o Misc (1/10) * Various meetings == Plan == o Complete backports o 2015.10 Snapshot

10 years

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[ACTIVITY] 4th - 9th October

by Bernie Ogden

LAVA uinstance for benchmarking - TCWG-396 [3/10] * Long meeting with Renato + LAVA/lab people * Much thinking about the security side * Wrote up rough draft of what I understand the design to be Investigate effectiveness of noise control measures - TCWG-358 [3/10] * Set up new host node * Dealt with one host node crash, one target crash ** Noticed that target was writing logs to tmpfs, changed that so I can investigate next crash * Both sides stayed up through the weekend, hurrah * Some work on data-massaging scripts Misc [4/10] Heavier than usual week mail-wise, plus performance review prep =Plan= Clean up uinstance design, circulate to make sure we're all on same page Look at data from experiments so far Investigate B&B's Debian-building tools

10 years

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[ACTIVITY] 5 - 9 October 2015

by Kugan

== Progress == - 1 day off public holiday (2/10) - Upstream patch follow-ups (2/10) * https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html Trying to reproduce 1.cc failure found with Christophe's testing * https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html Committed it and verified this will not happen with linaro-5 branch - Widening pass (TCWG-547) - 4/10 * iterated based on review comments - Misc (2/10) * gcc/bug list * setup vpn to lab == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years

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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (1/10) - Removed redundant DefaultCPU in ARMTargetInfo * Buildbots (4/10) - Looong discussions upstream about stability of buildbots - Trial with IFC6410 marginally successfull, still not good enough, aborting - Moved benchmark buildbot to silent (avoid unnecessary spam) - Writing up some docs on current infra and plan * Infrastructure (3/10) - Long internal discussions about stability of TCWG validation - Agreeing on a LAVA micro-instance in TCWG for benchmarks * Background (2/10) - Code review, meetings, discussions, general support, etc. - Checking status of OpenMP on AArch64 (~10 failures out of ~240 tests) == Plan == More stuff...

10 years

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[ACTIVITY] 5-9 October 2015

by Christophe Lyon

== Progress == * Infrastructure/validation (3/10) - prototyping a new Jenkins to job properly allocate testers. This raises more questions.... * Backports (1/10) - a few reviews * GCC (3/10) - sent updated patch for vtbX34 AdvSIMD intrinsics - discussed a few regressions * Misc (conf calls, meetings, emails, ...) (3/10) == Next == * Backports reviews * Infrastructure * GCC devs

10 years

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[ACTIVITY] 5th October -- 9th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [4/10] After testing, patches are posted upstream. * In order to review one c++ debugging patch, learn some C++ abi, vtable and VTT, etc. Understand gcc dump by -fdump-class-hierarchy. [3/10] * Fix GDB cxx build breakage caused by my patch. [1/10] * Ask the effect of -fstack-check=specific to AArch64 prologue. GDB needs update. [1/10] * Misc, email, meeting. [1/10]. # Plan # * TCWG-162, commit patches if no objections. * TCWG-387, use libopcodes to decode instructions in GDB. -- Yao

10 years

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ILP32 is a parity feature to x86_64 (x32)

by Pinski, Andrew

10 years

2
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Fw: [Bug target/67877] New: Split stack needs to be support for AARCH64

by Pinski, Andrew

FYI. This is a parity feature with both PowerPC64 and x86_64. Needed to support GCCgo. Note full gold support is needed too. ---------- Forwarded message ---------- From: pinskia at gcc dot gnu.org <gcc-bugzilla(a)gcc.gnu.org> Date: Tue, Oct 6, 2015 at 3:30 PM Subject: [Bug target/67877] New: Split stack needs to be support for AARCH64 To: gcc-bugs(a)gcc.gnu.org https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67877 Bug ID: 67877 Summary: Split stack needs to be support for AARCH64 Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pinskia at gcc dot gnu.org Target Milestone: --- Target: aarch64-linux-gnu* To support gccgo better split stack should be implemented.

10 years

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[ACTIVITY] 28th August - 2nd October

by Bernie Ogden

Connect recovery - [2/10] Investigate effectiveness of noise-control measures - TCWG-358 [3/10] * Host node crashed, tried to recover it, failed, started building a new one Jenkins automation - TCWG-348 [3/10] * Everything in place up to first interaction with LAVA kvm * Considered LAVA team's micro-instance proposal Misc [2/10] =Plan= Discuss micro-instance proposal Work on whatever comes out of discussion Finish building new host node, get experiments running again

10 years, 1 month

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[ACTIVITY] 14th - 18th September

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [6/10] * Finished setup, started running experiments * Initial data pretty noisy, more runs needed * Kicked off more runs for week of Connect Ensure that all critical data is logged - TCWG-349 [1/10] * Logged a few more variables, tested, merged * Put down until we have a controlled image build Misc - [3/10]

10 years, 1 month

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[ACTIVITY] Week 40

by Yvan Roux

* 2 post-connect days off (4/10) == Progress == o Linaro GCC (3/10) * Backporting armv8-1 support * Dealing with conflicts o Misc (3/10) * Various meetings * Internal report on Connect == Plan == o Backports o Releases process tasks

10 years, 1 month

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[Weekly] 28 SEPTEMBER - 2 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (4/10) - Patch sent upstream for review - Fixed some failing tree-ssa testcases by modifying 'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate Aarch32 supports vector widening add - Fixed length attributes on patterns in neon.md - Added test cases to ChangeLog - Debugging failures on -flto and arm big endian * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (3/10) - Fixed some failing tree-ssa testcases by modifying 'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate Aarch64 supports vector widening add - Debugging tree-ssa test suite failures * Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10) - Patch checked in upstream on trunk * TCWG-77 - Transform end of loop conditions to min_expr (2/10) - Submitted upstream waiting for final approval - Merged multiple patterns into one pattern in match.md - Rewrote test case to work on all targets * Misc (1/10) - Conference calls == Next week == - Holiday/vacation

10 years, 1 month

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[ACTIVITY] 28 September-2 October 2015

by Kugan

== Progress == - 1 day off recovering from travel and 1 public holiday (4/10) - https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html (1/10) * Approved patch * re-based and retesting before committing - https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html (1/10) * Found a latent issue while testing patches * posted a patch for review - Widening pass (TCWG-547) - 4/10 * Working on review comments == Plan == * Monday public holiday * Post the revised patch for widening pass * commit approved patches

10 years, 1 month

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[ACTIVITY]

by Renato Golin

== Progress == * Monday off (2/10) * Buildbot (6/10) - Investigating sanitizer crash in Thumb2+NEON - Testing IFC6410 with Linaro 15.09 - CPUs good, 1.7GHz on all cores, stable, cool - Not enough space on local (fast) flash - USB stick stable, but slow (3h vs 2h on Chrome 2) - USB disk unstable and slow (power management, etc) - SATA broken, and slow * Infrastructure (1/10) - Discussing LAVA instance in TCWG lab, benchmarks - Playing with D02: corrupted system, but the machine is *fast* * Background (1/10) - Code review, meetings, discussions, general support, etc. == Plan == * More infrastructure meetings * More buildbot work * Whatever...

10 years, 1 month

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[ACTIVITY] 28 September-2 October 2015

by Yao Qi

# Progress # * TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10] Patches V1 are ready for upstream submission, but find opcodes has already interfaces to decode instructions, so decide to use opcodes for aarch64 GDB first. * TCWG-387, one patch exposing one opcode interface is pushed in. [4/10] Switch software single step code for aarch64 to using opcodes interface. Patch is pushed in. Rewriting prologue analyser to use opcode interface too. * TCWG-159, Kernel awareness in GDB. [1/10] Resume the work as Peter Griffin has cycles to do so. We are happy with the plan so far. * Review arm software breakpoint in GDBserver patches. [1/10] * Misc, [2/10] # Plan # * TCWG-387, TCWG-373 -- Yao

10 years, 1 month

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[ACTIVITY] 28 September-2 October 2015

by Christophe Lyon

== Progress == 2 days off (4/10) * Infrastructure/validation: (3/10) further checking of cross-testing results stability on aarch64-linux - found a workaround for a timestamp problem (_Pragma3 testcase) - looked at c11-atomic-exec-5 whose execution time ranges between 1s and 1h :-) - forcing make check to -j8 seems to work well, will work on a nicer improvement * reported and briefly looked at failure in a new libstdc++ test (directory_iterator) on armv5t * Misc (conf calls, meetings, emails, ....) (2/10) * Internal (1/10) - GNU linker patch review

10 years, 1 month

2
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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.1 2015.08-rc2

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain Release-Candidate GCC 5.1-2015.08-rc2 Archives. http://snapshots.linaro.org/components/toolchain/binaries/5.1-2015.08-rc2/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.1-2015.08 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at http:// https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * 2015.08-rc2 * The Linaro 2015.08-rc2 release-candidate binary toolchain is based on the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in how the binary toolchains were built. The compiler itself was not changed. * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are now correctly configured. This was broken in 2015.08-rc1. The cross-compiler targetting armv8l-linux-gnueabihf is now correctly configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8 --with-float=hard --disable-multilib --enable-multiarch. * Glibc’s slibdir and libdir were once again modified to address Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. The following are now the correct locations: libdir=lib/ (linker-scripts and static archives) slibdir=usr/lib/ (shared objects) rtlddir=lib/ (dynamic linker) * 2015.08-rc1 * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now provided. Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A) cross binary toolchain product release and CARD-1637 – Enable Aarch32 (32-bit ARMv8-A) cross binary toolchain product releases , armv8l-linux-gnueabihf targetted toolchains are now available as part of this release-candidate. * Python support in GDB for both Linux and Mingw32 (32-bit windows). Delivered as requested in the linaro-toolchain mailing list post title – windows binary builds with gdb-python enabled?. * Added missing expat support to GDB. This addresses the following linaro-toolchain mailing list post – "Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal targets." * A fix for multilib enablement in baremetal toolchains (as described in ABE Review 6862). * Library Paths are now congruent with older Linaro Toolchain path layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. libdir=lib/ (shared objects) slibdir=usr/lib/ (static libraries) rtlddir=lib/ (dynamic linker)

10 years, 1 month

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbot (2/10) - Investigating sanitizer crash in AArch64 - Found: 247264, reverted 247674 - Other sanitizer crashes * Maintenance (4/10) - More VMA investigations, discussions - More TargetTuple discussions - Investigating BLX bug on ARMv4 (PR24858) * Background (4/10) - Code review, meetings, discussions, general support, etc. - Connect stuff, orchestrating meetings next week == Progress 2 == Connect == Plan == * Look into new kernel for dragon boards * Look into libraries bot, try to upstream it * Continue VMA discussions, prototype

10 years, 1 month

1
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[ACTIVITY] 21th-25th September

by Yao Qi

# Progress # * TCWG-189, Aarch64 fast tracepoint. [2/10] Done. Patches are committed. * TCWG-373, Support displaced stepping on aarch64-linux. [4/10] GDB works basically, still need to refactor and polish the code. * TCWG-374, Test displaced stepping on aarch64-linux. [1/10] Add new tests. * TCWG-166, gdbserver support for tracepoints on ARM. [3/10]. Review patches, play with patches, and investigate on some issues. Ongoing. # Plan # * TCWG-373, TCWG-374, and TCWG-166. -- Yao

10 years, 1 month

1
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problems with gdb in 4.9-2014.09_linux 32-bit

by Sergio R. Caprile

Hello, I'm starting work on an ARM Cortex-A5 platform. I've setup a cross-build environment on Centos 6, my toolchain is gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux since my build system is 32-bits (I don't have 64-bit hardware/OS available). I've written a simple hello_world and managed to compile on my build environment and execute in the target system. However, I can't debug the application. #include <stdio.h> int main(int argc, char **argv) { printf("Hello world! (hola mundo) [v2]\n"); return 0; } [toradex@EL-Toradex Hello_world]$ ~/gcc-linaro/bin/arm-linux-gnueabihf-gcc -g -o Hello_world main.c I've already confirmed that the program to debug runs OK, I've connected via SSH and run it, it just prints a hello message as expected. When I try to debug, I get a SIGSEGV and then the following reports: If I use the provided gdbinit in gcc-linaro/share/gdb/gdbinit, I get the following error: ---------------------------------------------------------------------- /home/toradex/gcc-linaro/share/gdb/gdbinit:6: Error in sourced command file: Python scripting is not supported in this copy of GDB. ---------------------------------------------------------------------- If I don't, then gdb complains it can't locate source files: ---------------------------------------------------------------------- Can't find a source file at "/cbuild/slaves/oorts/crosstool-ng/builds/arm-linux-gnueabihf-linux/.build/src/eglibc-linaro-2.19-2014.08/elf/dl-fini.c" Locate the file or edit the source lookup path to include its location. ---------------------------------------------------------------------- The SIGSEGV occurs before main(), I can't do anything on startup: ---------------------------------------------------------------------- TARGET: ------ root@colibri-vf:~# gdbserver :2345 /home/root/Hello_world BUILD: ----- [toradex@EL-Toradex ~]$ gcc-linaro/bin/arm-linux-gnueabihf-gdb workspace/Hello_world/Debug/Hello_world GNU gdb (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) 7.6.1-2013.10 Copyright (C) 2013 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=i686-build_pc-linux-gnu --target=arm-linux-gnueabihf". For bug reporting instructions, please see: <https://bugs.launchpad.net/gcc-linaro>... Reading symbols from /media/sf_EL-Toradex/Hello_world/Debug/Hello_world...done. (gdb) target remote 192.168.1.6:2345 Remote debugging using 192.168.1.6:2345 Reading symbols from /home/toradex/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/arm-linux-gnueabihf/libc/lib/ld-linux-armhf.so.3...done. Loaded symbols for /home/toradex/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/arm-linux-gnueabihf/libc/lib/ld-linux-armhf.so.3 process_dl_debug (dl_debug=0x0, dl_debug@entry=<error reading variable: Cannot access memory at address 0x34>) at rtld.c:2415 2415 rtld.c: No such file or directory. (gdb) continue Continuing. Program received signal SIGSEGV, Segmentation fault. 0x76fe36f8 in _dl_sort_fini (maps=0x7efff98c, nmaps=0, used=0x0, ns=<optimized out>) at dl-fini.c:70 70 dl-fini.c: No such file or directory. (gdb) ---------------------------------------------------------------------- I do need some help here. Following is what I know how to get out of /proc/mypid/ Thanks. ---------------------------------------------------------------------- AT "ERROR READING VARIABLE" root@colibri-vf:~# cat /proc/438/maps 00010000-00011000 r-xp 00000000 00:0d 15533 /home/root/Hello_world 00020000-00021000 rw-p 00000000 00:0d 15533 /home/root/Hello_world 76fd8000-76ff7000 r-xp 00000000 00:0d 15010 /lib/ld-2.19-2014.04.so 76ffd000-76ffe000 r-xp 00000000 00:00 0 [sigpage] 76ffe000-77000000 rw-p 0001e000 00:0d 15010 /lib/ld-2.19-2014.04.so 7efdf000-7f000000 rw-p 00000000 00:00 0 [stack] ffff0000-ffff1000 r-xp 00000000 00:00 0 [vectors] root@colibri-vf:~# cat /proc/438/stack [<8002b2c4>] ptrace_stop+0x11c/0x214 [<8002c3b8>] get_signal+0x2c8/0x534 [<80011088>] do_signal+0x1a0/0x3ec [<80011468>] do_work_pending+0x90/0xd0 [<8000e5e0>] work_pending+0xc/0x20 [<ffffffff>] 0xffffffff root@colibri-vf:~# cat /proc/438/stat 438 (Hello_world) t 435 438 412 34816 438 1073741824 33 0 0 0 0 0 0 0 20 0 1 0 171447 286720 20 4294967295 65536 66668 2130705728 2130705728 1996328256 0 0 268435456 0 2147660484 0 0 17 0 0 0 0 0 0 132204 132488 135168 2130705997 2130706020 2130706020 2130706405 0 root@colibri-vf:~# cat /proc/438/status Name: Hello_world State: t (tracing stop) Tgid: 438 Ngid: 0 Pid: 438 PPid: 435 TracerPid: 435 Uid: 0 0 0 0 Gid: 0 0 0 0 FDSize: 32 Groups: 0 VmPeak: 304 kB VmSize: 280 kB VmLck: 0 kB VmPin: 0 kB VmHWM: 80 kB VmRSS: 80 kB VmData: 4 kB VmStk: 136 kB VmExe: 4 kB VmLib: 124 kB VmPTE: 6 kB VmSwap: 0 kB Threads: 1 SigQ: 0/819 SigPnd: 0000000000000000 ShdPnd: 0000000000000000 SigBlk: 0000000000000000 SigIgn: 0000000010000000 SigCgt: 0000000000000000 CapInh: 0000000000000000 CapPrm: 0000003fffffffff CapEff: 0000003fffffffff CapBnd: 0000003fffffffff Cpus_allowed: 1 Cpus_allowed_list: 0 voluntary_ctxt_switches: 1 nonvoluntary_ctxt_switches: 0 root@colibri-vf:~# cat /proc/438/syscall 0 0x0 0x0 0x0 0x0 0x0 0x0 0x7efffd40 0x76fd8d40 root@colibri-vf:~# AFTER "CONTINUE", WHEN "SIGSEGV" -------------------------------- root@colibri-vf:~# cat /proc/438/maps 00010000-00011000 r-xp 00000000 00:0d 15533 /home/root/Hello_world 00020000-00021000 rw-p 00000000 00:0d 15533 /home/root/Hello_world 76ea1000-76fca000 r-xp 00000000 00:0d 15031 /lib/libc-2.19-2014.04.so 76fca000-76fd2000 ---p 00129000 00:0d 15031 /lib/libc-2.19-2014.04.so 76fd2000-76fd5000 rw-p 00129000 00:0d 15031 /lib/libc-2.19-2014.04.so 76fd5000-76fd8000 rw-p 00000000 00:00 0 76fd8000-76ff7000 r-xp 00000000 00:0d 15010 /lib/ld-2.19-2014.04.so 76ff7000-76ff8000 rw-p 00000000 00:00 0 76ff8000-76ffc000 r--p 00000000 00:0d 14058 /etc/ld.so.cache 76ffc000-76ffd000 rw-p 00000000 00:00 0 76ffd000-76ffe000 r-xp 00000000 00:00 0 [sigpage] 76ffe000-77000000 rw-p 0001e000 00:0d 15010 /lib/ld-2.19-2014.04.so 7efdf000-7f000000 rw-p 00000000 00:00 0 ffff0000-ffff1000 r-xp 00000000 00:00 0 [vectors] root@colibri-vf:~# cat /proc/438/stack [<8002b2c4>] ptrace_stop+0x11c/0x214 [<8002c3b8>] get_signal+0x2c8/0x534 [<80011088>] do_signal+0x1a0/0x3ec [<80011468>] do_work_pending+0x90/0xd0 [<8000e5e0>] work_pending+0xc/0x20 [<ffffffff>] 0xffffffff root@colibri-vf:~# cat /proc/438/stat 438 (Hello_world) t 435 438 412 34816 438 1073741824 49 0 0 0 0 0 0 0 20 0 1 0 171447 1585152 74 4294967295 65536 66668 2130705728 0 1996371704 0 0 268435456 0 2147660484 0 0 17 0 0 0 0 0 0 132204 132488 135168 2130705997 2130706020 2130706020 2130706405 0 root@colibri-vf:~# cat /proc/438/status Name: Hello_world State: t (tracing stop) Tgid: 438 Ngid: 0 Pid: 438 PPid: 435 TracerPid: 435 Uid: 0 0 0 0 Gid: 0 0 0 0 FDSize: 32 Groups: 0 VmPeak: 1548 kB VmSize: 1548 kB VmLck: 0 kB VmPin: 0 kB VmHWM: 296 kB VmRSS: 296 kB VmData: 24 kB VmStk: 136 kB VmExe: 4 kB VmLib: 1312 kB VmPTE: 6 kB VmSwap: 0 kB Threads: 1 SigQ: 0/819 SigPnd: 0000000000000000 ShdPnd: 0000000000000000 SigBlk: 0000000000000000 SigIgn: 0000000010000000 SigCgt: 0000000000000000 CapInh: 0000000000000000 CapPrm: 0000003fffffffff CapEff: 0000003fffffffff CapBnd: 0000003fffffffff Cpus_allowed: 1 Cpus_allowed_list: 0 voluntary_ctxt_switches: 2 nonvoluntary_ctxt_switches: 1 root@colibri-vf:~# cat /proc/438/syscall 0 0xffffffff 0x1934 0x76ffed90 0x76ea1000 0x0 0x0 0x0 0x76fe36f8 root@colibri-vf:~# --

10 years, 1 month

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[ACTIVITY] 14th-18th September

by Yao Qi

# Progress # * TCWG-188, aarch64 GDB multi-arch support. [2/10] All patches went upstream except that one is blocked by kernel patch. The work is done! * TCWG-189, aarch64 fast tracepoint support. [2/10] Update them and post V2 out. Pending for review. * TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10] Think about it, and break it into pieces. Refactor fast tracepoint code so that some can be reused for displaced stepping. * TCWG-375, Don't skip gdb.asm/asm-source.exp on aarch64. [1/10] Patch is pushed in. * TCWG-166, Review arm tracepoint patches from Ericsson upstream. [1/10] May have something wrong for permanent breakpoint on thumb code. Need to figure out a case to trigger that. * Misc, meeting and training. [2/10] # Plan # * TCWG-189, TCWG-373, TCWG-166. -- Yao

10 years, 1 month

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[ANNOUNCE] Linaro GCC 5 2015.09 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.09 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn227732 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn227732 * Backport of [Bugfix] [AArch32] PR target/26702 * Backport of [Bugfix] [AArch32] PR target/26702 * Backport of [Bugfix] [AArch32] PR rtl-optimization/34503 * Backport of [Bugfix] [AArch32] PR target/64208 iwmmxt pattern * Backport of [Bugfix] [AArch32] PR target/65924 * Backport of [Bugfix] [AArch64] PR 65770 vstN_lane on bigendian * Backport of [Bugfix] [AArch64] PR 65375 Fix RTX cost for vector SET * Backport of [Bugfix] [AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types * Backport of [Bugfix] [AArch64] PR target/66049 * Backport of [Bugfix] [AArch64] PR 63949 * Backport of [Bugfix] PR rtl-optimization/64616 Move insns without introducing new temporaries in loop2_invariant * Backport of [Bugfix] PR rtl-optimization/66076 * Backport of [Bugfix] PR tree-optimization/65447 * Backport of [AArch32] Add cpu_defines.h for ARM * Backport of [AArch32] Additional bics patterns * Backport of [AArch32] Add support for CFI directives in fp emulation routines for ARM * Backport of [AArch32] Add support for crtfastmath * Backport of [AArch32] Apply arm.h change for previous commit * Backport of [AArch32] (*arm_subsi3_insn): Fixed redundant alternatives * Backport of [AArch32] Fix up bootstrap and fix typo in related changelog entry * Backport of [AArch32] Handle UNSPEC_VOLATILE in rtx costs and don't recurse inside the unspec * Backport of [AArch32] insns attributes and alternative cleanups * Backport of [AArch32] Make tune params tables more self-documenting * Backport of [AArch32] Remove vec_shr and vec_shr optabs * Backport of [AArch32] Use uppercase for code iterator names * Backport of [AArch64] Add alternative 'extr' pattern, calculate rtx cost properly * Backport of [AArch64] Add branch-cost to cpu tuning information * Backport of [AArch64] Add __extension__ and __always_inline__ to crypto intrinsics * Backport of [AArch64] Add vcond(u?)didi pattern * Backport of [AArch64] Fix aarch64_rtx_costs of PLUS/MINUS * Backport of [AArch64] Fix Cortex-A53 shift costs * Backport of [AArch64] Fix geniterators.sh to use standard BRE syntax in sed * Backport of [AArch64] Fix up new line in previous commit * Backport of [AArch64] Handle FLOAT and UNSIGNED_FLOAT in rtx costs * Backport of [AArch64] Idiomatic 64x1 comparisons in arm_neon.h * Backport of [AArch64] Implement -m{cpu,tune,arch}=native using only /proc/cpuinfo * Backport of [AArch64] In aarch64_class_max_nregs use UNITS_PER_VREG and UNITS_PER_WORD * Backport of [AArch64] Make aarch64_min_divisions_for_recip_mul configurable * Backport of [AArch64] Properly cost FABD pattern * Backport of [AArch64] Properly cost MNEG/[SU]MNEGL patterns * Backport of [AArch64] Properly handle mvn-register and add EON+shift pattern and cost appropriately * Backport of [AArch64] Properly handle SHIFT ops and EXTEND in aarch64_rtx_mult_cost * Backport of [AArch64] Remember to cost operand 0 in FP compare-with-0.0 case * Backport of [AArch64] Use extend_arith rtx cost appropriately * Backport of [AArch64] Use mov for add with large immediate * Backport of [AArch64] Fix a couple of bugs regarding loop invariant motion discovered by spec2k6 on aarch64 * Backport of [Musl libc] Add musl support to GCC * Backport of [Musl libc] libitm fixes for musl support * Backport of [Musl libc] musl libc config * Backport of [Musl libc] mips musl support * Backport of [Musl libc] unwind fix for musl * Backport of [Musl libc] libstdc++, libgfortran gthr workaround for musl * Backport of [Musl libc] fixincludes update for musl support * Backport of [Musl libc] [AArch32] [4/13] arm musl support * Backport of [Musl libc] [AArch64] [3/13] aarch64 musl support * Backport of [Testsuite] [AArch32] advsimd-intrinsics.exp: dg-do-what=compile if HW does not have Neon * Backport of [Testsuite] [AArch32] Fix test for pr64616 * Backport of [Testsuite] [AArch32] Require Thumb2 effective target * Backport of [Testsuite] [AArch32] Fix r222371 (PR target/26702) * Backport of [Testsuite] Cleanup advsimd-intrinsics.exp, removing unnecessary loop * Backport of [Testsuite] don't clobber dg-do-what-default in advsimd-intrinsics.exp * Backport of [Testsuite] don't try to execute simd.exp tests on targets without NEON * Backport of [Testsuite] move check-gcc parallelize value into C front end * Backport of [Testsuite] new vqmovn test * Backport of [Testsuite] new vqmovun test * Backport of [Testsuite] new vqrdmulh_lane test * Backport of [Testsuite] new vqrdmulh_n test * Backport of [Testsuite] new vqrdmulh test * Backport of [Testsuite] new vqrshl test * Backport of [Testsuite] new vqrshn_n test * Backport of [Testsuite] new vqrshun_n test * Backport of [Testsuite] new vqshl_n test * Backport of [Testsuite] new vqshl test * Backport of [Testsuite] new vqshlu_n test * Backport of [Testsuite] new vqshrn_n test * Backport of [Testsuite] new vqshrun_n test * Backport of [Testsuite] Reinstate torture-init and torture-finalize in advsimd-intrinsics.exp * Backport of [Misc] Try REG_EQUAL for nonzero_bits * Backport of [Misc] Don't reset ssa_name infor in struct iv * Backport of [Misc] make clean' fix * Backport of [Misc] Make vector_compare_rtx cope with VOID mode constants * Backport of [Misc] set_nonzero_bits_and_sign_copies/combine.c * Backport of [Misc] Expand pow (x, CONST) using square roots when possible * Backport of [Doc] [AArch32] (ARM Options, mtune): add missing entries * Backport of [Doc] Add missing jit and lto info..... * Backport of [Doc] Declaring Attributes of Functions/split by target * Backport of [Doc] reorganize (Type Attributes) and (Variable Attributes) * Backport of [Doc] Update __atomic builtins documentation * Backport of [Doc] Update definition location of attribute_spec in documentation Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list":http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product:http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support":mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 1 month

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[ACTIVITY] 7th-11th September

by Bernie Ogden

Ensure all critical (benchmarking) data is logged - TCWG-349 [1/10] * Added logging of several factors * Documented what we do and don't log Noise control experiments on Juno - TCWG-349 [4/10] * Rediscovered that my Juno is an r0, not an r1 * Rebuilt target image in a carefully scripted way * Fiddled about with differences between local and LAVA targets * Ran a couple of trials to test infrastructure Connect preparation - [2/10] * General sorting out of tickets et al * Final pass through benchmarking presentation Misc - [3/10] =Plan= Merge 'logging' branch Final pass through logging documentation Run some noise experiments on Juno If time, work on Jenkins benchmarking jobs

10 years, 1 month

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[ACTIVITY] 7 - 11 September 2015

by Omair Javaid

== Progress == LLDB development -- Progress to add support for un-alinged watchpoints on AArch64 [TCWG-367] [5/10] -- Truncating watched bits wasnt accepted as a solution, will look into issues during connect. -- Trying to figure out a way to use multiple watchpoint slots for a single watchpoint. Miscellaneous [1/10] -- Meetings, emails, discussions etc. -- Travel preparations Holiday 10 - 11 September 2015 - Travelling to US == Plan == Holiday 14 - 18 September 2015 Connect 21 - 25 September 2015 Holiday 28 September - 5th October 2015

10 years, 1 month

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Building for armv6/ARM1136J-S using ABE

by Bill Davis

Hi, I've tried probably a dozen different ABE build command lines with various combinations of cpu/arch/tune on the latest tree and on the 2014.09 release and am unable to build for the armv6/1136J-S. Before bothering the list, I scoured the gzipped archive back through 2013, and there is little mention of any problems OR successes with armv6. I am wondering if armv6 is supported, and if so, what is the secret sauce ABE command line to build successfully for the 1136J-S. Some of the builds I tried were missing tarball components, others fail later on such as the one below that gets through building gcc and bombs building the eabi. -------------------- 'abe.sh -target arm-linux-gnueabi -build all -set cpu=arm1136j-s' produces the following, see further below for the gcc version data: arm-linux-gnueabi-gcc ../sysdeps/arm/aeabi_memclr.c -c -std=gnu99 -fgnu89-inline -O2 -Wall -Werror -Winline -Wno-error=undef -Wundef -Wwrite-strings -fmerge-all-constants -frounding-math -g -Wstrict-prototypes -I../include -I/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu -I/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master -I../sysdeps/unix/sysv/linux/arm -I../sysdeps/arm/nptl -I../sysdeps/unix/sysv/linux/include -I../sysdeps/unix/sysv/linux -I../sysdeps/nptl -I../sysdeps/pthread -I../sysdeps/gnu -I../sysdeps/unix/inet -I../sysdeps/unix/sysv -I../sysdeps/unix/arm -I../sysdeps/unix -I../sysdeps/posix -I../sysdeps/arm/armv6 -I../sysdeps/arm/include -I../sysdeps/arm -I../sysdeps/wordsize-32 -I../sysdeps/ieee754/flt-32 -I../sysdeps/ieee754/dbl-64 -I../sysdeps/ieee754 -I../sysdeps/generic -I.. -I../libio -I. -nostdinc -isystem /home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/lib/gcc/arm-linux-gnueabi/5.1.1/include -isystem /home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/lib/gcc/arm-linux-gnueabi/5.1.1/include-fixed -isystem /home/billd/_build/sysroots/arm-linux-gnueabi/usr/include -D_LIBC_REENTRANT -include /home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/libc-modules.h -DMODULE_NAME=libc -include ../include/libc-symbols.h -o /home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o -MD -MP -MF /home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o.dt -MT /home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o /tmp/ccTT8UgL.s: Assembler messages: /tmp/ccTT8UgL.s:492: Error: lo register required -- `add pc,r3,#(0xffff0fc0-0xffff0fff)' /tmp/ccTT8UgL.s:490: Error: invalid immediate: -61441 is out of range make[2]: *** [/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/libc-start.o] Error 1 --- here is the gcc -v output for the build above. ---- ./arm-linux-gnueabi-gcc -v Using built-in specs. COLLECT_GCC=./arm-linux-gnueabi-gcc COLLECT_LTO_WRAPPER=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/libexec/gcc/arm-linux-gnueabi/5.1.1/lto-wrapper Target: arm-linux-gnueabi Configured with: '/home/billd/_build/snapshots/gcc.git~linaro-gcc-5-branch/configure' SHELL=/bin/bash --with-bugurl=https://bugs.linaro.org --with-mpc=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu --with-mpfr=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gmp=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu --with-gnu-as --with-gnu-ld --disable-libstdcxx-pch --disable-libmudflap --with-cpu=arm1136j-s --with-cloog=no --with-ppl=no --with-isl=no --disable-nls --enable-c99 --with-fpu=vfpv3-d16 --with-float=softfp --with-mode=thumb --disable-multilib --enable-multiarch --disable-libssp --disable-libquadmath --disable-threads --without-headers --with-newlib --disable-libmudflap --disable-bootstrap --disable-decimal-float --disable-libgomp --disable-libatomic --disable-libsanitizer --disable-plugins --disable-libitm MAKEINFO=echo --enable-languages=c --with-sysroot=/home/billd/_build/builds/sysroot-arm-linux-gnueabi --disable-shared --with-glibc-version=2.18 --build=x86_64-unknown-linux-gnu --host=x86_64-unknown-linux-gnu --target=arm-linux-gnueabi --prefix=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu Thread model: single gcc version 5.1.1 20150608 (Linaro GCC 5.1-2015.06-1~dev)

10 years, 1 month

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[ACTIVITY] Week 37

by Yvan Roux

== Progress == o Linaro GCC validation (8/10) * Finished on-going backports validation * Still dealing with jenkins/infra instability * Prepared branch merge * Continue on my new reviewing/validation tool o Misc (2/10) * Various meetings * AArch64 libunwind patch review == Plan == o Finish branch merge o GCC snapshot o Travel to SFO'15

10 years, 1 month

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[ACTIVITY] 7-11 September 2015

by Christophe Lyon

== Progress == * GCC (4/10) - AdvSIMD failures on aarch64_be: looking at tbl[34] intrinsics * Releases/snapshots/validation (3/10) * Misc (3/10) - meetings, conf-calls, emails - Connect preparation == Next == * GCC aarch64_be AdvSIMD * Validation / reviews / backports * Connect preparation

10 years, 1 month

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[Weekly] 07-11 SEPTEMBER 2015

by Michael Collison

== This week == * TCWG-316 -Exploit vector multiply by scalar instructions when multiple scalars are used as coefficients in a loop (5/10) - Wrote patterns to allow combine pass to mergenon-standard multiply by lane patterns. * Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10) - Updated patch based on upstream comments and re-sent upstream * TCWG-77 - Transform end of loop conditions to min_expr (1/10) - Writing dejagnu test case. - Writing function to check for min expr support on target * Misc (1/10) - Conference calls * Holiday (2/10) == Next week == - Complete TCWG-77 and send upstream - Continued investigation into TCWG-316

10 years, 1 month

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[activity] 07 - 11 Sep 2015

by Prathamesh Kulkarni

== This week == * TCWG-80 (1/10) - PRE and dead-store elimination ipa pass (WIP upstream) already handles optimization * TCWG-120 (2/10) - Investigating 3 possible approaches: a) fold arm_andsi3_insn/arm_cmpsi_insn to zeroextractsi_compare0_scratch/andsi3_compare0_scratch b) Undo cse in test conditions, and modify arm_rtx_costs to fold arm_andsi3_insn/arm_cmpsi_insn to zeroextractsi_compare0_scratch/andsi3_compare0_scratch c) Expand directly to zeroextractsi_compare0_scratch/andsi3_compare0_scratch - Not sure whether the generated assembly is better (in terms of speed) than with trunk. asm diff at -O1: http://pastebin.com/yXBHHkhM * TCWG-72 (2/10) - Rebased Kugan's patch * TCWG-299 (3/10) - Simple workaround for PR65837 - configure gcc with --with-fpu=neon - Firefox trunk doesn't build with gcc for arm, using apt-get source firefox - LTO build fails with out-of-memory on my laptop in qemu-arm chroot * TCWG-319 (1/10) - Benchmarking setup with Bernie on Juno for running SPEC. - SPEC Runs without error on Juno-{a53,a57} and APM * Misc (1/10) - Meetings == Next Week == - Continue with TCWG-120, TCWG-72, TCWG-319

10 years, 1 month

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Missing expat support in GDB 7.8

by Andreas Schmidl

Hi! The pre-built version of the stable version of Linaro Toolchain (Linaro GDB 2015.02-3) for Windows is shipped with GDB 7.8-2014.09-1-git. GDB was built with the following options: (gdb) show configuration This GDB was configured as follows: configure --host=i686-w64-mingw32 --target=arm-linux-gnueabihf --with-auto-load-dir=$debugdir:$datadir/auto-load --with-auto-load-safe-path=$debugdir:$datadir/auto-load --without-expat --with-gdb-datadir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/share/gdb (relocatable) --with-jit-reader-dir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/lib/gdb (relocatable) --without-libunwind-ia64 --without-lzma --without-guile --with-separate-debug-dir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/lib/debug (relocatable) --without-zlib --without-babeltrace As you can see in the output GDB was built without expat support. This is a major problem for widely used micro controllers like ARM Cortex A8 (e.g. used in Beaglebone Black), because the technical description of this microcontroller is loaded out of xml files (arm-with-neon.xml part of GDB). It's also possible to do that manually with "set tdesc filename <xml-file>, before connecting to the target. Without having the expat option enabled the g package, which is sent from gdbserver during establishing a connection to gdb, can't be parsed correctly. The result is in the first step a warning because of the missing xml support and later on a error regarding the unexpected content of the g package: warning: Can not parse XML target description; XML support was disabled at compile time Remote 'g' packet reply is too long: 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0fcffbe00000000407afdb6300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Old GDB versions of Linaro Toolchain like 7.6.1-2013.10 doesn't have that problem because they were compiled with enabled expat support. In my opinion there can be two root causes regarding that missing expat support: a) Expat support was explicitly disabled with --without-expat option during the built of GDB. b) On the build machine there wasn't a expat library available when gdb was built. Best regards, Andreas Schmidl

10 years, 1 month

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[ACTIVITY]

by Renato Golin

== Progress == * Libraries (1/10) - Working on getting the libc++ tests green * Maintenance (6/10) - Working with Vinicius on the gnueabi memcpy issue - More TargetTuple/TargetParser discussions - More sanitizers discussions, patch reviews * Background (3/10) - Code review, meetings, discussions, general support, etc. - Connect stuff == Plan == * Look a bit more on the library issues, try to upstream the bot changes * Check instability in SciMark2 * Change HD from a D01 * Continue discussion about the sanitizer's multiple VMA problem * Prepare for Connect, travel arrangements, etc.

10 years, 1 month

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[ACTIVITY] 07 Sep -- 11 Sep

by Yao Qi

# Progress # * TCWG-857, [7/10] One patch is upstreamed. The rest of them are in the queue. Upgrade juno board linux kernel to 4.2.0-rc4+ to test some multi-arch kernel patches. It isn't easy to run that new kernel on juno board, takes much time on this. * Misc [3/10]. Meetings, online trainings, etc. # Plan # * Continue to upstream multi-arch patches. * Some upstream patch reviews on tracepoint. -- Yao

10 years, 1 month

1
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help: cortex-a7 u-boot hang at pcie with gcc-linaro-4.9

by Liu Ting

Hello guys, I am newbie here and need your kindly help:) When trying to use gcc-linaro-4.9 to build u-boot for ls1021atwr (ARM Cortex-A7 MPCore compliant with ARMv7-A architecture), we face issue. U-boot hangs at PCI-E. After tracing the code, the issue is located at the line "*val = readl(addr);". u-boot/drivers/pci/pcie_layerscape.c: ls_pcie_read_config(): if (PCI_BUS(d) == hose->first_busno) { ... } else { ... if (PCI_BUS(d) == hose->first_busno + 1) { #PCI_BUS(d) 1, hose->first_busno 0 ls_pcie_cfg0_set_busdev(pcie, busdev); addr = pcie->va_cfg0 + (where & ~0x3); #pcie->va_cfg0 0x24000000, where 0xc } else { .... } } *val = readl(addr); The gcc source we used is gcc-linaro-4.9-2015.02.tar.xz<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/gcc-l…> (link<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/>) which is based on FSF GCC 4.9.3-pre+svn220525. Meanwhile, gcc-linaro-4.9-2015.01.tar.xz<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/gcc-l…> does not have this issue. After Bisecting, we tracked down a gcc commit: https://git.linaro.org/toolchain/gcc.git/commitdiff/e4f9e85e8152379aef37377… 2015-01-23 Jakub Jelinek <jakub(a)redhat.com> PR rtl-optimization/63637 PR rtl-optimization/60663 * cse.c (merge_equiv_classes): Set new_elt->cost to MAX_COST if elt->cost is MAX_COST for ASM_OPERANDS. (find_sets_in_insn): Fix up comment typo. (cse_insn): Don't set src_volatile for all non-volatile ASM_OPERANDS in PARALLELs, but just those with multiple outputs or with "memory" clobber. Set elt->cost to MAX_COST for ASM_OPERANDS in PARALLEL. Set src_elt->cost to MAX_COST if new_src is ASM_OPERANDS and elt->cost is MAX_COST. * gcc.dg/pr63637-1.c: New test. * gcc.dg/pr63637-2.c: New test. * gcc.dg/pr63637-3.c: New test. * gcc.dg/pr63637-4.c: New test. * gcc.dg/pr63637-5.c: New test. * gcc.dg/pr63637-6.c: New test. * gcc.target/i386/pr63637-1.c: New test. * gcc.target/i386/pr63637-2.c: New test. * gcc.target/i386/pr63637-3.c: New test. * gcc.target/i386/pr63637-4.c: New test. * gcc.target/i386/pr63637-5.c: New test. * gcc.target/i386/pr63637-6.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@220323 138bc75d<https://git.linaro.org/toolchain/gcc.git/object/138bc75d>-0d04-0410-961f-82ee72b054a4<https://git.linaro.org/toolchain/gcc.git/object/82ee72b054a4> Before this commit, u-boot can boot up. So any hint/suggestion? if more details needed, please feel free to tell us. Thank you in advance. -Ting

10 years, 1 month

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[ACTIVITY] 31 August - 4 September 2015

by Omair Javaid

== Progress == LLDB development -- Testing and bug fixing lldb on hikey AArch64 [TCWG-231] [4/10] -- Looking into multi-threaded watchpoint test failures on AArch64 highkey board. -- Fixed watchpoint installation lag and unexpected behaviour. Submitted http://reviews.llvm.org/D12522 -- Start work to add support for un-alinged watchpoints on AArch64 [TCWG-367] [3/10] Miscellaneous [3/10] -- Meetings, emails, discussions etc. -- Laptop LCD screen malfunctioned, found a temporary replacement. == Plan == LLDB development -- Progress towards un-allinged watchpoint support on AArch64 LLDB -- Fix broken parts of LLDB testsuite on AArch64.

10 years, 1 month

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[ACTIVITY] Week 36

by Yvan Roux

== Progress == o Linaro GCC validation (8/10) * Reviewed, validated and committed more backports * New stability issues after executor number increased * Started to script branch merge * Developed a new tool to avoid wasting time in gerrit/jenkins/logs navigation o Upstream GCC (1/10) * Looked at and updated some bugzillas o Misc (1/10) * Various meetings == Plan == o Continue backports/validation/branch merge

10 years, 1 month

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[ACTIVITY] 31th Aug - 04th Sep

by Kugan

== Progress == * Widening pass (TCWG-547) – 6/10 - Looked at “Error: unaligned opcodes detected in executable segment” * Spent lot of time trying to understand the root cause. * Got some suggestions from Jim and looking into it. - Posted some of the important patches for review. * https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00399.html * https://bugs.linaro.org/show_bug.cgi?id=1318 (2/10) - Tried reproducing with the source provided without success. - Could build and reproduce with emacs-24.4 release. - Trunk GCC version 6.0.0 20150902 works. - GCC version 4.9.3 20150209 (Linaro GCC 4.9-2015.02) fails. * Misc - 2/10 - gcc-patches, gcc-bugs list == Plan == * Continue with widening pass * Fix Bug1318

10 years, 1 month

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[ACTIVITY] 31st August - 4th September

by Bernie Ogden

Holiday [4/10] Multinode wrapper - TCWG-350 [2/10] * Merged to benchmarking branch, roughly documented * Tested & added job definition templates Setting up VPN [2/10] * Much struggling with mutt, pgp, VM vs real system, Mac vs Linux * Still not working, but wrote up what I've learned on the Collaborate page Misc [2/10] * ARM admin, meetings, mail, etc etc =Plan= Last pass through benchmarking presentation Finish multinode/updating benchmarking docs Back to Juno noise control experiments Back to Jenkins - get it to drive multinode

10 years, 1 month

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[ACTIVITY] 24th - 28th August

by Bernie Ogden

(Reporting with new Jira numbers) Holiday [6/10] Investigate effectiveness of noise control - TCWG-358 [2/10] * Learned to build OE filesystems * Got Juno running with more or less provenance-tracked firmware, kernel, filesystem Misc - [2/10] * Pushed through some updates to benchmark sources * Struggled with Collaborate permissions to share source/results handling rules * Remaining multinode tests passed

10 years, 1 month

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[Weekly] 31 AUGUST - 04 SEPTEMBER 2015

by Michael Collison

== This week == * TCWG-832 -Exploit vector multiply by scalar instructions when multiple scalars are used as coefficients in a loop (4/10) - Continued investigation. * TCWG-833 - Exploit Wide Add operations when appropriate (4/10) - Reworked Aarch64 patch to avoid redundant moves - Sent patch upstream for review - Debugging Aarch64 tree-dump regression suite failures - Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10) - Separated patch from Bugzilla 67321 patch and sent upstream - Pinged upstream for comments * Misc (1/10) - Conference calls == Next week == - USA Labor day holiday, September 7th - Additional investigation into TCWG-832

10 years, 1 month

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[ACTIVITY] 31st August - 04 September 2015

by Prathamesh Kulkarni

== This Week == * TCWG-120 (8/10) - Resolved df issue in my patch, sent to tcwg list for review, - VRP makes the issue latent at -O2. Reproducible with -fno-tree-vrp - Taking another approach to run a "specialized" combine pass before combine pass that folds arm_andsi3_insn/arm_cmpsi_insn to zeroextracsi_compare0_scratch or andsi3_compare0_scratch without relying on combine. Patch: http://pastebin.com/gLVg7pbN Asm diff at -O1: http://pastebin.com/yXBHHkhM Asm diff at -O2 -fno-tree-vrp: http://pastebin.com/EKj6hXkt * Misc (2/10) - Meetings - Had a look at vect test-cases failing due to LTO == Issues == - No access to Juno - Can't login to IRC via ZNC (can connect directly). == Next Week == - Continue with TCWG-120 - Start looking at TCWG-80

10 years, 1 month

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[ACTIVITY]

by Renato Golin

== Progress == * Holidays (4/10) * Buildbots (2/10) - Several breakages, Clang alignment issue sill breaking self-hosted bots... * Maintenance (2/10) - Backtracks on the TargetParser, code heavily modified, discussions ensued. - Helping Vinicius with __aeabi_memcpy in the kernel * Releases (0/10) - Release 3.7.0 final validated / uploaded - Waiting for final switch * Background (2/10) - Code review, meetings, discussions, etc. - Backlog of emails, reviews == Plan == Look at libc++ / RT / unwind again see if I can reduce the errors in both AArch64 and ARM to zero. == Issues == The power cuts and the effect it had on my buildbots made me spend 3 days of my holidays to fix. Other buildbot breakages made me spend another 2, and I couldn't wait until I was back, or it would have wasted an entire week (as it has happened before). In a nutshell, I can't have holidays. Yay!

10 years, 2 months

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[ACTIVITY] 31th Aug - 04th Sep

by Yao Qi

# Progress # * Holiday on Monday [2/10] * TCWG-857, [4/10]. All the multi-arch work are done (I hope) but patches can't be sent out until kernel patches are pushed in upstream. ** Collect some arguments from kernel folks to defend my change "32-bit CPSR to 64-bit PSTATE". Patch is posted out. ** Finish the patch to convert siginfo_t between 32-bit debuggee and 64-bit debugger. Done. Will post it next week. ** Get right TLS base in multi-arch debugging. Patch is done. * Happen to see we can improve GDB performance in some case by avoid sending some packets. Patch is done, but need to collect some performance data. [2/10] * Misc [1/10] ** Close some tickets, TCWG-567, TCWG-876, as they are done. * TCWG-757 [1/10], many patches review. # Plan # * Continue to upstream multi-arch patches. * Upgrade my juno board kernel to git master to test kernel patches for multi-arch debugging work properly. * Collect some GDB performance data for my patch. -- Yao

10 years, 2 months

1
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Odd Linaro GCC 4.8 2015.06 behavior with precompiled headers

by Dragan Stancevic

Hi- It seems that there is some discrepancy between Linaro GCC 4.8 2015.06 and Linaro GCC 4.8 2014.11 with regards to precompiled headers. It appears that 2015.06 doesn't even attempt to open the precompiled headers according to strace. I have been looking on gcc mailing list but have not been able to find any fixes related to precompiled headers. Does anyone have any pointers as to what should I be looking at to get to the bottom of this issue? This simple program compiles without any problems on 2014.11, but fails on 2015.06 because 2015.06 doesn't even attempt to read tst.h.gch created by "make header" dragans@tst:~$ cat Makefile PROJ=tst CC=arm-linux-gcc LD=arm-linux-ld all: header $(PROJ) header: $(PROJ)._ cp $(PROJ)._ $(PROJ).h $(CC) -x c-header -c $(PROJ).h $(PROJ): $(RM) $(PROJ).h $(CC) $(PROJ).c -o $(PROJ) clean: $(RM) $(PROJ).h.gch $(PROJ).h $(PROJ) dragans@tst:~$ cat tst._ #include <stdio.h> dragans@tst:~$ cat tst.c #include "tst.h" int main(int argc, char**argv) { char *s = "Test"; printf("%s\n", s); return 0; }

10 years, 2 months

1
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[ACTIVITY] 24 - 28 August 2015

by Omair Javaid

== Progress == LLDB development -- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [7/10] -- Improve error handling of AArch64 watchpoint code. Submitted, got reviewed and committed http://reviews.llvm.org/D12328 -- Looked into ways to improve watchpoint installation lag. -- Looked into issues pertaining to un-alligned watchpoints installation. -- Committed upstream arm hardware breakpoint and watchpoint support [TCWG-770] [TCWG-794] [1/10] -- Ran lldb testsuite in various combinations to figure out Arm and AArch64 status [1/10] -- Testing on chromebook with precise chroot works. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Try to find ways to debug lldb-server platform forked gdbserver instance. -- Test, debug and fix testsuite failures on Arm and AArch64.

10 years, 2 months

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[ACTIVITY] 17 - 21 August 2015

by Omair Javaid

== Progress == LLDB development -- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [2/10] -- Looked into watchpoint tests which are still failing after committing watchpoint support and bug fixes. -- Modifications to arm hardware breakpoint and watchpoint support [TCWG-770] [TCWG-794] [7/10] -- Resubmitted the pending patch http://reviews.llvm.org/D9703 -- Testing on chromebook with precise chroot works. Miscellaneous [1/10] -- Meetings, emails, discussions etc. -- Looking into slow data transfer issues on chromebook and highkey board == Plan == LLDB development -- Get patches reviewed and committ them. -- Continue looking into tests which are still failing on Arm and AArch64 -- Run test comparison between linux x86, android arm and linux arm

10 years, 2 months

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[ACTIVITY] Week 3

by Yvan Roux

o 3 days off (6/10) == Progress == o Linaro GCC validation (3/10) * Reviewed, validated and committed on-going backports * backported more revisions o Misc (1/10) * Various meetings == Plan == o Continue backports/validation

10 years, 2 months

1
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[ACTIVITY] 24th - 28th August

by Kugan

== Progress == * Annual Leave (2/10) * Widening pass (TCWG-547) - 6/10 - Fixed all execution test failure. - bootstrap failure due to “Drop copy-rename” is still not resolved. Found a workaround. - Sorted debug_stmt handling * TACT 1/10 - Started looking to cross execution set-up * Misc - 1/10 - gcc-patches, gcc-bugs list == Plan == * Continue with widening pass

10 years, 2 months

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[activity] 24-49 August

by Prathamesh Kulkarni

== This Week == * TCWG-777 (3/10) - Fixed ICE with the patch - toolchain builds with the patch. - Sent patch to tcwg list for review - Investigating why combine fails to combine arm_andsi3_insn/arm_cmpsi_insn into zeroextractsi_compare0_scratch when the pass uses ud-chains to find def but works when def is found using ad-hoc way. * TCWG-871 (4/10) - Getting familiar with firefox build system - LTO build lto/non-lto on x86 and arm (doc) - Figuring out how to resolve "plugin needed to handle lto object" error. tried the following: binutils configured with: --enable-plugin, --enable-lto gcc configured with: --enable-lto --with-ld-plugin=<just built ld> Doesn't appear to work. * TCWG-835 (1/10) - Build failure with spec (PR67399) * Misc (2/10) - Meetings - Looked at rtl dataflow (df.h and df*.c) and ree.c == Next Week == Continue with TCWG-777, TCWG-835, TCWG-871

10 years, 2 months

1
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[Weekly] 24-28 AUGUST 2015

by Michael Collison

== This week == * TCWG-832 -Exploit vector multiply by scalar instructions when multiple scalars are used as coefficients in a loop (2/10) - Initial investigation. * TCWG-833 - Exploit Wide Add operations when appropriate (4/10) - Ramana is reviewing Aarch32 patch - Recoded Aarch64 support to use vect_select - Debugging Aarch64 lto, tree-dump regression suite failures * TCWG-834 - Use non-unit stride loads by preference when applicable (1/10) - TCWG 834 is Bugzilla 67323 upstream; Richard Biener took ownership as a vectorizer failure - My plan was to write a test case that failed until fixed, but Richard indicated this is not standard practice - Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10) - Separated patch from Bugzilla 67321 patch and sent upstream - Pinged upstream for comments - Bugzilla 67320 - Incorrect standard names for wide addition (1/10) - committed upstream in trunk * Misc (1/10) - Conference calls == Next week == - Resolve Aarch64 TCWG-833 patch, validate and upstream - Additional investigation into TCWG-832

10 years, 2 months

1
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[ACTIVITY] 24th - 28th August

by Charles Baylis

Bug 1764/PR67280 C++ wrong code bug (no card yet) [9/10] Misc [1/10]

10 years, 2 months

1
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[ACTIVITY] 17th - 21st August

by Charles Baylis

Holiday [2/10] Bug 1764/PR67280 C++ wrong code bug (no card yet) [4/10] Misc [4/10]

10 years, 2 months

1
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[ACTIVITY] 24th - 28th August

by Yao Qi

# Progress # * TCWG-857 [3/10] With one kernel fix, HW breakpoint works for unaligned address (2-byte aligned). Debug linux kernel with KGDB. KGDB exposes an existing GDB bug, I fixed it, but need some time thinking about how to submit it upstream. * TCWG-567, arm watchpoint fixes [4/10]. All fails are fixed, but need another round of test to confirm. ARM HW watchpoint doesn't work on 4.0.0 kernel, but I don't investigate on it. * TCWG-757 [2/10], some patches review. * Misc, meeting, [1/10] # Plan # * TCWG-857. * Upstream the leftover of aarch64 multi-arch patches. -- Yao

10 years, 2 months

1
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[ACTIVITY] Week 34

by Yvan Roux

== Progress == o Linaro GCC validation (9/10) * Analysed x86_64 fstack-protector and sse2 issue * This is due to "ulimit -v" usage which brakes asan testing and gcc testsuite caching mechanism. * Validation is now stable on Hetzner/Austin hardware * Documented summer validation issues * Validate and committed on-going backports o Upstream GCC (0/10) * Armeb OOM fix committed into gcc-5 o Misc (1/10) * Various meetings == Plan == o 3 days off o Continue backports/validation

10 years, 2 months

1
0
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[ACTIVITY] 17th - 21st August

by Kugan

== Progress == * Widening pass (TCWG-547) - 8/10 - Fixed all but one execution test failure. - aarch64 and x86 are clean - arm has one but this looks like a latent issue (in expand); looking into it - Latest trunk with aarch64 miscompiles stage2 fwprop (-fno-forwprop works). This happens with the commit 94f92c36a83d66a893c3bc6f00a038ba3dbe2a6f [PR64164] Drop copyrename, use coalescible partition as base when optimizing - Tried forcing the same promote_mode for x86_64 and can reproduce it with x86_64 also. - Looking into it to see if this is an error with the commit * Misc - 2/10 - gcc-patches, gcc-bugs list == Plan == - Continue with widening pass

10 years, 2 months

1
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[ACTIVITY] 17th - 21st August

by Bernie Ogden

Upcoming Absences * Away from this Wednesday until next Tuesday, inclusive Benchmark infrastructure - TCWG-360 [1/10] * Finished filling out cards/bugs for benchmarking work * Which makes the rest of this report more fine-grained Multinode wrapper - TCWG-888 [2/10] * Completed oversubscription workaround * Herded most tests through * Uncovered one significant bug, seems fixed Centralized source/results storage - TCWG-722 [1/10] * Wrote draft of source/results handling rules * Confirmed that old repos are subsets of new repos Noise control experiments - TCWG-897 [2/10] * Learned more about firmware, openembedded * Juno running a minimal filesystem, needs some tidying up Misc [4/10] * Including a further 1/10 of ARM management =Plan= * Herd remaining multinode tests through ** Depends on LAVA lab coming back from power cut ** And queues being short enough * Progress (finish?) Juno bring-up * Share source/results rules draft

10 years, 2 months

1
0
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[Weekly] 17-21 AUGUST 2015

by Michael Collison

== This week == * TCWG-833 - Exploit Wide Add operations when appropriate (8/10) - Reworked patch to use vect_select instead of unspec as requested by Ramana - Bugzilla 57195 (mode iterator bug) blocked compiling new pattern - Created patch which successfully bootstrapped - Created Bugzilla 67320 - Incorrect standard names for wide addition (documentation bug) - Successfully regression tested Aarch32 changes - Send Aarch32 patch upstream for review - Reworking patch for Aarch64 to use vect_select as well - Created Bugzilla 67321 - [ARM] Exploit wide adds when appropriate - Created Bugzilla 67322 - [Aarch64] Exploit wide adds when appropriate * TCWG-834 - Use non-unit stride loads by preference when applicable (1/10) - Created Bugzilla 67323 to track until fixed in GCC 6 by Richard Biener - Began writing test case that fails * Misc (1/10) - Conference calls == Next week == - Respond to Aarch32 TCWG-833 upstream requests and hopefully check-in patch - Complete Aarch64 TCWG-833 patch, validate and upstream - Finish testcase for TCWG-834 and submit upstream

10 years, 2 months

1
0
0 0

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