== Issue ==
* None.
== Progress ==
* Refine and send the patch to fix pr61225 in Combine pass for review (2/10).
* Send out the ARM backend patch to keep some constant in register
(TCWG-486, 2/10).
* Rebase and test ccmp related patches (TCWG-488, 2/10).
* R/M toolchain related work (4/10).
== Plans ==
* Ping pending patches.
== Planed leaves ==
* Aug. 18 - 26.
* Benchmarks (CARD-716 3/10)
- Working on Linaro's SPEC scripts for LLVM
- Running SPEC2000 INT/FP (C/C++ only) on both ARMv7 and AArch64
- Re-writing some EEMBC scripts to be more stable
- EEMBC reported some regressions from 3.4.2
- But still same when compared with GCC 4.8 (all in Jira)
* Toolchain (CARD-862 3/10)
- Fixing bugs in the assembler/libc++abi
- http://llvm.org/PR20529
- http://llvm.org/PR20025
- Investigating other bugs in the assembler
- http://llvm.org/PR18926
- http://llvm.org/PR20422
* LLVM 3.5 Release (TCWG-476 1/10)
- Building and testing release candidate 2
* Background (3/10)
- Code review, meetings, discussions, etc.
- Buildbot failures
- Plan for 2014 H2
- Basic LLD AArch64 support landed upstream
== Plan ==
* Take actual holidays
* Work on more assembler fixes
* Finish SPEC runs, hopefully test last release candidate
* Have a look at the bots, libraries, CMake, NEON, etc
== Progress ==
* Upstream work (2/10, CARD-341)
- Patch review
- Submitted a fix for armeb-eabi configurations of binutils
- Tested and removed aarch64 lowlevellock.h
- Tidied up glibc patchwork
* Rewrote src-release as a shell script (4/10, TCWG-487)
- Allows building releases as xz
- 80% less evil than existing makefile
* Booting upstream kernel on Chromebook (2/10)
- Kernel configured and built
- I think I have a plan...
* Off Wednesday (2/10)
== Issues ==
* None
== Plan ==
* Upstream kernel on Chromebook
* malloc app benchmarks
* Potentially glibc 2.20 release week
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
BeagleBoard and Pandaboard setup for gdb testing [1/10]
* Got both alive and working with minimal os
* Trying ubuntu prebuilt binaries didnt work.
Out of office to get internet fixed and buy accessories for boards. [1/10]
Eid Public Holidays in Pakistan from 29th July till 1st August [8/10]
== Plan ==
BeagleBoard and Pandaboard setup
* Get linux running on both boards
* Run gdb test scripts on both boards
* Compare test results outputs with chromebook and x86
Update and Submit Aarch64 record replay patches.
Resume work on Aarch64 prologue analysis.
== Progress ==
GNU Tools Cauldron
* Some useful corridor meetings with various GNU tools developers
and maintainers.
TCWG Sprint [8/10]
* Got to meet the team and discuss TCWG roadmap.
* Some useful howtos specially back porting and patch review howtos.
* Sprint with ARM and useful discussions on gdb patch review.
Return travel from UK on Friday 25th July.[2/10]
== Plan ==
Get over travel fatigue and resume office.
Get missing components and set up pandaboard and beagle board for gdb testing.
Eid Public Holidays in Pakistan from 29th July till 1st August
== Progress ==
* Installed dmucs on the TCWG build slaves, which works in DejaGnu
to do cpu load based scheduling of executing cross tests
remotely. (TCWG 511 - 4/10)
* Spent some time trying to improve SSH performance for cross
testing by opening the SSH connection via expect, and keeping it
open. (TCWG 512 - 2/10)
* Attended GNU Tools Cauldron and Linaro Sprint. (13/10)
* Worked with Bernie on changes to the benchmarking branch.
* Installed a Jenkins instance on my home server which uses my own
build farm for testing Jenkins/Cbuildv2 changes without screwing
up validation. (TCWG 1378 - 1/10)
- Experimented with some new plugins that might be useful.
(TCWG 1378 - 1/10)
- Added command line options to jenkins.sh so it'll work on
different Jenkins installations.
* Fixed bare metal testing for arm*-none-eabi*. (2/10)
* Fixed several Cbuildv2 bugs in bugzilla (TCWG 1378 - 2/10)
- #167 - tcwgweb.sh not accurate.
- #183 - cbuild2 configure --enable-bootstrap sets
'enable_bootstrap' not 'bootstrap'.
- #249 - cbuild2.sh --help only works after configure is run
* Reviewed and approved patches:
- Add configure option to choose compiler languages
- Enable parallelism by default
- Add support for --march
- Add support for --enable and --disable make_docs in configure
and cbuild2.sh
- lib/checkout.sh: Make checkout() dryrun safe when repodir
doesn't yet exist
- lib/stamp.sh: check_stamp() --force and --dryrun should return 1
- cbuild2.sh: Make --dump a do_ option so it's position doesn't
matter
- lib/make.sh: hello_world() will now return 1 if the compilation
or link fails
* Experiment with Docker to see if it has any advantages over a
chroot, which it seems to. (2/10)
* Refactor building binary tarballs. Now it doesn't run the test
first, it assumes the branch has already been validated. (2/10)
* Fix aach64_be-none-elf builds.
== Plan ==
* Fix current breakage in cbuild2/master.
* Get back to SSH performance improvements (TCWG 512).
* Get my D01 board working finally, since I killed my Odroid U2.
* Work through more cbuildv2 bug reports (TCWG 1378).
== Issues ==
* Sorry, several weeks of status in one activity report, I need to
get back to doing these weekly...
== Progress ==
- Travelling from TCWG sprint (2/10)
- Zero/sign extension elimination (TCWG-291) 2/10
* Posted the modified patch and some discussions. Further testing.
-SHA1 regression (TCWG-468) 4/10
* Looked at IRA's uses of back end cost model. It might be a
limitation (See the notes below). Looking at the test-case from sha1
which also has inline asm whose constraints are causing further issues.
- Misc (2/10)
* Looked at bugs assigned (https://bugs.linaro.org/show_bug.cgi?id=85)
* Set-up LLVM
== Plan ==
- Sha1 regressions
- Fixing assigned Bugs
---------------------------------------------------------------------
In AArch64, some of the integer operations support “w” constraint
(FP_REGS). For example *addsi3_aarch64 pattern supports it. However, not
all of the integer operations supports it. In the cases where it is
supported, all the operands have to be in FP_REGS and it will not work
if we have one operand in FP_REGS and other in GENERAL_REGS.
If there is an allocno whose pseudo register is used only in
*addsi3_aarch64 insns, it will have low cost for register class FP_REGS
(as in the case of a28 below exacted from an example). If the other
pseudo register used in *addsi3_aarch64 (a27 in the example below) is
also used in instructions (rorsi3_insn in the exaple below) that does
not support “w” constraint, there is going to be a cost involved in
moving it from FP_REGS to GENERAL_REGS (or other way)
Currently IRA dosent seems to be considering this dependency in
considering this inter dependency in cost calculation.
=Progress=
cbuild2 benchmarking - TCWG-360 [7/10]
* Integrated benchmarking more into the core of cbuild2
* 'Audited' the benchmarks lying around on toolchain64
* Persuaded cbuild2 to use git-over-ssh
Meetings/mail/etc [3/10]
=Plan=
cbuild2 benchmarking
* Convert eembc integration into reviewable patches
* Get cross-compilation working
* Get remote targets working
== This week ==
* Neon intrinsic testing (4/10)
- Patched sources with Christophe's patches
- Ran Neon intrinsic tests for vclz and vqadd
- Investigating regressions
* On leave Monday and Tuesday; out sick Wednesday (6/10)
== Next week ==
* Continued Neon intrinsic testing
== Issues ==
* None.
== Progress ==
* Rework the patch to fix pr61225 in Combine pass. (4/10)
* Investigate code-size regression when skipping arm_split_constant in
expand (TCWG-486, 4/10).
- For reg & 0xffff, zero_extendhi instruction is more efficient.
- For "PLUS", the define_insn_and_split "*arm_addsi3" is only
available when "reload_completed || !arm_eliminable_register
(operands[1])". The cprop and combine passes can not recover it back
when there is no chance to optimize the constant.
* R/M toolchain related work (2/10).
== Plans ==
* Send out the patches for review.
* Refine ccmp related patches.
== Planed leaves ==
* Aug. 18 - 22.
== Progress ==
* Toolchain (CARD-862 2/10)
- Helping debug some sanitizer work
- Re-evaluating compiler-rt on ARM with CMake
* LLVM 3.5 Release (TCWG-476 2/10)
- Working on SPEC to run with LLVM
* Background (6/10)
- Code review, meetings, discussions, patches, etc.
- Email and patch backlog due to Cauldron and sprint
- Investigating and fixing buildbot/build failures
== Plan ==
* Finish SPEC-LLVM integration, run against 3.5 vs. 3.4.2
* Test Release Candidate 2, when it comes
* Back to compiler-rt work...
== Progress ==
* Various small tasks (3/10)
- Catching up on email
- Bug report investigations
- Expenses from Cauldron/Sprint
- Pushing patches
- Tidy some JIRA cards
* Investigated gdb testsuite failures on Chromebook (2/10)
- Looks like a kernel issue, need to try a newer kernel on Chromebook
* Investigated state of ARM and AArch64 glibc testsuites for 2.20 release (2/10)
- Results look ok but a couple of things need investigation at some point
* Triaged bugzilla bugs (1/10)
* Built releases of binutils, eglibc and gdb for 2014.08 (2/10)
== Issues ==
* None
== Plan ==
* Get a newer kernel booting on Chromebook
* Look at improving src-release for xz tarballs
* Figure out what to do with glibc testsuite failures on AArch64
--
Will Newton
Toolchain Working Group, Linaro
Hi guy,
In order to have soft-float support in toolchain, I tried to build our toolchain using Linaro ct-ng script.
I used "linaro-armeb-linux-gnueabihf" configuration then change floating point option from hard to soft.
There is the error I have:
[ERROR] /projects/broadcom-linux/joelz/r/linaro-gcc-build/.build/armeb-linux-gnueabi/build/gcc-core-shared/lib/gcc/armeb-linux-gnueabi/4.8.3/../../../../armeb-linux-gnueabi/bin/ld: error: /projects/broadcom-linux/joelz/r/linaro-gcc-build/.build/armeb-linux-gnueabi/build/gcc-core-shared/lib/gcc/armeb-linux-gnueabi/4.8.3/libgcc.a(bpabi.o) uses VFP register arguments, /projects/broadcom-linux/joelz/r/linaro-gcc-build/.build/armeb-linux-gnueabi/build/build-libc/elf/librtld.map.o does not
For short, libgcc.a(bpabi.o) uses VFP register arguments, but librtld.map.o does not.
The C library used is eglibc version (Linaro 2.19-2014.04), is this a way to make eglibc work with sfot-float?
Thanks!
Joel
I was using arm-eabi builds on Linaro Android 4.9 toolchain 2014.06.
I've just downloaded 2014.07 and found out there is not an arm-eabi
toolchain.
I need arm-eabi to build Linux kernels and arm-none-eabi toolchain from
here:
http://releases.linaro.org/14.07/components/toolchain/binaries/gcc-linaro-a…
is not capable of building LTO kernels.
Error pops up : "cc1: error: -fno-fat-lto-objects are supported only with
linker plugin"
TL;DR, I need arm-eabi builds from Linaro Android toolchains.
arm-none-eabi builds are not built with linker plugin enabled.
Short week (Friday off)
== Progress ==
* GCC trunk cross-validation (2/10)
- catch up with backlog, reported newly introduced FAILs
- analyzed logs of spurious failures, improved reporting of such cases
- the script will know send a separate email with the svn ids
it has selected for validation, to help fill the backports spreadsheet
* Infrastructure (2/10)
- started deployment of past releases to help us quickly
reproduce/investigate bug reports
- 14.* binary releases deployed on toolchain64 (/work/toolchains)
- automation not yet possible because of problem with the lab
internal squid proxy preventing the download of
http://releases.linaro.org/14.07/components/toolchain/binaries for
parsing
- started deployment of past toolchains built from the source
releases using cbuild2 but ran into build problems
* Neon intrinsics tests (1/10)
* Misc (conf calls, meetings) (3/10)
- 1-1 calls to get feedback after Cauldron+Sprint
- a bit of bugzilla triage
- backports reviews for 14.08 release
== Next ==
Holidays, back on Aug 18th
Hi Linaro-toolchain team,
I notice that the Linaro toolchain binary only support hard-float. We have a platform which is ARMv7 based does not support VFP.
Could you generate toolchain binary for ARmv7 that allows soft-float?
Thanks,
Joel
The Linaro Toolchain Working Group (TCWG) announces the 2014.07-1 release
of the Linaro GCC 4.9 source package. This is a respin of the 2014.07
release which
contained a backport of a revision that is only relevant to trunk.
Changes in this GCC source package release are:
* Updates to GCC 4.9.1 (svn212635)
* Revert backport of [AArch32] Fix PR target/61154.
Please find the original 2014.07 release notes below:
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.07
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.07 is the fourth Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn212419 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1-pre+svn212419
* Backport of [AArch32] Wrap long literals in HOST_WIDE_INT_C in
aarch-common.c
* Backport of [AArch32] Rewrite TLC Intrinsics.
* Backport of [AArch32] Remove vzip, vuzp, vtrn builtins and cleanup
* Backport of [AArch32] Use enum name instead of integer value for
PARAM_SCHED_PRESSURE_ALGORITHM.
* Backport of [AArch32] Vectorise bswap*
* Backport of [AArch32] Fix PR/61331
* Backport of [AArch32] Fix PR target/61154
* Backport of [AArch32] Use mov_imm type for movw operations consistently
* Backport of [AArch32] Remove XFmode from ARM backend.
* Backport of [AArch64] Rewrite REV Intrinsics.
* Backport of [AArch64] Implement HARD_REGNO_CALLER_SAVE_MODE.
* Backport of [AArch64] Support tail indirect function call.
* Backport of [AArch64] Fix stack protector for ILP32
* Backport of [AArch64] ILP32 dynamic linker
* Backport of [AArch64] Correct signedness of builtins, remove casts from
arm_neon.h
* Backport of [AArch64] clarify stack layout diagram
* Backport of [AArch64] Implement movmem for the benefit of inline memcpy
* Backport of [AArch64] Fix REG_CFA_RESTORE mode.
* Backport of [AArch64] Fix layout of frame layout code.
* Backport of [AArch64] Fix some reg-to-reg move scheduler types.
* Backport of [AArch64] Implement CRC32 ACLE intrinsics + testsuite.
* Backport of [AArch64] Implement ADD in vector registers for 32-bit scalar
values.
* Backport of [AArch32/AArch64] TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64
* Backport of [AArch32/AArch64] Use signed chars in gcc.dg/pr60114.c.
* Backport of [AArch32/AArch64] Rewrite UZP Intrinsics.
* Backport of [AArch32/AArch64] Rewrite TRN Intrinsics.
* Backport of [AArch32/AArch64] Rewrite EXT Intrinsics.
* Backport of [genattrtab] Fix memory corruption, allocate enough memory for all
bypassed reservations
* Backport of Fix PR c/60114
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
=Progress=
GNU Cauldron
TCWG Sprint [8/10]
* Really helpful to meet (almost) everybody
* Some useful discussion, too
memcpy on A15 - TCWG-390 [1/10]
* Should have let this lie but I had an odd 1/2 day and some data
begging to be looked at
* Turned out I'd fat-fingered the wrong data
* But I gained more evidence suggesting that cortex-strings
benchmark is too noisy
(Non-sprint) meetings/mail etc [1/10]
=Plan=
cbuild2 benchmarking
* Fit what I have into Rob's worldview
* Hopefully convert it into some reviewable patches
Follow up on some notes from Cauldron, sprint
== Progress ==
* GNU Cauldron (4/10)
- GCC+LLVM presentation had some positive reviews
- Discussed sanitizers roadmap
- Very interesting meeting with QuIC
* TCWG Sprint (4/10)
- Mostly about GNU tools
- Team Mission streamlined, looking good
- LLVM roadmap attracted some attention
- We could have some bite-sized work from other team members?
* Release 3.5 testing (TCWG-476 2/10)
- No test regressions
- Spotted some benchmark regressions
- ARMv7 is overall the same on EEMBC
- AArch64 is overall 10% faster on EEMBC
* Weekend working, Friday off
== Plan ==
* Release week!
- Investigate 3.5 performance regressions on v7
- Work around the lack of perf on v8?
- Run SPEC on both v7 and v8 and spot regressions
== Progress ==
* Attend GNU Cauldron.
* TCWG Sprint (8/10)
- Participated in Discussions about TCWG/GNU tools.
- Partcipated in Discussions with ARM mainatiners.
- Discussed about Connect plans.
- LLVM status.
- Attend Backport Demo by Yvan / some Bug fix Activity.
* Friday off traveling back home (2/10)
== Plan ==
* Continue LTO bootstrap issue
* Benchmark Core mark with LTO
* Upstream patch review.
== Issues ==
* Large Memory Model put on hold now.
* Waiting on ARM on Aarch64 SYS V ABI.
== This week ==
* TCWG Sprint (8/10)
- Validation process greatly clarified including roadmap
* Launchpad 1318831 - Invalid unpoisoning of stack redzones on ARM (2/10)
- Finished validating and working thru git review isses with Launchpad
== Next week ==
* Begin neon intrinsic testing
* I will be off on Monday and Tuesday
Hi all concerned:
this test code I given below: AARCH32
[https://email-cn04.huawei.com/owa/14.3.158.1/themes/base/pgrs-sm.gif]
Test function[X][X]
{
volatile unsigned int val0 = 0;
volatile unsigned int val1 = 0;
asm volatile(“mrrc p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1))
val0 &= ~(1<<6);
val1 &= ~(1<<6);
asm volatile(“mcrr p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1));
}
After compiling, the result is:
mrrc 15, 1, r2, r3, cr15
str r2, [fp, #-28]
str r3, [fp, #-24]
ldr r3, [fp, #-28]
bic r3, r3, #64;
str r3, [fp, #-28]
ldr r3, [fp, #-24]
bic r3, r3, #64
str r3, [fp, #-24]
mcrr 15, 1, r2, r3, cr15
obviously , it is not what I expect. I have val0 an vl1 two vars, but the compiling result is only one val takes effect.
especia I have to mention is AARCH32.
thanks.
Peter
Hi,
Do you happen to know the answer to the git/svn questions below? Thanks.
-----Original Message-----
From: LDTS [mailto:support@linaro.zendesk.com]
Sent: 25 July 2014 08:43
To: Scott Douglass
Subject: Request received: accessing toolchain source releases - Member user
Thank you for contacting Linaro.
Your request (#927 <https://support.linaro.org/requests/927> ) has been received and is being reviewed by Linaro Developer Technical Support (LDTS). One of our Support agents will be in contact with you as soon as possible. If you would like our agent to contact you via phone, please include your phone number in the comments.
To view your ticket and/or add additional comments, reply to this email or click the link below:
http://support.linaro.org/requests/927
Scott Douglass
Jul 25 16:43
Hi,
I’ve been looking at https://wiki.linaro.org/WorkingGroups/ToolChain (https://wiki.linaro.org/WorkingGroups/ToolChain) and I see the Tree links that give me the git repository and commit id for the current releases of the toolchains (for example, 4.9-2014.06-1 => https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8… (https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8…
My first question is: is there a straight-forward way (for example, a tag) to find the commit ids of older (4.9) releases? Or is searching the commit messages the best way?
Also, is there svn access as well or just git access? (Git access is enough, but svn access would be slightly easier for me.)
Also, I has a couple comments on that wiki page:
It says “Pre-built versions that run on generic Linux or Windows are available at http://launchpad.net/linaro-toolchain-binaries.”, but it looks like the that Launchpad project is no longer being maintained (no 4.9 and no recent 4.8). Perhaps the wiki page should be updated (and the Launchpad description updated).
The wiki page also links to https://wiki.linaro.org/Cycles/Next/Release/Status (https://wiki.linaro.org/Cycles/Next/Release/Status) which seems even more out-of-date than the Launchpad binaries; perhaps that link should be updated/removed, too.
Thanks.
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Hi all,
I'm working on booting Linaro LSK 3.10.40 kernel in be8 mode on our Cortex-A9 system.
There is an issue related to VFP instruction. It complain "vstmia" is an undefined instruction.
The VFP is supported in CPU and CONFIG_VFP and CONFIG_VFPv3 are enabled in kernel config.
Are there any patch need to be done for VFP in BE mode?
The booting log show as following:
call sys_access(/init)
Freeing unused kernel memory: 2832K (c0600000 - c08c4000)
kernel_init: try to execute '/init' (ramdisk_execute_command)
en->run_init_process(/init)
init (1): undefined instruction: pc=0000aab8
Code: f00f dff8 2a20 1268 (acec) 108b
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004
The disassembly code show the undefined instruction is "vstmia".
armeb-linux-gnueabihf-objdump -D busybox_unstripped > busy.asm
0000aa90 <__sigsetjmp>:
...
aab6: 6812 ldr r2, [r2, #0]
aab8: ecac 8b10 vstmia ip!, {d8-d15}
aabc: f412 7f00 tst.w r2, #512 ; 0x200
The rootfs is busybox 1.22.1 compiled by Linaro BE hard floating toolchain.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
Thanks,
Joel
== Progress ==
* On Holiday from 14th to 17th July 2014.
* Travel to Cambridge to attend TCWG Sprint and GNU Tools Cauldron on
Friday 18th July.
== Plan ==
* Attend GNU Tools Cauldron 18th to 20th July.
* Attend TCWG Sprint 21st to 24th July.
* Friday 18th July return back after attending TCWG Sprint and GNU
Tools Cauldron in UK.
== Progress ==
* Testing and Analysis of testsuite failures in arm-linux-gdb [TCWG-509] [6/10]
-- Run ARM GDB testsuite on local chromebook, remote chrombook and
pandaboards.
-- Investigation of failures on arm.
* AArch64 GDB handling of functions with empty prologue. [TCWG-504] [1/10]
-- Short list aarch64 prologue skipping requirements.
* Browsing gdb related upstream discussions and reviewing aarch64
regset rework stuff. [1/10]
* Preparation for travel to UK, obtaining medical NOC document for
international travel. [2/10]
== Plan ==
* On Holiday from 14th to 17th July 2014.
* Travel to Cambridge to attend Sprint and Cauldron.
=Progress=
cbuild2 benchmarking - TCWG-360 [7/10]
* Much fighting with benchmarking branch on a panda
* Ported eembc benchmarking over to my way of doing things
* A bit of cleanup around the 'reduce noise by shutting down services' stuff
* Slew my ailing Ubuntu VM, started bringing up a beagle as a 2nd
sacrificial target
lowlevellock.h - TCWG-435 [1/10]
* Roland patch review/thinking about how to test a corner case
Meetings/mail/etc [2/10]
=Plan=
Cauldron/TCWG sprint
Hopefully some cbuild2 benchmarking progress
== Progress ==
* Annual leave Monday to Wednesday (6/10)
* Travel to Cauldron/Sprint (2/10)
* Catching up on email, pushing patches, bugs etc. (2/10)
== Issues ==
* None
== Plan ==
* GNU Tools Cauldron
* Toolchain Sprint
--
Will Newton
Toolchain Working Group, Linaro
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.07
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.07 is the fourth Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn212419 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1-pre+svn212419
* Backport of [AArch32] Wrap long literals in HOST_WIDE_INT_C in
aarch-common.c
* Backport of [AArch32] Rewrite TLC Intrinsics.
* Backport of [AArch32] Remove vzip, vuzp, vtrn builtins and cleanup
* Backport of [AArch32] Use enum name instead of integer value for
PARAM_SCHED_PRESSURE_ALGORITHM.
* Backport of [AArch32] Vectorise bswap*
* Backport of [AArch32] Fix PR/61331
* Backport of [AArch32] Fix PR target/61154
* Backport of [AArch32] Use mov_imm type for movw operations consistently
* Backport of [AArch32] Remove XFmode from ARM backend.
* Backport of [AArch64] Rewrite REV Intrinsics.
* Backport of [AArch64] Implement HARD_REGNO_CALLER_SAVE_MODE.
* Backport of [AArch64] Support tail indirect function call.
* Backport of [AArch64] Fix stack protector for ILP32
* Backport of [AArch64] ILP32 dynamic linker
* Backport of [AArch64] Correct signedness of builtins, remove casts from
arm_neon.h
* Backport of [AArch64] clarify stack layout diagram
* Backport of [AArch64] Implement movmem for the benefit of inline memcpy
* Backport of [AArch64] Fix REG_CFA_RESTORE mode.
* Backport of [AArch64] Fix layout of frame layout code.
* Backport of [AArch64] Fix some reg-to-reg move scheduler types.
* Backport of [AArch64] Implement CRC32 ACLE intrinsics + testsuite.
* Backport of [AArch64] Implement ADD in vector registers for 32-bit scalar
values.
* Backport of [AArch32/AArch64] TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64
* Backport of [AArch32/AArch64] Use signed chars in gcc.dg/pr60114.c.
* Backport of [AArch32/AArch64] Rewrite UZP Intrinsics.
* Backport of [AArch32/AArch64] Rewrite TRN Intrinsics.
* Backport of [AArch32/AArch64] Rewrite EXT Intrinsics.
* Backport of [genattrtab] Fix memory corruption, allocate enough memory for all
bypassed reservations
* Backport of Fix PR c/60114
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* More work on launchpad bugs (3/10)
- Moved gdb bugs over to bugzilla and closed down Launchpad tracker
- Found secret location of Linaro eglibc bugs in Launchpad!
- Triaged, moved, closed as many bugs as possible, some still remain
* Respin of binutils 2.24 2014.07 release (1/10)
* Get binutils ARM testsuite all passing on EABI, mostly on OABI (2/10)
* glibc patch review and build warning fixes (2/10, CARD-341)
* Annual leave on Friday (2/10)
== Issues ==
* None
== Plan ==
* 4 days in Berlin
* Travel to Cauldron
--
Will Newton
Toolchain Working Group, Linaro
Hello Will and list,
do you have a prepackaged static libfdt.a for aarch64?
I think it's part of some of the released images you provide, but
maybe you have it also available as a single package?
Thank you,
Claudio
== Week of July 7th ==
- Continued working on toolchain testing improvements (CARD-1378, 6/10)
-- Further Jenkins fixes and improvements
-- Various bits of build farm administration
-- Investigated feasibility of [really] remote cross-testing -- yes, it is feasible!
- STREAM performance regression (TCWG-388, 2/10)
-- Resumed patch submission (now that testing is working much better)
- Various meetings and discussions (2/10)
--
Maxim Kuvyrkov
www.linaro.org
== Week of June 30th ==
- Continued working on toolchain testing improvements (CARD-1378, 6/10)
-- Troubleshooted Jenkins jobs
-- Various cbuild2 improvements
- Migrated master VM of TCWG dev environment to AWS (2/10)
-- It is now at tcwg-dev-env-master.linaro.org
- Various meetings and discussions (2/10)
-- Attempted to test QEMU's aarch32 crypto support
-- Organized travel for GCC GSoC student to GNU Tools Cauldron. Thanks Linaro for providing sponsorship for this!
--
Maxim Kuvyrkov
www.linaro.org
=Progress=
memcpy regression on A9 - TCWG-390 [6/10]
* Not down to the branch predictor after all
* Can be fixed for A9 with explicit pld, but this isn't free
cbuild2 benchmarking - TCWG-360 [1/10]
* Dug out my branch, merged in trunk, refreshed memory
Meetings/mail/etc [3/10]
* Including a little patch review for Roland's lowlevellock.h (TCWG-435)
=Plan=
Close TCWG-390 as wontfix
Lots more cbuild2 benchmark automation
Keep up with lowlevellock.h
== Progress ==
* Recovered from flu on leave 7th and 8th July (4/10)
=LTO bootstrap -tcwg180 (2/10)=
Git bisect experiments shows bootstrap compare errors apprearing and
disappearing at trunk at different revisons.
Alteast 3 revisons LTO bootstrap passes
r210740 2488876068f541a341472c3aeedadccc255f0696 PASS
r210854 271fe9cf111f6b581451bbfb4d346757877896cd PASS
r210973 487fea840105dbb0ff516b797e7d86bea82ef74a PASS
It is hard to do backport of revisons which fixes this bug. Need to
discuss with LTO people in GCC mailing list
=Reload spill fix -tcwg180 (2/10)=
Emailed my status on benchmarking
https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00450.html
This bug cannot be fixed without performance degradation. So if it
cannot be up streamed, the reporter can use the patch to build his
package atleast. Planning to close this bug if I did not receive any
comments from maintainers.
=Misc (2/10)=
* GCC internal team meeting
* Meeting with Ryan
== Plan ==
* Benchmark coremark -O3 vs -O3 -flto.
* Email to marcus on ABI for large memory model in Aarch64.
* Cauldron preparation.
== Planed leaves ==
* Jul 18- 25: Travel to Cambridge.
== Progress ==
- 8th and 9th on holiday (4/10)
- Zero/sign extension elimination (TCWG-291) 3/10
* Patch one is accepted
* Posted the modified patch 2 after some discussions
* Started analysing the code generated for coremark and spec2k
* Looks there are more places that can be improved. I will post
additional patches after completing it
- Launchpad bugs (3/10)
* https://bugs.launchpad.net/gcc-linaro/+bug/1320965
* https://bugs.launchpad.net/gcc-linaro/+bug/1331112
== Plan ==
- sha1 regressions
- 15th and 16th on holiday
== Progress ==
* One day off.
* Test and send out the local NLS patch for community review (1/10).
* Test ccmp patches. Can not reproduce a FAIL in previous regression
test with the latest trunk(TCWG-488, 1/10).
* Test codes to skip arm_split_constant (TCWG-486, 3/10). Performance
results seam OK for spec2000, coremark dhystone and eembc.
* R/M toolchain related work (3/10).
== Plans ==
* Ping pending patches.
* Update ccmp patches.
== Planed leaves ==
* Jul. 15 - 25: Travel to Cambridge.
* Aug. 4 -8: Annual leaves.
== This week ==
Provide ldp/stp peephole optimization for Aarch64 [TCWG-446] [0/10]
- Halted development due to duplicate ARM development project by
Bin Cheng
Launchpad 1318831 - Invalid unpoisoning of stack redzones on ARM [3/10]
- Verifying test results
Launchpad 1267761 - miscompilation of unsigned comparison on aarch64 [2/10]
- Testing under way on Jenkins
Neon intrinsic tests [4/10]
- background work to gain familiarity with effort
Misc Meetings [1/10]
== Next week ==
- Verify testing on Launchpad 1267761 and 1318831
- Begin investigating compiler bugs discovered by neon intrinsic tests
== Future ==
== Progress ==
* GCC trunk cross-validation
- reported a few regressions
* Automation Framework (2/10)
- looked at Jenkins configuration & logs of some failures
* AArch64 libsanitizer (1/10)
- tried to use cbuild2 in the lab to build & test on HW, but all my
build attempts failed for various reasons
* Neon intrinsics tests (3/10)
- feedback from upstream requests some renaming changes + GNU coding
style fixes
- since reformating the existing testsuite is a manual and
error-prone task, it will bring additional delay in improving GCC
testsuite.
- it's probably more efficient to run the existing tests regularly
and start reporting & fixing the bugs identified, not waiting for the
full conversion
- updated the existing tests for fp16 and poly* types support with
GCC (reference built with armcc)
- interestingly, compiling the original testcases with armcc for
aarch64 caused ICE on 28 source files.
* Misc (meetings, conf-calls, ....) (4/10)
== Next ==
Holidays for 2 weeks
== Progress ==
* Monday holiday
* Automation Framework (CARD-1378 6/8)
- TCWG D01 moved in, Chromebooks out
- Movng LLVM buildbots to D01s
- D01s have no NEON support... :S
- We might have to move some Chromes back in
- Moving hackboxes to Chromebook 2s
* Background (2/8)
- Code review, meetings, discussions, etc.
== Plan ==
* Deal with NEON issue in the rack
* Finish Cauldron presentation
* Try to get the D01s as buildbots, even without NEON
== Progress ==
* AArch64 GDB reverse watchpoints issue. [TCWG-503] [4/10]
-- Found a new fix in generic process record implementation.
Testing stalled by too many 2500 failures seen on arm-linux-gdb in
general and some 850 record/replay implementation.
* AArch64 GDB handling of functions with empty prologue. [TCWG-504] [4/10]
-- Analysis of prologue generated by aarch64-gcc
-- Make an understanding of code implementation for arm-linux-gdb.
-- Try to reproduce reported bugs.
* Testing and Analysis of testsuite failures in arm-linux-gdb [TCWG-509] [1/10]
* Browsing gdb related upstream discussions. [1/10]
== Plan ==
* AArch64 GDB reverse watchpoints issue. [TCWG-503]
-- Test and submit fix for target record for the case where we cant
step breakpoints.
* Investigate issues in arm-linux-gdb testsuite results. [TCWG-509]
* Travel preparations to UK for Tools cauldron and TCWG sprint.
-- Obtain health certificate for international travelers.
* On Holiday from 14th to 17th July 2014.
=Progress=
memcpy regression on A9 - TCWG-390 [7/10]
* Tweaked bench.py some more
* Cobbled together a bare metal version of cortex-strings benchmark
* Was surprised to find that the problem does not relate to Linux
* Have some evidence that points at the branch predictor
Meetings/mail/etc [3/10]
=Plan=
See if A9 performance is recoverable without sacrificing other targets
Push some of my improvements into the cortex-strings repo
Possibly write up my cortex-strings-benchmarking-in-lava method
Back to cbuild benchmark automation
== Progress ==
Zero/sign extension elimination (TCWG-291) 10/10
- Patch updated based on review comments.
- Regression tested with standard set-up
- Created test-cases.
- Set-up additional architectures for validation
* aarch64-none-elf --with-abi=ilp32 (Foundation model)
* aarch64-none-linux-gnu --with-abi=ilp32 seems to be broken.
* Set-up qemu based s390x-ibm-linux
* Tried x86_64-linux -mx32 but ran into many issues.
- Patch now waiting for s390x-ibm-linux. All others are OK.
- will post once the results are available
== Plan ==.
- Spec2k regressions
- sha1 regressions
- 8th and 9th on holiday.
== This week ==
Provide ldp/stp peephole optimization for Aarch64 [TCWG-446] [6/10]
- Investigated options for improving ldp/stp pairing and developed
patch
- Testing underway
Launchpad 1267761 - miscompilation of unsigned comparison on aarch64 [1/10]
- Backported revision 206529 from trunk
- Testing under way on Jenkins
Launchpad 1296942 - marked fixed released based on backport by Yvan Roux
[1/10]
- July 4th holiday [2/10]
== Next week ==
Complete testing on Launchpad 1267761 and TCWG-446 and initiate code review
== Future ==
Travel to Cambridge on July 11th for Cauldron and TCWG Spring
Am 05.07.2014 17:36, schrieb Emilio Pozuelo Monfort:
> Control: reassign -1 gcc4.8,gcc4.9
>
> Hi,
>
> This is still a problem with GCC 4.9. Is there any progress on this? This is
> making aegisub FTBFS on armel, blocking the libass transition.
afaik, no. See also https://gcc.gnu.org/ml/gcc/2014-07/msg00000.html
== Progress ==
* Toolchain (CARD-862 2/9)
- Investigating LLD, MCLinker
* Automation Framework (CARD-1378 4/9)
- Lots of validation and lab meetings
- Planning and designing a new rack:
- Replace all chromebooks with D01s
* Background (3/9)
- Code review, meetings, discussions, etc.
- A bit more on Cauldron's presentation
- Revamping LLVM plan, TCWG mission, Validation docs
* Some illness...
== Plan ==
More rack stuff... Monday holiday.
== Progress ==
* Patch review, testing and follow-up (3/10, CARD-341)
- glibc 2.20 freeze still not announced
- submit more warning fix patches
- reviewed series of gdb thumb prologue patches
* Get postgresql malloc benchmark using unix domain sockets (2/10, TCWG-441)
* Built releases of eglibc and binutils for 2014.07 (3/10)
* Started looking at moving binutils and gdb bugs in launchpad to
bugzilla (1/10)
* Other small things (1/10)
- Investigated a couple of other small issues for various people
- Meetings
== Issues ==
* None
== Plan ==
* Clear up more old bugs and move to bugzilla/JIRA/upstream
* malloc benchmarking
* glibc patches
--
Will Newton
Toolchain Working Group, Linaro
The Linaro Toolchain Working Group is pleased to announce the 2014.06
release of Linaro GCC 4.7.
As announced at Linaro Connect USA 2013 Linaro GCC moved to a pattern
of quarterly stable releases, with engineering releases in the
intervening months. This is the third stable release, and contains no
known regressions compared to the 2014.04 release.
Linaro GCC 4.7 2014.06 is the twenty forth release in the 4.7 series.
Based off the latest GCC 4.7.5+svn211571 release, this is the eleventh
release after entering maintenance and the final one.
Interesting changes include:
* Updates to GCC 4.7.4+svn211571
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing
list":http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at #linaro-tcwg
* Bug reports should be filed in Launchpad against "Linaro GCC
project":http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro
support":mailto:support@linaro.org
== Progress ==
* AArch64 GDB reverse watchpoints issues. [TCWG-503] [6/10]
-- Proposed a fix which failed testing now working on an alternate
fix in gdb process record target implementation.
* Further progress on AArch64 GDB handling of functions with empty
prologue. [TCWG-504] [2/10]
-- Analysed different type of obj files and how they are being handled by gdb.
* Investigate and improve ARM gdb frame unwinding [TCWG-157] [1/10]
-- Try to reproduce reported bugs.
* Miscellaneous [1/10]
-- Setting up gdb remote testing with hackboxes.
-- Meetings etc.
== Plan ==
* AArch64 GDB reverse watchpoints issue. [TCWG-503]
-- Figure out a new fix in gdb process record implementation, test
it and then justify it.
* AArch64 GDB handling of functions with empty prologue. [TCWG-504]
-- Further investigation.
=Progress=
memset performance improvement - TCWG-156 [2/10]
* Bugfixed/improved cortex-strings-bench-on-lava
memcpy regression on A9 - TCWG-390 [6/10]
* Scanned through lots of data
* Learned some perf and some streamline
* Still don't know what's going on here
lowlevellock performance bugs - TCWG-435 [0/10]
* Stalled until someone reacts to my pings
Meetings/mail/etc [2/10]
* Including some questions about whether we need softfloat support in
binary releases
=Plan=
Keep prodding at memcpy with perf/streamline
Explore repeatability of cortex-strings benchmark
See how much quicker I can make cortex-strings benchmark without
compromising repeatability
Possibly try out a bare metal version of (a subset of) cortex-strings benchmark
* Analysis of PR61411 (CARD-341) [2/10]
* Attempted to analyse VP8 decode performance on Aarch64 vs Aarch32
(TCWG-?) [6/10]
. took a while to find compatible libvpx source and compilers :(
. can't find a good way to profile on Aarch64, perf is broken, gprof
results look implausible
* Misc [2/10]
== Issues ==
* None
== Progress ==
* Take care Linaro binaries release (1/10).
* Send out ccmp patches for community review (TCWG-488, 1/10).
* loop2_invariants heuristics tune (1/10, TCWG-469). One patch was
committed @r212135.
* Constant optimization (TCWG-486, 7/10 )
- Try to keep constant in register when expanding. But benchmark
results show regression due to combine behavior changes.
- Try to keep unsigned constant when expanding. For crc |= 0x8000,
crc is unsigned short. If 0x8000 is represented as unsigned value, no
need to split 0x8000. But in middle-end, wide_int_storage::set_len and
trunc_int_for_mode always do sign extension. "trunc_int_for_mode
(INTVAL (op), mode) == INTVAL (op)" is always checked when checking
operand (e.g. in general_operand of recog.c). And in RTL, there is no
"unsigned" information at all.
== Plans ==
* Update ccmp patches according to comments.
* Continue on constant optimization.
* Ping pending patches.
== Progress ==
* Zero/sign extension elimination (TCWG-15) (10/10)
- Posted two patches for review and gone through few iterations
- Looked at flag_wrapv and !flag_strict_overflow regressions
* ARM (and possibly some other targets) truncates negative values and
this makes them incompatible with the value range in SSA. One solution
is to ignore any gimple statements that load negative constants when
eliminating zero/sign extension elimination.
* We also loose the OVF(INF) information in tree when they are
converted to wide_int and propagated to SSA.
- Testing on a target that support PTR_EXTEND
* Trying to set-up x86_64-linux with -mx32. Still not able to compile
as I am getting various errors in glibc. Looking into it,
== Plan ==
* Upstream zero/sign extension elimination activities
== Week of June 23rd ==
- Continued working on toolchain testing improvements (CARD-1378, 6/10)
-- Various cleanups and improvements to cbuild2.
-- Troubleshooting of Jenkins stability problems.
-- Increasing test coverage for arm big-endian toolchains.
- Various meetings and discussions (3/10)
--
Maxim Kuvyrkov
www.linaro.org
== Week of June 16th ==
- Continued working on toolchain testing improvements (CARD-1378, 6/10)
-- Refactored cbuild2's schroot support after Rob's review
-- Posted updated patches
- Started moving TCWG dev environment master vm to Linaro's AWS (1/10)
-- This the the VM from where toolchain64.lava.schroot and maximk.schroot are synchronized.
-- Once migrated, all TCWG admins can access it, not just me.
- Various meetings and discussions (2/10)
--
Maxim Kuvyrkov
www.linaro.org
== Week of June 9th ==
- Continued working on toolchain testing improvements (CARD-1378, 6/10)
-- Added support for native testing inside schroot
-- Troubleshooting of various problems
-- Assisted Yvan in testing of the 2014.06 source release and general fire-fighting
- Various meetings and discussions (2/10)
- Interviewed 2 potential assignees (1/10)
--
Maxim Kuvyrkov
www.linaro.org
== Progress ==
* Patch review, testing and follow-up (4/10, CARD-341)
- glibc 2.20 freeze upcoming
- submit some warning fix patches
* Add support for ARM HWCAP2 to glibc (2/10, TCWG-499)
* Submit a patch for increasing ld max page size on ARM (1/10)
* Reformatted backports spreadsheet for glibc, binutils and gdb (1/10)
* Investigated language runtimes (1/10)
* Meetings (1/10)
== Issues ==
* None
== Plan ==
* More glibc patch work for the freeze (1st July)
* malloc benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* GCC trunk cross-validation (CARD-647) (6/10)
- email robot is now working
- added list of "ignored" tests when reporting regressions, mainly
because they are unstable when run under qemu (threads...)
- a57+crypto FPU config looks OK
- tried to use "contrib/test_summry" to send results, but that would
flood gcc-testresults mailing-list
- looked at impact of using CFLAGS/CFLAGS_FOR_TARGET etc upon
libstdc++ tests. Needs deeper investigation
- robustified scripts to handle more compute farm errors (random
"interrupted system call")
* AArch64 libsanitizer: no progress this week
* Neon intrinsic tests: review started
* Misc (meetings, conf-calls, ...) 4/10
- 4.7-2014.06 release done, benchmarks on-going
== Next ==
* GCC cross-validation
- look more deeply at the impact of the various CFLAGS (on testsuites results)
* Neon intrinsic tests:
- handle feedback
* AArch64 libsanitzer: resume work
* Publish 4.7-2014.06 release
== Progress ==
* Toolchain (CARD-862 1/10)
- Testing Compiler-RT on autoconf/ARM
- Checking LLD
* Automation Framework (CARD-1378 6/10)
- Writing script to manage TCWG rack
- Testing D01 with new kernel
- Testing Chromebook 2 vs. 1 vs. D01 for LLVM
- Cleaning up failed Chromebooks
- Pointlessly working on beagle bones
* Background (3/10)
- Code review, meetings, discussions, etc.
- Starting the GCC + LLVM presentation
== Plan ==
* continue trying to build compiler-rt with autoconf on ARM
* continue working on the LLVM + GCC presentation
* initial investigations on lld and MCLinker
The Linaro Toolchain Working Group (TCWG) announces the 2014.06-1 release of
the Linaro GCC 4.9 source package. This is a respin of the 2014.06 release which
fixes some issues on AArch64 big-endian and in AArch64 libjava.
Changes in this GCC source package release include:
* Updates to GCC 4.9.1-pre+svn211964
* Revert backport of [AArch64] Define TARGET_FLAGS_REGNUM.
* Backport of [AArch64] Cost model improvements.
Please find the original 2014.06 release notes below:
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.06
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.06 is the third Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1-pre+svn211054 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1-pre+svn211054
* Backport of [AArch32] PR rtl-optimization/60663
* Backport of [AArch32] Suppress Redundant Flag Setting for Cortex-A15.
* Backport of [AArch32] Support ORN for DIMode.
* Backport of [AArch32] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A.
* Backport of [AArch32] Allow any register for DImode values in Thumb2.
* Backport of [AArch32] Initialize new tune_params values.
* Backport of [AArch32] Initialise T16-related fields in Cortex-A8
tuning struct.
* Backport of [AArch32] Enable tail call optimization for long call.
* Backport of [AArch64] TRY_EMPTY_VM_SPACE Change for ILP32.
* Backport of [AArch64] Fix TLS for ILP32.
* Backport of [AArch64] vrnd<*>_f64 patch.
* Backport of [AArch64] Fix possible wrong code generation when
comparing DImode values.
* Backport of [AArch64] Add a space to memory asm code between base
register and offset.
* Backport of [AArch64] Fix aarch64_initial_elimination_offset calculation.
* Backport of [AArch64] vqneg and vqabs intrinsics implementation.
* Backport of [AArch64] Vreinterpret re-implemention.
* Backport of [AArch64] Define TARGET_FLAGS_REGNUM.
* Backport of [AArch64] Merge longlong.h from glibc tree.
* Backport of [AArch64] add, sub, mul in TImode.
* Backport of [AArch64] Add handling of bswap operations in rtx costs.
* Backport of [AArch64] Fully support rotate on logical operations.
* Backport of [AArch64] Use standard patterns for stack protection.
* Backport of [AArch64] VDUP Testcases.
* Backport of [AArch64] Vectorise bswap[16,32,64].
* Backport of [AArch64] Enable TBL for big-endian.
* Backport of [AArch64] Reverse TBL indices for big-endian.
* Backport of [AArch64] Relax modes_tieable_p and cannot_change_mode_class.
* Backport of [AArch64] Improve vst4_lane intrinsics.
* Backport of [AArch64] Rewrite and tests ZIP Intrinsics.
* Backport of [AArch64] libitm Enabled.
* Backport of [AArch64] Support full addressing modes for ldr/str in
vectorization scenarios
* Backport of [AArch32/AArch64] rtx costs (FMA, Cortex-A8, ...).
* Backport of Fix warning in libgfortran configure script.
* Backport of Remove PUSH_ARGS_REVERSED from the RTL expander
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Sorry for sending this late this week.
== Progress ==
* Ran gdb testsuite on arm and x86. Investigated failures on
arm-native-gdbserver config. [2/10]
* Investigate shared library gdb test failures with dejagnu on remote
connections. [TCWG-504] [2/10]
* Debug AArch64 GDB reverse watchpoints issue. [TCWG-503] [2/10]
* Debug AArch64 GDB handling of functions with empty prologue. [TCWG-504] [2/10]
* Understand gdb remote vs native feature parity patches. [1/10] [TCWG-263]
* Miscellaneous [1/10]
-- Setting up chromebook with 14.04
-- Meetings etc.
== Plan ==
* Further progress on AArch64 GDB reverse watchpoints issue. [TCWG-503]
* Further progress on AArch64 GDB handling of functions with empty
prologue. [TCWG-504]
== Progress ==
* Track down and fix build, testing, and Jenkins issues. (TCWG - 1378
9/10)
- Reinstalled everything needed for toolchain build and Jenkins on
the repaired chromebooks.
- Setup D01 and APM boards for toolchain building and testing,
added them to the Jenkins matrix.
- Updated qemu to the latest to get aarch32 & crypto support.
* Meetings and Misc (1/10)
== Plan ==
* Fix bare metal testing for aarch64.
* Continue working with the D01 boards.
* Track down and fix build, testing, and Jenkins issues. (TCWG - 1378)
== Issues ==
* Gerrit triggers only build trunk, and not the branch specified
in the review request.
== Progress ==
* More work on malloc microbenchmark (5/10, TCWG-160)
- Script for plotting results
- Analyze performance with SystemTap probe points
- Tidy up and submit v3
* Further work on ld issue on master (1/10, CARD-341)
* Patch review and testing (2/10, CARD-341)
* Annual leave on Friday (2/10)
* Still no luck on getting Ubuntu on wg boards
== Issues ==
* None
== Plan ==
* Make sure we have everything we need for glibc freeze at month end
* malloc app benchmark work
--
Will Newton
Toolchain Working Group, Linaro
=Progress=
memcpy regression on A9 - TCWG-390 [6/10]
* cortex-strings benchmarks suggest this isn't just an outlier, nor
entirely about preload
* Quick test on A15 suggests a similar (less severe) issue
* Got cortex-strings benchmarks more-or-less running via lava
memset performance improvement - TCWG-156 [1/10]
* GNU benchtests not as repeatable as hoped
lowlevellock performance bugs - TCWG-435 [1/10]
* Converted a bunch of inline functions into macros for coldfire
Meetings/mail/etc [2/10]
=Plan=
Carry on generating memcpy data, develop some hypotheses
Bugfix lava-ization of cortex-strings benchmarks as & when
Explore repeatability of cortex-strings benchmark
See how much quicker I can make cortex-strings benchmark without
compromising repeatability
Try to get lowlevellock.h committed for at least arm/aarch64
== Progress ==
* TCWG-418 : Bug fix Reload spill failure (3/10)
Bench marked coremark – no degradations with patch.
CPU2000 runs – Workedon running them as native in chromebook.
Issues with space.
* TCWG-181 : LTO enablement (3/10)
GCC 4.9 FSF no ICE . Linaro 14.07 release has ICE.
GIT bisect experiments on trunk on Aarch64 hardware.
* Misc: (2/10)
- Various meetings .
- PGO bootstrap runs on Aarch64 hardware - pass.
* AMD team out on 19th (2/10).
== Next ==
* GIT bisect experiments on LTO bootstrap.
* Continue Benchmark reload spill failure fix
* Explore on Large memory model support for aarch64
* Cbuildv2 release packaging on native.
== Progress ==
* Benchmarking and regression testing (TCWG-468) (3/10)
- More aarch64 spec2k benchmarking of patches and against fsf 4.9 release
- Spec2k a15 benchmarking on chromebook
* Zero/sign extension elimination (TCWG-15) (5/10)
- Fixed regressions found and broke the patch into two
- Looking at improving zero/sign extension elimination as it is not
happening for one test-case now
- Plan to benchmark the changes and post for review once this is done.
* LP spec2k regression bugs (2/10)
- #1320965 : Cant reproduce ICE but goes into infinite loop with
-floop-interchange at -O3; Looking into it
-#1330725 : Invalid as -fno-strict-overflow is needed for 254.gap.
== Plan ==
* Benchmarking and spec2k bugs.
* Upstream zero/sign extension elimination activities.
== Issues ==
* None.
== Progress ==
* loop2-invariant heuristics tuning (TCWG-469, 2/10). Two patches were
committed @r211818 and r211885. Another two are in review.
* Test the rebased ccmp patches (TCWG-488, 2/10).
* Send out a patch to enhance cprop pass by checking rtx_cost. Collect
benchmark results and update the patch according to comments
(TCWG-486, 6/10).
== Plans ==
* Ping pending patches.
* Continue on patches to optimize constant in loop.
== Progress ==
* GCC trunk cross-validation (CARD-647) (5/10)
- fixes to email-driven robot, now generating html reports
- trouble shooting transcient problems with the compute farm
- added a57+crypto FPU configuration, still under test
- added libstdc++ reports
* AArch64 libsanitizer (TCWG-58)
- Started looking at results. Different errors when running on HW
and under QEMU (where it goes in an infinite loop)
* Misc (meetings, conf-calls, ...) 3/10
- 4.7-2014.06 branch merge completed.
- 4.9 backports reviews
- trouble shooting connexion to tcwgXXX boards
== Next ==
* GCC cross-validation
- more fixes and enhancements
- continue testing of the email robot
* Neon intrinsic tests:
- discuss with upstream
* AArch64 libsanitizer:
- investigate generated code and cause for infinite loop
* Make 4.7-2014.06 final release
== Progress ==
* Automation Framework (CARD-1378 8/10)
- Setting up D01s
- Wasting time on Pandas
- Setting up serial console
- Preparing Chromebook2s
- Testing remote gcc check
* Background (2/10)
- Code review, meetings, discussions, etc.
== Plan ==
* help Guodong with D01 stabilisation
* have a look at compiler-rt autoconf build for buildbots
* start looking at the LLVM + GCC presentation
* probably more lab stuff...
=Progress=
memcpy regression on A9 - REQ-363 [3/10]
* Verified regression on a couple of targets, some investigation around cause
lowlevellock performance bugs - TCWG-435 [3/10]
* Upstreamed, some reworking based on review, obsessed about odd code
change & intermittent test failure
memset improvement - TCWG-156 [1/10]
* Started looking at glibc benchtests as a quicker way of doing
1st-round benchmarking
Meetings/mail/etc [3/10]
=Plan=
More of the above -
* Get some memset benchmarks running
* Carry on with lowlevellock patches (breaks m68k build, apparently)
* More memcpy investigation
== Progress ==
* GDB arm v8 record/replay
-- Investigated prologue analysis and stepping issues. [3/10] [TCWG-484]
-- Updates to JIRA cards.
-- Updates to patches stalled till next week.
* GDB arm v7 record/replay
-- Prepare SIMD instruction recording support patches for re
submission. [1/10]
-- Chromebook issues stalls Testing and submission till next week.
* GDB on Android improvements [3/10]
-- Discussions with community developers
-- Review of already submitted patches for catch syscall and exec events.
-- Making things work with available upstream patches.
* Miscellaneous [3/10]
-- Compassionate leave on Monday 9th June 2013.
-- Submit application for travel health certificate for UK travel in July.
-- Confirm travel and hotel booking after UK visa approval.
== Plan ==
* GDB arm v8 record/replay
-- Update all patches after upstream comments.
-- Investigate all remaining testsuite failures.
-- Update all related jira cards and create new for persisting test failures.
* GDB arm v7 record/replay
-- Update and resubmit upstream.
* GDB Remote vs Native feature parity (GDB on Android improvements) [CARD-321]
-- Prioritize todo list in light of currently active upstream development.
== This week ==
Out sick Tuesday and Wednesday (4/10)
Launchpad cleanup (6/10)
Launchpad 944572 - Infinite loop printing "warning: missing braces
around initializer" in g++
- fix released
Bugs marked "won't fix" after investigation:
Launchpad 683683 - run-init on omap3, omap4 in natty dies if busybox
is built with -marm
Launchpad 757427 - gconftool-2 segfaults on arm [shrinkwrap]
Launchpad 768384 - G++ gets stuck (100% cpu never finish) when
compiling C++ code with -O2/3
Launchpad 771675 - shrink-wrap optimization produce buggy code
Launchpad 625228 - Avoid unnecessarily saving $lr on Thumb-1
Launchpad 771832 - bogus reference to unused symbols
Launchpad 788841 - GCC ICE: internal compiler error: in push_minipool_fix
Launchpad 795131 - [armel, vfp] ICE in simplify_gen_subreg_concatn,
at lower-subreg.c:468
Launchpad 803798 - FTBFS on armel: error: unable to find a register
to spill in class 'VFP_LO_REGS'
Launchpad 807156 - GCC (g++):internal compiler error: in
extract_insn, at recog.c:2104
Launchpad 821455 - internal compiler error: in translate_clast, at
graphite-clast-to-gimple.c:1123
Launchpad 839959 - 4.5-2011.08 internal compiler error
Launchpad 841437 - fftw3 version 3.2.2-1 failed to build on armel
Launchpad 887158 - NULL pointer deref in mark_reg_pointer
Launchpad 890657 - Please merge the fix for upstream bug 45102
Launchpad 892880 - MIPS: link error against __unpack_d with
--enable-target-optspace
Launchpad 903178 - [4.6 regression/armhf] ICE, unable to find a
register to spill in class 'LO_REGS'
Launchpad 903347 - [armel/armhf] file fails to compile (indefinite loop?)
Launchpad 903951 - The kernel on staging-panda does not boot with the
11.12 released toolchain
Launchpad 937864 - Produces NEON code on armhf even when explicitly
asked not to
Launchpad 941676 - ppl ftbfs in precise on powerpc
Launchpad 943264 - ICE in arm_select_dominance_cc_mode, at
config/arm/arm.c:10625
Launchpad 1049614 - Assembler messages with -O0: Error: offset out of
range
== Next week ==
On vacation June 16th - June 20th
== Future ==
No Plans
= Progress ==
* Went to UK VISA office and submitted application and bio metrics (2/10)
* Tried Installing chrubuntu on chromebook. But failed and later found that
SD card issue. Given SD card back in office for replacement. Installed
crouton and other packages for building gcc and testing gcc testsuites
(1/10)
* Reload spill failure (bug fix) on armhf target (3/10)
Tested conservative patch that prevent ior_scc_scc patterns for thumb2
target using chrome book.
Thumb2 compare condition test cases fails. Found that these test cases
using constants for operands 2 and 5. Change conservative patch to allow
constant operands for thumb2 target in ior_scc_scc patterns. Testing is in
progress.
* LTO experiments (2/10)
Drilling down ICE with LTO on GCC 4.9 branch.
* Misc (1/10)
- 1-1 meetings (Ryan, Christophe) (0.5/10)
- AMD internal support work and meetings (0.5/10)
* Installed some packages and tested christophe libsantizer patch on
hardware (1/10)
== Plan ==
* Continue bug fixing.
* LTO bootstrap failure
== Progress ==
* Public holiday (2/10)
* Benchmarking and regression testing (TCWG-468) (8/10)
- Ran release benchmarking in chrome-book
- Set-up package build environment and ran ubutest
- spec2k benchmarking of patches that was included in 2014.06 release
on aarch64
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
== Issues ==
* None.
== Progress ==
* Work out 4 patches to enhance loop2-invariant heuristics and send
out for community review (TCWG-469, 3/10).
* Test the rebased ccmp patches (TCWG-488, 2/10).
* Investigate how to optimize large constant. Patch is in testing
(TCWG-486, 5/10). Basic idea is:
- Do not split large constant when expanding.
- Improve cprop pass to check the rtx_cost when propagating constants.
== Plans ==
* Ping pending patches.
* Send out ccmp patches for review.
* Send out patches to optimize constant.
== Progress ==
* Kernel (CARD-1246 1/10)
- Helping LLVMLinux to test in LAVA
* Background (9/10)
- Code review, meetings, discussions, etc.
- Setting up Chromebooks again (up, crouton)
- Setting up APM boards (up)
- Setting up D01 boards (bricked 2)
== Plan ==
* work with guodong, fabo, tyler, to revive the D01s
* put crouton on llvm-chrome-test to be ready for release 3.5
* have a look at compiler-rt autoconf build
* keep helping LLVMLinux with LAVA
Monday off. (2/10)
== Progress ==
* GCC trunk cross-validation (CARD-647) (3/10)
- improved scripts to avoid consuming to much memory
- improved kill signals handling when generating reports
- back to normal
- started looking at adding libstdc++ in the reports
- started looking at adding aarch32/armv8 configuration
- email-driven robot looks operational. Started testing with Kugan
* GCC 4.9 branch cross-validation (CARD-647)
- it's now running
* Neon intrinsic tests (CARD-???) (2/10)
- discussion started: scan-assembler directives may be difficult to maintain
- original testsuite maintenance: preparing aarch64 support
* AArch64 libsanitizer support (TCWG-58)
- Venkat tested my patch on HW, need to study the results and
compare with qemu
* Misc (meetings, conf-calls, ...) (3/10)
- 4.7-2014.06 branch merge prepared, validation started
== Next ==
* GCC cross-validation
- check patch to add libstdc++ in the reports
- define configuration for aarch32/armv8
- continue testing of the email robot
* Neon intrinsics tests:
- handle feedback
- original testsuite: continue aarch64 support, investigate output
formatting problems
* AArch64 libsanitizer support:
- analyze results
- use cbuild2 + tcwgbuild configs to run the tests myself on HW
* Backports reviews
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.06
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.06 is the third Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn211054 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1+svn211054
* Backport of [AArch32] PR rtl-optimization/60663
* Backport of [AArch32] Suppress Redundant Flag Setting for Cortex-A15.
* Backport of [AArch32] Support ORN for DIMode.
* Backport of [AArch32] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A.
* Backport of [AArch32] Allow any register for DImode values in Thumb2.
* Backport of [AArch32] Initialize new tune_params values.
* Backport of [AArch32] Initialise T16-related fields in Cortex-A8
tuning struct.
* Backport of [AArch32] Enable tail call optimization for long call.
* Backport of [AArch64] TRY_EMPTY_VM_SPACE Change for ILP32.
* Backport of [AArch64] Fix TLS for ILP32.
* Backport of [AArch64] vrnd<*>_f64 patch.
* Backport of [AArch64] Fix possible wrong code generation when
comparing DImode values.
* Backport of [AArch64] Add a space to memory asm code between base
register and offset.
* Backport of [AArch64] Fix aarch64_initial_elimination_offset calculation.
* Backport of [AArch64] vqneg and vqabs intrinsics implementation.
* Backport of [AArch64] Vreinterpret re-implemention.
* Backport of [AArch64] Define TARGET_FLAGS_REGNUM.
* Backport of [AArch64] Merge longlong.h from glibc tree.
* Backport of [AArch64] add, sub, mul in TImode.
* Backport of [AArch64] Add handling of bswap operations in rtx costs.
* Backport of [AArch64] Fully support rotate on logical operations.
* Backport of [AArch64] Use standard patterns for stack protection.
* Backport of [AArch64] VDUP Testcases.
* Backport of [AArch64] Vectorise bswap[16,32,64].
* Backport of [AArch64] Enable TBL for big-endian.
* Backport of [AArch64] Reverse TBL indices for big-endian.
* Backport of [AArch64] Relax modes_tieable_p and cannot_change_mode_class.
* Backport of [AArch64] Improve vst4_lane intrinsics.
* Backport of [AArch64] Rewrite and tests ZIP Intrinsics.
* Backport of [AArch64] libitm Enabled.
* Backport of [AArch64] Support full addressing modes for ldr/str in
vectorization scenarios
* Backport of [AArch32/AArch64] rtx costs (FMA, Cortex-A8, ...).
* Backport of Fix warning in libgfortran configure script.
* Backport of Remove PUSH_ARGS_REVERSED from the RTL expander
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* GDB arm v8 record/replay
-- Fixed issues showing up when building code with default
optimization. [TCWG-484] [3/10]
-- Fixed failures in until-reverse test cases. [TCWG-484] [1/10]
-- Investigation of failures in watchpoint-reverse and solib test
cases. [TCWG-484] [2/10]
-- Writing NEWS and changelog entries for all patches. [1/10]
* GDB Remote vs Native feature parity (GDB on Android improvements)
[2/10] [CARD-321]
-- Scored through recently submitted patches.
-- Ran testsuite in native and remote modes.
-- Started review of related open jira cards
* Miscellaneous
-- Visit uk visa office for passport collection. [1/10]
== Plan ==
* GDB arm v8 record/replay
-- Update all patches after upstream comments.
-- Investigate all remaining testsuite failures.
-- Update all related jira cards and create new for persisting test failures.
* GDB arm v7 record/replay
-- Update and resubmit upstream.
* GDB Remote vs Native feature parity (GDB on Android improvements) [CARD-321]
-- Further progress towards creating a tasks list and timeline.
* Miscellaneous
-- Finalize travel and obtain health certificate for travel to UK.
== Progress ==
* Zero/sign extension elimination (TCWG-15) (2/10)
- Posted patch for comment
* benchmarking (TCWG-468) (1/10)
- Ran a53 benchmarks
* regressions (7/10)
- THUMB1 regression for ARM fenv
* Issue due to thumb1 not supporting mrc/mcr. Patch to fix this is
posted for review.
- Regression when allocating 128bit integer to VFP register
* When LRA assigns DImode value to TImode register, it is not
setting up it in the right place of TImode. Due to this, one of the
moves becomes dead. Patterns needs to be checked.
* VFP registers store big-endian values in little-endian format.
Hence, subreg for mode greater than word has to
be aware of this. As it is, aarch64_cannot_change_mode_class will need
the fix like done in ARM.
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
= Progress ==
* LTO experiments (3/10)
Tested with various compiler revisions and in native X86 machines. Compare
errors in gcc 4.9 Linaro 14.05 version. Aarch64, LTO bootstrap passes in
trunk. On FSF GCC 4.9 branch encountering ICE. Opened PRs in GCC Bugzilla.
* Misc (2/10)
- 1-1 meetings (Ryan, Christophe and Maxim) (0.5/10)
- AMD internal support work and meetings (0.5/10)
Sick Leave on 2nd June (2/10)
UK VISA application processing (3/10)
== Plan ==
* UK VISA processing attend interview, biometrics.
* Continue bug fixing.
* LTO bootstrap failure
* Test libsanitizer patch for christophe.
=Progress=
lowlevellock performance bugs - TCWG-435 [1/10]
* All ready to go
cbuild benchmarking - TCWG-360 [4/10]
* Completed a draft implementation for spec2k
* Parked pending review
Meetings/mail/etc [5/10]
=Plan=
Send lowlevellock patches to list
Get back to benchmarking/improving cortex-strings memset