== Summary ==
- http://cards.linaro.org/browse/TCWG-13
- performance regression is due to alignment of function.
- there is an increase in runtime of core_state_transition even
though there is no difference in the code generated with the patch
- Adding nops seems to improve the locality and performance; it gets
better than without the patch for THUMB2.
- Get spec2000 results for http://cards.linaro.org/browse/TCWG-14 to
decide on the next step
- Couldn’t get SPEC2000 results with CBUILD
- set-up spec benchmarks in chromebook and now running locally.
-
https://blueprints.launchpad.net/gcc-linaro/+spec/better-end-of-loop-counte…
- Initial investigation shows that the code generated is same as
expected.
== Plan ==
- http://cards.linaro.org/browse/TCWG-13 - follow it up
- Get spec2000 results for http://cards.linaro.org/browse/TCWG-14 to
decide on the next step
- Look for improvement in VRP for zero/sign extension
== Progress ==
* Running around JM/lencode bug
- caused by a codegen opt (ICMP fold) that had repercussions only on A9
and A15 code generation
- spent three days trying to reduce the case when the problem fixed itself
miraculously >:(
* Planning for the future
- Agreeing on short-term plans for Q2
* Buildbot
- Working on self-hosting bot
- Moved local buildmaster to hackbox
* Investigating LLVMLinux
- Building Android kernel with LLVM
- Investigating breakage in Debug mode
== Plans ==
* Continue self-hosting bot
* Try running a CBuild benchmark with LLVM
* Start putting up together the infrastructure for release 3.3
* Try to extract useful information from perf database
Progress:
* qemu maintenance
** sent arm-devs and target-arm pullreqs now we're in softfreeze
* VIRT-4
** received Arndale board, confirmed it works (took several
hours mostly due to bonkers power switch design)
** VIRT-49
*** making progress; updated card with a list of sub-subtasks
Plans:
* keep pushing on with VIRT-49
* finish config of arndale board, test running KVM on it
* book travel/hotel for Connect Dublin
* office move Fri 26/Mon 29
-- PMM
All,
http://cbuild.validation.linaro.org/helpers/recent was reporting an Internal
Server Error earlier today, and after looking at the logs the resultant
cause was because the gcc-4.8+svn198079 Lava job
(https://validation.linaro.org/lava-server/scheduler/job/52224) decided that
it was an a9 (as opposed to a9hf) job and that it didn't no which version of
Ubuntu it was running on.
The caused the logs to be put in
http://cbuild.validation.linaro.org/build/gcc-4.8+svn198079/logs/armv7l--cb…
The tcwg-web app then fell over because it couldn't pass the
armv7l--cbuild-panda-es06-cortexa9r1 name.
I fixed the issue by manually renaming the build log directory to:
http://cbuild.validation.linaro.org/build/gcc-4.8+svn198079/logs/armv7l-pre…
And once the cron job which scans the builds had run everything now works.
Actions:
1. Paul - do you mind taking a look at the build and seeing what went wrong
- my initial cursory glance makes me believe its the board having heat
issues causing random things to happen.
2. Paul & Matt - Looking at the code (and from something else Michael said
to me last week) I think having hostnames with '-' characters in them will
confuse the cbuild interface. I propose changing cbuild to do a s/-/_/g on
all the hostname it reads as a workaround. I don't plan on changing actual
hostnames of boards. Paul is this going to cause a problem for you in Lava?
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
Hi,
Some time ago I had some problems linking my project libraries for
Android using the Linaro toolchain 4.7.1 which I reported to the
list:
http://lists.linaro.org/pipermail/linaro-toolchain/2012-June/002631.html
I ended up using the 4.6.x version of the compiler because
I could not find a fix and I did not get any hints from
the mailing list.
Now I need to really switch to 4.7(for better C++11 support)
but I'm pretty much having the same issue with the 4.7.3 version:
E.g.
System/Logging/DroidLogger.cpp.o: requires unsupported dynamic reloc
R_ARM_REL32; recompile with -fPIC
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error:
/home/marius/Development/ToolChains/Android/experimental_ndk/sources/cxx-stl/gnu-libstdc++/4.7.3/libs/armeabi-v7a/libsupc++.a(eh_globals.o):
requires unsupported dynamic reloc R_ARM_REL32; recompile with -fPIC
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error: hidden symbol '__dso_handle' is not defined locally
/home/dev/android/android_linaro_toolchain_4.7/bin/../libexec/gcc/arm-linux-androideabi/4.7.3/real-ld:
error: hidden symbol '__dso_handle' is not defined locally
I'm using it with the Android NDK version r8e.
I have downloaded the prebuilt binaries:
android-toolchain 4.7 (ICS, JB) <http://www.linaro.org/downloads/> 4.7-2013.03
13.03
(Linaro GCC 4.7-2013.03) 4.7.3 20130226 (prerelease)
Does anyone have any hints on how to overcome the above mentioned problem?
--
Marius Cetateanu | Software Engineer
T +32 2 888 42 60
F +32 2 647 48 55
E mce(a)softkinetic.com
YT www.youtube.com/softkinetic
SK Logo <www.softkinetic.com>
Boulevard de la Plaine 15, 1050, B-Brussels, Belgium
Registration No: RPM/RPR Brussels 0811 784 189
Our e-mail communication disclaimers & liability are available at:
www.softkinetic.com/disclaimer.aspx
Hi Matt,
This week I found an error in LLVM that can only be reproduced on ARM
hardware, if the GCC that compiles it specifies --mcpu=cortex-a15. The
error is a segfault on one of the tests compiled by that Clang/LLVM. As you
can see, it's not something trivial that we'd expect people to do easily.
My question is: How do we tackle this type of bug?
One option is to do all the debugging and interface with the original patch
author until we fix the problem. This works well for simple bugs, but in
this case I'm not sure it will work.
Another option was to have a board on Linaro's DMZ with no access to
anything else internally, so that people could log in and debug the problem
in situ.
This board would have to be setup just for the debugging with a random
password given only to the author of the patch and cleaned up right after
the bug is fixed (to avoid external abuse).
We could use the same board for LLVM, GCC, GDB, etc. but it should be easy
to re-flash it to a minimum system, so that we don't spend too much time
setting it up.
Does anyone have a better idea?
cheers,
--renato
Hi,
Feel free to point me at a newer toolchain. Was building the SNU
OpenCL SDK native on my chromebook running ubuntu raring when I hit
the following:
make: Entering directory `/home/tgall/opencl/SNU/src/runtime/build/cpu'
arm-linux-gnueabihf-g++ -fsigned-char -march=armv7-a -mfloat-abi=hard
-mfpu=neon -ftree-vectorize -ftree-vectorizer-verbose=0 -fsigned-char
-fPIC -DDEF_INCLUDE_ARM -g -c -o smoothstep.o
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common/smoothstep.c
-I/home/tgall/opencl/SNU/inc
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/async
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/atomic
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/conversion
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/geometric
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/integer
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/math
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/reinterpreting
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/relational
-I/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/vector -O0 -g
In file included from
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/cl_cpu_ops.h:47:0,
from
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/common/smoothstep.c:34:
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/type/cl_ops_floatn.h:
In function 'float2 operator-(float, float2)':
/home/tgall/opencl/SNU/src/runtime/hal/device/cpu/type/cl_ops_floatn.h:114:1:
internal compiler error: output_operand: invalid operand for code 'P'
Please submit a full bug report,
with preprocessed source if appropriate.
See <file:///usr/share/doc/gcc-4.7/README.Bugs> for instructions.
Preprocessed source stored into /tmp/cciluYVq.out file, please attach
this to your bugreport.
Traceback (most recent call last):
File "/usr/share/apport/gcc_ice_hook", line 34, in <module>
pr.write(open(apport.fileutils.make_report_path(pr), 'w'))
File "/usr/lib/python2.7/dist-packages/problem_report.py", line 254, in write
self._assert_bin_mode(file)
File "/usr/lib/python2.7/dist-packages/problem_report.py", line 632,
in _assert_bin_mode
assert (type(file) == BytesIO or 'b' in file.mode), 'file stream
must be in binary mode'
AssertionError: file stream must be in binary mode
make: *** [smoothstep.o] Error 1
tgall@miranda:~/opencl/SNU$ arm-linux-gnueabihf-g++ --version
arm-linux-gnueabihf-g++ (Ubuntu/Linaro 4.7.2-23ubuntu2) 4.7.3
I've attached the preprocessed source as well.
FWIW, I don't hit this when building with -O3. In this case I was
compiling for debug.
Thanks!
--
Regards,
Tom
"Where's the kaboom!? There was supposed to be an earth-shattering
kaboom!" Marvin Martian
Tech Lead, Graphics Working Group | Linaro.org │ Open source software
for ARM SoCs
w) tom.gall att linaro.org
h) tom_gall att mac.com
== Progress ==
* Disable-peeling:
- some benchmarking jobs ran, thanks to the new boards in cbuild.
- Spawned other jobs for reference
* Libsanitizer:
- Built native GCC on snowball to understand the isatty() behaviour
compared to qemu.
* Neon intrinsics codegen:
- resumed looking at the vuzp crc example from Steve Capper.
* Neon intrinsics codegen:
- added fp16 support (works with RVCT, GCC does not support it yet)
* Internal support
== Next ==
* Disable-peeling: analyze results when available.
* Revert-coalesce-vars: idem.
* Libsanitizer: analyze isatty() on board
* Neon intrinsics: continue with vuzp example.
One day off this week.
== Issues ==
* None
== Progress ==
* Linaro GCC 4.8, 4.7 and 4. 2013.04 released (with CL and MG)
* Boehm-gc AArch64 support backport in GCC:
- support committed.
* Libunwind AArch64 support:
- Resumed ongoing work.
== Plan ==
* Libunwind AArch64 support:
- Fix and submit upstream
== Progress ==
* Started investigating dwarf test suite failures on ARM.
* Created a new comparison between arm native gdb and arm remote gdb.
* More investigation of test cases to figure out causes of test cases that
are not run or unsupported.
* Experimentation with screens on gateway to speed up remote debugging,
didnt work.
* 1:1 with Matt.
* Took a day off on Friday 12th April 2013 for car checkup in workshop.
* Received Invitation letter from Arwen on Friday which means now visa
application only needs hotel booking information.
*** Still No blue-print available to log work in JIRA.
== Plan ==
* Setup arm gdb to debug itself and debug dwarf problems on arm.
* Fill up the arm native vs arm remote comparison sheet.
* Submit Ireland visa application after receiving invitation letter and
hotel booking details.
* Setup screens for remote testing using toolchain cbuild infrastructure.
== Progress ==
* gc sections tests
Completed upstream of g-c section patches after updating review comments.
Closed the card associated with the work.
http://cards.linaro.org/browse/TCWG-27
* gprof support work for Aarch64
Read gprof internal documents from sourceware.org.
Working on GCC side to support gprof for Aarch64.
Misc
------
11-4-2013 was a local holiday.
== Plan ==
* Continue gprof support work for Aarch64
* Attend internal team meetings on 16 and 17th.
== Summary ==
- http://cards.linaro.org/browse/TCWG-14
Coremark ARM mode gives about 2% performance improvement with about 1%
code size reduction. Thumb2 mode however has performance regression even
though code size reduces about 0.6%. Performance regression here is like
what we are seeing in EPILOGUE_UESES
changes(http://cards.linaro.org/browse/TCWG-13). Spawned spec in CBUILD
to see the impact with spec2000.
- http://cards.linaro.org/browse/TCWG-13
Thumb2 mode performance regression is due to the percentage of time
spent in core_state_transition. Looks like an alignment issue; same asm
is generated for this function with the patch. Investigating it.
== Plan ==
- Plan to resolve http://cards.linaro.org/browse/TCWG-13 this week.
- Get spec2000 results for http://cards.linaro.org/browse/TCWG-14 to
decide on the next step
== Progress ==
* Setting up Chromebook with Ubuntu 13.04.
* Developing patch to integrate new memcpy into glibc with IFUNC.
* Debugging and submitting a patch for linker issue with IFUNC.
== Issues ==
* None.
== Plan ==
* Get newlib mempcy patch accepted.
* Follow up memcpy in bionic.
* Submit memcpy IFUNC patch to glibc list.
* Get binutils tests into cbuild.
--
Will Newton
Toolchain Working Group, Linaro
Progress:
* qemu maintenance
** rebased qemu-linaro again
** preparing for upstream softfreeze on 15th
** review virtio patches and anything else that needs
attention pre-freeze
** scan of buglist; provided analysis of problem for LP:1090038,
closed a few stale bugs
** fixed a bug in an edgecase in fused multiply-accumulate emulation
* VIRT-4 [Guest migration support for KVM]
** VIRT-51
*** patches committed upstream, work item complete
** VIRT-73
*** updated Juan's patches to use VMState for ARM CPU migration,
fixed a few bugs noted along the way, submitted upstream
[work item now just pending review & commit]
Plans:
* qemu maintenance
* VIRT-4
** VIRT-49
-- PMM
The Linaro Toolchain Working Group is pleased to announce the 2013.04
release of Linaro GCC 4.8, Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.8 2013.04 is the first release in the 4.8 series. Based off the
latest GCC 4.8.0+svn197294 release, it includes performance improvements and
bug fixes.
Interesting changes include:
* Our first 4.8 based release
* Updates to GCC 4.8.0+svn197294
* Initial optimized support for Cortex-A53 for arm*-*-* targets
* Improved support for new ARMv8-A instructions for arm*-*-* and
aarch64*-*-* targets.
* Backport of optimizations concerning whether to use Neon for 64-bit
bitops for arm*-*-* targets.
Linaro GCC 4.7 2013.04 is the thirteenth and last development release in the
4.7 series before entering maintenance. Based off the latest GCC 4.7.2+svn197188
release, it includes ARM-focused performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.2+svn197188
* Includes arm/aarch64-4.7-branch up to svn revision 196381
* Backport vectorizer cost model
* Turn off 64-bit Bitops in Neon
Linaro GCC 4.6 2013.04 is the 26th release in the 4.6 series. Based
off the latest GCC 4.6.3+svn197511 release, this is the thirteenth
release after entering maintenance and the last regular one.
Interesting changes include:
* Updates to 4.6.3+svn197511
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.8-2013.04https://launchpad.net/gcc-linaro/+milestone/4.7-2013.04https://launchpad.net/gcc-linaro/+milestone/4.6-2013.04
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release pages:
https://launchpad.net/gcc-linaro/4.8/4.8-2013.04https://launchpad.net/gcc-linaro/4.7/4.7-2013.04https://launchpad.net/gcc-linaro/4.6/4.6-2013.04
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
Hi all,
Currently the binutils job that gets run via cbuild configures with
--enable-gold. I guess this could be useful to ensure the gold build
is not broken, but has the downside of slowing down the build and
causing make check to fail.
I propose we do not enable gold until such a time as we wish to
formally support gold and fix the broken make check.
Does anybody have any objections to doing that?
Thanks,
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Investigated gdb test cases that are failing on
arm-remote gdbserver configuration.
-- Fixed some failures by updating host cross compiler version
-- Fixed some failures by fixing environment issue where not being loaded
properly.
-- All test cases that need to build a shared library and transfer it to
remote target FAIL due to problems which seems like dejaganu limitations.
* Ran GDB test suite on x86_64 remote gdbserver configuration and compared
performance of same configuration on arm.
* Got most documentation ready for Ireland Visa application, still waiting
on invitation letter and hotel booking details.
*** Still No blue-print available to log work in JIRA.
== Plan ==
* Investigate compiler version specific and general failures on arm remote
gdbserver configuration.
* Start on investigation/fixing of arm specific failures in gdb test suite
results.
* Submit Ireland visa application after receiving invitation letter and
hotel booking details.
* Planned Holiday
-- Planned Day off on Friday 12th April 2013 for car checkup in workshop.
== Summary ==
- benchmarking coremark with VRP based extension elimination
* extension elimination in some cases affecting other optimizations
* With this improvements are marginal (details below)
== Plan ==
- study crc where extension elimination is resulting in bad code
- Find a solution
==Details==
If an assignment gimple statement has RHS expression value that can fit
in LHS type, truncation is redundant. Zero/sign extensions are redundant
in this case and rtl statement can be replaced as
from:
(insn 12 11 0 (set (reg:SI 110 [ D.4128 ])
(zero_extend:SI (subreg:HI (reg:SI 117) 0))) c5.c:8 -1
(nil))
to:
(insn 12 11 0 (set (subreg/s/u:HI (reg:SI 110 [ D.4128 ]) 0)
(subreg:HI (reg:SI 117) 0)) c5.c:8 -1
(nil))
With this change, for the following case:
short unPack( unsigned char c )
{
/* Only want lower four bit nibble */
c = c & (unsigned char)0x0F ;
if( c > 7 ) {
/* Negative nibble */
return( ( short )( c - 16 ) ) ;
}
else
{
/* positive nibble */
return( ( short )c ) ;
}
}
asm without elimination
unPack:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
and r0, r0, #15
cmp r0, #7
subhi r0, r0, #16
uxthhi r0, r0
sxth r0, r0
bx lr
.size
asm with elimination
unPack:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
and r0, r0, #15
cmp r0, #7
subhi r0, r0, #16
sxth r0, r0
bx lr
In some cases, changed rtl statement is not eliminated by later passes
and is generated as a mov instruction. Worse, it also seems to affect
the other optimization passes and resulting in worse code for crc. Not
found the cause for it yet.
== Progress ==
* gc sections tests
Completed adding gc-section test cases.
1. TLS and GOT tests.
http://sourceware.org/ml/binutils/2013-03/msg00273.html
2. PLT tests.
http://sourceware.org/ml/binutils/2013-03/msg00273.html
* Evaluate gprof work.
There is one function hook "find_call" which is machine dependent and
is written for i386.c/sparc
Then there are changes in configure.in to add architecture details.
* 1-1 with Matt.
== Plan ==
Continue gprof support work for Aarch64
== Progress ==
* Buildbots
- All ARM build-bots GREEN! Hurray!!! :D
- Improving sort comparison functions makes output reproducible on all
machines
- Fixed fpcmp, which fixes sqlite3 report
- A bad commit broke lots of tests, reverted
- Adding a self-hosting check-all Pandaboard
- In theory, it works, but config is not perfect yet
* Arndale
- Suse image is not stable enough, installed Linaro (325)
- Fathi got GCC bootstrapping with it, should work
- Installed a heat-sink on the board, should reduce problems
- Still got network issues, may be the mac address
- Someone could liaise with Dave Pigott to get a new MAC on the DHCP
* EuroLLVM 2013
- Badges, finishing touches
== Plan ==
* Holidays next week, then
* Check with Galina about Beagle bots
* Finish Panda self-host + test-suite A9 bot
* Gather info and hardware for 3.3 release tests
* Plan for the future!
== Progress ==
* Short week (2 days)
* Tested memcpy on big endian.
* Updated newlib memcpy patch.
* More digging into glibc IFUNC.
== Issues ==
* None.
== Plan ==
* Try and get newlib mempcy patch accepted.
* IFUNC...
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Disable-peeling:
- Still waiting for the results from cbuild. Because of many merges
(pre-release week), there are a lot of jobs in the queue :-(
* Libsanitizer:
- tried to understand why isatty(2) returns true when executing the
testsuite via qemu.
* Neon intrinsics codegen:
- benchmarking in bare-machine shows that GCC is actually ~5% faster
than RVCT on this sample codec.
- to be further discussed internally
* Neon intrinsics testsuite:
- looking at FP16 support.
* Turnoff 64bits ops in Neon:
- backport in 4.8 done by Matt during the release merges.
* Arndale: a few attempts to use it, but it's still unstable.
* Internal support
== Next ==
* Disable-peeling: Analyze bench results when available.
* Revert-coalesce-vars: Analyze bench results when available.
* Libsanitizer: contine isatty(2) study wrt qemu/expect.
* Neon intrinsics: check internally for other codecs
[short week, two days]
Progress:
* qemu maintenance
** arm-devs pull request (and associated code review, etc)
* VIRT-4 [Guest migration support for KVM]
** VIRT-49: implement cp15 sync with kernel
*** some forward motion, but partway through realised some work
I thought had been committed last year hadn't been, so:
** VIRT-73
*** new work item, covering updating the migration state for the
CPU itself to use VMState structures, by updating, testing
and tweaking some patches from Juan Quintela from last year
*** have done the 'update' part; tests and tweaks still todo
-- PMM
Summary:
* Investigate conditional compare.
Details:
1. Expand conditional compare as TRUTH_AND_EXPR/TRUTH_IOR_EXPR for tests.
2. Test tree-level changes for conditional compare.
* Fix/workaround most ICE issues in regression tests.
* Still some fails which expected VRP can optimize the cases.
3. Try to build Coremark and find that conditional compare does block
optimizations, which leads to worse performance.
Plan:
* Investigate VRP and other optimizations to handle conditional compare.
* Raise the propose for upstream discussion.
Planned leaves:
* April 4-8: Chinese Ching Ming Festival and annual leaves.
* April 12: Internal team event.
* April 16-17: Internal training.
Best Regards!
-Zhenqiang
== Progress ==
Started investigating gdb test cases that are failing on
arm-remote gdbserver configuration.
Completed investigation on all timeout gdb test cases failures in
arm-remote gdbserver configuration.
Setup a ubuntu test machine for gdb testing on x86_64 in
remote gdbserver configuration.
Initiated visa process for Ireland and sent requests for required documents
to Arwen.
*** No blue-print available to log work in JIRA.
== Plan ==
Complete investigation of all failure gdb test cases on arm-remote
gdbserver configuration.
Run gdb test suite in x86_64 remote gdbserver configuration and compare
with all other configurations already tested including arm remote to figure
out any similar failures while running test suite remotely on two different
machines.
Book travel to Ireland and complete visa process.
Summary:
* Investigate how to expand conditional compare.
Details:
1. Try to expand conditional compare to RTL
* It seams hard to expand conditional compare to just one cond_exec
insn during expand, since it has to know the cc (GT, LT, etc) set from
previous instruction and tell the later instruction which cc (GT, LT,
etc) it set.
* Try to add new RTL key-word and insn pattern.
2. Follow up Linaro toolchain binaries bug in Yocto build: 1159392,
1161348 and 1161351.
Plan:
* Generate asm for conditional compare.
Planned leaves:
* April 4-8: Chinese Ching Ming Festival and annual leaves.
* April 12: Internal team event.
* April 16-17: Internal training.
Best Regards!
-Zhenqiang
== Progress ==
- Very short work week. I was on leave last Wednesday and Thursday (27th
and 28th).
- Posted patch for gc-section tests for TLS and got related relocs.
- Discussing with Marcus on patch I wrote for gc section tests on PLT
related relocs.
== Plan ==
- Post patch for gc section tests for PLT relocs.
- Complete gc section tests for other generic cases.
- Understand and evaluate gprof support work for Aarch64
== Progress ==
working on http://cards.linaro.org/browse/TCWG-14
- All but 2 test cases are passing and extension elimination for the
simple cases are eliminated
- one of the test failure was due to bug with value range propagation
pass. Have to investigate this further.
- In one instance even though extensions are removed, 1 more instruction
is generated (for crc) - Need to investigate it
- Got the chromebook and Set up Ubuntu; boot strapping gcc now
== Plan ==
- Start with the benchmarking
- investigate the performance and VRP issue
- Also start with http://cards.linaro.org/browse/TCWG-13 in parallel
== Issues ==
* None
== Progress ==
* Libunwind AArch64 support:
- Most of the testsuite is now fine
- but some fixes still needed before upstream submission.
== Plan ==
* Libunwind AArch64 support:
- Fix and submit upstream.
== Progress ==
* Disable-peeling:
- benchmarked locally on snowball. Observed a few regressions in spec2k.
To be analyzed and confirmed with the results from cbuild.
- patched cbuild to work-around a bzr bug which prevented these jobs
from being spawned.
* Libsanitizer: sent patch upstream.
Discussion about interactions with qemu.
* Revert-coalesce: spawned thought-to-be reference jobs for benchmarking.
* Neon intrinsics codegen:
- First analysis of sample codecs seems to indicate that gcc
generates sequences of interdependent instructions where rvct manages
to insert some code in between.
- To be confirmed by dedicated benchmarking, probably in bare-machine mode.
* Neon intrinsics testsuite:
- Added support for polynomial variants (*_p8, *_p16)
- Identified wrong code generated by gcc-linaro-4.7; did not check with trunk.
- Transforming into a dejagnu forms will probably be a lot of work :-(
* Internal activities
== Next ==
* Disable-peeling:
- analyze bench results from cbuild when available
- compare with the results from my snowball
* Libsanitizer:
- resume investigation about isatty problem when ran under qemu.
* Turnoff 64bits ops In Neon:
- backport in linaro-4.8 once the process has been clarified.
* Revert-coalesce:
- check bench results
* Neon intrinsics codegen:
- perform dedicated benchmarking
== Progress ==
* Booked flight for LCE.
* Benchmarked and ran tests on new memcpy implementation.
* Attempted but failed to get new memcpy tested on big endian (still todo).
* Committed new memcpy implementation to cortex strings.
* Passed new memcpy to Android team for bionic.
* Submitted newlib patch for new memcpy.
* Committed binutils ld-elfvsb testsuite fixes, native testsuite now green!
* Further investigation of IFUNC in glibc.
== Issues ==
* Pandaboard ES still a bit flakey, Chromebook hopefully on its way to
replace it.
== Plan ==
* Iron out issues with native binutils make check in cbuild/LAVA.
* Get newlib memcpy patch committed.
* Investigate testing memcpy on big endian (qemu user, models?).
* IFUNC...
--
Will Newton
Toolchain Working Group, Linaro
Progress:
* qemu maintenance
** https://ci.linaro.org/jenkins/job/qemu-ltp/ now shows graphs
of LTP test results for linux-user mode
** rebased qemu-linaro and got it working again (omap3 display
code needed rework after upstream changes)
** investigated why Christoffer Dall's kernels weren't booting:
turns out to be that vexpress now requires CONFIG_REGULATOR
but doesn't force it to be set or set it in the vexpress_defconfig
** rebased/resent/pinged various in-flight patches
* VIRT-4 [Guest migration support for KVM]
** VIRT-49: implement cp15 sync with kernel
*** located my work on this from last year, refreshed my
memory on how far I'd got and what I was planning to do
-- PMM
== Progress ==
* Re-installed the panda buildbot, using USB drive as bot dir
* Reviewing lots of ARM patches (more than usual)
* Trying Arndale again, some errors, some passes, cooler might be
responsible
- Got one internal error, one build error and one pass with Ubuntu kernel
+ patch
- Trying Suse image:
- It has a broken serial driver (makes things much harder)
- sshd does not start by default (in conjunction with serial bug, it's a
killer)
- Now running on a precarious mode, hopefully enough for our needs
* sqlite3 error due to VMUL.f64 while on x86_64 "long double" is f128
- sqlite3 is the best example on what NEVER to do with floating point
values >:|
- Sent patch, working around TILE-Gx issues
== Issues ==
* Still a bit ill, productivity reduced
* Not having a wired network on my desk wastes a LOT of my time
== Plan ==
* Push the sqlite3 patch though
* Continue fixing the 4 remaining broken tests
* Continue with Arndale investigation with Christophe and Zhenqiang
Hi folks,
I'm trying again the bootstrap of GCC on Arndale and it goes pretty well
until it has to install libgcc that it just compiled.
When I build first time, I get an error while installing libgcc:
make[4]: Entering directory
`/home/linaro/devel/gcc/build/objs/armv7l-unknown-linux-gnueabihf/libgcc'
/bin/bash /home/linaro/devel/gcc/src/libgcc/../mkinstalldirs ../.././gcc
(...)
/bin/bash /home/linaro/devel/gcc/src/libgcc/../mkinstalldirs ../.././gcc;
/usr/bin/install -c -m 644 ./libgcc_s.so.1 ../.././gcc/libgcc_s.so.1; rm -f
../.././gcc/libgcc_s.so; /usr/bin/install -c -m 644 ./libgcc_s.so
../.././gcc/libgcc_s.so
Live child 0x01dec548 (install-shared) PID 4405
Reaping losing child 0x01dec548 PID 4405
make[4]: *** [install-shared] Error 1
Though, if I run that command by hand, it works...
I then re-ran make and the first point there is an error is on gmp:
This program built for arm-unknown-linux-gnueabihf
Reading makefiles...
Reading makefile `Makefile'...
Reaping losing child 0x01866320 PID 4784
make[3]: *** [config.h] Error 1
Removing child 0x01866320 PID 4784 from chain.
make[3]: Leaving directory `/home/linaro/devel/gcc/build/objs/gmp'
Need a job token; we have children
Duplicate the job FD
Live child 0x00ae17f8 (all-stage1-libiberty) PID 4755
Live child 0x00be3508 (all-stage1-gmp) PID 4736
Reaping losing child 0x00be3508 PID 4736
make[2]: *** [all-stage1-gmp] Error 2
Removing child 0x00be3508 PID 4736 from chain.
Released token for child 0x00be3508 (all-stage1-gmp).
make[2]: *** Waiting for unfinished jobs....
Live child 0x00ae17f8 (all-stage1-libiberty) PID 4755
I can't notice anything wrong on gmp (all objects are there), other than a
number of symlinks to a missing directory:
gmp-mparam.h -> /home/linaro/devel/gcc/src/gmp/mpn/generic/gmp-mparam.h
the directory "generic" doesn't exist, and lots of files in "mpn" also
point there. Could be a red herring, though.
Any ideas?
cheers,
--renato
PS: this doesn't look like an Arndale specific bug, so we might still be
able to use them for GCC bootstrapping...
Summary:
* Send out shrink-wrap related patches for review.
* Investigate how to add a new tree code.
Details:
1. Fix lp:1157050 and lp:1107659 for Linaro toolchain binaries.
2. Test shrink-wrap dwarf/unwind info and send out the patches for review.
3. Make progress on conditional compare support. With some hard-codes
in gcc, it can gimplify a small case to conditional compare on tree
and no assert until expand.
Plan:
* Investigate how to expand conditional compare GIMPLE to RTL and emit asm.
Planned leaves:
* March 31.
* April 4-8.
Best Regards!
-Zhenqiang
Hi all,
I'd like to run the binutils testsuite in a native configuration
regularly to find any regressions. Do we have any infrastructure for
doing this?
It looks like LAVA would be useful but it looks complex and I am not
sure if we use that already for running toolchain tests (I think there
was a Connect session about that?).
Thanks,
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Disable-peeling:
- benchmarking locally on snowball
- failed to build reference branch on cbuild, for an unknown reason
* Turnoff 64bits ops in Neon:
- committed upstream in 4.9 (now stage 1)
- benches of backport into Linaro-4.7 OK: no significant diff,
except +12.6% on spec2k's crafty)
- Filed merge request.
* Vectorizer cost model:
- benches of backport inot Linaro-4.7 OK (no significant diff, as expected).
- Filed merge request.
* Revert-coalesce:
- benches ran in cbuild, but no *-diff.txt file generated.
* Libsanitizer:
- testsuite results OK. All unsupported tests are normal.
* Neon intrinsics codegen:
- got internal feedback
* GDB reverse debug:
- filed 2 bug reports after internal requests.
* Misc:
- filed several bug reports against cbuild to track the problems I observed.
== Next ==
* Disable-peeling:
- analyze bench results
- understand/'fix what's wrong with cbuild
* Turnoff 64bits ops in Neon:
- backport to Linaro-4.8
* Revert-coalesce:
- manually compute bench differences if unable to have cbuild do it.
* Libsanitizer:
- propose patch upstream.
== Progress ==
Knocked out more GDB remote configuration failures that were failing due to
timeouts.
Had 1:1 with Matt for direction on GDB improvement plan.
Looked around for Ireland visa process and filled out visa application.
== Plan ==
Complete review of remote timeout based test case failures.
Start work on the GDB improvement blueprint in JIRA from this week.
Get remaining documentation for Ireland visa and complete application.
== Progress ==
- Looking at TLS relocs and coming up with test cases for garbage
collecting them.
- Patch for missedout testcases in gc section is up streamed. Thanks to Marcus.
== Plan ==
- Complete gc section test cases for TLS relocs.
- Understand and evaluate gprof support work for Aarch64
Misc
-----
Leave on Wednesday and Thursday (27th and 28th)
== Progress ==
- Worked on VRP based zero/sign extension elimination at tree level
- Some regression test cases are failing; investigating them
== Plan ==
- Analyse the reason for test case failure and fix them
- Extend the code to handle all the possible cases (currently
implemented for subset to get the framework working)
== Issues ==
* None
== Progress ==
* Libunwind AArch64 support:
- basic implementation for building lib and testsuite done
- but even a simple test case doesn't work for the moment
== Plan ==
* Libunwind AArch64 support:
- continue AArch64 specific implementation and informtation gathering
== Progress ==
* EuroLLVM paper review
* Disabled EH tests on ARM for now
* Fixed TSVC: NEON vs. VFP VMUL.f32 (and IEEE 754 correctness)
* Changed FeatureNEONForFP to false on EABI ARM targets unless unsafe-math
* Trying Arndale again, with u-boot patched, not good
* Broken Panda buildbots, trying to fix
== Issues ==
Got ill on Tuesday and only worked partially, if at all, the rest of the
week
Hopefully will be better next week...
== Plan ==
* Fix our panda buildbot, maybe add more
* Final try on Arndale GCC bootstrap before giving up
* Continue fixing test-suite failures (only 5 left)
Progress:
* VIRT-4 [Guest migration support for KVM]
** VIRT-51: vexpress migration:
** wrote and submitted patches for all the devices that need fixes
** tracked down a painful bug where the guest just hung on vmload
to a missing state-save for a timer device, submitted patch
** remaining work for this item is just responding to patch review
-- PMM
Hi folks,
I found an issue while fixing a test using the wrong VMUL.f32, and I'd like
to know what should be our choice on this topic that is slightly
controversial.
Basically, LLVM chooses to lower single-precision FMUL to NEON's VMUL.f32
instead of VFP's version because, on some cores (A8, A5 and Apple's Swift),
the VFP variant is really slow.
This is all cool and dandy, but NEON is not IEEE 754 compliant, so the
result is slightly different. So slightly that only one test, that was
really pushing the boundaries (ie. going below FLT_MIN) did catch it.
There are two ways we can go here:
1. Strict IEEE compatibility and *only* lower NEON's VMUL if unsafe-math is
on. This will make generic single-prec. code slower but you can always turn
unsafe-math on if you want more speed.
2. Continue using NEON for f32 by default and put a note somewhere that
people should turn this option (FeatureNEONForFP) off on A5/A8 if they
*really* care about maximum IEEE compliance.
Apple already said that for Darwin, 2 is still the option of choice. Do we
agree and ignore this issue? Or for GNU/EABI we want strict conformance by
default?
GCC uses fmuls...
cheers,
--renato
Hello,
I am having an issue with using the gcc toolchain for armv8. I am trying to
cross compile a simple program (helloworld.c) as suggested in the link :
https://wiki.linaro.org/HowTo/HelloAarch64.
But when I try executing the binary on the simulated armv8 (using
foundation model), I am getting error in GLIBC, specifically
"/lib/libc.so.6: version `GLIBC_2.16' not found" . Could you please help me
as to what could be wrong here?
Thanks,
Pavan
== Progress ==
* Analyzed Android kernel linker issue and created LP #1154165 to track it.
* Triaged remaining binutils Launchpad tickets.
* Setup my Pandaboard with Linaro 13.01 (13.02 oopses on boot) to run tests.
* binutils: Committed fix for LP #517081 (Floating-point assembly and
disassembly bugs on armel) upstream.
* binutils: Committed a fix for ARM EABI tests upstream.
* Lots of admin stuff.
== Plan ==
* Get binutils testsuite green in a native configuration (fix LP #812276).
* Investigate getting binutils testuite automated via cbuild/Lava.
* More bugs...
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
Reviewing GDB tests that FAIL due to timeout problems in remote
configuration.
Made some changes to some of the GDB tests that FAIL on arm targets to
check if they work by minor modifications.
Sick Days: Had been sick due to cough n fever and a drop in blood pressure
made me take most part of Thursday and Friday off.
== Plan ==
Get with Matt for Post- Connect work targets.
Review remaining GDB tests that FAIL due to timeout problems in remote
configuration.
Further experiments with GDB test suite to check support for unsupported
tests on arm.
The Linaro Toolchain and Platform Working Groups are pleased to announce
the 2013.03 release of the Linaro Toolchain Binaries, a pre-built version
of Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2013.03
* Linaro GDB 7.5 2012.12
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link your
programs against.
Interesting changes include:
* gcc updated to 4.7-2013.03:
* Updates to GCC 4.7.2+svn196272
* Includes arm/aarch64-4.7-branch up to svn revision 196225
* A fix for LP #1135633: [linaro regression] alsa-tools FTBFS with error
"unable to find a register to spill in class ‘AREG’"
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian 6.0.2,
Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation 5.7 and
later, and should run on any Linux Standard Base 3.0 compatible
distribution. Please see the README about running on x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2013.03
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Short week to ...
== Progress ==
* Configured GCC testsuite to run on the Foundation model.
* Boehm GC AArch64 support:
- Submitted gc integration patch in GCC upstream for review.
- libatomic_ops AArch64 support branch re-tested and merged in mainline.
== Next ==
* AArch64 libunwind support.
== Progress ==
- Closed the blue print for gc-sections implementation since the patch
got upstreamed.
- Opened new blue print for adding more test coverage to gc-sections tests.
- Submitted a patch to enable missed out gc-sections test cases from
ld-elf group.
- Wrote gc-sections test cases for few GOT related relocs.
== Plan ==
- Understand equivalences created during CFG traversal for jump threading.
- Look at GCC code for a simple test case where jump threading is missed out.
- Continue writing gc-sections test cases for remaining relocs.
== Progress ==
- Monday was a public holiday
- Studied benchmarks and analysed the rtl/asm for redundant sign extensions
- Came up with simple test cases based on this (have 6 test cases now)
- Looked at gcc tree documentations and helper macros; tried it by
adding more debug dumps for types at tree level
== Plan ==
- Start with the algorithm for sign extension elimination
- Skipping manual changes at source level/asm level to see the
performance improvement for now.
Short week...
== Progress ==
* Catch up on internal tasks / email that piled up during holidays + Connect
* Resumed work on disable-peeling:
- local benchmarking on snowball
- restarting benchmarks via cbuild for an additional check
== Next ==
* Check benchmark results on disable-peeling
* Have a look at how to dejagnu-ize my Neon intrinsic tests
* Check results of libsanitizer branch
* Check results of 'revert-coalesce' branch
* Check bench results of '4.7-backport-vect-cost-model'
* Check bench results of '4.7-turnoff-64bits-ops'
* Investigate why cbuild did not generate all the comparisons I
expected (*-diff.txt files)
* Check whether 2013.03 release process exposed the same problems I
observed with 2013.02.
Progress (in a 1 day week...):
* qemu maintenance:
** released qemu-linaro 2013.03
** arm-devs pullreq
* VIRT-4 [Guest migration support for KVM]
** audited vexpress code for migration issues: there are a few
devices needing minor cleanup, and one (pflash_cfi01) which
has no migration support at all and needs it writing
* KVM other:
** reviewed virtio-blk refactoring patchset
-- PMM
== Progress ==
* Recuperating from Connect, catching up on email
* Attended David's and Maddog's presentation on Monday
* Investigating Arndale bug (seems to work with new kernel)
- Bootstrapping LLVM works, GCC doesn't
* Reviewing patches upstream (Mans', Tim's, others)
* Fixed three bugs on test-suite that depended on RNGs
- Only two more tests broken only in ARM
- Five others broken on both (but only visible on our bot)
- Nine EH tests that need disabling, for now
== Plan ==
* Tackle the two last ARM specific bugs
* If time allows, clear the other 5
* Try to disable any EH-specific test on ARM
* Start talks about getting an internal binary distribution process going
This is to let you know that the migration of lists.linaro.org has been
successfully completed.
As per the email I sent on Wednesday, it may take some time for the new
address of the server to be seen by your computer. You can check this by
trying to connect to the web site:
http://lists.linaro.org/
If you are able to connect and you do not get an error, this means you are
connecting to the new server and you can send email to the lists.
If you experience any problems after the weekend and you find that you
still cannot connect to the server, please reply to this email to let us
know.
Regards
Philip
IT Services Manager
Linaro
The Linaro Toolchain Working Group is pleased to announce the 2013.03
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2013.03 is the twelth release in the 4.7 series. Based
off the latest GCC 4.7.2+svn195745 release, it includes ARM-focused
performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.2+svn196272
* Includes arm/aarch64-4.7-branch up to svn revision 196225
* A fix for LP #1135633: [linaro regression] alsa-tools FTBFS with error
"unable to find a register to spill in class ‘AREG’"
Linaro GCC 4.6 2013.02 is the 25th release in the 4.6 series. Based
off the latest GCC 4.6.3+svn196247 release, this is the twelth
release after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn196247
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2013.03https://launchpad.net/gcc-linaro/+milestone/4.6-2013.03
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release pages:
https://launchpad.net/gcc-linaro/4.7/4.7-2013.03https://launchpad.net/gcc-linaro/4.6/4.6-2013.03
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro QEMU 2013.03.
Linaro QEMU 2013.03 is the latest release of qemu-linaro. Based off
upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
This release has been updated to be based on upstream's recent 1.4.0
release. It also includes ARM KVM support patches which are in sync
with the ABI as committed to the upstream Linux kernel for 3.9.
This feature is still under development but will no longer be subject
to kernel-vs-userspace ABI breaks.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2013.03
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
-- PMM
Hello
You are receiving this email because you are subscribed to one or more
mailing lists provided by the lists.linaro.org server.
IT Services are announcing planned maintenance for this server scheduled
for *Friday 15th March 2013, starting at 2pm GMT*. The purpose of the work
is to move the service to another server. There will be some disruption
during this maintenance.
In order to ensure that you do not accidentally try to use the service
while it is being moved, the current server will be shut down at 2pm.
A further email will be sent on Friday afternoon to confirm that the
migration of the service is completed. However, due to the way servers are
found, it may take a while before your computer is able to connect to the
relocated service.
After the old server has been shut down, email sent to any of the lists
will be queued, but it is possible that the sending server will still
trying to deliver the email to the old server rather than the new one when
it is started.
It is therefore *strongly* recommended that you do not send any email to an
@lists.linaro.org email address until you can connect to the new service,
which you will be able to test by trying to use a web browser to connect to
http://lists.linaro.org after you receive the email confirming that the
migration has been completed. Since the old service will be shut down, if
you are able to connect, you can be sure you have connected to the new
service.
If by Monday you are still unable to connect to the service or you are not
able to send email to an @lists.linaro.org email address, please send an
email to its(a)linaro.org.
Thank you.
Regards
Philip
IT Services Manager
Linaro
== This Week ===
* Couldnt help my luck and wasnt able to reach Hong Kong due to delay in
visa processing by Hong Kong immigration department.
* Remotely attended live streams of Linaro Connect Asia
* Tried to reproduce all open bugs under linaro-gdb project on launchpad
and created a review sheet.
* Created a comparison sheet to figure out why certain gdb tests are
failing or not being run in different configurations.
== Next week ==
* Try to enable some native only tests and see if the functionality can be
tested for remote configurations as well.
* Set out some priority on blue prints and bugs under linaro-gdb project
and start with some stuff with higher priority.
* Caught some flu over the weekend and still a bit down with fever n
headache.
Progress:
* Linaro Connect Asia (Hong Kong)
* Lots of discussions with virtualization team (first time we've
all been able to meet up!), making sure we all understand our TODO
list, priorities, etc, and getting these details written up in JIRA
* Presentation of KVM current status and discussion of next steps;
we tried to keep the focus on the discussion/audience input part
and I thought it was pretty good
* Several linked conversations on UEFI and how it boots hypervisors
(including KVM); came to a conclusion everybody was happy with
(UEFI mostly runs in SVC mode but provides mechanisms so UEFI
bootloader code can start the kernel in Hyp mode as it requires);
Grant Likely will be moving this forward
* KVM/ARM support patchset for QEMU was accepted into upstream this week!
* looked at fixing QEMU's totally broken model of the versatile PCI
controller
-- PMM
== This Week ===
* Compiled GDB graphical report and test-case statistics out of the results
generated by running gdb-test suite in different configurations.
* Worked on release testing of QEMU. All configurations mentioned in
release template have been tested alongwith an extra configuration of 13.01
ubuntu on vexpress.
* Kept running around for my Hong Kong visa which is still not with me.
== Next week ==
* Try to make it to The Connect in Hong Kong or at least attend remotely.
* Participate in various activities at The Connect.
Progress:
* qemu-linaro: rolled tarball, sent it off for testing
* investigated and reviewed fixes for upstream regressions in
ADC/SBC instruction implementation
* sent updated versions of various patchsets
* fixed review comments on QEMU KVM support patchset, resent
* reviewed a pile of ARM patches from other people and sent arm-devs
pullreq
-- PMM
Hi,
I got the crosstool-ng from the 2013.02 release and wanted to build the linaro-aarch64-linux-gnu target locally. During the build, I'm encountering errors. I didn't do any menuconfig for the above target before starting the build.
I'm seeing the following errors with the first during the ppl build ...
[INFO ] Installing PPL
[EXTRA] Configuring PPL
[ERROR] configure: error: Cannot find GMP version 4.1.3 or higher.
[EXTRA] Saving state to restart at step 'cloog'...
...
(from build-ppl/config.log ....
...
configure:11257: result: no
configure:11392: error: Cannot find GMP version 4.1.3 or higher.
GMP is the GNU Multi-Precision library:
see http://www.swox.com/gmp/ for more information.
....)
...
[INFO ] Installing CLooG/ppl
[EXTRA] Configuring CLooG/ppl
[ERROR] checking for version 0.10 (or later revision) of PPL... configure: error: Can't find correct version of PPL.
[EXTRA] Saving state to restart at step 'mpc'...
...
(from build-cloog-ppl/cobnfig.log ...
...
configure:11237: error: Can't find correct version of PPL.
...)
If I'm building a known target with the released version, why am I seeing these errors?
Thanks,
Kalai
The Linaro Toolchain and Platform Working Groups are pleased to announce
the 2013.02 release of the Linaro Toolchain Binaries, a pre-built version
of Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2013.02-01
* Linaro GDB 7.5 2012.12
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link your
programs against.
Interesting changes include:
* binutils is upgraded to 2.23.1
* eglibc is upgraded to 2.17
* kernel header is upgraded to 3.7
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian 6.0.2,
Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation 5.7 and
later, and should run on any Linux Standard Base 3.0 compatible
distribution. Please see the README about running on x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2013.02
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Hi,
in the example below I want to explicitly generate a "store exclusive
pair" instruction with an asm statement:
typedef struct {
long unsigned int v1;
long unsigned int v2;
} mtype;
int main () {
mtype val[2] ;
val[0].v1 = 1234;
val[0].v2 = 5678;
int status;
do {
__asm__ __volatile__(
" stxp %0, %2, %3, %1"
: "=&r" (status), "=Q" (val[1])
: "r" (val[0].v1), "r" (val[0].v2)
);
} while (status != 0);
if (val[1].v1 == 1234 && val[1].v2 == 5678)
return 0;
return 1;
}
The generated assembly is:
.L7:
ldr x0, [sp]
ldr x1, [sp,8]
.L3:
add x3, sp, 16
stxp x2, x0, x1, [x3]
cbnz w2, .L7
and the issue is that the assembler is not happy of the register x2
used to store the exclusive access status, it should be w2, but
looking at constraint.md it seems that there is no constraint to say
that we want the 32bit version of the register. Any idea ?
Many thanks
Yvan
== This Week ===
* Wrote a python script that parses GDB Testsuite log file and filters out
all results and tests which were not passed.
* Wrote another python script that compares filtered output of GDB log
taken out from different configurations. This script compares results of
various tests which didn't pass in current configuration with their
corresponding results in GDB log of other configurations.
* Generated various comparison pie charts and bar charts to show the
testing results of GDB in different configurations.
* Updated Wiki pages with help for people getting started with remote
Pandaboards.
* Updated wiki pages with help for people getting started with GDB
development and testing remotely.
* Ran after my visa agent for quick processing of my Hong Kong visa.
== Next week ==
* Manual analysis of GDB test results for any possible issues on ARM
platform.
* Finish up the comparison document of all GDB test suite log files.
* Follow up on hong kong visa application.
* Flying to Karchi this Friday to catch flight to Hong Kong permitting visa.
== Progress ==
* Implementing GC sections support in binutils.
Tested the patch for enabling gc section.
"make ld-check" now passes after setting compiler in the PATH.
Used the patched binutils source and built GCC for aarch64-none-elf.
Ran gcc tests on V8 foundation model.
Submitted the patch to FSF binutils for a review.
* Analysis on jump threading in GCC.
Not much progress this week.
Identified few areas where we can improve.
- In Normal jump threading see if we can thread across loop latch and
loop header.
- Lowering switch cases in simple and see if threading benefits.
- Improve threading in VRP.
Misc
------
* Was on leave Friday 22nd.
* Attend tool chain weekly meet, and stand up call
* Had a look at one x86_64 related patch.
== Next week ==
* Update review comments if any and upstream gc sections support patch .
* Continue analysis on jump threading in GCC.
Hi,
I tried to generate a binary containing only ARM 32-bit ISA.
The toolchain I used is
gcc-linaro-arm-linux-gnueabihf-4.7-2013.01-20130125_linux.
The compilation options are -O3 -mcpu=Cortex-A15 -marm -static.
I could get 32-bit ARM ISA for my own C code, but not the C lib functions,
such as
strcpy. Is there a way to invoke 32-bit ARM ISA C library code?
Thanks,
Tien-Pao
== Progress ==
- Fix EPILOGUE_USES regression in CoreMark
- CBUILD tasks had to be respwaned. Zhenqiang sent me links and
instructions. Build tasks are still in the queue.
- Tried with some simple test cases mostly to understand dataflow
and register allocator modules in gcc.
- Remove Unnecessary Zero/Sign Extensions
- Looked in detail a patch
http://old.nabble.com/new-sign-zero-extension-elimination-pass-to29991676.h…
which does extension elimination with sudo registers. This patch is
not part of gcc mainstream. There were some concerns of runtime, using
existing passes to handle this and not catching all the extension in
the discussion.
- Looked at gcc pass ree which does elimination after register
allocation. As it is, it does not eliminate some of the cases I tried.
Looking into it.
== Plan for next week ==
- Work on Remove Unnecessary Zero/Sign Extensions and get ready to
discuses this in connect. It might not be possible to run this with
CBUILD therefore going to try with simple test cases already discussed
and considered by others.
== Progress ==
* February 4.7 release:
- Released a respin of 4.7 2013.02, which fixes an issue with
multiarch on x32 and kfreebsd builds.
* Boehm GC AArch64 support:
- Fixed 128-bit atomic load/store and 'compare and swap' functions
- Testsuite is now OK
* AArch64 porting meeting:
- No new requirements
* Infrastructure:
- Wifi now usable on my laptop
== Next ==
* vacation
* Connect
== Progress ==
* smin-umin: waiting for benchmark results with 'coalesce-vars' patch
reverted on trunk.
* libsanitizer: its backtrace printing facility relies on unwinding
info not present by default in binaries. Adding -funwind-tables
improves the results in GCC testsuite.
There is still an interaction between runtest/qemu and isatty() which
confuses dejagnu. Forcing libsanitizer's internal_isatty to return 0
fixes it. TBC.
* vectorizer cost model: backport in 4.7 required to remove a part,
for lack of new vectorizer infrastructure (arm_add_stmt_cost).
* 'turnoff 64bits ops in Neon': waiting for benchmark results after
backporting on 4.7.
* internal tasks
== Next ==
* holidays next week
* Connect week after
Progress:
* updated various Virtualization category cards in cards.linaro.org
with my comments and clarifications
* rebased qemu-linaro on upstream 1.4.0
* upstream code review: pl330 and others
* prompted by LP:1129571 into another look at the linux-user threading
issues. I dusted off an ancient patch I'd written to address one
part of these, rebased it and rewrote it to work properly.
* KVM/ARM kernel patches are now upstream, so we can submit the QEMU
patches; started on a final rebase, polish and test
Absences:
* NB: I now work a 4 day week, excluding Wednesdays
* 4-8 March: Linaro Connect Asia (Hong Kong)
-- PMM
Hi folks,
Attached is the Linpack benchmark, which I ran GCC and Clang with and
without vectorization (though most of the loops are not vectorized).
Reading the output of LLVM loop vectorizer, it also doesn't do much, but
the net gain is due to the basic-block vectorizer. Does GCC has a similar
concept?
The results are also attached.
cheers,
--renato
The Linaro Toolchain Working Group announce the 2013.02-01 Linaro GCC 4.7
release. This is a respin of the 2013.02 release because of an issue with
multiarch for x32 and kfreebsd builds in the previous one.
Please find the original 2013.02 announcement below.
The Linaro Toolchain Working Group is pleased to announce the 2013.02
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2013.02 is the eleventh release in the 4.7 series. Based
off the latest GCC 4.7.2+svn195745 release, it includes ARM-focused
performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.2+svn195745
* Includes arm/aarch64-4.7-branch up to svn revision 195716
* Support for Cortex-A7 backported from trunk
Linaro GCC 4.6 2013.02 is the 24th release in the 4.6 series. Based
off the latest GCC 4.6.3+svn195744 release, this is the eleventh release
after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn195744
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2013.02https://launchpad.net/gcc-linaro/+milestone/4.6-2013.02
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release pages:
https://launchpad.net/gcc-linaro/4.7/4.7-2013.02https://launchpad.net/gcc-linaro/4.6/4.6-2013.02
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
On 6 November 2012 02:48, Rob Herring <robherring2(a)gmail.com> wrote:
>
> On 11/05/2012 05:13 AM, Russell King - ARM Linux wrote:
> > On Mon, Nov 05, 2012 at 10:48:50AM +0000, Dave Martin wrote:
> >> On Thu, Oct 25, 2012 at 05:08:16PM +0200, Johannes Stezenbach wrote:
> >>> On Thu, Oct 25, 2012 at 09:25:06AM -0500, Rob Herring wrote:
> >>>> On 10/25/2012 09:16 AM, Johannes Stezenbach wrote:
> >>>>> On Thu, Oct 25, 2012 at 07:41:45AM -0500, Rob Herring wrote:
> >>>>>> On 10/25/2012 04:34 AM, Johannes Stezenbach wrote:
> >>>>>>> On Thu, Oct 11, 2012 at 07:43:22AM -0500, Rob Herring wrote:
> >>>>>>>
> >>>>>>>> While v6 can support unaligned accesses, it is optional and current
> >>>>>>>> compilers won't emit unaligned accesses. So we don't clear the A bit for
> >>>>>>>> v6.
> >>>>>>>
> >>>>>>> not true according to the gcc changes page
> >>>>>>
> >>>>>> What are you going to believe: documentation or what the compiler
> >>>>>> emitted? At least for ubuntu/linaro 4.6.3 which has the unaligned access
> >>>>>> support backported and 4.7.2, unaligned accesses are emitted for v7
> >>>>>> only. I guess default here means it is the default unless you change the
> >>>>>> default in your build of gcc.
> >>>>>
> >>>>> Since ARMv6 can handle unaligned access in the same way as ARMv7
> >>>>> it seems a clear bug in gcc which might hopefully get fixed.
> >>>>> Thus in this case I think it is reasonable to follow the
> >>>>> gcc documentation, otherwise the code would break for ARMv6
> >>>>> when gcc gets fixed.
> >>>>
> >>>> But the compiler can't assume the state of the U bit. I think it is
> >>>> still legal on v6 to not support unaligned accesses, but on v7 it is
> >>>> required. All the standard v6 ARM cores support it, but I'm not sure
> >>>> about custom cores or if there are SOCs with buses that don't support
> >>>> unaligned accesses properly.
> >>>
> >>> Well, I read the "...since Linux version 2.6.28" comment
> >>> in the gcc changes page in the way that they assume the
> >>> U-bit is set. (Although I'm not sure it really is???)
> >>
> >> Actually, the kernel checks the arch version and the U bit on boot,
> >> and chooses the appropriate setting for the A bit depending on the
> >> result. (See arch/arm/mm/alignment.c:alignment_init().)
> >
> > That is in the kernel itself, _after_ the decompressor has run. It is
> > not relevant to any discussion about the decompressor.
> >
> >> Currently, we depend on the CPU reset behaviour or firmware/
> >> bootloader to set the U bit for v6, but the behaviour should be
> >> correct either way, though unaligned accesses will obviously
> >> perform (much) better with U=1.
> >
> > Will someone _PLEASE_ address my initial comments against this patch
> > in light of the fact that it's now been proven _NOT_ to be just a V7
> > issue, rather than everyone seemingly buring their heads in the sand
> > over this.
>
> I tried adding -munaligned-accesses on a v6 build and still get byte
> accesses rather than unaligned word accesses. So this does seem to be a
> v7 only issue based on what gcc will currently produce. Copying Michael
> Hope who can hopefully provide some insight on why v6 unaligned accesses
> are not enabled.
This looks like a bug. Unaligned access is enabled for armv6 but
seems to only take effect for cores with Thumb-2. Here's a test case
both with unaligned field access and unaligned block copy:
struct foo
{
char a;
int b;
struct
{
int x[3];
} c;
} __attribute__((packed));
int get_field(struct foo *p)
{
return p->b;
}
int copy_block(struct foo *p, struct foo *q)
{
p->c = q->c;
}
With -march=armv7-a you get the correct:
bar:
ldr r0, [r0, #1] @ unaligned @ 11 unaligned_loadsi/2 [length = 4]
bx lr @ 21 *arm_return [length = 12]
baz:
str r4, [sp, #-4]! @ 25 *push_multi [length = 4]
mov r2, r0 @ 2 *arm_movsi_vfp/1 [length = 4]
ldr r4, [r1, #5]! @ unaligned @ 9 unaligned_loadsi/2 [length = 4]
ldr ip, [r1, #4] @ unaligned @ 10 unaligned_loadsi/2 [length = 4]
ldr r1, [r1, #8] @ unaligned @ 11 unaligned_loadsi/2 [length = 4]
str r4, [r2, #5] @ unaligned @ 12 unaligned_storesi/2 [length = 4]
str ip, [r2, #9] @ unaligned @ 13 unaligned_storesi/2 [length = 4]
str r1, [r2, #13] @ unaligned @ 14 unaligned_storesi/2 [length = 4]
ldmfd sp!, {r4}
bx lr
With -march=armv6 you get a byte-by-byte field access and a correct
unaligned block copy:
bar:
ldrb r1, [r0, #2] @ zero_extendqisi2
ldrb r3, [r0, #1] @ zero_extendqisi2
ldrb r2, [r0, #3] @ zero_extendqisi2
ldrb r0, [r0, #4] @ zero_extendqisi2
orr r3, r3, r1, asl #8
orr r3, r3, r2, asl #16
orr r0, r3, r0, asl #24
bx lr
baz:
str r4, [sp, #-4]!
mov r2, r0
ldr r4, [r1, #5]! @ unaligned
ldr ip, [r1, #4] @ unaligned
ldr r1, [r1, #8] @ unaligned
str r4, [r2, #5] @ unaligned
str ip, [r2, #9] @ unaligned
str r1, [r2, #13] @ unaligned
ldmfd sp!, {r4}
bx lr
readelf -A shows that the compiler planned to use unaligned access in
both. My suspicion is that GCC is using the extv pattern to extract
the field from memory, and that pattern is only enabled for Thumb-2
capable cores.
I've logged PR55218. We'll discuss it at our next meeting.
-- Michael
== Progress ==
* smin-umin: spawned build jobs for gcc-trunk with 'coalesce-vars'
patch reverted (from A.Oliva), so that I can then run benchmarks to
compare its effect with the one observed on gcc-4.7.
* libasan: thanks to Peter, I am able to run sample programs under
qemu. Ran GCC testsuite, observed some failures, to be investigated.
* vectorizer cost model: committed upstream in 4.8.
* Released gcc-linaro-4.6-2013.02 and gcc-linaro-4.7-2013.02.
* backported 'turnoff 64 bits ops in Neon' from upstream to
gcc-linaro-4.7. Waiting for builds to complete to launch benchmark
jobs.
* internal tasks
== Next ==
* smin-umin: look at benchmarks results if available
* libasan: analyse testsuite results
* 64bits ops in Neon; look at benchmarks results if available
* get more codec samples
Christophe.
== Progress ==
* February merge 4.6 and 4.7
- Another issue raised by Matthias, fix merged.
- The merge request exposed a new failure on i686 (ld seg. fault)
which looks like the ones we had on i686 before the release,
re-spawned the job to see if we can reproduce.
* Boehm GC AArch64 support:
- Fixed some defect, identified some cases not implementable by
atomic builtins, worked on inline asm versions.
- re-installed working environment to be able to test the gcc
integration (thanks to Matt)
* Aarch64 porting meeting:
- No new requirements.
== Next ==
* Review roster.
* Boehm GC AArch64 support:
- fix libatomic_ops
- validate GCC's Boehm gc integration
* libunwind aarch64 support:
- continue.
== This Week ===
* Got the remote Pandaboard RootFS updates, Thanks to Dave again.
* Got the SSH tunnels going for remote GDB test suite executions, thougt a
single remote run takes eternity to complete.
* Analysis of GDB test suite log files separated the failures and other
test cases which were not passed as for the analysis.
* Preliminary analysis done on GDB logs for remote configuration on ARM in
comparison with native configuration.
== Next week ==
* Try to complete log file analysis and post results.
* Try to run GDB test suite using QEMU.
* Follow up on hong kong visa application
--
*** Sorry about spamming I got the subject wrong in the first email.
== This Week ===
* Tried running GDB test suite with QEMU linux user-mode with not much
success
* Configured Pandaboard and ran GDB test suite in native and
native-gdbserver configurations.
* More of office setup and purchase of some bits and pieces
* Gateway set up and Pandaboard access finally worked after some help from
Dave and Matt.
* Finally purchased Ticket for the Connect and also filled visa application
* Attended Weekly toolchain call
* Still suffering from a bad run of cough n flu, done with antibiotics now.
* Public Holiday on 5th Feburary
== Next week ==
* Continue with Analysis of GDB status on ARM in different configurations
possible.
* SSH tunnels and port forwarding setup to gateway and lab for smooth
access.
* Follow up on hong kong visa application
== Progress ==
* Implementing GC sections support in binutils
Wrote a patch to update some AARCH64 GOT and PLT symbol ref counts
while sweeping sections.
During "make ld-check" some tests are not running. Checking the issue.
Discussed with Matt and decided to use default gc_mark hook. Most
ports care BFD_RELOC_VTABLE_INHERIT
and BFD_RELOC_VTABLE_ENTRY relocs during gc section marking. Now
these relocs are not supported in AARCH64.
* Analysis on jump threading in GCC
Switch cases are not lowered in GCC till RTL expand stage.
Looking at a patch on lowering switch to GIMPLE and see jump
threading behaves.
Misc
------
* Attend tool chain weekly meet, and stand up call
* Had a look at one x86_64 related GCC build error.
== Next week ==
* Continue Implementing GC sections support in binutils and test the patch.
* Continue analysis on jump threading in GCC. Planning to look at Tree
VRP as per Andrew pinski suggestion.
Hello,
I am currently trying to determine how much I can optimize OpenCV using the
ARM's VFP and the Linaro nano image. I have downloaded the
arm-linux-gnueabihf-gcc & arm-linux-gnueabihf-g++ compilers, successfully
cross-compiled OpenCV using those compilers (with -O3 -mfloat-abi=hard
-ftree-vectorize -funroll-loops), and compiled an example OpenCV program
with the arm-linux-gnueabihf-g++ compiler (with the same flags). However,
when I try and run my executable within Linaro (running on a gumstix overo)
I get "/lib/arm-linux-gnueabihf/libm.so.6: version `GLIBC_2.15' not found
(required by /usr/lib/libopencv_core.so.2.2).
I assume that this is because on my build machine (x86 Ubuntu 10.04) where
I cross compiled the OpenCV libraries I am using libc-2.15, and on the
target (gumstix) the loader can't find libc-2.15. However, within the
gcc-linaro-arm-linux-gnueabihf-4.7 tar ball I downloaded today, there is a
libc-2.15.so file in there that I copied into /lib/ on the gumstix. Still
no success though when I try running my executable.
Any recommendations on things to try? I am hesitant to just put a newer
version of glibc in Linaro as it seems like that could screw a lot of
things up. Should I attempt to re-build OpenCV somehow with an older
version of glibc (namely libc-2.13)?
Also, please let me know if this is the wrong forum for this question and
where I should post it instead.
Thanks,
Derek
== Progress ==
-Spawned CBUILD tasks with and without the patch proposed by Chung-Lin
Tang to test current status of "Fix EPILOGUE_USES regression in
CoreMark". Job is still in the queue.
-Read references listed in gcc/ira.c to understand gcc IRA and went
through the source code.
-Experimented with simple test cases to analyse IRA debug output.
== Plan for next week ==
- Analyse CoreMark results if ready and work on improvements.
- Start with research for Removing unnecessary zero/sign extends when
not working on "Fix EPILOGUE_USES regression in CoreMark.
== Progress ==
* Vectorizer
- Progressing on the global structure alias analysis (discussions, drafts,
failed attempts)
- Interesting Linpack results for vectorizer, investigating performance
- http://www.systemcall.org/blog/2013/02/llvm-vectorizer/
- http://llvm.org/bugs/show_bug.cgi?id=15247
* Buildbots
- Took Chromebook out, since Pandas are fast enough
- Creating LNT test-suite buildbot
- http://llvm.org/viewvc/llvm-project?view=revision&revision=175081
- http://lab.llvm.org:8011/builders/clang-native-arm-lnt
- Still a few rounds until it works properly
* Distributed Builds
- Distributed compilation works somewhat on Pandas
-
http://www.systemcall.org/blog/2013/02/distributed-compilation-on-a-pandabo…
- It's better, cheaper and easier to use Chromebooks / Arndales, though...
* LAVA
- Tracking LLVM git repo in git.linaro.org
- Trying to build from that repo, LAVA doesn't like it... :/
* EuroLLVM
- We're not sponsoring it any more, will still help organize
== Plan ==
* Continue Global Alias Analysis, I seem to be getting close to something
worth sending (and learning a lot in the process)
* Make sure LNT buildbot is up and running with vectorizer (O3)
* Check with Dave Piggot why git.linaro doesn't work with LAVA
* Inspect why some (loop+bb) vectorized results are poor on ARM
Progress:
* rebased qemu-linaro and sorted out with Serge what he requires
in the way of patches for Ubuntu's upcoming code freeze. I plan
to set up and test the 2013.03 release a week or two early both
so that there is a patchset ready for the Ubuntu freeze and also
to avoid clashing with Connect week.
* some patches to clean up QEMU's logging functions so they can
be used more widely in place of ad-hoc printf
* cleanup patchset to get rid of sysbus_add_memory() function
* LP:1079080 -- fixed serious bug in QEMU's Thumb-mode srs insn
* upstream discussion about what to do about QEMU's disassembler
license-clash issues:
http://lists.gnu.org/archive/html/qemu-devel/2013-02/msg02122.html
* NB: I now work a 4 day week, excluding Wednesdays
-- PMM
I downloaded the aarch64 binaries to a ubuntu machine:
wink@ssi-primary:~$ uname -a
Linux ssi-primary 3.5.0-21-generic #32-Ubuntu SMP Tue Dec 11 18:51:59 UTC
2012 x86_64 x86_64 x86_64 GNU/Linux
And when I try to run gcc-4.7.3:
wink@ssi-primary:~$ ls -al
~/aarch64-toolchain/gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/bin/aarch64-linux-gnu-gcc-4.7.3
-rwxr-xr-x 1 wink wink 553068 Oct 18 14:21
/home/wink/aarch64-toolchain/gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/bin/aarch64-linux-gnu-gcc-4.7.3
I get a file not found:
wink@ssi-primary:~$ strace
/home/wink/aarch64-toolchain/gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/bin/aarch64-linux-gnu-gcc-4.7.3
-v
execve("/home/wink/aarch64-toolchain/gcc-linaro-aarch64-linux-gnu-4.7+bzr115029-20121015+bzr2506_linux/bin/aarch64-linux-gnu-gcc-4.7.3",
["/home/wink/aarch64-toolchain/gcc"..., "-v"], [/* 19 vars */]) = -1
ENOENT (No such file or directory)
dup(2) = 3
fcntl(3, F_GETFL) = 0x8002 (flags
O_RDWR|O_LARGEFILE)
fstat(3, {st_mode=S_IFCHR|0620, st_rdev=makedev(136, 0), ...}) = 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0)
= 0x7fa688be5000
lseek(3, 0, SEEK_CUR) = -1 ESPIPE (Illegal seek)
write(3, "strace: exec: No such file or di"..., 40strace: exec: No such
file or directory
) = 40
close(3) = 0
munmap(0x7fa688be5000, 4096) = 0
exit_group(1) = ?
I must have done something real stupid, any help appreciated.
-- Wink
== Progress ==
* Very short working week.
* Discussions about next steps in Lava integration.
* Followed up on Arndale/GCC build issues.
== Next week ==
* Review pending Backports
* Investigate bootstrap ICE PR56184 further
== Future ==
* Run HOT/COLD partitioning benchmarks
* Analyse ARM results
* On x86_64 to see what the actual benefit we could get
* fix-gcc-multiarch-testing
* Come up with strawman proposal for updating testsuite to handle
testing with varying command-line options.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== Progress ==
* 64-bits ops in Neon: upstream accepted the patch for gcc-4.9-stage1
* smin-umin: several benchmarks runs necessary to confirm that the
generic patch I suspected actually caused the regression. However, it
also brings improvements in other benches (office-type).
* looked at libasan: very little configuration seems necessary, but
running a sample program under qemu leads to asan runtime complains.
* internal tasks
== Next ==
* smin-umin: run benchmarks on trunk to confirm the regression is also present.
* vectorizer cost model: handle Richard's feedback.
* get more codecs sample codes.
* libasan: understand error messages
Christophe.
== Progress ==
* February merge 4.6 and 4.7
- backport a patch from upstream to resolve conflicts
- this backport introduced some merge issues
- fix pushed and merge request ongoing
* Boehm GC AArch64 support:
- libatomic_ops maintainer rework the patch to make the usage of
gcc atomic builtins available on the other targets
- test exhibit some failures
* libunwind aarch64 support
- bug status moved to critical
- configuration and machine description done
- implementation ongoing
* Aarch64 porting meeting:
- Cancelled this week
== Next ==
* February merge 4.6 and 4.7
- log new testsuite failures in launchpad
* Boehm GC AArch64 support:
- fix libatomic_ops
- validate GCC's Boehm gc integration
* libunwind aarch64 support
- conitnue.
== Progress ==
* Implementing GC sections support in bintuils
Looking at aarch64 relocations to consider while sweeping.
* Cbuild experiments to test gcc svn aarch64 4.7 branch.
Connection problems to the cbuild machines are solved now.
Thanks to Matt. Spawned the build.
Misc
------
* Attend tool chain weekly meet, and stand up call
* Had a look at one x86_64 related patch that gone into GCC trunk.
== Next week ==
* Continue Implementing GC sections support in binutils.
* Start analysis on jump threading in GCC.
== Progress ==
-Attended 1:1 and other team meetings
-Read linaro wiki and on boarding instructions
-Backported Cortex A7 pipeline description to Linaro 4.7 gcc from fsf
trunk and got it reviewed
== Plan for next week ==
- Look into CoreMark regresses in Thumb-2 mode when using the LR regnum.
- Start with research for Removing unnecessary zero/sign extends
Progress:
* Linaro's KVM/QEMU mini-summit, aimed at summarising current status,
identifying what needs to be done and what Linaro should be doing:
https://wiki.linaro.org/LEG/Engineering/Virtualization/201302MiniSummit
* implemented support for variable-length qdev array properties in QEMU
and sent out patch for this plus vexpress fixes which use it
* investigated how to run the Linux Test Project syscall tests under
QEMU to improve the quality of our linux-user mode testing
(wrote up a howto for the QEMU wiki: http://wiki.qemu.org/Testing/LTP
many thanks to fabo for whipping up a Jenkins job to run these nightly)
* couple of trivial linux-user patches as example low-hanging fruit
revealed by the LTP test results
-- PMM