[Short week: 3 days]
* looked at (but failed to reproduce) a hang in QEMU reported
by Christoffer when shutting down a KVM ARM guest using TUN/TAP
networking
* investigated LP:1084148 (segfault in qemu usermode) sufficiently
to diagnose it as probably another of qemu's "can't handle
multithreaded guest programs" bugs
* fixed some problems with QEMU's secondary CPU boot code which
were masked by errors in QEMU's GIC model but revealed by
real hardware (ie KVM); fixed the GIC model bugs as well
* investigated LP:955379 (cmake hangs under qemu-arm-static).
Tracked down to a race condition involving signal delivery,
the fix to which would require the significant redesign I
sketched out here a year or so ago:
http://lists.gnu.org/archive/html/qemu-devel/2011-12/msg00384.html
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
== Blueprints ==
Initial Current Actual
initial-aarch64-backport 31 Oct 2012 7 Dec 2012*
aarch64-baremetal-testing 31 Oct 2012 7 Dec 2012*
fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012
backport-fma-intrinsic 31 Dec 2012 31 Dec 2012
fused-multiply-add-support 31 Dec 2012 31 Dec 2012
gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012
== Progress ==
* Admin
* Interviewing
* Preparation for taking over from Michael
* Investigate patches for literal pool layout bug
* Applied
* PINGed triplet backport patches upstream
* Other bug issues
* Including an issue running SPEC2K on x86 with recent trunk
* And a 4.6 gcc-linaro only issue
== Next Week ==
* Start leading Toolchain team
* Run HOT/COLD partitioning benchmarks
* Analyse ARM results
* On x86_64 to see what the actual benefit we could get
* initial-aarch64-backport & aarch64-baremetal-testing
* Finish documentation
* gcc-investigate-lra-for-arm
* Analyse benchmarks
* fix-gcc-multiarch-testing
* Come up with strawman proposal for updating testsuite to handle
testing with varying command-line options.
== Future ==
* backport-fma-intrinsic & fused-multiply-add-support
* Backport patches once fix-gcc-multiarch-testing has been done.
== Planned Leave ==
* Monday 24 December - Monday 31 December
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi,
I think I have identified some issues with the atomic builtins, but I want
your advises.
For instance :
A: __atomic_store_n (addr, val, __ATOMIC_SEQ_CST);
gives the armv7 code:
DMB sy
STR r1, [r0]
DMB sy
but if I have well understood, the DMBs instructions only provide the
property that the
code is sequentially consistent, but not the atomicity for which we have to
use the
LDREX/STREX instructions. Thus I think that the code should be :
DMB sy
1: LDREX r2, [r0]
STREX r1, r2, [r0]
TEQ r1, #0
BNE 1b
B: __atomic_load_n (addr, __ATOMIC_ACQUIRE);
gives the armv7 code:
DMB sy
LDR r0, [r0]
but the load-acquire semantique specifies that all loads and stores
appearing in program order
after the load-acquire will be observed after the load-acquire, thus the
DMB should be after the
LDR, no ?
--
Yvan
Hi,
I'm working on the libatomic-ops (part of the Boehm gc) AArch64 support,
I mainly use GCC's __atomic builtins to do this, but in our 4.7 version
they don't use the load acquire / store release instructions now available
in the ARMv8 ISA. These instructions are used in the mainline GCC
(in atomic.md) but not in their exclusive form, I understand that it should
be due to the performance penalty, but I want your feeling on that point
as I don't find the ARMv8 ISA really clear.
If we want to implement an atomic load acquire, is
LDAR x1, [x0]
sufficient, or do we have to write it like that :
L: LDAXR x0, [x3]
STEX x1, x0, [x3]
CBZ x0, L1
Thanks
Yvan
All,
[Editiorial: Michael & I discussed making what we do as a working
group more visible at Connect. One thing we discussed was making our
meeting minutes more visible by emailing actions out after each
meeting. This will be part of the job of the 'minuter' - a job I plan
to spread around as I am useless at it whilst also running a call -
more info on the Wiki:
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings]
The minutes of the performance call held on 27 November 2012 can be found at:
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-11-27
In summary the actions from the meting are:
* mgrettondann split LRA blueprint
* Christophe to update Hot/Cold partitioning bugzilla
* mgrettondann: benchmark on Hold/Cold partitioning
* Michael to log a ticket to improve reporting of benchmarks when the
run complete.
* Ramana to log EEMBC failure with Hot/Cold partitioning into bugzilla.
* Christophe to backport bswap16 builtin, except for the testcase
which fails in one of our configurations (Thumb1 + hard FP ABI)
The next performance call will be on 11 December 2012 and the agenda
can be found at:
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-12-11
Thanks,
Matt
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
The Linaro Toolchain Working Group is pleased to announce the 2012.11
release of the Linaro Toolchain Binaries, a pre-built version of
Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2012.11
* Linaro GDB 7.5 2012.09
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.11
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Summary:
* Investigate shrink-wrap result.
* Prepare for Linaro toolchain binary release, script merge and aarch64 test.
Details:
1. Investigate shrink-wrap result of function Ray_In_Bound. By
default, ARM/MIPS/PPC/X86 toolchain can not shrink-wrap the function.
For ARM, there is copy "r6 = r1" which blocks the optimization. By
hacking the assemble code, I got ~3% performance improvement for
453.povray benchmark.
2. Setup AARCH64 simulation environment by following
http://www.linaro.org/engineering/armv8.
3. Write scripts to collect branch cost performance. It will take
weeks to get all the benchmark results.
4. Smoke test Linaro toolchain binaries 2012.11 release.
5. Try export crosstool-ng trunk to a bzr project. bzr fast-import
always fail on Ubuntu 10.04, but it works on 12.04.
6. RM toolchain related work.
Plans:
* Collect performance data for branch cost tuning.
* Linaro binary toolchain 2012.11 release.
* Verify shrink-wrap bugs.
Best regards!
-Zhenqiang
== Progress ==
* Turn off 64-bits bitops in Neon: initial implementation under
benchmarking.
Currently it modifies the handling of: add, sub, and, or, xor, shifts,
not. In some case the generated code is quite larger, so it will careful
benchmarking.
* Started looking at "disable peeling" blue-print. Reading GCC source code
to get more familiar with that area.
* Internal support
== Blueprints ==
Initial Current Actual
initial-aarch64-backport 31 Oct 2012 30 Nov 2012
aarch64-baremetal-testing 31 Oct 2012 30 Nov 2012
fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012
backport-fma-intrinsic 31 Dec 2012 31 Dec 2012
fused-multiply-add-support 31 Dec 2012 31 Dec 2012
gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012
== Progress ==
* Admin
* Interviewing
* Investigate patches for literal pool layout bug
* Took longer than expected as the 'simple' fix is wrong due to GCC not
knowing how large instructions actually are.
* Patch posted upstream
* Post triplet backport patches upstream
* Other bug issues
* Including an issue running SPEC2K on x86 with recent trunk
== Next Week ==
* Run HOT/COLD partitioning benchmarks
* Analyse ARM results
* On x86_64 to see what the actual benefit we could get
* initial-aarch64-backport & aarch64-baremetal-testing
* Finish documentation
* gcc-investigate-lra-for-arm
* Analyse benchmarks
* fix-gcc-multiarch-testing
* Come up with strawman proposal for updating testsuite to handle
testing with varying command-line options.
== Future ==
* backport-fma-intrinsic & fused-multiply-add-support
* Backport patches once fix-gcc-multiarch-testing has been done.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi,
I try ARM, MIPS, PowerPC and X86 on povray benchmark. No one can
shrink-wrap function Ray_In_Bound.
Here is:
bool Ray_In_Bound (RAY *Ray, OBJECT *Bounding_Object)
{
...
for (Bound = Bounding_Object; Bound != NULL; Bound = Bound->Sibling)
{...}
return (true);
}
For ARM O2/O3, "Bound" is allocated to "r6" during ira. So there is copy
r6 = r1 before
testing Bound != NULL
The copy (using r6) blocks the shrink-wrap optimization since r6
should be saved. Need enhance shrink-wrap to handle this case.
Overall, for povray benchmark,
54 functions are shrink-wrapped for ARM;
59 functions are shrink-wrapped for X86;
25 functions are shrink-wrapped for MIPS;
26 functions are shrink-wrapped for PowerPC.
Thanks!
-Zhenqiang
On 15 November 2012 01:58, 남관우 <kw46.nam(a)samsung.com> wrote:
>
> Hi,
>
>
>
> As your guide, i tried to build again.
>
>
>
> without : -mapcs -fno-common -fstack-protector --param==ssp=buffer-size=4
>
>
> and -fPIC instead of -fpic
>
>
>
> But it is failed with same the message. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03)
>
>
>
> Thank you,
>
> Kwanwoo Nam.
>
>
>
> ------- Original Message -------
>
> Sender : 남관우<kw46.nam(a)samsung.com> S4(선임)/선임/SLP개발그룹(무선)/삼성전자
>
> Date : 2012-11-14 21:45 (GMT+09:00)
>
> Title : Re: Re: Re: unexpected reloc type 0x03 error with gcc-4.6.4 (2012.10 version)
>
>
>
> Hi,
>
>
>
> Here is our LDFLAGS.
>
> -Wl,--rpath=/usr/lib -Wl,--as-needed
>
>
>
> And i try to build with your guide.
>
> without : -mapcs -fno-common
> and -fPIC instead of -fpic
>
>
>
> But it is failed with same the message. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03)
Ta. I'm afraid we don't have enough information to solve this.
Could you please send a full build log and we can go from there.
gzipped on a public server is best.
-- Michael
== Blueprints ==
Initial Current Actual
initial-aarch64-backport 31 Oct 2012 30 Nov 2012
aarch64-baremetal-testing 31 Oct 2012 30 Nov 2012
fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012
backport-fma-intrinsic 31 Dec 2012 31 Dec 2012
fused-multiply-add-support 31 Dec 2012 31 Dec 2012
gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012
== Progress ==
* Admin
* Interviewing
* Hand over prep with Michael
* Release Week
* Made 2012.11 releases of gcc-linaro 4.6 and 4.7.
* LEG interations:
* Investigated CILK+ and how much work to port to AArch64.
* HOT/COLD partitioning
* Ran benchmarks on ARM
* LRA
* Ran x86-64 benchmarks
== Next Week ==
* Investigate patches for literal pool layout bug
* Post triplet backport patches upstream
* Run HOT/COLD partitioning benchmarks
* Analyse ARM results
* On x86_64 to see what the actual benefit we could get
* initial-aarch64-backport & aarch64-baremetal-testing
* Finish documentation
* gcc-investigate-lra-for-arm
* Analyse benchmarks
* fix-gcc-multiarch-testing
* Come up with strawman proposal for updating testsuite to handle
testing with varying command-line options.
== Future ==
* backport-fma-intrinsic & fused-multiply-add-support
* Backport patches once fix-gcc-multiarch-testing has been done.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== Progress ==
* Infrastructure:
- Managed to have my laptop re-installed by IT with a native Ubuntu 12.04,
(as a beta tester).
- Re-setup my working environment.
* GCC release process familiarization.
* Boehm GC AArch64 support:
- Resume libatomic-ops work.
* Some internal support
== Next ==
* Continue on the Boehm GC AArch64 support.
== Progress ==
* Started working on "Turn off 64 bits Bitops in Neon in GCC" blueprint.
* branch review for aarch64-4.7 merge.
A lot of time wasted due network instability making it difficult to
checkout a GCC branch from launchpad/bzr.
* Internal support for infrastructure problems.
* Resumed discussions with our internal IT and Christian Bejram to try to
decrease our constraints.
The Linaro Toolchain Working Group is pleased to announce the 2012.11
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2012.11 is the eigth release in the 4.7 series. Based
off the latest GCC 4.7.2+svn193200 release, it includes ARM-focused
performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.2+svn193200
* Also includes arm/aarch64-4.7-branch up to svn revision 193328.
Fixes:
* LP #1065122
* LP #1065559
* LP #1067760
Linaro GCC 4.6 2012.11 is the 21st release in the 4.6 series. Based
off the latest GCC 4.6.3+svn193199 release, this is the eigth release
after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn193199
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2012.11https://launchpad.net/gcc-linaro/+milestone/4.6-2012.11
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release pages:
https://launchpad.net/gcc-linaro/4.7/4.7-2012.11https://launchpad.net/gcc-linaro/4.6/4.6-2012.11
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi,
I've encountered a case where gcc produces a broken program: a branch that should never be taken is taken, and wrong values are written to memory (and printed out).
The code is fairly ordinary and small. It can be seen here: http://pastebin.com/0Hspz8mw
This happens when -funroll-loops flag is used in conjunction with -O2 or -O3. It doesn't seem to happen when it is used with -O1.
Another few things that influences the program flow from from incorrect to correct run (gives expected outpus) are:
- Adding/removing printf's inside the inner loop
- Changing the order of the expressions in the "if" clause. i.e. from this:
if ((y < mu) || (y >= H - md) ||
(x < ml) || (x >= W - mr))
to this:
if ((x < ml) || (y >= H - md) ||
(y < mu) || (x >= W - mr))
- Assigning ml inside f() to the same value (3) it's getting from the function arguments.
All of these shouldn't change how the program behaves but it does.
I compiled this with two different compilers/environments:
1. g++ (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3, running on 3.2.1-42-linaro-lt-mx6 (native compilation on the ARM board)
Compilation command:
g++ -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 -O3 -std=c++0x -funroll-loops -o test_bug_sa_loops_linaro test_bug.cxx
2. arm-fsl-linux-gnueabi-g++ (Freescale MAD -- Linaro 2011.07 -- Built at 2011/08/10 09:20) 4.6.2 20110630 (prerelease)
Running on a freescale LTIB built linux (3.0.15-1359-g1b64ead)
Compilation command:
arm-fsl-linux-gnueabi-g++ -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 -O3 -std=c++0x -funroll-loops -o test_bug_sa_loops test_bug.cxx
In all the variations I tried it seems that -funroll-loops is critical for this problem to appear.
I'd be glad to hear some comments on this.
Mickey.
This mail was sent via Mail-SeCure system.
On 10 November 2012 05:11, "Frank Müller" <franky1976(a)gmx.net> wrote:
> Michael Hope <michael.hope(a)linaro.org>:
>> My suspicion is that we/crosstool-NG enable extra features like
>> Graphite or GCC is built with a different level of checking. If you
>
> I suspected Graphite as well and removed it in my own builds without noticable difference.
>
>> have the time, could you check the flags passed to GCCs configure?
>> You can do this on Ubuntu using:
>>
>> apt-get build-dep gcc
>> apt-get source gcc
>> dpkg-buildpackage -uc -us -b
>>
>> and compare the configure line with the one in crosstool-NG's build.log.
>
> Isn't this the same as gcc -v? I've posted the lines at http://lists.linaro.org/pipermail/linaro-toolchain/2012-October/002913.html
Good point. There's nothing obvious in the list. Ubuntu explicitly
adds --enable-checking=release but it's the default for release
branches like ours.
I can reproduce the slowdown in a smaller testcase. Compiling pcre
with -O3 -mfpu=neon -march=armv7-a -mtune=cortex-a8 takes 18.8 s for
the Ubuntu Precise 4.6 compiler, 17.8 s for the Ubuntu Quantal 4.7
compiler, and 41.2 s for the Linaro 4.7 2012.10 build. I've logged
LP: #1077739 to track. I'll spin a --enable-checking=release build
just to check.
> The above lines do not work for me, the last line misses a changelog file:
>
> # dpkg-buildpackage -uc -us -b
> tail: cannot open `debian/changelog' for reading: No such file or directory
> dpkg-buildpackage: error: tail of debian/changelog gave error exit status 1
Yip, you need to change to the just-extracted source directory first.
-- Michael
On 14 November 2012 00:48, 남관우 <kw46.nam(a)samsung.com> wrote:
>
> Hi,
>
>
>
> First, our CFLAGS is here.
>
>
>
> -O2 -g -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -Wformat -Wformat-security -Wl,--as-needed
> -fmessage-length=0 -march=armv7-a -mtune=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb -Wa,-mimplicit-it=thumb
> -mapcs -mno-sched-prolog -mabi=aapcs-linux -Uarm -fno-common -fpic
>
>
>
> It was occurred with the message. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03)
>
>
>
> Second,
>
> -O2 -g -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -Wformat -Wformat-security -Wl,--as-needed
> -fmessage-length=0 -march=armv7-a -mtune=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb -Wa,-mimplicit-it=thumb
> -mapcs -mno-sched-prolog -fno-common -fpic
>
>
>
> It was occurred too. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03)
Hi there. I don't know the cause but I'm suspicious of a few things.
Could you try the following builds?
The most likely:
* Without -mapcs
* Without -fstack-protector --param=ssp-buffer-size=4
Less likely:
* Without -fno-common
* With -fPIC instead of -fpic (should make no difference on ARM)
Could you also send through the linker command line? It would be
great to get a full log up on pastebin or similar.
-- Michael
Hi Michael,
Recently I tested the linaro toolchain gcc-4.6 version and try to
build our codes.
it's okay to compile the codes, but when launching the binary it
occures following messages.
/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03
I tested it both "hard float" and "soft float". the result is same.
do you have any clues?
Test environment:
toolchain: gcc-4.6.4 (2012.10 version) soft float option.
Thank you,
Kyungmin Park
hi,
I use beaglebone ,and the CPU is AM3359 from TI
can I use the linaro toolchain to the u-Boot linux kernel and android files?if I can ,which tool chain you suggest you use.
other question, your android realese file also can use my CPU(AM3359),Can I build image and download to my SD and run it?
thanks for your reply.
zhangzhangwei
2012-11-09
== Progress ==
* Watched some Connect sessions (ARMv8, GCC performance)
* AArch64 GDB support testing and backport investigation:
- Activities blocked until patches with the pthread interface update
are ready.
* Boehm GC AArch64 support:
- Read documentation on the garbage collector and ARMv8.
- Asked for advices to the maintainers.
- Started to port the libatomic_ops.
== Next ==
* Continue on the Boehm GC AArch64 support.
* Attended LinuxCon Europe / ELC-Europe / QEMU Summit / KVM Forum
(an overlapping set of conferences across a week in Barcelona)
LCE/ELC: brief summary of interesting sessions (I've only listed
ones which seem most relevant to ARM just to keep the length of this
report down):
* "Devicetree and its stumbling blocks" -- a view from a kernel
developer perspective of some of the issues with doing platform
data to dt conversions: (a) dt is supposedly OS independent and
an external ABI, implying more need for cleanliness and long term
supportable interfaces. (b) conversions imply a need to generalise
bindings to be usable across many devices (c) what do we do about
configuration / policy choices?
My take is that the kernel folks are tying themselves in knots
to try to preserve the (somewhat fictional in practice) idea that
any kernel will work with any older device tree blob and they'd
find it easier if they declared an amnesty for breaking changes
before some deadline date...
* Developing and testing industrial hardware with QEMU
Rather than developing/testing sw against expensive/limited
availability hw, use a model -- easier automation, ability to
simulate error conditions, etc. If your hardware is basically
a PCI card in an x86 box QEMU's fairly easy to use for this.
* UEFI Secure Boot
A summary of the current status of UEFI Secure Boot: it's mandatory
for Win8 hardware; Linux implication is that we need to be able to
maintain simple "out of box boot off distro CD"; optionally, if we
have end-to-end signed binaries we have access to environments which
will end up mandating it (read: government). Fortunately people
have come together to tackle this and it looks like we're in good shape.
http://mjg59.dreamwidth.org/18945.html is a good summary.
* Kernel report by Jonathon Corbet
ARM featured fairly prominently in this stats-driven roundup:
64-bit ARM support was first listed bullet point for 3.7 features
Pointed out that Linaro and other embedded-ARM kernel contributions
are notably up, ARM mess has been cleaned up.
KVM Forum:
* Concurrency in QEMU
Plans for splitting QEMU's "big lock" into finer grained mutexes;
should improve I/O scalability for KVM guests and realtime guest
latency. However some tricky locking design issues to be solved.
I am as usual sticking my oar in occasionally to remind people that
the world is not solely x86-and-PCI...
* qtest
A summary of QEMU's new qtest framework, how it works and how to
write tests. We're going to start insisting on test cases for new
patches, so I need to write some basic tests for a few ARM devices
so I know how it works :-)
* ARM Virtualization for the Masses
Christoffer Dall's talk introducing the ARM virt. extensions and KVM
work. Well received, various questions afterwards (some elements of
"why doesn't this work the way the x86 stuff does", also lots of
"does this work on the Samsung/Google Chromebook" :-))
QEMU Summit:
* This was an invite-only afternoon with perhaps 20 or so of the
main QEMU contributors; broadly focused on "process" issues like
release management, patch flow and security bug handling. Productive
session; minutes should be available on the QEMU mailing list shortly.
This is likely to be repeated next year.
Informal discussions (IME the most important and worthwhile part):
* virtio related : ran through current status of virtio-mmio patches
with Anthony Liguori and Alex Graf, confirmed what changes we need
to make and what the next steps with this should be. Some enthusiasm
for getting this patchset in in the early part of the QEMU 1.4
release if we can. I'm really happy that we've unblocked this bit of
work which had stalled slightly trying to figure out the right approach.
Long term we will probably end up using virtio-pci on ARM but this
is really dependent on hardware with good PCI support appearing.
* SystemC : the upstream community is not currently interested in
SystemC support, but there is some work on the QEMU core which would
be a useful cleanup for QEMU itself and also useful for the SystemC
folk. I'm hopeful that this might help to bring people working with
QEMU in SystemC closer to the "QEMU upstream" community and mailing
list, but it will be a gradual process both socially and technically
if it does happen.
* an informal enquiry about whether system emulation of virt. mode
in ARM was planned or how much work it would be
* in-kernel-irqchip: common ABI cross architecture
the current ABI is a bit x86-specific, useful discussion about
what POWER/S390/ARM would need. There will probably be some more
ioctls coming along but the good news is that what the KVM ARM
patches have currently fits into the proposals with only a very
trivial tweak; we can add support for the new ioctls later if
they are useful for us.
-- PMM
== Blueprints ==
Initial Current Actual
initial-aarch64-backport 31 Oct 2012 30 Nov 2012
aarch64-baremetal-testing 31 Oct 2012 30 Nov 2012
fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012
backport-fma-intrinsic 31 Dec 2012 31 Dec 2012
fused-multiply-add-support 31 Dec 2012 31 Dec 2012
gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012
== Progress ==
* Returned from Connect and followed up.
* Updated performance blueprints for next iteration
* Backporting Doko's triplet patches to 4.7
* Patches ready except for problems building Ada
* HOT/COLD partitioning
* Rebuilt with TBB/TBH disabled always
* Started investigated LRA for ARM
== Next Week ==
* Post triplet backport patches upstream
* Run HOT/COLD partitioning benchmarks
* On ARM to see if TBB/TBH is making the difference previously seen
* On x86_64 to see what the actual benefit we could get
* initial-aarch64-backport & aarch64-baremetal-testing
* Finish documentation
* gcc-investigate-lra-for-arm
* Benchmark on x86_64 to see what the benfit could be.
* fix-gcc-multiarch-testing
* Come up with strawman proposal for updating testsuite to handle
testing with varying command-line options.
== Future ==
* backport-fma-intrinsic & fused-multiply-add-support
* Backport patches once fix-gcc-multiarch-testing has been done.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Dear all,
we have an ARM Cortex-A8 board where we are running our application. I am in charge of maintaining the Linux on it and the toolchain/SDK setup. So far we've been running Poky/OpenEmbedded and using the cross compiler that came about during the compilation.
For easier maintenance, we are now switching to Linaro. The image is set up and I can compile, however I notice a peculiar fact: the binary distribution of Linaro's gcc (https://launchpad.net/linaro-toolchain-binaries/trunk/2012.10/+download/gcc…) has a significantly larger compilation speed than a version of arm-linux-gnueabihf-gcc that is shipping with Ubuntu. In our particular case, using Ubuntu's version it takes less than 6 minutes to compile our software, but 10 minutes when we use Linaro's version. The makefiles and source are exactly the same, only the compiler is different. I also tried an older version (4.6) of Linaro's gcc to match the Ubuntu one (tested the 12.04 shipped version), with no significant difference.
Compiler flags for the system are -march=armv7-a -mtune=cortex-a8 -mfpu=neon -mfloat-abi=hard
Running with -ftime-report, most of the additional time seems to be spent in the parser. Adding -fno-graphite-identity -fno-graphite for Linaro's gcc did not make a difference.
I believe I tried to use crosstool-ng to make my own version, but I don't remember the results as this was over 7 weeks ago. I also did not have a chance to compare performance of the binaries. I do notice a difference in compilation sizes (4.8 MB for Ubuntu's 4.6 version, 4.1 MB for Linaro's 4.7 versions - can't test anything other right now).
I would like to use Linaro's gcc as the crosscompiler for our project, as it is an easy setup. Repackaging Ubuntu's version is an option, though (some of the team do not use Ubuntu, plus I'd like everybody to use EXACTLY the same version of the crosscompiler). So there is no real "problem" for me, per se, but I am extremely curious as to what is going on here. It seems that Linaro's gcc has additional patches or maybe just different default settings that cause additional time to be spent in the parser. It would be interesting to know what exactly this is and whether/how it can be disabled in those cases where time of compilation is more important than e.g. performance gain.
TIA for replying.
Best
Frank
* Attended Linaro Connect; notable sessions:
+ Ubuntu plans for QEMU for Ringtail release
= upstream qemu has merged qemu-kvm back in so
Ubuntu will switch to qemu from qemu-kvm for x86
= also makes sense now to use upstream qemu for all archs
(following Debian) rather than using qemu-linaro for non-x86:
reasons for using q-l in Ubuntu now mostly fixed (ie upstream
ARM support no longer dire). Ubuntu will carry omap3 patches
to avoid dropping that feature in the changeover
= makes sense for Linaro too as we now have an automated
package-to-PPA setup for people who need bleeding-edge and
also will want Ubuntu to transition to a more stably released
and supported QEMU codebase to use for KVM-on-ARM-servers
+ KVM Testing plans
= worked through a list of things that would be nice to test;
useful feedback from people in the session about what matters.
Missing: specific commitment by anybody to write tests :-)
+ various informal discussions about possibilities for v8 QEMU
* this week: at LinuxCon Europe / ELC-Europe / KVM-Forum / QEMU Summit
-- PMM
Hi toolchain people,
I've gone through and massaged our meetings and 1-on-1s to handle the
recent daylight savings changes. Most meetings now start at 9:15 am GMT
and 1-on-1s are packed before them if possible.
Let me know if I should massage them further,
-- Michael
== Progress ==
* Attended Linaro Connect
* Worked out focus for performance in next iteration:
* Cortex-A15
* Other discussions on:
* Transitioning from cbuild->LAVA
* ARMv8 GNU Tools support
* big.LITTLE Toolchain tuning
== Next Week ==
* Backport Doko's configury changes for arm-none-linux-gnueabihf support
* Remerge HOT/COLD partitioning to test like for like (TBB generation)
* Benchmark LRA vs Reload on x86 and x86-64
* Write up strawman for non-multitest testing in GCC
== Future ==
* Decide whether the effort to develop HOT/COLD partitioning is worth it.
* Support LRA on ARM.
* Attend Connect in Hong Kong...
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Dear All,
We have ARM cross compiler, and building our code. we got below error.
we have GCC Linaro 4.6.4.
arm-linux-gnueabi/bin/ld: DIV usage mismatch between
/home/Release/libasm.a(Blt32_Neon.o) and /home/Release/liblayer.so
arm-linux-gnueabi/bin/ld: failed to merge target specific data of file
/home/Release/libasm.a(Blt32_Neon.o)
is it related to below link ?
http://sourceware.org/ml/binutils/2012-03/msg00211.html
thanks
Hi,
here's some patches for gcc-linaro to make it work with
--host=arm-linux-androideabi
They're the quick and dirty thing to do and look like they could have
been written by Microsoft, needed something working in time for
Connect ;)
gcc-4.7-android-workarounds.patch: Workarounds for things that go
wrong, but where the true cause is yet to be determined (e.g. why
would configure think we have fread_unlocked and friends when we
don't?)
gcc-4.7-libitm-android.patch: Workaround for Bionic not knowing Elf32_auxv_t
gcc-4.7-no-unneeded-multilib.patch: Get the multilib config in sync
with regular Linux
gcc-4.7-stlport.patch: Use stlport instead of libstdc++ (yes, this
sucks - but it's what Android decided to do). Still needs to link
libstdc++ because Bionic contains a libstdc++.so (but it's more like a
libsupc++ - no STL there, but needed for stlport to work).
ttyl
bero
== Progress ==
* HOT/COLD partitioning for PGO
* Initial look at results
* Patch Tracking & Backporting
* Testing Doko's configury changes for arm-none-linux-gnueabihf support
* Connect Prep
* LRA Investigations
* Sign/zero extension II
== Next Week ==
* Linaro Connect
== Future ==
* Attend Connect
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Summary:
* Validate and release Linaro binary toolchain 2012.10
* Test
Details:
1. Release Linaro binary toolchain 2012.10
* Fix windows installer issue due to version format change.
* Validate and release Linaro binary toolchain 2012.10.
2. Identify the root cause of PR 54902 (lp:1065559), and Richard
Biener fixed it.
3. Enable SPEC2006 test. Testing is ongoing.
Planed Leaves:
* Nov. 5-7: Off site teambuilding event.
* Nov. 9, 12-13: Annual leaves
Plans:
* Performance test for shrink-wrap.
Best regards!
-Zhenqiang
== track-kvm-abi-changes ==
* updated qemu patches to match Christoffer's v13 tree, committed
all fixes suggested in previous round of code review, rebased
and sent RFC v3 of the QEMU KVM/ARM support patches
== other ==
* rebased qemu-linaro on master; found and fixed a bug which
meant that beagle models crashed when the kernel tried to touch
the USB-OHCI device
* submitted some minor QEMU cleanup patches (last lot of stuff
before softfreeze next week, I expect)
* usual upstream review/etc
* started to look at virtio-mmio patches
* prep for Linaro Connect next week
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
== Progress ==
* Aarch64 GDB support testing:
- Ran the GDB testsuite via gdbserver on x86
- Made a board file to run against the model
- Tried debugging a simple hello world via gdbserver:
It fails while loading the image, because of a mismatch between
kernel and GDB ptrace interface.
* Aarch64 GDB backport investigation:
- Backported to the Linaro GDB 7.5 release.
- Discussed with ARM people the ptrace issue.
== Next ==
* On vacation.
The Linaro Toolchain Working Group is pleased to announce the 2012.10
release of the Linaro Toolchain Binaries, a pre-built version of
Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2012.10
* Linaro GDB 7.5 2012.09
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.10
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Hi All,
I wanted to see the difference in objdump of an application where I can
make the difference between the VFPV3 and VFPV4 support. I tried enabling
the flag -mfpu=vfpv3 and -mfpu=vfpv4 for ARM Cortex A15 toolchain in my
test code but cannot see the difference in two objdumps.
According to my survey, the fused multiply and accumulate is the only
instruction that can create the difference in two. Can any one provide the
sample test code for the same? Precisely, I wish to see the difference in
performance for vfpv3 and vfpv4.
Looking forward to your reply.
Thanks and Regards,
Jubi
Summary:
* Linaro bug analysis
* Validation
Details:
1. Linaro bug analysis:
* lp:1065122: Triaged. A fix patch was committed to 4.7 and trunk.
* lp:1065559: Confirmed. Need more investigation to find the root cause.
* lP:1065509: Can not reproduce it with the latest Linaro toolchain.
* lp:1066095: Investigate and invalid it since the reporter can not
reproduce it now.
2. Bug fix and smoke test for Linaro binary toolchain 2012.10 release.
3. Clean up shrink-wrap related patches and send to Linaro mail-list for review.
Plans:
* Linaro binary toolchain 2012.10 release.
* Shrink-wrap performance test.
Planed leave:
* Oct. 26
Best regards!
-Zhenqiang
== Progress ==
* Read wikis on OpenEmbedded and FastModel
* Aarch64 GDB support testing :
- Managed to run OE rootfs and kernel under FastModel
- Configured the ssh/scp access to the model
* Aarch64 GDB backport investigation :
- Discussed with ARM the port and plans
- Identified upstream patches
== Next ==
* Continue on Aarch64 GDB.
Short week (two days):
== other ==
* implemented QEMU patches to track and tell the kernel where the
various bits of the VGIC should be mapped in the address space;
however these seem to cause the host kernel to Oops...
* added a log message category for "guest just did something that's
probably a bug in the guest", so we can use it instead of random
printf/aborting QEMU
* generate inline code for Neon 64 bit negate and 32 bit abs,
rather than calling helper functions
* updated and resent new versions of some minor cleanup patches
which had got lost/obsoleted by QEMU internals changes
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
== Progress ==
* HOT/COLD partitioning for PGO
* Submitted merge request for current changes so that we can
benchmark and see how much benefit we can actually expect
* Patch Tracking & Backporting
* Backported Uli's fix for insn splitting at -O0 to 4.7
* Started backporting Doko's configury changes for
arm-none-linux-gnueabihf support
* Connect Prep
* Started investigating LRA
* Admin
* Interviewing
== Next Week ==
* Prepare for Connect
* Investigate zero/sign extension
* Investigate LRA
* Investigate Conditional Comparison benefits
* AArch64
* Document processes
== Future ==
* Attend Connect
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi Ramana,
The attached file is a reference patch to add more dwarf/unwind info
in epilogue. Please help to review.
Without the patch, dwarf check fail for the following cases when
enabling shrink-wrap:
tst ... L1 //simple_return
push ...
...
pop ... //.cfa_offset is not 0
L1:
bx lr //common simple_return
Thanks!
-Zhenqiang
== other ==
* upstream patch review
* target-arm pull request
* reviewed/committed some boot wrapper patches from Tixy to init the CCI
* rebased various qemu kvm-related patches on current upstream master,
sent out RFC v2 for review (matching kernel -v12 patches); this is
getting some useful review feedback
* added check for 'does KVM support vfp-d32' rather than just
assuming it on the QEMU side
* discussed API for userspace to tell KVM the base address of the
VGIC with Avi, Christoffer [todo: write QEMU patches to go with
C's proposed kernel patches]
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
Summary:
* Test shrink-wrap.
* Identify the root cause of dwarf check fail when enabling shrink-wrap.
Details:
1. Test shrink-wrap on PandaBoard with Precise
* Bootstrap is OK
* No make check regression
* No performance change for SPEC2000 INT.
2. Identify the root case for dwarf check fail on ARM, while they are
OK on X86 and MIPS when enabling shrink-wrap.
* "push" related INSNs are set as RTX_FRAME_RELATED_P in prologue; but
not all "pop" related INSNs are set as RTX_FRAME_RELATED_P.
* Prologue uses REG_FRAME_RELATED_EXPR notes to tell the dwarf backend
SP is adjusted; but no such kind of notes in epilogue.
* In addition, dwarf info for INSNs to adjust SP are not handled
correctly in epilogue.
Plans:
* Verify shrink-wrap related bugs
* Prepare Linaro binary toolchain 2012.10 release
Best regards!
-Zhenqiang
The Linaro Toolchain Working Group is pleased to announce the 2012.10
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2012.10 is the seventh release in the 4.7 series. Based
off the latest GCC 4.7.2+svn191881 release, it includes ARM-focused
performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.2+svn191881
* Backport changes to use VLD1 for Neon quad loads.
Fixes:
* LP 1053348: Missing binary files
Linaro GCC 4.6 2012.10 is the twentieth release in the 4.6 series.
Based off the latest GCC 4.6.3+svn191880 release, this is the seventh
release after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn191880
* A fix to LP #1029454
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2012.10https://launchpad.net/gcc-linaro/+milestone/4.6-2012.10
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release pages:
https://launchpad.net/gcc-linaro/4.7/4.7-2012.10https://launchpad.net/gcc-linaro/4.6/4.6-2012.10
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== Progress ==
* Completed Linaro ramp up process.
* Obtained my SSH security exception
* Crosstool-ng :
- Repoduced the aarch64 builds (bare and linux)
- Updated gcc to Linaro 2012.10 and submitted the merge request.
* Cbuild autobuilder :
- Not able to spawn a job on seabright (lack of permission)
== Misc ==
* One day off.
== Progress ==
* builtin_bswap16:
* Backported missing patch from thunk to Linaro/4.7. One test still
failing in the hard-float + thumb configuration because it forces
armv6 and results in a unsupported configuration: vfp-1 + hard-float.
Resumed discussion about a fix I proposed 3 weeks ago.
* PGO/hot-cold partitioning/Spec2k:
* read doc about spec2k
* started looking at 254.gap causing an ICE.
* started studying qemu traces about 175.vpr crashing when compiled
using profiling info. Cold code returns from a function using a
clobbered lr value.
== Next ==
* builtin_bswap16:
* complete backport to linaro-gcc 4.7.
* PGO/hot-cold partitioning/Spec2k:
* investigate compiler crash and runtime failures.
== Progress ==
* Deputising for Michael
* 4.6 and 4.7 2012.10 releases
* Included extra AArch64 merge into gcc-lianro/4.7
* AArch64 support
* Did another merge
* Starting another one.
* HOT/COLD partitioning for PGO
* PINGed If/Then/Else block conversion patch
* Started reworking postreload-gcse.c patch
* Ran into issues with vanilla gcc-linaro/4.7 not being able to
build for 'arm-none-linux-gnueabihf' without some configury magic
* Admin
* Interviewing
== Next Week ==
* Do another AArch64 merge.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi Guys,
I just found an issue in kernel code and thought we must have a
compilation warning for such cases.
Submitted a bug here:
https://bugs.launchpad.net/gcc-linaro/+bug/1064218
Problem description:
-------------------------
When we have following declaration:
struct foo {
char array[5];
....
};
And have a definition like:
struct foo foo_abc = {
.array = "12345",
};
Problem here is: size of array is 5 bytes and so we can actually add a
string with four characters only to it, as '\0' will take
an additional space.
But with my definition of foo_abc.. i had 5 characters + '\0'... that
will make it 6 and that will overflow the array..
What will actually happen here?
- compiler will not add '\0' at all?
-or it will go outside of boundaries of array?
--
viresh
On 5 October 2012 12:10, Rob Herring <robherring2(a)gmail.com> wrote:
> I've been scratching my head with a "scheduling while atomic" bug I
> started seeing on 3.6. I can easily reproduce this problem when doing a
> wget on my system. It ultimately seems to be a combination of factors.
> The "scheduling while atomic" bug is triggered in do_alignment which
> gets triggered by this code in net/ipv4/af_inet.c, line 1356:
>
> id = ntohl(*(__be32 *)&iph->id);
> flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id ^ IP_DF));
> id >>= 16;
>
> This code compiles into this using "gcc version 4.6.3 (Ubuntu/Linaro
> 4.6.3-1ubuntu5)":
>
> c02ac020: e8920840 ldm r2, {r6, fp}
> c02ac024: e6bfbf3b rev fp, fp
> c02ac028: e6bf6f36 rev r6, r6
> c02ac02c: e22bc901 eor ip, fp, #16384 ; 0x4000
> c02ac030: e0266008 eor r6, r6, r8
> c02ac034: e18c6006 orr r6, ip, r6
>
> which generates alignment faults on the ldm. These are silent until this
> commit is applied:
Hi Rob. I assume that iph is something like:
struct foo {
u32 x;
char id[8];
};
struct foo *iph;
GCC merged the two adjacent loads of x and id into one ldm. This is
an ARM specific optimisation done in load_multiple_sequence() and
enabled with -fpeephole2.
I think the assembly is correct - GCC knows that iph is aligned and
knows the offsets of both x and id. Happy to be corrected if I'm
wrong, but I think the assembly is valid given the C code.
-- Michael
== Progress ==
* builtin_bswap16:
* backporting of builtin_bswap16 for ARM to Linaro/4.7: one of the
tests fails. Waiting for Ramana's return to see if he can help me
identify the patch needed from trunk.
* Useless zero extensions: despite Ulrich support I didn't succeed
to rewrite the bswap16 pattern in a way that would avoid
generating useless zero extension. Asking for help on gcc list
shows that it would actually need a complete new optimization
pass, which has already been discussed several times.
* PGO/hot-cold partitioning/Spec2k:
* looking at spec2k build & run system
* Branch reviews: approved Matt's october merges for Linaro-gcc 4.6 and 4.7.
Briefly looked at aarch64-4.7 merge request.
== Next ==
* builtin_bswap16:
* try to complete backport to linaro-gcc 4.7.
* PGO/hot-cold partitioning/Spec2k:
* investigate compiler crash and runtime failures.
* setup Snowball
== Progress ==
* Started Linaro ramp up process.
* Started to look at Crosstool-ng and CBuild
* Fighting against proxy and bazaar configuration
== Next Week ==
* Continue the started tasks.
== Progress ==
* 4.6 and 4.7 start of month merges
* Fixed missing binary files issues whilst doing this.
* 4.7 AArch64 merge into gcc-linaro/4.7
* Completed initial merge
* Admin
* Interviewing
== Next Week ==
* Deputise for Michael
* Do GCC-Linaro releases
* Fix up any issues with aarch64 merge.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Adding linaro-toolchain
On Tue, Oct 02, 2012, Khem Raj wrote:
> On Tue, Oct 2, 2012 at 4:59 PM, Tim Bird <tim.bird(a)am.sony.com> wrote:
> > When I try to build the Linux kernel version 3.6 with the gcc-4.7
> > nightly build Linaro toolchains,
>
> linaro binutils needs to back port
>
> http://sourceware.org/git/?p=binutils.git;a=commit;h=3fd1fadc205bc69410080a…
>
> >
> > $ arm-eabi-gcc --version
> > arm-eabi-gcc (Linaro GCC 4.7-2012.09-1~dev) 4.7.2 20120910 (prerelease)
> > $ arm-eabi-as --version
> > GNU assembler (Linux/GNU Binutils) 2.23.51.0.3.20120918
> >
> > I get a compiler error (actually, assembler error):
> >
> > AS arch/arm/lib/copy_from_user.o
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S: Assembler messages:
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r3,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:118: Error: selected processor does not support ARM mode `ldralt r3,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:119: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:120: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:121: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:122: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:123: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:124: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:173: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > make[2]: *** [arch/arm/lib/copy_from_user.o] Error 1
> > make[1]: *** [arch/arm/lib] Error 2
> > make[1]: *** Waiting for unfinished jobs....
> >
> >
> > This appears to be related to the following bug report for binutils:
> > http://sourceware.org/ml/binutils/2012-09/msg00128.html
> >
> > I'm compiling the kernel for PandaBoard
> >
> > Any ideas for work-arounds or fixes for this? Note that the ldralt instruction
> > doesn't actually appear in copy_template.S (maybe it's coming from a macro?)
> > -- Tim
> >
> > =============================
> > Tim Bird
> > Architecture Group Chair, CE Workgroup of the Linux Foundation
> > Senior Staff Engineer, Sony Network Entertainment
> > =============================
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev(a)lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev
--
Loïc Minier
== GCC ==
* Implemented patch to prevent lower-subreg pass from splitting
pseudo register moves during first pass. Committed to mainline.
* Updated patch to perform 64-bit integer shifts in NEON registers
to avoid NEON single to NEON double register hazard. Re-started
testing via Launchpad branch neon-shifts-4.7-v3.
* Rebased patch to improve 32-to-64-bit extended from core into
NEON registers, added backport of lower-subreg mainline fix.
New Launchpad branch neon-extendsidi-4.7-v3.
* Tested reload patch to fix aarch64 find_reloads_subreg_address
bug on multiple platforms to prepare for mainline.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
== Progress ==
* builtin_bswap16:
* patch to catch (x<<8)|<x>>8) committed upstream after confirmation
it was OK by PowerPC guys.
* backporting of builtin_bswap16 for ARM to Linaro/4.7: one of the
tests fails. Trying to isolate the trunk change that would make is
pass.
* useful discussions with Ulrich to investigate if we could avoid
generating useless zero-extensions after rev16. I still need to
experiment.
* PGO/hot-cold partitioning:
* applied info from Matt, I have now a usable Spec2000 setup based
on qemu.
== Next ==
* builtin_bswap16:
* try to avoid useless zero-extensions.
* PGO/hot-cold partitioning:
* investigate runtime failures.
* run on a Snowball board.
== Progress ==
* 4.7 AArch64 merge into gcc-linaro/4.7
* Got Foundation model working
* Ran testsuite - results OK - some obvious infrastructure issues though
* Hot/Cold partitioning in PGO:
* Posted second patch upstream
* Had basic flaw with it pointed out (shame was the flaw fixed the issue)
* Admin
* Interviewing
== Next Week ==
* Start of month branch merges.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* ARM/aarch64-4.7-branch merge into gcc-linaro/4.7.
* Investigate failure in testsuite run
* Check that I am merging the svn branches correctly.
* Participate in sprint
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
(two week rollup report since week 38 was a short week for me)
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== other ==
* looked briefly at the result of running the clang static analyzer
over QEMU
* wrote some fixes to totally broken code in the ds1338 model as
result
* reviewed some nice TCG optimisation patches from Aurelien which bump
up performance for ARM guests by 10-15%
* reviewed, bugfixed and committed some patches for the bootwrapper
from Dave Martin
* removed obsolete SMC API support from bootwrapper (lets us knock
the final item off a blueprint)
* implemented the new movcond TCG IR insn in the ARM backend
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
Summary:
* Validate and release Linaro binary toolchain 2012.09
* Identify the root cause of dwarf check fail in native build when
enabling shrink-wrap.
Details:
1. Validate and release Linaro binary toolchain 2012.09.
2. Analyze the dwarf check fail in native build when enabling shrink-wrap:
* Root cause: tail calls from simple-return path and normal return
path are optimized as one common tail call.
* To fix it, use simple-return to indicate the one from simple-return
path, which will block the optimization to mix them.
Plans:
* Test shrink-wrap performance.
Planed leaves:
* Sept. 30 - Oct. 7: Mid-Autumn Festival and National Day of China's holiday.
Best regards!
-Zhenqiang
Hi,
I am using Linaro Toolchain for compiling UEFI and I am getting alignment
fault as exception while running UEFI on Origen Board.
When I was using other cross compilers the issue was not there.
The crash report is as follows:
Data Abort Exception PC at 0x4F84DCDC CPSR 0x60000133 nZCveAifT_svc
/home/shiva/workspace/armserver/uefi_origen/edk2/Build/OrigenBoard-Exynos/DEBUG_ARMLINUXGCC/ARM/FatPkg/EnhancedFatDxe/Fat/DEBUG/Fat.dll
loaded at 0x4F84D000 (PE/COFF offset) 0xCDC (ELF or Mach-O offset) 0xA9C
0xF8BD6037 LDRH r6, [sp, #0x37]
R0 0x0000000B R1 0x0000000A R2 0x4FCEEAD8 R3 0x80000000
R4 0x4F836010 R5 0x4F863619 R6 0x00000000 R7 0x4F837F10
R8 0xFFFFFFFF R9 0x00000000 R10 0x00000001 R11 0x00000000
R12 0x00000000 SP 0x4FCEEA20 LR 0x4F84DCDD PC 0x4F84DCDC
DFSR 0x00000001 DFAR 0x4FCEEB17 IFSR 0x0000140B IFAR 0x00910883
Alignment fault: read from 0x4FCEEB17
Instruction Domain fault on Page at 0x00910883
ASSERT
/home/shiva/workspace/armserver/uefi_origen/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c(304):
((BOOLEAN)(0==1))
--
Thanks and Regards,
Shiva.
Interested in working with us on improving the performance of Linux on
ARM? We’re looking for motivated engineers to work in our toolchain
team on compiler technology, developer tools, and low level
performance libraries. You will use your specialised knowledge to work
in the open, work upstream, and make ARM flavoured improvements to a
range of tools that are fundamental to making the latest mobile and
server products.
We’re currently looking for:
* GCC developers
* Developer tools engineers, especially on the GNU tools like binutils and GDB
* ARM performance engineers, to work on a range of low level libraries
We’re a distributed team. Working from the home office is an option.
Please see the careers page on our website for more information and
how to contact us.
-- Michael
== GCC ==
* Committed patch to use vld1.64/vst1.64 instead of vldm/vstm
to GCC mainline and Linaro GCC 4.7
* Committed patch to use vld1/vst1 to implement vec_set/vec_extract
to GCC mainline and Linaro GCC 4.7
* Posted patch to perform 64-bit integer shifts in NEON registers
for mainline inclusion. Started to address review comments.
* Rebased patch to improve 32-to-64-bit extends from core
into NEON registers; ran into lower-subreg regression.
* Worked on implementing fix for lower-subreg regression.
* Handed over (Richard's) auto-inc-dec patches to Matt.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The Linaro Toolchain Working Group is pleased to announce the 2012.09
release of the Linaro Toolchain Binaries, a pre-built version of
Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2012.09
* Linaro GDB 7.5 2012.09
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
Interesting changes include:
* gdbserver is stripped.
* gdbtui is replaced by "gdb --tui"
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.09
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Summary
* Prepare Linaro binary toolchain 2012.09 release
* Fix lp:1036170/pr50970
Details:
1. Prepare Linaro binary toolchain 2012.09 release
* Update linaro gcc and gdb to 2012.09 release
* Workaround gdb lsb build issue.
* Strip gdbserver.
* Smoke tests.
2. Merge shrink-wrap patch to lp:gcc for cbuild test. But dwarf checks
fail when building fortan related codes at stage 2.
3. Identify the root cause of lp:1036170/pr50970 and work out a patch to fix it.
Plans:
* Linaro binary toolchain 2012.09 release.
* Fix shrink-wrap build fail issues.
Planed leaves:
* Sept. 30 - Oct. 7: Mid-Autumn Festival and National Day of China's holiday.
Best regards!
-Zhenqiang
== Progress ==
* Discussed big-endian patches for vext tests: careful review of the
specification is required and this patch might actually expose GCC
bugs in big-endian/Neon.
* builtin_bswap16:
* Posted 2 implementations of the generic patch for
(x<<8)|(x>>8). The 2nd one looks OK, but I was asked to make some
checks on powerPC, which are on-going.
* backporting it to Linaro/4.7. On-going: merged obvious patches but
one test does not produce the same code as on trunk.
* validations in cbuild in with GCC configured for thumb and hard FP
showed that some bswap16 tests fail because they force armv6,
which leads to unsupported thumb1 configuration. Proposed
testsuite modification to make this easier, under discussion with
Matt & Richard.
== Next ==
* builtin_bswap16:
* check powerPC results and have the patch accepted upstream.
* measure probable regression in libav when using the builtin
instead of an asm().
* complete backport in Linaro/4.7.
* PGO/hot-cold partitioning: start working on this blueprint.
== Progress ==
* Fixed
https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/1029454
* After investigating further found that this was actually an issue
already fixed in FSF upstream
* 4.7 AArch64 merge into gcc-linaro/4.7
* Did an initial merge of upstream ARM/aarch64-4.7-branch into gcc-linaro/4.7
* So far it hasn't broken other platforms
* Investigated getting FastModels working for me
* Hot/Cold partitioning in PGO:
* Tidied up current patches ready for reposting upstream
* Handed current status to Christophe
== Next Week ==
* HOT/COLD partitioning for PGO:
* Complete hand-over to Christophe
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* ARM/aarch64-4.7-branch merge into gcc-linaro/4.7.
* Get a test run of aarch64 targetted compiler complete
* Confirm no code generation changes for other back-ends
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
* Admin
* Several interviews
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== track-kvm-abi-changes ==
* folded in Christoffer's interrupt ABI changes
* updated to new ONE_REG ABI for register accesses
* QEMU now in sync with the kernel patchset Christoffer has just sent to alkml
== other ==
* qemu-linaro 2012.09 released
* various meetings/status calls
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
Summary
* Workaround the unwind issue for shrink-wrap
* Verify Linaro tickets.
Details:
1. Debugging the failed cases for shrink-wrap. To workaround the
unwind issue, update arm_expand_epilogue to generate return not
simple_return when sp is changed.
2. Setup Linaro toolchain and verify 8 tickets:
*Linaro gcc:
lp:1036170: Function pointer dereferenced twice. It is ARM special bug
which is confirmed in 4.6, 4.7 and FSF trunk only on ARM.
lp:1048709: wrong assembler, out of range vldr instruction. Confirmed
in Linaro 4.6. Can not reproduce it in 4.7 or FSF 4.6.
lp:1014658: It is c++11 related issue in 4.6.
lp:944572: It is a gcc general issue.
lp:972503 and lp:1039401 can not be reproduced.
* Linaro binary toolchain:
lp:1046718: confirmed and fixed it.
lP:1049498: invalid
Plans:
* Prepare Linaro binary toolchain 2012.09 release.
* Performance test for shrink-wrap.
* Follow-up the tickets.
Best regards!
-Zhenqiang
== Progress ==
* Committed patch to fix 3 testcases in big-endian after upstream comments.
* Updated patch to make vext tests support big-endian after upstream comments.
* builtin_bswap16:
* Committed implementation for ARM.
* Investigating testsuite regressions caused by my patch to catch
(x<<8)|(x>>8)
== Next ==
* Continue with bswap16 support.
== Progress ==
* Started looking at
https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/1029454
* Confirmed the failure
* Unfortunately the git bisect I thought would find the fix didn't
* Hot/Cold partitioning in PGO:
* Some further investigations
* Talked to Uli about one failure - he gave me some further pointers
* Admin
* Some interviewing
== Next Week ==
* Continue looking at 1029454: cselim tree optimizer generates incorrect code
* Start looking at merging the ARM public 4.7 GCC branch into gcc-linaro/4.7
* Hot/Cold Partitioning:
* Investigate remaining silent code-gen faults and non-termination
issue in SPEC
* If failures are fixed start profiledbootstraps and tests on the
central boards.
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== GDB ==
* Created and published Linaro GDB 7.5 release.
== GCC ==
* Posted patch to use vld1.64/vst1.64 instead of vldm/vstm
for mainline inclusion.
* Posted patch to use vld1/vst1 to implement vec_set/vec_extract
with scalar operand residing in memory.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro GDB 7.5.
Linaro GDB 7.5 2012.09 is the first release in the 7.5 series.
***NOTE*** Linaro GDB 7.5 2012.09 is identical to the FSF GDB 7.5 release,
except for the change in version number and Linaro branding, since all
Linaro GDB features were already accepted upstream and are included in
the FSF release as-is. Future releases in the Linaro GDB 7.5 series may
include additional ARM-focused bug fixes and enhancements.
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.5-2012.09
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro QEMU 2012.09.
Linaro QEMU 2012.09 is the latest monthly release of qemu-linaro. Based
off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
There are no major changes in this month's release, but it has
been updated to be based on upstream's recent 1.2.0 release.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2012.09
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The Linaro Toolchain Working Group is pleased to announce the 2012.09
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2012.09 is the sixth release in the 4.7 series. Based
off the latest GCC 4.7.1+svn191123 release, it includes ARM-focused
performance improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.7.1+svn191123
* Adds support for the NEON vext instruction when shuffling
* Backports improvements to scheduling transfers between VFP and core registers
* Backports support for the UBFX instruction on certain bit extract idioms
Fixes:
* PR54252 ICE with too wide alignment assertion on vectorised code
* PR54212 ICE due to generating a predicated NEON vdup instruction
Linaro GCC 4.6 2012.09 is the nineteenth release in the 4.6 series.
Based off the latest GCC 4.6.3+svn191000 release, this is the sixth
release after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn191000
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2012.09https://launchpad.net/gcc-linaro/+milestone/4.6-2012.09
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.7/4.7-2012.09
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
-- Michael
Summary:
* Test shrink-wrap code
Details:
1. Add simple_return support in function thumb2_expand_return for
shrink-wrap. Here is the make check status
* One new fail is due to code size increase. We'd disable it when
optimizing function for size on THUMB2.
* Other new fails is due to dwarf info. Root cause is ICE at function
maybe_record_trace_start
gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row));
Here is the failed code segment:
tst ... L1
push {r4}
...
ldr r4, ...
L1:
bx lr // common simple return from two branches.
Here are the results for cur_row and ti->beg_row of trace starting at L1:
{cfa = {offset = 0, base_offset = 0, reg = 13, indirect = 0, in_use =
0}, cfa_cfi = 0x0, reg_save = 0x0}
{cfa = {offset = 4, base_offset = 0, reg = 13, indirect = 0, in_use =
0}, cfa_cfi = 0x0, reg_save = 0x7ffff726ab70}
Try gcc-linaro-4.5-2011.03. It does not generate the common bx lr.
test L1
push {r4}
...
pop {r4}
bx lr
L1:
bx lr
There is similar bug about it. But the fix is useless for us:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50833
Plans:
* Continue shrink-wrap task.
Best regards!
-Zhenqiang
== Progress ==
* Neon vext support for builtin_shuffle:
* Committed vext patch upstream, as well as a small cleanup patch.
* Merged vext support into gcc-linaro/4.7 branch.
* Posted upstream a follow-up patch to make vext tests support
big-endian.
Filed PR 54517: wrong code generation in big-endian with inline in
these tests.
* Updated patch to fix 3 testcases in big-endian after upstream comments.
* Implement builtin_bswap16:
* Posted upstream a patch to implement bswap16. Discussion on-going,
to have less duplication between arm and thumb patterns.
* Investigating how to make GCC catch the (x<<8)|(x>>8) construct
(where x is unsigned short) and map it to rev16, like
builtin_bswap16.
== Next ==
* Continue with bswap16 support.
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== track-kvm-abi-changes ==
* merged in Christoffer's patches altering the IRQ delivery ABI
== other ==
* resent some patches as qemu trunk has reopened after 1.2 release
* misc upstream review work
* prep for qemu-linaro 2012.09 release
* AFDS (annual review) season again
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
== Progress ==
* Started looking at symbol_ref splitting benchmark results
* One big regression ~18%
* Started to investigate whether code alignment was the problem as before
* Hot/Cold partitioning in PGO:
* https://blueprints.launchpad.net/gcc-linaro/+spec/hot-cold-partitioning-in-…
* Sent fixes so far upstream
* Spent most of the week looking at a Silent Code Gen fault in reload.
* Admin
* Some interviewing
== Next Week ==
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
* Hot/Cold Partitioning:
* Investigate remaining silent code-gen faults and non-termination
issue in SPEC
* If failures are fixed start profiledbootstraps and tests on the
central boards.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
All,
I have run into a(nother) problem with reload with
-freorder-blocks-and-partition.
Attached is my WIP patch (some of this has been sent up to gcc-patches
for review), and also the profile information (tarred up) I have
gathered in the train session
I get a segfault when executing crafty, which seems to come from
incorrect code generation in iterate.c.
The following shows some of the RTL dump after IRA
(insn 3087 1471 3088 163 (clobber (reg:DI 682 [ D.7985 ])) -1
(nil))
(insn 3088 3087 3085 163 (set (subreg:SI (reg:DI 682 [ D.7985 ]) 0)
(sign_extend:SI (mem/c:QI (reg/f:SI 1417) [0
transposition_id+0 S1 A8]))) 735 {*thumb2_extendqisi_v6}
(expr_list:REG_DEAD (reg/f:SI 1417)
(nil)))
...
(insn 3089 1477 1478 163 (set (subreg:SI (reg:DI 682 [ D.7985 ]) 4)
(ashiftrt:SI (subreg:SI (reg:DI 682 [ D.7985 ]) 0)
(const_int 31 [0x1f]))) 130 {*arm_shiftsi3}
(nil))
...
(insn 2898 2622 2899 203 (set (reg:SI 1677)
(mem/u/c:SI (symbol_ref/u:SI ("*.LC60") [flags 0x2]) [2 S4
A32])) 635 {*thumb2_movsi_vfp}
(insn_list:REG_LABEL_OPERAND 1525 (expr_list:REG_EQUIV (label_ref:SI 1525)
(nil))))
(insn 2899 2898 3491 203 (set (reg:SI 1678)
(ior:SI (reg:SI 1677)
(const_int 1 [0x1]))) 98 {*iorsi3_insn}
(expr_list:REG_DEAD (reg:SI 1677)
(nil)))
(insn 3491 2899 3492 203 (set (reg:DI 1734 [orig:682 D.7985 ] [682])
(reg:DI 682 [ D.7985 ])) 636 {*movdi_vfp}
(nil))
...
(jump_insn 2900 3499 2625 203 (set (pc)
(reg:SI 1678)) 727 {*thumb2_indirect_jump}
(expr_list:REG_DEAD (reg:SI 1678)
(expr_list:REG_CROSSING_JUMP (nil)
(nil))))
...
Insns 2898, 2899, and 2900 form the standard Thumb-2 indirect jump
sequence. Insn 3491 is a move that has been generated as part of
emit_moves in IRA for the loop it belongs to (effectively copying r682
into r1734).
Now despite thinking that r1678 is live throughout insn 3491 after
reload this part of the RTL dump looks like
(insn 2898 2622 2899 212 (set (reg:SI 4 r4 [1677])
(mem/u/c:SI (symbol_ref/u:SI ("*.LC60") [flags 0x2]) [2 S4
A32])) 635 {*thumb2_movsi_vfp}
(insn_list:REG_LABEL_OPERAND 1525 (expr_list:REG_EQUIV (label_ref:SI 1525)
(nil))))
(insn 2899 2898 3491 212 (set (reg:SI 4 r4 [1678])
(ior:SI (reg:SI 4 r4 [1677])
(const_int 1 [0x1]))) 98 {*iorsi3_insn}
(nil))
(insn 3491 2899 3493 212 (set (reg:DI 4 r4 [orig:682 D.7985 ] [682])
(mem/c:DI (plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])) [9 %sfp+-672 S8 A64])) 636 {*movdi_vfp}
(nil))
...
(jump_insn 2900 3497 2625 212 (set (pc)
(reg:SI 4 r4 [1678])) 727 {*thumb2_indirect_jump}
(expr_list:REG_CROSSING_JUMP (nil)
(nil)))
That is all of r682, r1678, and r1734 have been assigned to hard
register r4. This is incorrect - as insn 2900 wants to be using r1678
from insn 2899.
Looking at the logs it seems to me that r1734 because its original is
r682 and that is assigned r4.
The reload dump says the following about the liveness of the registers
for various insns:
insn=3087, live_throughout: ..., dead_or_set: 682
insn=3088, live_throughout: ..., dead_or_set: 682
insn=3089, live_throughout: ..., dead_or_set: 682
insn=2898, live_throughout: ..., 682, ..., dead_or_set: 1677
insn=2899, live_throughout: ..., 682, ..., dead_or_set: 1677, 1678
insn=3491, live_throughout: ..., 682, 1678, ..., dead_or_set: 1734
insn=2900, live_throughout: ..., 682, 1734, ..., dead_or_set: 1678
This suggests to me that the compiler should know assigning the same
hard-register to r682 and r1678 is incorrect as they have overlapping
live-ranges, and are not duplicates of each other.
The compiler is configured as follows:
Target: arm-none-linux-gnueabi
Configured with:
/work/sources/gcc-fsf-enable-hot-cold-partitioning/configure
--target=arm-none-linux-gnueabi
--prefix=/work/builds/gcc-fsf-enable-hot-cold-partitioning-arm-none-linux-gnueabi/tools
--with-sysroot=/work/builds/gcc-fsf-enable-hot-cold-partitioning-arm-none-linux-gnueabi/sysroot
--disable-libssp --disable-libgomp --disable-libmudflap
--enable-languages=c,c++,fortran --with-cpu=cortex-a9 --with-fpu=neon
--with-float=softfp --enable-build-with-cxx : (reconfigured)
/work/sources/gcc-fsf-enable-hot-cold-partitioning/configure
--target=arm-none-linux-gnueabi
--prefix=/work/builds/gcc-fsf-enable-hot-cold-partitioning-arm-none-linux-gnueabi/tools
--with-sysroot=/work/builds/gcc-fsf-enable-hot-cold-partitioning-arm-none-linux-gnueabi/sysroot
--disable-libssp --disable-libgomp --disable-libmudflap
--enable-languages=c,c++,fortran --with-cpu=cortex-a9 --with-fpu=neon
--with-float=softfp --enable-build-with-cxx
Thread model: posix
gcc version 4.8.0 20120821 (experimental) (GCC)
The gcc command line looks like:
./xgcc -B`pwd` -march=armv7-a -mtune=cortex-a9 -mthumb -mfpu=neon
-mvectorize-with-neon-quad -mfloat-abi=softfp
-fprofile-use=.../186.crafty -freorder-blocks-and-partition
-fno-common -fdump-noaddr -O3 -dp -save-temps iterate.c -o iterate.o
Does anyone have any hints as to where I should go looking?
Thanks,
Matt
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
First I am trying to learn and am in no way an expert.
I have searched and searched for a walkthrough on how to compile LKMs for my
pandaboard ES. My target is the pandaboard running Linaro 12.08. I am using
Linaro toolchain binary 12.08. My confusion comes from me not knowing where
the kernel sources are (really how to get them) and the target libraries. I
guess what I expect is the target's rootfs with kernel source to be
somewhere on my Ubuntu Host so I can link to them.
I have tried the following make file configs. But obviously, I don't have
the correct path for KERNDIR as I don't know if it even exists on my host.
And the second make file seems like a native compile.
My previous experience with buildroot:
KERNDIR=/opt/buildroot/build_arm/linux-2.6.20.7/
export CROSS_COMPILE=arm-linux-
export ARCH=arm
obj-m += pwr_led.o
all:
make -C $(KERNDIR) M=$(PWD) modules
clean:
make -C $(KERNDIR) M=$(PWD) clean
Web examples:
obj-m = foo.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
Could you please set my head straight by pointing me to a webpage or briefly
walking through the steps?
Thanks,
Todd
Assaf,
Just to let you know that linaro-toolchain-dev(a)lists.launchpad.net is
a closed list, a better place for this question is
linaro-toolchain(a)lists.linaro.org.
On 3 September 2012 11:41, Assaf Hoffman <hoffman(a)marvell.com> wrote:
> Hi,
>
> Where can I find Linaro toolchain manuals?
The manuals are distributed as *.info files, as per FSF GCC. These
are found in .../share/info/ under wherever you installed your
toolchain.
One way to view these is to run info as follows:
info -f .../share/info/gcc.info
> I’m looking for Linaro supported optimization flag list.
>
> Is it a super set of FSF GCC?
Linaro GCC 4.X supports all the options of FSF GCC 4.X, it may also
support options that were added in later versions of FSF GCC if the
appropriate functionality has been backported. The info files will
document these new options.
Unfortunately, I do not have an easy to read list of these options (if
indeed there are any), so I can't provide you with any further
pointers at the moment.
Thanks,
Matt
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Summary:
* Release Linaro binary toolchain 2012.08
* Start shrink-wrap task
Details:
1. Validate and release Linaro binary toolchain 2012.08.
2. Start shrink-wrap task
https://launchpad.net/gcc-linaro/+spec/shrink-wrapping:
* Learn the background from the mail-list discussion:
http://old.nabble.com/Shrink-wrapping%3A-Introduction-to31220423.html
* Build X86/MIPS trunk toolchain to check the changes.
* Try to apply ARM backend related patches. It can get correct
result for several small cases. But lots of new fails in gcc
make-check. "pop_multiple_with_writeback_and_return" is not handled
correctly.
Plans:
* Continue the shrink-warp work.
Best regards!
-Zhenqiang
(Short week: 4 days, bank holiday)
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== track-kvm-abi-changes ==
* working through design of how we do sync of register state between
QEMU and the kernel and how we handle migration (the two turn out
to be related and I now have a nice looking design that resolves
both of these at once)
* both the interrupt injection ABI and the coprocessor access
ABI are changing (again!)
== other ==
* fixed an embarrassing bug which made qemu-system-arm segfault
on 32 bit hosts; luckily spotted just in time for QEMU 1.2 release
* AFDS (annual review) season again
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
== Progress ==
* Bank Holiday on Monday
* Got symbol_ref split benchmarking going
* Hot/Cold partitioning in PGO:
* https://blueprints.launchpad.net/gcc-linaro/+spec/hot-cold-partitioning-in-…
* Investigated and fixed all compile-time failures in SPEC
* Investigated and fixed a silent code-gen fault in SPEC
== Next Week ==
* Look at symbol_ref split benchmarking results
* Hot/Cold Partitioning:
* Investigate remaining silent code-gen faults and non-termination
issue in SPEC
* If failures are fixed start profiledbootstraps and tests on the
central boards.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== Progress ==
* Validation of my vext patch in big-endian mode proved that proper
support would be non-trivial.
Spent a lot of time writing a self-testing executable test, which
works in both big and little endian modes.
Posted an updated patch which makes no optimization in big-endian.
After discussion with Ramana, I will post a 2nd patch which improves
the testing in big-endian mode.
* In the process, wrote a patch to fix 3 other testcases which used to
fail in big-endian mode.
* Received no answer from the original contributor of bswap16 support patch.
== Next ==
* Have my vext patch accepted on trunk.
* Continue with bswap16 support.
(Short week: 3 days)
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== clean-up-kvm-patches ==
* patches as they stand look good; currently blocked waiting
for changes to go into kernel side
== track-kvm-abi-changes ==
* thinking about some interesting corner cases in accessing
cp15 state via KVM, notably how userspace should get at the
cache ID registers, which are exposed by hardware as a "select"
and "read value of selected register" cp15 register pair.
Consensus seems to be that the kernel should deal with converting
this into a simple interface that userspace can use to just
read all the ID register state at once.
== other ==
* fixed breakage in ARM TCG host support (recent changes had failed
to account for the ABI requirement that 64 bit arguments to functions
must be passed in even-odd register pairs)
* KVM bootwrapper: pushed 64-bit-addresses-in-dtb patch to main repo;
reviewed patch from Guodong Xu adding uInitrd support
KVM blueprint progress tracker:
http://apus.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&…
-- PMM
The Linaro Toolchain Working Group is pleased to announce the 2012.08
release of the Linaro Toolchain Binaries, a pre-built version of
Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2012.08
* Linaro GDB 7.4 2012.06
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
Interesting changes include:
* Enable threaded gold linker in Linux package
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.08
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Summary:
* Identify the root cause of performance regression for the "split2" patch.
* Validate Linaro binary toolchain prerelease.
Details:
1. Identify the root cause of performance regression for the "split2" patch.
* Code alignment is the root cause for the performance regression
(Michael reproduced it with "__attribute__ ((aligned(16)))").
* "build-id" section is the root cause of result difference from
cbuild test (the additional section makes the function address
different).
* Workout a small case to show the impact of code alignment on performance.
2. Linaro binary toolchain 2012.08 prerelease validation. All tests pass.
Absence:
* Annual leave: Aug. 24.
Plans:
* Linaro binary toolchain 2012.08 release.
* Start shink-wrap work.
Best regards!
-Zhenqiang
== Progress ==
* Fixed problems with my patch for "constant vec permute operation for
the vext instruction" blue-print, validated in cbuild.
* Ported it to trunk and submitted for review. R.Earnshaw requested
validation on big-endian. I need to upgrade my qemu to have it
supported.
* Compiled my Neon intrinsics testsuite with LLVM (version 3.2 trunk 160543).
It compiles at O0/O1/O2/O3, but only O0 produces the expected results.
Errors include: vset_lane, vld3, and vld4.
* Started looking a bswap16 support
== Next ==
* Have my "constant vec permute operation for the vext instruction"
patch accepted on trunk
* Continue with bswap16 support.
== Progress ==
* Follow up from 2012.08 Toolchain release
* Updated Wiki pages
* Start working on symbol_ref split benchmarking.
* Backport to PR54212 done upstream to 4.6 and 4.7
* Started picking up Hot/Cold partitioning in PGO blueprint:
* https://blueprints.launchpad.net/gcc-linaro/+spec/hot-cold-partitioning-in-…
* Got SPEC running locally and I think I have reproduced Ramana's failures.
== Next Week ==
* Bank Holiday on Monday
* Investiagte SPEC failures in Hot/Cold PGO
* Get symbol_ref benchmarking going properly
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org