Hello,
I've been following up on the discussion we had on Monday regarding stack
alignment, and noticed that I had mis-remembered the current state of
affairs. Ramana asked me on Tuesday to provide a write-up of the actual
status, so here we go ...
To summarize the background of the problem: on ARM, the incoming stack
pointer is only guaranteed to be aligned to an 8 byte boundary. This means
that objects on the stack (local variables, spill slots, temporaries etc.)
cannot easily be aligned to more than 8 bytes. This can potentially cause
problems in two situations:
1) The object's default alignment (according to its type) is larger than 8
bytes
2) The object has a forced non-default alignment that is larger than 8
bytes
The first situation should in theory never appear, since according to the
ARM ABI all types have a default alignment of at most 8 bytes. However,
due to the current mix-up in GCC, vector types actually are considered to
have a 16-byte alignment requirement in GCC.
The second situation can only appear with local variables that are declared
using attribute ((aligned)).
We had discussed on Monday that we need to fix the second situation, since
this can always occur and is supported on other platforms. By doing so,
we would then automatically fix the first situation as well.
However, this reasoning turns out to be incorrect. There are currently in
GCC *two* completely separate mechanisms that can be used to align objects
on the stack to larger than the ABI guaranteed stack pointer alignment:
A) Re-alignment of the full stack frame. This is what is used by the Intel
back-end (and only the Intel back-end). At function entry, generated code
will align the stack pointer itself to whatever is necessary to fulfil
alignment requirements of all objects on the stack. This may necessitate
follow-on changes: the frame pointer, if there is one, will likewise need
to be aligned at runtime. Also, since incoming stack arguments are now no
longer at a fixed offset relative to the stack pointer *or* frame pointer
in some cases, we might need an extra register as argument pointer. This
method allows extra alignment for *any* object on the stack, but needs
significant back-end support in order to be enabled on any non-Intel
architecture.
B) Dynamic allocation of selected stack variables. This is implemented by
common code with no involvement of the back-end. In effect, the code in
cfgexpand.c:expand_stack_vars that decides on how to allocate local
variables on the stack will remove all variables that require extra
alignment and place them into an extra structure. Generated prologue code
will then in effect dynamically allocate and align that structure on the
stack, and just store a pointer to it as "variable" into the normal stack
frame. All other areas of the frame are unaffected. Since this method
just simulates code the programmer could have written themselves using
alloca, it does not require *any* back-end support and is enabled by
default everywhere. However, it only works for regular local variables,
and not for any other objects on the stack.
Objects on the stack *except* local variables always use default alignment.
Since on most platforms, except Intel and *currently* ARM, the ABI stack
pointer alignment is sufficient to implement default alignments, method B)
as above is able to fulfil all stack alignments. Intel uses method A), so
they're also OK. In effect, it's only ARM due to the vector type
alignment problem that runs into the situation that neither method works.
Under those circumstances, given that:
- we want to fix vector type alignment in order to become ABI compliant
- once we've fixed this, we're in the same situation as other platforms and
method B) already fixes stack alignment problems
- implementing method A) is therefore both quite involved *and* actually
superfluous
I'd now rather recommend that we *don't* try to implement method A) (full
stack-frame re-alignment) on ARM.
Comments?
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
GDB for Android:
* Continued conversation about .note.ABI-tag.
* Committed upsream the second of three patches for building
gdbserver on Android.
* Continued working on a crtbrand.c for bionic.
2012.04 release:
* Tested the gdb-linaro/7.4 branch on armv5tel, x86 and x86_64, both
natively and remotely. Compared results against the 2012.02 release.
* Ran the release process, made the release.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi,
GDB for Android:
* Investigated .note.ABI-tag generation in glibc and FreeBSD.
Wrote crtbrand.c for bionic based on FreeBSD's crtbrand.c.
Tried to integrate it with bionic's build system.
* Contacted Google engineers about adding .note.ABI-tag to Android
binaries.
2012.04 release:
* Started working on the release. Applied the latest patches from
the FSF 7.4 branch to gdb-linaro/7.4 and also my patches to compile
gdbserver with the Android toolchain.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
* Linaro GCC
Spun release tarballs for Linaro GCC 4.6 and 4.7. Pushed them to
Michael's servers and launched the testing.
Continued trying to get the 64-bit NEON stuff to work. The negdi2 patch
needed some reworking following upstream review, and the extend patch
has mysteriously reintroduced a performance regression when the
operation is done in core-registers, which needs to be solved, but the
other patches seem ok at the moment, although the shift stuff is blocked
on benchmarking.
I've begun looking at how my changes affect spec2000, and whether the
register allocation could be done better. Unfortunately, given that the
test systems are currently giving spec results with a low level of
consistency (and therefore confidence), this has mostly been by visual
inspection, so far.
* Other
Public Holiday on Monday.
I have a cross toolchain I configured with "--with-arch=armv7-a --with-cpu=cortex-a9 --with-tune=cortex-a9" and I want the linker to emit armv4t compatible thumb interworking, but I can't seem to get it to.
I noticed that if I create a armv4t toolchain with "--with-arch=armv4t --with-cpu=arm7tdmi --with-tune=arm7tdmi" and then I pass "--use-blx" to the linker it will emit armv7 thumb interworking. There doesn't seem to be any inverse "--no-use-blx" type switch though. Is this a bug/limitation of the linker or am I misunderstanding something?
-Allen
nvpublic
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-04-10 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* completed last of the register conversions, started on the final
check-through and polish before it goes out to the mailing list
* implemented changes following review of the clean-up-reset patchset
== other ==
* qemu-linaro 2012.04 final testing (confirming an audio issue on
the vexpress model LP:977610 wasn't a regresion) and release
* patch review: pl330 dma controller model
* patch review: samsung's sd card model overhaul
* minor patch: fix compile failure on bsd
* minor patch: fix failure to reset timer on a9 mptimer reset
* minor patch: diagnose attempts to use python3 at configure time
* sent arm-devs.next pullreq
* put together a bug report in the form of a youtube video (!) as
requested by the gmail folks
-- PMM
== GCC ==
* Committed fix for LP #968766 (PR tree-optimization/52880)
to FSF mainline and Linaro GCC 4.6 and 4.7.
* Created merge reqest to fix LP #972648 for Linaro GCC 4.6
by backporting mainline patch; pending approval.
* Updated patch to use vld1.64/vst1.64 instead of vldm/vstm
for vector moves. Testing detected problems in GCC core
memory alignment logic (GCC assumes vector types are
naturally aligned, which contradicts ARM ABI and ARM
back-end assumptions). Started discussion on possible
fixes.
* Updated and retested patch to use vld1/vst1 to implement
vec_set/vec_extract for cases where the scalar operand
resides in memory.
* Ongoing work on fixing LP #959242.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro GDB 7.4 2012.04.
Linaro GDB 7.4 2012.04 is the second release in the 7.4 series. Based
off
the latest GDB 7.4, it includes a number of ARM-focused bug fixes and
enhancements.
Interesting changes include:
* gdbserver can now be compiled with Android's toolchain.
* Additional fixes from the GDB 7.4 branch, one of them being
that it doesn't require makeinfo to build anymore.
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.4-2012.04
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro QEMU 2012.04.
Linaro QEMU 2012.04 is the latest monthly release of qemu-linaro. Based
off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
New in this month's release:
- ppoll syscall now supported in ARM linux-user mode
- the SETEND instruction in the Thumb encoding now UNDEFs to
match behaviour for the ARM encoding
- the OMAP36xx UART FIFO status registers are now implemented
(thanks to Jan Vesely)
Known issues:
- Graphics do not work for OMAP3 based models (beagle, overo)
with 11.10 Linaro images.
- Audio may not work on Versatile Express models with the latest
Linaro kernel/hardware packs (LP:977610).
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2012.03
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The Linaro Toolchain Working Group is pleased to announce the 2012.04
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2012.04 is the first release in the 4.7 series. Based
off the latest GCC 4.7.0+svn186061 release, it includes performance
improvements especially around 64 bit operations.
Interesting changes include:
* Our first 4.7 based release
* Updates to GCC 4.7.0+svn186061
* Better use of 16 bit Thumb-2 instructions for smaller code size
* Implements 64 bit ones complement in NEON
* Adds support for the ARMv6 saturation instructions
* Backports the NEON lexer improvements for faster compilation
* Backports the 64 bit multiply, divide, and mod improvements
Fixes:
* LP: #960283 slp pass assert when compiler configure with --enable-checking
Linaro GCC 4.6 2012.04 is the fourteenth release in the 4.6 series.
Based off the latest GCC 4.6.3+svn186060 release, this is the first
release after entering maintenance.
Interesting changes include:
* Updates to 4.6.3+svn186060
Fixes:
* LP: #960283 slp pass assert when compiler configure with --enable-checking
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.7-2012.04https://launchpad.net/gcc-linaro/+milestone/4.6-2012.04
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.7/4.7-2012.04
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
-- Michael
All,
In the below code, I tried few compiler options and got following observations:
1) arm-linux-gnueabi-gcc -O2 -mcpu=cortex-a15 -mfpu=neon -ftree-vectorizer-verbose=6 -ftree-vectorize
Compiler throws following info messages:
foo.c:16: note: not vectorized: unsupported use in stmt.
foo.c:16: note: not vectorized: unsupported use in stmt.
foo.c:18: note: not vectorized: unsupported use in stmt.
foo.c:18: note: not vectorized: unsupported use in stmt.
2) -O2 -mcpu=cortex-a15 -mfpu=neon
None of the generated code contains the NEON instructions. Code generated with case 1 is taking 3000 cycles, and code generated by option 2 is taking 2500 cycles.
Even if vectorization failed in case1, it should not generate more inefficient code than case 2. My belief was that the executables from both would take same cycles, any thing done for doing unsuccessful vectorization must be reverted if it did not succeed.
###################################################################
#define SIZE1 20
#define SIZE2 26
unsigned int array[SIZE1][SIZE2];
void foo()
{
unsigned int i,j;
unsigned int max = 0;
for(i = 0; i < SIZE1; i++)
{
for(j = 0; j < SIZE2; j++)
{
if (array[i][j] > max)
{
max = array[i][j];
index = j;
}
}
}
printf("Max value: %u Index: %u\n", max, index);
}
Regards
RKS
Hi there. The 2012.04 toolchain release is this week.
Ulrich, I see your fix for LP: #968766 has been approved upstream. In
theory it's too late but I'm happy to land it if you are. Could you
decide and let Andrew know by the middle of Tuesday? Andrew, if you
don't hear from Ulrich then spin away.
Andrew, could you run the release process on Tuesday please? There's
one extra step this month: once you've uploaded and spawned the job,
go to the scheduler screen and click on 'Release' beside each of the
ursas. I reserved them to make sure they'd be idle and ready to pick
up the release build when ready.
Thiago, let us know if Ulrich or I can lend a hand with the GDB release.
-- Michael
Hi there,
At the last call Michael asked if we could push this call back by 30
minutes given the changes due to daylight savings. Does anyone have
any objections to a new time of 10 a.m. BST - 11 a.m. Central
European - 9 p.m. New Zealand. ?
cheers
Ramana
* GCC
Identified the latent bug that's upset my NEON-shifts testing. It turns
out the define-insn-and-shift patterns in arm/sync.md have no length
attributes set.
Now that the NEON 64-bit shifts appear to be not broken, I've relaunched
the 64-bit extend testing.
Identified the problem with my NEON-64-bit-negate patch: I already knew
it works better (produces more optimal code) with my NEON-immediates
patch, but it turns out that at -O0 the other patch is a hard
requirement or else bad things happen in output_move_vfp.
Backported Ramana's patch for ARM-mode testing of my recent Thumb 64-bit
test cases. I've applied it to Linaro GCC directly, without a merge
proposal, as it's a very low-risk patch.
Caught up with some launchpad blueprint fiddling.
Completed the merges from 4.6 and 4.7 FSF. The 4.7 merge was tricky as
it required working around a BZR bug; I've posted the workaround to the
toolchain list.
* Other
On leave on Tuesday
Public holiday on Friday.
Attached a copy of the ARM Linux ABI document to KBentry 39 so we're
hosting it somewhere, at least. Posted an internal Mentor/CS question
about getting its old home restored, and getting a relicensed edition to
allow others to use it as the basis for a hard-float equivalent.
=== Progress ===
* Worked on VFP addressing patch and corrected the failures.
* Got SPEC2k up and running with hot cold partitioning. Some SEGVs
that need investigation. In
general results appear to be better in quite a few cases.
* Investigated an issue with a merge request for upstream 4.7 branch
into our tree. There was a testsuite
failure and I wasn't able to reproduce it with a local i386 rebuild of
the toolchain. Therefore we'll have to
let this go in.
== Plans ==
* I will be away for 2 days this week attending the LLVM conference in London.
* Pursue backporting gnu_unique_object upstream.
* Finish off the VFP addressing modes patch upstream.
* Look at some of the existing blueprints and start discussions around
prioritizing this.
* Investigate some of the SEGVs with h-c partitioning.
Absences.
* Apr 12-13 : Euro-LLVM London.
* Linaro Connect Q2.12 - May 28 - June 1 -
Summary:
* Revise the patch for relocatable NLS support.
* Code size benchmark analysis.
Details:
1. Revise the patch for relocatable NLS support: lp:918926.
* Read the gcc configure and makefile.
* It seams hard to get the relative dir if the gcc is configured
with --bindir=... --datadir/datarootdir. E.g.
--bindir=/opt/bin
--datarootdir=/tmp/data
2. Code size benchmark analysis with -Os
* Investigate regression in small cases.
3. Try to build linaro gcc trunk with crosstool-ng. But it reports
error when configuring libquadmath.
* configure:9829: error: Link tests are not allowed after GCC_NO_EXECUTABLES.
* Manual check or a simple case show libc.so can be linked.
Plans:
* Tuning optimization heuristics for -Os
Planed leaves:
* April 9 - 11: Vacations
Best regards!
-Zhenqiang
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-04-10 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== other ==
* LP:970252 got a beagle board booting so I could read the UART
version register; reviewed and applied to qemu-linaro the set
of patches provided by Jan Vesely (thanks!)
* sent a patchset cleaning up the GIC model so it is a self-contained
sysbus device; this should make it easier to just drop in a
functionally equivalent device which is a shim for an in-kernel
GIC model that uses the hardware VGIC features
* upstream review:
save/load support for sd.c [patchset from Samsung]
SPI bus [patchset from Petalogix]
* put together qemu-linaro prerelease tarball and did some testing
* performance evaluation finished and submitted
Continued work on neon 64-bit correctness. This is really dragging out
now. I had hoped to have had it fixed by now, but subtle bugs are subtle.
The 16-bit opcodes patch is now committed both upstream and in Linaro
GCC 4.7, however, so that's some progress at least.
Posted benchmark results for the the 64-bit shifts in core registers.
The results are inconclusive: the benchmark runs are too noisy.
As part of closing out the Windows toolchain card, I've documented the
binary build release process at:
https://wiki.linaro.org/WorkingGroups/ToolChain/BinaryBuild/ReleaseProcess
The interesting thing is a script that pulls builds from S3 and posts
them to Launchpad. There's a curl command at the end that does the
upload and might be useful.
-- Michael
On 1 April 2012 05:56, Ramana Radhakrishnan
<ramana.radhakrishnan(a)linaro.org> wrote:
> I find it a bit worrying that all the nptl tests are failing with a
> common error message
>
> http://builds.linaro.org/toolchain/eglibc-2.16~svn17843
>
> Aborted'
> make[6]: *** [/scratch/cbuild/slave/slaves/tcpanda05/eglibc-2.16~svn17843/eglibc/default/build/nptl/tst-cond7.out]
> Error 1
> libgcc_s.so.1 must be installed for pthread_cancel to work
> Didn't expect signal from child: got `Aborted'
>
> Why don't we have libgcc_s.so.1 installed on the system - shouldn't
> that be there if there was a gcc properly installed on the system ?
This is a bug on my side. I believe EGLIBC likes to have libgcc_s.so
in the top of the build directory - at least that's the impression I
got from reading the cross-test documentation the other day.
I've logged LP: #971064 and will look into it.
-- Michael
Hi Ricardo, Matthias. GCC 4.7 is almost here and it's likely that
Linaro GCC 4.7 will come out for next month's 2012.04 milestone.
For the binary toolchain to work we need the 4.7 runtime libraries on
the target. Matthias, what are your plans? How much of 4.7 is
packaged so far? Ricardo, could we pull these updates to libgcc,
libstdc++, and others into the LEB?
These should be backwards compatible but there's always a risk. Using
the 4.5 runtime with a 4.4 compiler back on Maverick was OK.
-- Michaele
Hi,
GDB for Android:
* Submitted upstream three patches for building gdbserver on Android.
Reworked two of them based on review comments, and committed one.
* Investigated ARM EABI build attributes and .note.ABI-tag as ways
of marking binaries as Android apps so that GDB can differentiate
them from regular Linux ARM binaries. Build attributes are quite
sophisticate and overkill for this purpose, and would also be out
of place for Android on x86. .note.ABI-tag is simpler and more
appropriate. Now experimenting with generating the .note.ABI-tag
section on Android binaries.
* Tried to find ARM GNU/Linux ABI supplement [1] but couldn't,
contacted Mentor Graphics' webmaster about the problem. No
response so far.
Obs: This Friday (04/06) will be a holiday in Brazil and hopefully I
will be AFK.
[1] http://www.codesourcery.com/gnu_toolchains/arm/arm_gnu_linux_abi.pdf
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
== GCC ==
* Committed fix for LP #960283 (PR tree-optimization/52686) to
FSF mainline as well as Linaro GCC 4.6 and 4.7.
* Worked on patch to use vld1.64/vst1.64 instead of vldm/vstm
for vector moves. Created merge request for testing.
* Worked on patch to use vld1/vst1 to implement vec_set/vec_extract
for cases where the scalar operand resides in memory.
Created merge request for testing.
* Ongoing work on fixing LP #959242.
* Ongoing work on improving end-of-loop value computation.
== Misc ==
* I'll be attending the Linux Foundation Collaboration Summit
in San Francisco next week, and present on "GDB on ARM".
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Summary:
* Linaro binary toolchain 2012.03 release.
* Investigate relocatable NLS support.
* Code size benchmark analysis.
Details:
1. Linaro binary toolchain 2012.03 release.
* Bump and spawn 2012.02-20120326 build.
* Validate the release candidate.
* Update wiki for binary build tasks.
2. Investigate relocatable NLS support: lp:918926.
* Root cause: gcc and binutils use a fixed LOCALEDIR (which is
$prefix/share/locale) to call bindtextdomain.
* Workout a reference patch for gcc to use relative dir
(.../bin/../share/locale) to call bindtextdomain.
3. Code size benchmark analysis with -Os
* Collect code size benchmark data.
* In most cases, gcc 4.7 gets better result than gcc 4.6.
* Investigate regression in several small cases.
4. Read the tree and rtl dump files to learn the optimizations and
impacts on code size.
Plans:
* Fix lp:918926.
* Investigate code size regression in gcc 4.7.
* Tuning optimization heuristics for -Os.
Planed leaves:
* April 2 - 4: Chinese Qingming Festival.
* April 9 - 11: Vacations
Best regards!
-Zhenqiang
=== Progress ===
* Caught up on email backlog.
* Reworked the ARM backend specific bits of the VFP addressing modes
patch and submitted again for some benchmarking and testing. Finished
the PRE_MODIFY and POST_MODIFY bits of that as well.
* Wrote up a small blueprint on the shrink-wrapping work.
* Wrote up my Linaro performance review and sent it for review.
* Looked at lower-subreg work that Kenneth Zadeck posted very quickly
to see if it addressed some of the issues around and old intrinsics
patch that Richard Sandiford submitted last year. It looks promising
and might even have some impact on our 64 bit neon work . It fixes the
2 cases where things didn't look good. ( Upstream bug reports PR48941
and PR51980) but it falls over while building glibc. Sent a bug report
to Kenneth about this.
* The perf packages on OMAP4 in our latest releases from 12.03 are
just broken, they don't work. Reported the issue to Paul Larson on IRC
to check what's going on. perf top doesn't work reliably on the
kernels and there appears to be some issues with interrupt support for
some of these . I specifically ran into
https://bugs.launchpad.net/ubuntu/+source/linux-ti-omap4/+bug/956693 .
* Answered a few questions from Uli about my prototypes for the vld1
replacing vldm instructions and a vget_lane patch.
== Plans ==
* Work through some of the blueprints before the call next week.
* Set up perf on my panda. It works on my AC100 - so the inclination
was to also have something that worked on my panda but clearly it
doesn't.
* Finish off the VFP addressing modes patch and get it in.
* Look at Partial Partial PRE next or attempt the next project.
Absences.
* Apr 12-13 : Euro-LLVM London.
* 1 week holiday sometime before that - to be booked
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-04-10 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* posted 14-patch patchset which creates a QOM class per CPU type
and moves a lot of the reset/constant-feature-register setup to
the init functions for these new classes. This is then a much
nicer base to sit cp15 rework on.
* solved the final design knot of how to handle registers whose reset
value depends on the CPU type (the QOM patches make this much more
straightforward)
== other ==
* upstream patch review
* updated Paul Brook's BE8 userspace support patch and sent out a v2
* ran through qemu-linaro buglist identifying fixes to go into next
release
* linaro performance review ate up a lot of time this week and
will probably do so next week too :-(
I've changed the development focus in the Launchpad project to Linaro
GCC 4.7. This means that:
* Checking out lp:gcc-linaro now gives you the 4.7 branch
* New merge requests are targeted to 4.7 by default
This doesn't affect any already checked out branches or pending merge requests.
-- Michael
Hi,
GDB for Android:
* Wrote three patches for the build system allowing gdbserver
to be cross-compiled on Android [which were submitted upstream
this Monday].
* Started studying the ARM EABI to work on a way to mark a binary
as an Android application as opposed to a regular Linux EABI one.
* Wrote self-evaluation for Linaro performance review.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
The PandaBoard auto builders are having a hard time keeping with
longer build and test times of 4.7 and the re-enabled libstdc++ tests.
For reference, here's how much each step costs:
Bootstrap GCC with C, C++, Fortran, and Obj-C: 9 hours
Test GCC: 9.5 hours
Test libstdc++: 4.4 hours
Test libgomp: 0.9 hours
Other tests: 0.2 hours
for a grand total of 23.8 hours. Every new commit gives a merge
request and trunk build for both A9 and ARMv5 giving 95 hours of
compute time. GCC 4.6 takes five hours to build and 5.5 to test.
This is just a FYI. I'll think about ways of speeding things up or
adding capacity. An i.MX6 with 2 GB of RAM and SATA would be nice...
-- Michael
Hi Michael,
I'm seeing what looks like bogus testsuite failures again:
https://code.launchpad.net/~uweigand/gcc-linaro/lp-960283-4.7/+merge/99069
I suspect this is still caused by the .ident version string, which now
appears to be:
[gcc-linaro/~uweigand revision 114974]
While it no longer contains the branch name, it still contains my user
name, which happens to include the string "and" ...
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
== Progress ===
* Off sick for 4 days last week.
* Looked at the results for the vfp writeback modes and caught up with
some analysis on the one day I did work.
=== Plans ===
* Catch up on email after absences.
* Catch up on patches backlog
Absences.
* Apr 12-13 : Euro-LLVM London.
* 1 week holiday sometime before that - to be booked
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
---
* Linaro GCC
Applied my ARM conditional-execution and thumb 16-bit instruction size
optimization patch to upstream and Linaro 4.7.
Continued work on (slowly) working the bugs out of my 64-bit NEON
patches. Figuring out bootstrap failures is not easy! Eventually
discovered that:
* the NEON shifts patch was broken because combine was using the
patterns in ways they weren't intended.
* the NEON neg patch was broken because it needed an early-clobber
marker on the scratch register.
I've also reworked the use of insn_enabled to make it a little less
clunky. It's just an aesthetic change though.
If all goes well with my weekend bootstrap builds I should have the
patches reposted next week.
* Other
Richard Earnshaw asked me to bless use of a CS patch submitted to
gcc-patches@ by a third party. I dug out the original patch from the CS
archives and posted that to the message thread.
Summary:
* Validation for embedded toolchain 2012q1 update release and Linaro
binary toolchain 2012.03 release.
* Failed case analysis for -Os.
* Read benchmark code
Details:
1. Validation for embedded toolchain 2012q1 update release and Linaro
binary toolchain 2012.03 release.
2. Root cause the new failed cased pr30951.c with -Os.
In function tree_swap_operands_p (fold-const.c), there is a check
if (optimize_function_for_size_p (cfun))
return 0;
which blocks to swap (x != x + 10) to (x + 10 != x). And the
following optimization can only handle (x + 10 != x).
3. Read some benchmark codes to find the opportunities for code size
optimization.
Plans:
* Finalize Linaro binary toolchain 2012.03 release.
* Read benchmark codes.
Best regards!
-Zhenqiang
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-03-30 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* more progress, mostly in figuring out how to connect the cp15 patches
with work by Andreas Färber to convert CPUs to QEMU's new object model.
* Patch series is now 36 patches long... (will probably split into two
parts for submission)
== other ==
* upstream patch review
* linaro performance review time again...
-- PMM
== GCC ==
* Posted second part of fwprop-subreg patch to gcc-patches.
* Investigated LP #960283, determined root cause, created patch,
and opened merge requests against Linaro GCC 4.6 and 4.7.
Opened mainline bugzilla PR tree-optimization/52686.
* Investigated LP #960274 and LP #960817, identified both as
duplicates of LP #960283.
* Investigated LP #959242, determined root cause. Ongoing
investigation of possible fixes.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The draft agenda for Monday's call is at:
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-03-26
and is:
* Review action items from last meeting
* Validation lab move is delayed
* Daylight savings changes done
* KVM
* Blueprints are (half) spawned
* Rusty away prep
* Other business
* multiarch
* [[MichaelHope/Sandbox/MultiarchNotes]]
* Want to get upstream(s)
* Richard's thoughts
* Interaction with multilib
* Reducing the number of builds
* 4.7 status
* Import/merge working?
* Keep an eye out for other improvements/regressions
Feel free to edit!
-- Michael
Konstantinos, Loïc, and I talked last night about multiarch. Linaro
want multiarch and will use it in all our products and hence need to
get it upstream. There's another meeting in a week to figure out
what's next.
I've written a page on the uses, issues, and history at:
https://wiki.linaro.org/MichaelHope/Sandbox/MultiarchNotes
Please edit and add and correct things. The page isn't Linaro's
position but we need to have answers for the arguments.
I see no particular blockers especially if we separate the concerns.
-- Michael
I've added a new job called 'porter' which reserves the first tcpanda
that comes free. This can be used to reproduce a bug or benchmark
result against an existing binary build.
For example, say you want to see if a fault exists on recent trunk:
* Go to http://ex.seabright.co.nz/helpers/buildlog/gcc-4.8
* See the last successful ARM build was gcc-4.8~svn185503
* Go to http://ex.seabright.co.nz/helpers/scheduler/spawn
* Spawn a job called 'porter' into the a9-builder queue
* Keep polling http://ex.seabright.co.nz/helpers/scheduler until a
board shows as 'porter/ready'
* Log into the board using ssh cbuild(a)board.v
* Change to /scratch/cbuild/slave/slaves
* rsync the binary across using rsync
control:~/cbuild/build/gcc-4.8~svn185503/gcc-*cortexa9*xz .
* Extract the binary and have at it
The board will drop back into the queue after 48 hours. You can
release it early by doing a 'killall sleep'. Please do any work under
/scratch/cbuild/slave/slaves as this is automatically deleted when the
next job starts.
Zhenqiang, could you add this to the jobs page please?
-- Michael
I've create a blueprint covering the basic functions in libav that are
implemented as inline assembly:
https://blueprints.launchpad.net/gcc-linaro/+spec/investigate-libav-inline-…
These are a mix of multiplies, clipping, byte swap, and unaligned
access. We do OK on half of them but at least byte swap and 32x32 ->
top half of 64 aren't as good as they could be.
Let's discuss the investigation at the next performance meeting.
-- Michael
Hi,
Linaro bugs:
- #926472: Native gdb can't know multithreads of Android processes
Tried to reproduce but couldn't do a GDB build similar to
the bug reporter's. Found a workaround for him anyway.
- #942529: gdb failed to debug application (gdb reports about
internal error)
Reproduced the bug and found out it's fixed in GDB 7.4. It's a bug
in Ubuntu GDB not Linaro, so reassigned to the Ubuntu project.
Linaro GDB is already at version 7.4 so we're good.
- #954714: dropped patch reintroduces gcore relro backtrace problem
Reviewed the proposed patch. It's good.
GDB for Android:
- Started creating patches for build problems when trying to compile
gdbserver for Android. Will have patches to submit in the next
few days.
- Studied libthread_db.c to see what's special about it that it has
to be statically linked. Didn't find anything and indeed Android's
own libthread_db.so works fine. Didn't get an answer yet when
I asked about it on the Android mailing list.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
==Progress===
* Did some work to improve code generation for addressing modes in VFP
registers.
* Looked at some more cases and detected that there are 2 areas of
improvement for
the future
* shrink-wrapping
* Too many unnecessary ldm / stm stacking for cases with small
structures being
passed .
* Committed configure.ac changes.
* Committed MALLOC_ABI_ALIGNMENT changes.
* Looked at some upstream testsuite failures. There are about 54 too
many test failures in vect.exp that
need to be looked at at some point.
=== Plans ===
* Push vfp wb patches upstream.
* Resurrect partial-partial PRE
Absences.
* 1 week holiday sometime before that - to be booked
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
I've created blueprints for the libav missed optimisations and added
references to Ramana's page at:
https://wiki.linaro.org/RamanaRadhakrishnan/Sandbox/RRQ112ConnectLibavgcc46…
Those that are new and in progress I've assigned to the relevant
person. Ulrich, I couldn't find a end of loop counter blueprint so I
created a new one.
-- Michael
This is the first announcement on upcoming changes to the supported
Linaro GCC versions.
GCC 4.7 is expected out in the next two weeks. We plan to switch to
4.7 for the Linaro GCC 2012.04 release and, as part of that, will put
Linaro GCC 4.6 into maintenance and retire Linaro GCC 4.5. While in
maintenance we will continue to update, fix bugs, and do releases on
4.6. No further changes or releases will be made to 4.5. All
historical releases and branches will stay available.
For more informatio, please see the flyer at:
https://wiki.linaro.org/WorkingGroups/ToolChain/Flyer
especially the section on Lifecycle:
https://wiki.linaro.org/WorkingGroups/ToolChain/Flyer#Lifecycle
The formal change notes will be sent after the 2012.04 release.
-- Michael
Hi,
OpenEmbedded:
* rebased against current OE-core
* my patch that introduces an image fs alignment is now upstream
* noticed that the newly introduced bdwgc recipe (the Hans Boehm
Garbage collector which is needed by guile) uses a version of libatomic
that fails when building in Thumb mode
* has been fixed upstream already
* pulseaudio/libatomics-ops_1.2.bb has the same issue and just sets
ARM_INSTRUCTION_SET to "arm" (probably until a new version gets pulled in)
* we can use the same workaround till then
* found a bug in the recipe for the Linaro external binary toolchain
where some header files are placed into a wrong directory during the
install step
* which prevents python from being built
* now fixed
Please note that I'll be on vacation till 04/13/2012.
Regards,
Ken
Hi Ken. I've made a meta-linaro project on Launchpad and created the
near term blueprints. See:
https://blueprints.launchpad.net/meta-linaro
You're almost done with the initial layer work. Next is scripting up
the build and integrating with LAVA followed by turning on the build
for other architectures.
I've dropped the build in the cloud investigation. Let's use
tcserver01 as it works and is fast enough. Keep an eye on the
validation lab cloud the Validation guys are talking about - we might
shift there later.
I've sent the draft card to Loïc who will massage the text and get it
on the TSC agenda. The current blueprints focus on toolchain
validation and come to a hard stop past there. Once we have TSC
approval we can go further and talk with the Platforms guys about who
does what.
-- Michael
The Validation lab is shifting to a new location this week so I've
started a graceful shutdown of the tcpanda boards. Merge requests
will continue to queue and run on x86 but will back up until the lab
comes online at the end of this week. If the backlog gets too big
then I'll re-enable an ursa board or two.
Please work as normal but expect the builds results to take longer to
come through.
-- Michael
Hi there. Over the next three months both GCC 4.7 and Ubuntu 12.04
'Precise' are coming out. We'll switch over to these pretty quickly
which will affect our internal testing and anyone using the binary
toolchain.
The changeover plan including dates, details of what's happening, and
backwards compatibility is at:
https://wiki.linaro.org/MichaelHope/Sandbox/BinariesMigration
Comments and concerns are welcome,
-- Michael
* Linaro GCC
Spun release tarballs for Linaro GCC 4.5 and 4.6. Launched the build and
test runs. When those completed, briefly checked the results, and
launched the package build tests and benchmark runs.
Continued trying to figure out how my NEON 64-bit immediates patch had
caused a bootstrap failure. The problem turned out to be an assembler
bug ([1]). I've adjusted my patch to work around the problem. This is
the only real way to do it given that, even if I fixed the assembler
right away, there'll be broken assemblers knocking around for some time
to come. The compiler now bootstraps correctly in a manual build. I've
submitted it for testing on Michael's systems, so hopefully this patch
will be ready to post back upstream soonish.
Continued trying to figure out the neon shifts bootstrap failure. I ran
a cross-compiler test suite run, but didn't witness any obvious
problems. Launched a manual bootstrap to reproduce the problem (once the
board because available after testing the immediates patch), so I should
have something to work with next week.
Attempted to merge lp:gcc/4.7 to lp:gcc-linaro/4.7, but got a bzr error.
I asked for help on #bzr, and 'jelmer' is looking into it. Apparently
the history didn't import in quite the same way as lp:gcc/trunk, or
something.
Helped Dmitry Antipov with a relocation (possible) bug.
* Other
Two days leave (Thursday and Friday).
Booked flights and hotels to Hong Kong for Linaro Connect Q2.12
[1] http://sourceware.org/bugzilla/show_bug.cgi?id=13843
Summary:
* Linaro binary toolchain 2012.03 release.
* Make multilib and multiarch work together.
* Failed case analysis for -Os.
Details:
1. Handover Asa's linaro day-to-day jobs (check auto build health,
proposals health and ticket triage)
2. Linaro binary toolchain 2012.03 release.
* Update config to 2012.03
* Fix lp:939008 and patch for lp:939143
3. Multilib/multiarch investigation for linaro toolchain.
* Update the logic in set_multilib_dir to set multiarch_dir when it
matches the format (.:.:$(MULTIARCH_DIRNAME)). Now multilib and
multiarch can work together. A reference build to support
marm/march=armv5t is at http://people.linaro.org/~zhenqiangchen/
* Try to build -mfoat-abi=hard/-fpu=neon. But libgcc build fails
with message "ld: error ... uses VFP register arguments, ..."
4. Investigate new failed cases in -Os regression test.
* For gcc.dg/pr30951.c, both option -O0 and -O2 can optimize (x ==
x + 10) to (0). But -Os can not.
* For gcc.dg/atomic-lockfree.c and gcc.dg/atomic-noinline.c, the
optimization is correct. The test cases can only be test with -O0.
Plans:
* Code size benchmark tuning.
Best regards!
-Zhenqiang
Hi!
* V8 - SunSpider
The pieces for building in cbuild and parsing with the
linaro-toolchain-benchmark scripts are in place. Ran the SunSpider
benchmark across a few toolchains with the o2-neon and o3-neon variants.
I have documented my work on this page, but not analyzed the results yet.
https://wiki.linaro.org/AsaSandahl/Sandbox/JavaScriptBenchmark
What worries me is that there is too much variation in some of the test
results. Probably caused by the garbage collection kicking in at
unpredictable times. I will try to monitor the gc and investigate if it can
be controlled somehow.
I would like to do a gcc-4.4 run as well. Android's original toolchain is
based on gcc-4.4.3(?) and that is what I compared against when doing
measurements internally.
However, I have problem compiling C++ with gcc-4.4 - it is this one again:
home/asa-san/cbuild/slaves/ursa3/gcc-4.4.5/gcc-binary/bin/../libexec/gcc/armv7l-unknown-linux-gnueabi/4.4.5/cc1plus:
/home/asa-san/cbuild/slaves/ursa3/gcc-4.4.5/gcc-binary/lib/libstdc++.so.6:
version `GLIBCXX_3.4.14' not found (required by /usr/lib/libppl.so.7)
* Handed over daily tasks to Zhenqiang.
Regards
Åsa
Hi,
OpenEmbedded:
* verified that the release candidate of our 2012.03 toolchain
(both source and binary) is able to build the sato and qt4e images of
oe-core+meta-linaro - they are booting fine using QEMU
* out sick starting from Tue :/
Regards,
Ken
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-03-30 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* converted crn=1; still TODO: crn=0, some loose ends; then reassess
the design in the light of experience doing register conversion
* I've estimated another two weeks here but this might be out, because
in practice much of my time is sucked up by 'other' issues
== other ==
* tracked down cause of LP:947888 gpg crash bug: newer glibc use
/proc/self/maps to decide whether a printf format string using '%n'
is in writable memory, and qemu's maps emulation wasn't good enough
* fixed a thumb decoder bug where we were treating 'setend' like 'cps'
* investigated whether we had any conveniently testable cores which take
advantage of the ARM ARM latitude for UNDEFfing even on failed condition
code checks (answer, not really but the KVM code to handle this case
should be small enough not to worry about its not-yet-tested nature)
* qemu-linaro 2012.03 release (lots of bug fixes, plus exynos4 and
highbank models thanks to Samsung and Calxeda)
* code review: imx31 board patches
* rebased qemu-linaro on upstream and applied some new patches from
Christoffer for ARM KVM support
* LP:956799: added ppoll to QEMU arm-linux-user (a one liner...)
* boot-wrapper: moved initrd load address up so we can handle large
kernels (like Android!)
* sent pullreqs for target-arm, arm-devs patchqueues
== GCC ==
* Checked first part of fwprop-subreg patch into mainline.
* Checked Ira's vectorizer patches into mainline.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The final version of the 'Building at -O3' writeup is at:
https://wiki.linaro.org/Internal/ToolChain/BuildingAtO3
This updates the SPEC 2000 results to show that there is a net win
which is held back by a bad (but understood) regression in one
benchmark.
Thank you all for your work on this,
-- Michael
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro QEMU 2012.03.
Linaro QEMU 2012.03 is the latest monthly release of qemu-linaro. Based
off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
Highlights in this month's release:
- we now default to enabling 'reserve memory for guest' on 64 bit hosts
in linux-user-mode. This significantly reduces the chances of QEMU
being unable to satisfy a guest process mmap() request.
- Fix for a bug that was causing spurious failures of the glibc check
for "%n in a format string must be in a read-only area of memory"
when running in linux-user-mode.
- QEMU's built-in boot loader now supports passing a device tree blob
to the kernel: if you boot with -kernel mykernel (and optionally
-initrd myinitrd) you can now also use the new command line option
-dtb my.dtb to pass a device tree.
- This version includes an initial implementation of a model of the
Samsung Exynos4210 SoC, used by board models 'nuri' and 'smdkc210'
(thanks to Evgeny Voevodin, Maksim Kozlov, Igor Mitsyanko and
Dmitry Solodkiy from Samsung, who submitted this work to upstream
QEMU).
- This version includes an initial implementation of a model of the
Calxeda Highbank SoC, used by board model 'highbank' (thanks to Rob
Herring and Mark Langsdorf of Calxeda, who submitted this work to
upstream QEMU).
- various other minor bug fixes (detailed in the Changelog.LINARO).
Known issues:
- Graphics do not work for OMAP3 based models (beagle, overo)
with 11.10 Linaro images.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2012.03
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The GCC release tested up just fine. The branch is now open for commits.
The next release is Thursday the 12th of April. Note that this is the
week after Easter.
-- Michael
The Linaro Toolchain Working Group is pleased to announce the 2012.03
release of both Linaro GCC 4.6 and Linaro GCC 4.5.
Linaro GCC 4.6 2012.03 is the thirteenth release in the 4.6 series. Based
off the latest GCC 4.6.3 release, it contains a new scheduler pressure pass,
implements new instructions, and contains a number of bug fixes.
Interesting changes include:
* Updates to 4.6.3.
* Better performance by accounting for register pressure when
scheduling instructions.
* Support for the ARMv6 USAT/SSAT saturation instructions.
* Support for the VFP VCVT fixed to floating point conversion instruction.
Fixes:
* LP: #922474 Bug in __sync_lock_release with 64 bit primitives
* LP: #923397 Alignment attribute has no effect under certain conditions
* LP: #926855 [ARMhf] gcc produces assembler it can't compile
* LP: #936863 ICE in constprop.2 (ARM NEON related?)
* LP: #942307 'asm' operand requires impossible reload
* LP: #952565 Not compliant with the ABI for multi-register NEON intrinsics
Linaro GCC 4.5 2012.03 is the nineteenth release in the 4.5 series. Based
off the latest GCC 4.5.3+svn184976 release, this is a maintenance only
update.
Interesting changes include:
* Updates to 4.5.3+svn184976.
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.6-2012.03https://launchpad.net/gcc-linaro/+milestone/4.5-2012.03
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.6/4.6-2012.03
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
-- Michael
EEMBC have announced AndEBench, a mixed native/Java benchmark for
Android. It's available on the Market.
I don't know much more. It seems to be CPU bound and the test names
sound a bit like CoreMark. The source is available for license and
might be worth the Android guys looking into.
The awesome thing is they used the 2012.01 Linaro Binary toolchain
release to build the native parts - see the compiler version string in
the log :)
-- Michael
Hi,
GDB for Android:
* Wrote first draft of the GDB for Android card.
* Found out that there actually is a libthread_db.so in /system/lib
and was able to compile (after a small hack) an FSF gdbserver 7.3
which uses the libthread_db.so from Android and correctly shows
all threads in the process. So the libthread_db.so from Android
actually works, still have to learn why they don't use it.
* Tried to compile a native GDB which uses libthread_db.so but no
luck so far. There are many differences in bionic's header files
which upset libiberty and gnulib which are not easy to work around.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
We now do a SPEC ref run when benchmarking. I've updated the
linaro-toolchain-benchmarks scripts to handle the changes and spawned
some historical builds to do comparisons. All earlier builds have
been archived to prevent confusion.
The human readable summary is now also included in the results. See:
http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.6-2012.02/logs/armv7l-nat…
for an example.
Half an hour to build, 26 hours to run. Not too bad.
-- Michael
Here's brief notes on running different benchmark variants across the
auto builders. Asa, could you pull these plus your notes into a wiki
page?
Spawn a job:
http://ex.seabright.co.nz/helpers/scheduler/spawn
Merge requests are automatically built. Otherwise, drop arbitrary
tarballs into cbuild@orion:~/snapshots and spawn <tarball name minus
extension>. For example, scp gcc-4.6.3.tar.gz
cbuild@orion:~/snapshots; spawn gcc-4.6.3 into a9-builder.
Jobs:
* gcc-version - build and test GCC
* benchmarks-gcc-version - run coremark, denbench, eembc against the
already built version
* benchmarks-spec2000-gcc-version - run spec2000
Queues:
* a9-builders: anything that can naive build a A9 compiler
* a9-ref: reference A9 boards
* a8-ref: reference A8 boards
Variables:
* BENCHMARKS = list, such as coremark spec2000 pybench - run these
benchmarks instead of the defaults
Variants:
* By default we build o3-neon
* See http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/trunk/view/head:/l…
for all names
* Spawn a job with VARIANT_SRC = all and VARIANT_LIST = glob-pattern
Examples:
* VARIANT_LIST = o3-neon o3-vfpv3 (compare NEON with VFPv3D32)
* VARIANT_LIST = o3-neon-cortexa8 o3-neon-cortexa9 (compare
-mtune=cortexa8 vs -mtune=cortexa9(
* VARIANT_LIST = o3-neon-novect o3-neon (compare with/without the vectoriser)
-- Michael
I'd like to announce a change in how the Linaro Toolchain group notify
about our monthly releases. In the past we've sent one email per
product to the linaro-announce list. From this week forward a summary
of all products will be included in the main, end of month
announcement instead.
We'll continue to send a per product emails to the linaro-toolchain
list when the mid-month release is available. If you'd like to get
things two weeks early, please subscribe[1]. You can filter on the
word '[ANNOUNCE]' to filter out the development chatter. A RSS feed
is also available[2].
-- Michael
[1] http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[2] http://feeds.launchpad.net/linaro-toolchain/announcements.atom
All,
I need to supply a Linaro toolchain "aligned" (same source code)
bare-metal compiler to a group doing benchmarking on A15.
First off my assumption is that we will write our own boot and semi
hosting code. (semi-hosting for TI emulators/simulators is different
than ARM RDI semi-hosting.)
I was planning on looking at the two toolchains here[1] and here [2]:
[1] https://launchpad.net/linaro-toolchain-binaries
[2] https://launchpad.net/gcc-arm-embedded
I was then going to build a hybrid that was newlib based but appropriate
for armv7-a (instead of cortext-m3) and maybe even -mtune'ed for A15.
However looking at the gcc-arm-embedded release more[3] I see that it
supports ARMv7-R. It supports both thumb and non-thumb modes, both
softfp and hardfp ABIs.
What would I really gain by building my own? For app code the user
should be able to add -mtune=cortex-a15 and still be compatible with the
pre-built R4/R5 libraries. The only performance difference should be in
the library code and that should be only pipeline tuning if I understand
the difference between armv7-a and armv7-r correctly.
Am I missing something? Should I build my hybrid anyway?
[1] https://launchpadlibrarian.net/88152755/readme.txt
[BTW: has the below project been obsoleted by the gcc-arm-embedded one?
Perhaps gcc-arm-embedded should be referenced in the description of
the page below.
https://launchpad.net/linaro-toolchain-unsupported ]
Thanks,
Bill
Committed the 4.6.3 merge to Linaro GCC 4.6.
Merged from FSF 4.5 to Linaro GCC 4.5.
Thought about how to do register-class allocation for NEON v. core
registers case. Discussed the problem at the GCC performance meeting.
Lots of interesting discussion was had. I have some interesting
experiments to do, but the first step needs to be to get my 64-bit
operator patch to work correctly.
Tried to track down the problems in my NEON-immediates patch. The
problem is that it's putting constants in different pools in stage 3 to
what it does in stage 2. Presumably this is something to do with the
pool-offset attributes in the instruction patterns? My patch has caused
it to switch from using 'fldd' to using 'vmov' in some cases (the
instructions are aliases, but it's indicative of a different machine
description pattern in the compiler), but I don't know why the change
would be different between the different bootstrap stages? I made some
alterations to switch it back to `fldd` when it wasn't supposed to
change, but bootstrap still fails. More investigation required...again.
Rewrote the NEON one's-complement patch and posted it upstream.
Tracked down the cause of the bootstrap failures in my NEON 64-bit
shifts patch: out-of-range shift amounts were not handled leading to
ICEs. Reworked the constant shift handling cases, and resumbitted the
patch for testing. It's failed again. A job for next week.
Summary:
* Multilib test for linaro toolchain.
* Code size test for embedded toolchain.
Details:
1. Multilib test for linaro toolchain.
* Workaround the marm/march=armv5t build by setting the
MULTILIB_DEFAULT to mthumb.
* Investigate how to make multiarch and multilib work together.
Based on current multiarch/multilib patches, it is hard to make them
work together. Trying to set the default multilib dir to the multiarch
dir to workaround it. Need more work to build libgcc.
2. Code size investigation for embedded toolchain.
* Try to test benchmarks.
* Run gcc regression test with –mthumb/-mcpu=cortex=m3/-Os and
analyze the new failed cases. After skipping the cases based on
scan-assembler, warning/error message, etc, there are 5 new failed
cases in three categories:
(1) gcc.target/arm/neon/vst1_lanes64.c: known issue
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51631
(2) Wrong optimization for gcc.dg/atomic-lockfree.c,
gcc.dg/atomic-noinline.c and gcc.dg/pr30951.c.
(3) g++.dg/eh/filter1.C abort in libsupc++.
Plans:
* Root cause the new failed cases.
* Continue to investigate the multilib/multiarch issue.
Best regards!
-Zhenqiang
Hi Michael,
Spec2000 is now running successfully: there are results at
http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.7%2bbzr114965/logs/armv7l…
However, they seem to have been run in 'train' mode, and none of the
runs are long enough for comparison.
I thought the a9-ref queue was supposed to run in full 'ref' mode?
Andrew
Hi,
OpenEmbedded:
* removed the recipe for building the linux-linaro-3.1 kernel
* add support for the default OE-core kernel
* allows to build the linux-yocto_3.2 kernel for the
qemuarmv7a MACHINE using a vexpress defconfig
* updated the wiki on how to build OE-core with meta-linaro
https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core
* worked OEMetaLinaroCard
* started to talk to CI folks about automating the oe-core+meta-linaro
* wrote a script that automates the process
* ran it on tcserver01 to build the qt4e and sato images against the
source gcc-linaro-4.6-2012.02
Regards,
Ken
Hi Ken. In follow up to our 1-on-1 yesterday, here's what I'd like done next.
The goal is to use OE Core as a release test suite. The releases are
tarballs so we can keep the current recipe format and punt bzr support
for later. The first step is to be able to reliably build a release
in the cloud or validation lab.
In all cases keep the other teams in mind. Much of this is related to
Validation. Platform will be involved later. Ping them early.
Kernel:
We're starting with GCC and need a kernel to supply headers and to
boot some type of ARMv7 image. I don't want a linux-linaro recipe as
people will use it and it's too early for that.
Find a kernel, preferably from OE Core, that is recent, ARMv7, >= 512
MB RAM, and works well with qemu-linaro. Prefer vexpress-a9, else
OMAP?
Talking:
Say Hi to Validation re: EC2 and plans
Say Hi to the ARM landing team re: vexpress upstream support
Say Hi to Beth Flanagan re: Yocto's existing auto builders and any hints
Cloud builds:
Find out who is already doing OE builds in the cloud and how
Run a build locally and time
Push ~/downloads into the cloud, build, and time[1]
Figure how much this build will cost in dollars
[1] c1.xlarge might be best. Builds are normally I/O bound and the
cloud is I/O poor. Put /tmp and other chunks in a tmpfs? EC2 rounds
up to the nearest hour as well.
If the cloud is too expensive then we'll get a machine installed.
S3 for storage:
(only proceed if affordable)
Use S3 for storing the input tarballs
Use S3 either as a pre-mirror by serving over HTTP, or use s3cmd to
sync down the tarballs before starting the build
Scripting:
Re-use existing scripts if feasible. Integrate with LAVA providing we
can run exactly the same scripts on a laptop for debugging.
Script the bitbake, OE meta layer, and Linaro meta layer setup.
Script the configuration including setting the release tarball URL and
GCC preferred version.
Script the build and result capture, especially the log, any ICEs, and
the final sizes
Future:
OE can grab a repository seed then update based on that. Check if the
bzr backend supports this. If so, play with seeding to do tip builds.
Let me know what you think then we'll spawn blueprints. Let's keep an
eye on this as it's sounding expensive.
-- Michael
Hi Ken, Thiago. Could you try your hand at writing cards for the
OpenEmbedded Core meta-layer and GDB and Android? Here are some past
cards:
https://linaro-public.papyrs.com/TCWG2011-GCC-O3https://linaro-public.papyrs.com/TCWG2011-OPENOCD-SUPPORThttps://linaro-public.papyrs.com/TCWG2011-WINDOWS-TOOLCHAIN
They cover:
* An introduction
* The why/advantages
* The what/features
* The how/steps
* Dependencies
* Acceptance criteria (which is a post-tense version of the body)
A card should cover three calendar months. Check the unknowns - we
need to investigate the acceptance criteria and make sure there is no
unexpected side work in there.
We use roadmap cards as the highest level of organising our work.
Cards are the interface between working groups and the TSC and sit at
the project brief / deep but concise level.
Draft them on the wiki (cf https://wiki.linaro.org/KenWerner/Sandbox)
and we'll go from there.
-- Michael
== Issues ==
It would be nice to have perf installed on the porter boxes in the
canonical data center as well if we are allowed to run benchmarks
there. Filed RT request.
==Progress===
* Understood STB_GNU_UNIQUE_NOTE - Helped fix a problem with compiz
crashing but then it was a very nice testcase to investigate the
toolchain issue with. Thanks Alexandros.
* Merged pending patches.
* ABI fix
* Fix for ICE - LP bug 942307
* Off sick on Monday.
* Did some work to improve code generation for addressing modes in VFP
registers.
* Did some work in setting up SPEC2k for running hc partitioning
patches. Still needs to be completed.
=== Plans ===
* Ping configure.ac changes.
* Complete pending benchmark run with hc partitioning and look at
results with hc partitioning and run things. Was unable to run the vfp
benchmarks today as ex.seabright.co.nz was down.
* Resurrect partial-partial PRE
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
Hi Ken. This month's release is next week. Let's be aggressive and
see if we can use your meta-linaro layer to check the source release.
I want to use tcserver01 in the validation lab instead of the cloud
until we know how much it costs. I've added you an account and done a
test build to check that the dependencies are there. There's a shared
directory in /home/shared that includes downloads and a sstate-cache.
The machine seems fast enough for the job.
The tarball should be ready around Tuesday next week. Once ready,
could you mix it in with the meta-linaro layer, do a build, boot the
rootfs in qemu, and document as you go? Anything past that is
welcome.
It's all manual but a nice proof of concept. Can we check the binary
build as well?
-- Michael
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-??-?? || ||
(new blueprints & reestimate for this one pending still; will try to
do this early next week)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* converted cp15 crn={6,7,9}, still TODO just crn={0,1}. These take
longer than I was expecting because to find some useful compromise
between QEMU's previous (usually broken) behaviour and reality I
have to cross reference half a dozen different TRMs and several
revisions of the ARM ARM.
== other ==
* getting qemu-linaro into shape for next week's release:
applying patches, writing changelog, etc
* patch review for more exynos4 devices
* tracked down a regression in the spitz (zaurus) model,
sent patch
* first pass comments on blueprints for this quarter
* investigating LP:947888 (gpg crashes under qemu)
-- PMM
Hi Alexandros,
Could you use the linaro-toolchain list for stuff like this please?
You're more likely to find somebody who knows the answer that way.
I'm pretty sure the problem is not the compiler because, as far as I can
see, both architectures' compilers emit ".weak" directives. If there is
a problem, I'd say it's in the linker.
Your test case gives two different addresses on Lucid x86, and on ARM
(so you say, I've not tested it), but the same address twice on Precise.
This is a surprising result. *I* would have expected that static values
in different dlopen'd libraries would not be unified, but apparently
they are ... somtimes.
I'm afraid I don't really have any insight here. :(
Anyway, regardless of whether one is correct, or not, I'd suggest *not*
relying on this behaviour - it's clearly not portable. I say leave it at
arm's length in production software for a few years.
Andrew
On 06/03/12 14:27, Alexandros Frantzis wrote:
> On Tue, Mar 06, 2012 at 09:51:01AM +0800, Sam Spilsbury wrote:
>> On Mon, Mar 5, 2012 at 11:50 PM, Alexandros Frantzis
>> <alexandros.frantzis(a)linaro.org> wrote:
>>> Hi all,
>>>
>>> this is an update on my progress with the updated compiz branches.
>>>
>>> I have been trying to run our update compiz branches
>>> (compiz-*/linaro-gles2-update) on ARM (precise armhf), but I have stumbled onto
>>> the same issue Marc reported some days ago. In particular, I get:
>>>
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeWindow_index_4" already stored in screen.
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeScreen_index_4" already stored in screen.
>>>
>>> and then a segfault when I try to run compiz.
>>>
>>> Note that I *don't* have this problem when running on x86_64 precise.
>>>
>>> The issue can be recreated with:
>>>
>>> $ compiz composite opengl
>>>
>>> I added some debugging messages to pluginclasshandler.h to get a better
>>> feeling of what is going on, and ran on both my desktop and on ARM.
>>> This is the output near the point when GLScreen get initialized:
>>>
>>> ...
>>>
>>> compiz (core) - Info: get(): mIndex.initiated for "8GLScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "8GLScreen_index_4"
>>> compiz (core) - Info: initializeIndex(): Private index value added for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Get instance for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Spawning new class for "8GLScreen_index_4"
>>> compiz (core) - Info: ctor(): mIndex.initiated for "8GLScreen_index_4" : 1
>>> compiz (core) - Info: ctor(): Increasing reference count for "8GLScreen_index_4": 1
>>>
>>> --- x86_64 ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 1
>>> --- armhf ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "15CompositeScreen_index_4"
>>> compiz (core) - Fatal: initializeIndex(): Private index value "15CompositeScreen_index_4" already stored in screen.
>>
>> After the composite plugin loads and mIndex.initiated is set to 1,
>> place a watchpoint on mIndex.initiated (it should be a separate
>> template instantiation for each different class) and check if it
>> changes, or check if we are reading mIndex.initiated from a different
>> address, and if so, check the addresses of this for each constructor
>> and destructor being called. (could be a compiler bug, I've hit these
>> on this part of the code before).
>>
>>> -------------
>>>
>>> In the armhf case, CompositeScreen is erroneously considered not
>>> initialized, and is initialiazed again, therefore messing up the plugin system.
>>>
>>> I am trying to figure out if this is a manifestation of some kind of memory
>>> corruption that doesn't affect us on x86_64 for whatever reason (alignment,
>>> integer size etc), or something completely different.
>>>
>>> Thoughts?
>>>
>>> Thanks,
>>> Alexandros
>>
>>
>>
>> --
>> Sam Spilsbury
>>
>
> Hi all,
>
> (I have also added Michael, Andrew and Ulrich from the Linaro toolchain group
> to the recipients. Hi!)
>
> Checking the addresses, as Sam suggested, I found that there are two different
> PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex and
> PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex objects.
>
> After a bit of investigation, objdump gave an explanation:
>
> objdump -t /usr/lib/compiz/libcomposite.so | c++filt | grep mIndex
>
> -- x86_64 --
> 0000000000277a80 u O .bss 0000000000000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 0000000000277a70 u O .bss 0000000000000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> -- armhf --
> 00065648 w O .bss 00000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 00065658 w O .bss 00000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> ------------
>
> And the same kind of output for libopengl.so
>
> On x86_64 the symbols are marked 'u': 'unique global', whereas on armhf
> they are marked 'w': 'weak'. This seems to be causing our troubles.
>
> I have produced a small test case for this:
>
> http://people.linaro.org/~afrantzis/cpp_unique_global.tar.gz
>
> Building and running 'LD_LIBRARY_PATH=. ./main' on x86_64 prints out f1 and f2
> with the same address, whereas on armhf the addresses are different (i.e. two
> different objects). On x86_64 the symbol A<int>::a is 'u', on armhf it is 'w'.
>
> For completeness, when running without templates (edit a.h to change) the two
> printed addresses are different on both x86_64 and armhf. Also A::a is 'g':
> 'normal global' for both.
>
> Michael, Andrew, Ulrich can you please give us some insight into the situation?
> Does this seem like a compiler or linker bug on ARM, or is the code depending
> on undefined behavior, or something different? I have pasted the used g++
> versions at the end of the email.
>
> Thanks,
> Alexandros
>
> --- g++ x86_64 --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.6/lto-wrapper
> Target: x86_64-linux-gnu
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++,go --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --disable-werror --with-arch-32=i686 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
> --- g++ armhf --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/4.6/lto-wrapper
> Target: arm-linux-gnueabihf
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --enable-multilib --disable-sjlj-exceptions --with-arch=armv7-a --with-float=hard --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabihf --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
Hi!
* Bug reports
Made an effort clean up among the remaining not-triaged bug. Michael will
help out with 941676, where the failure is on power-pc.
* Wiki
Created a wiki page for running benchmarks in cbuild:
https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/RunningBenchmark…
* V8
Build system has changed in V8 from SCones to GYP. With GYP I can pass the
normal flags like CXXFLAGS to control the build, so this looks like a good
change.
I have created a cbuild make file, patterned after the other benchmark make
files.
Working on x86 sofar, will go for arm next week. Will also add a parser for
the results.
Regards
Åsa
== GCC ==
* Checked patch to generate usat/ssat instructions into
Linaro GCC 4.6 and 4.7.
* Submitted (first part of) fwprop-subreg patch for mainline.
* Submitted Ira's vectorizer patches for mainline.
* Ongoing work on improving end-of-loop value computation.
* Patch review week.
== Misc ==
* On leave 3/9 - 3/14.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi
Updated sysroots for binary toolchain are available at [1]. This time I
split -dev and -dbg sysroots so as long as dbgsym are not needed less
disk space is used.
Please take a look at them and report any issues.
1. http://people.linaro.org/~hrw/generic-linux/sysroots/20120301/
Hello,
My name is Jiandong Zheng and am working on a few ARM specific projects.
I have been using Linaro toolchain coming with Ubuntu to do Cortext-A9
building. I also need to maintain code for old ARM11 SoC so that Linaro
toolchain is my preference and it did the job well back in Maverick days
if I remember correctly.
However, in Precise, I have troubles running this ARM11 u-boot and
kernel built with Linaro toolchain, eventually I found that my old gcc
4.3.2 toolchain can still build workable u-boot and kernel so that
Linaro toolchain (gcc 4.6.2) seems the problem. I understand that
Linaro's focus has been ARMv7 or above but I am wondering if its
toolchain can still be used for older ARM architectures.
Thanks,
JD
Hi Michael,
A new bug triaging question.
https://bugs.launchpad.net/ubuntu/+source/ppl/+bug/941676
This one is special too because the failure is on powerpc.
This means, I cannot reproduce it easily, and scan through the toolchains
(without building).
Matthias has given some information and a guess of what is failing. My idea
was to just summarize this, and let the person who takes on the bug make
the powerpc investigation.
How do we handle bugs on other architectures in general?
Best regards
Åsa
Hi!
I need a little help with triaging of this bug, it is a little different
from the ones I have triaged so far:
https://bugs.launchpad.net/launchpad/+bug/945503 - gcc-4.7 branch imports
fail (timeouts)
It is already set to Confirmed, my question is what is needed to go to the
triaged stage?
Also, the comments from wgrant and jelmer somewhat indicates that there is
no problem.
Best regards
Åsa
Hello,
since this long-standing problem just hit me again, I had a quick look at
test failures in our farm that appear to occur whenever the directory name
contains a string that is being checked for via a "scan-assembler" test,
e.g.:
+FAIL: gcc.target/arm/sat-1.c scan-assembler-times ssat 4
+FAIL: gcc.target/arm/sat-1.c scan-assembler-times usat 4
I had been assuming this happens because the directory name somehow finds
its name into the assembler file, e.g. via a .file directive or DWARF data,
and therefore an additional instance of the search string is being detected
erroneously.
However, when I attemted to re-create the scenario by building myself
within a directory that has the same name, but on my local machine, the
tests when through fine. And indeed, inspecting the assembler source shows
that that there is no debug info at all; while there is a .file directive,
it contains just the file base name without any directory name; and in fact
the directory name does not show up at all within the assembler file.
Something must still be different in the runs that take place on the build
farm; but I currently do not understand what that might be.
Michael, is there a way to interact with the build process on the build
farm machines themselves to try and find out what's going on here?
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi toolchain folks,
I have a problem with U-boot compiled for an ARMv4 system (Integrator)
using Linaro 2012.02-20120222, it just crashes. Compiling the same
U-Boot with CodeSourcery 2010-q1 works fine.
Symptom:
Resetting CPU ...
undefined instruction
pc : [<07fdecd4>] lr : [<07fdeb34>]
sp : 07f91380 ip : 00000000 fp : 00000001
r10: 010258fc r9 : 00000000 r8 : 07f94f64
r7 : 07f94eb0 r6 : 00989680 r5 : 000186a0 r4 : 000186a0
r3 : 000003e8 r2 : 000f423f r1 : 000f4240 r0 : 05f5e100
Flags: nzCv IRQs on FIQs on Mode SVC_32
(repeated ad nauseam)
The only hint I have is the constant 000186a0, which appears
here in the put_dec() routine from U-boots vsprintf(), which is
nothing special, it's Douglas Jones' binary to decimal conversion
code from the Linux kernel, but the compiles objects DOES
contain calls to __aeabi_uidivmod, __udivsi3, __div64_32.
Do we know of any potential trouble in these helpers on ARMv4?
The file containing these functions is compiled like this:
arm-linux-gnueabi-gcc -M -g -Os -fno-common -ffixed-r8 -msoft-float
-D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x01000000
-I/var/linus/u-boot/build-integrator/include2
-I/var/linus/u-boot/build-integrator/include
-I/var/linus/u-boot/include -fno-builtin -ffreestanding -nostdinc
-isystem /home/linus/src/gcc-linaro-arm-linux-gnueabi-2012.02-20120222_linux/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux
-mno-thumb-interwork -march=armv4 -MQ
/var/linus/u-boot/build-integrator/lib/vsprintf.o vsprintf.c
>/var/linus/u-boot/build-integrator/lib/.depend.vsprintf
Yours,
Linus Walleij
Hi,
GDB on Android:
* Spent some time understanding the intricate build process used
to compile NDK's gdbserver.
* After a lot of tinkering and trial and error I was finally able
to produce a gdbserver binary which when running on the Android
emulator and talking to a GDB (also compiled by me) on the host
is able to show all threads and provide a useful backtrace.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi there. When you do a commit that fixes a bug, try adding a
'--fixes lp:123456' to the bzr commit. Launchpad recognises these and
automatically link the branch and merge request to the bug report.
This makes it easier for the reporter to see progress. If you forget
to update the bug status (such as bumping it from 'Triaged' to 'In
progress') then it's obvious that it's being worked on.
See https://bugs.launchpad.net/gcc-linaro/+bug/942307 for an example.
The status was 'Triaged' but there's an approved merge request which
shows work is being done.
-- Michael
Merged FSF GCC 4.7 to the Linaro GCC 4.7 branch.
Merged from GCC 4.6.3 release to Linaro GCC 4.6 branch.
Wrote and posted a patch to load DImode immediate constant into NEON
registers properly. Unfortunately, testing showed a bootstrap stage 2
vs. 3 miscompare, so there's something not quite right. However,
disassembly of the binaries hasn't revealed any problems, so this
failure is still a mystery. More investigation required.
Wrote and posted a patch to do DImode negation in NEON. Realised that I
had forgotten to do the core-register fall-back case; posted a new
version. Again, there's something annoyingly subtle that prevents
bootstrap. This time it looks like some sort of wrong code bug.
Investigating.
Wrote and posted a patch to do DImode one's complement in NEON. Richard
E questioned how it was written though. The tests passed successfully,
so that's a novelty this week!
Looked for other NEON instructions missing support. Didn't find any ...
but the machine description isn't exactly straight forward.
Considered the problems with choosing whether or not to do an operation
in NEON, or not. Discussed the existing state and possible solutions
with Ramana and Benrd (thanks Guys). Thought about it some more. Posted
a vague description of what might fix it to the linaro-toolchain list.
Awaiting replies.
Hi!
* Development benchmarks:
Finished the first implementation, sent to Michael for review.
* This became a very short week because of sickness.
Plans for week 10 is to triage existing bugs, and to get going again with
the SunSpider benchmark.
Regards
Åsa
Summary:
* Multilib on linaro toolchain.
Details:
1. Multilib test for linaro toolchain.
* Fix the multilib build issue when multiarch patch is applied.
* Fix a bug in crosstool-ng upstream to build multilib for glibc/eglibc.
* Successfully build multilib toolchain for armv6t2, cortex-a8 and
cortex-a9. And tests show it can link the correct libraries.
2. Still issues:
* Multilib and multiarch uses different directory structures.
Multilib build can not find the correct directories in the prebuilt
oneiric-sysroot.
* Build armv5t arm mode lib when default mode is thumb for armv7-a.
Annual leaves:
* Mar. 1-2.
Plans:
* Finalize the multilib solution for linaro binary toolchain.
* Work on code size optimization for the embedded toolchain.
Best regards!
-Zhenqiang
> The basic idea is that we add a new RTL optimization pass (or two) that
> assesses the usage of pseudo registers, and makes recommendations about
> what register class each should end up in, if there's a choice. These
> recommendations would then be used by later passes to get a better use
> of NEON. I might call this the "prealloc" pass, or something.
That sounds very much like the pre-reload that "new-ra" had at one
point (http://gcc.gnu.org/viewcvs/branches/new-regalloc-branch/gcc/pre-reload.c).
The problem with pre-reload for new-ra was that it was basically
reload instead of something nicer and cleaner. It also only ran just
before the register allocator, which is too late for the problem you
are trying to solve.
> Firstly, for each pseudo-register in a function, the pass would look at
> the insn constraints for each "def" and "use", and see how the registers
> relate to one another. This might determine things like "if rN is in
> class A, then rM must be also in class A".
At SUSE I tried to do this with the webizer pass (web.c). I wrote down
the ideas we implemented at the time (see
http://gcc.gnu.org/ml/gcc/2005-01/msg00179.html):
- web class, to replace regclass and choose register classes webs
instead of pseudos. This also includes splitting webs if a register
in a web really wants to be in two different classes to satisfy
constraints in two different insns. Right now, as far as I
understand, regclass just picks one and lets reload figure out how to
fix up that mistake.
- A semi-strict RTL mode. Right now there is just strict and
non-strict. On the branch there is a semi-strict mode which is the
same as strict RTL except that pseudo-registers are still allowed.
- pre-reload (which is related to web class) to make sure as many insn
constraints as possible are satisfied before the register allocator
goes to work. Basically, after pre-reload the insns stream should be
in semi-strict RTL form.
I used the webizer to unify defs and uses. I would split a web if it
needed multiple register classes (I inserted a mov, without checking
that a move existed from the source to the target register class), and
I put pseudos r1 and r2 in the same register class if there was an
insn (set (r1) (r2)) somewhere. The selection of the register classes
had a cost function, but I used rtx_cost, which is not very effective,
really. But I never took this experiment very far because for x86-64
the plan didn't work as well as I had hoped. I don't remember the
details, but the biggest problem I had with the experimental
implementation of these ideas (apart from lots of trouble with recog
for semi-strict RTL) was that there is a bit of an ordering problem
between combine on the one hand, and web-based register classes. If
you assign classes too early and don't allow things to change, then
combine fails too often. If you assign register classes after combine,
you may not get the instructions selected the way you want them to be.
This was when GCC still had the old local-alloc.c and global.c
allocators. Things may be different (better) with IRA and the upcoming
LRA stuff.
If you plan to work on this, I would suggest you discuss the plan on
the GCC mailing list also, with Jeff Law and Vladimir Makarov in CC
because they are working on a reload rewrite (LRA).
Ciao!
Steven
Hi,
OpenEmbedded:
* Worked on the meta-linaro layer and added libgcc and crosssdk
recipes to satisfy some bitbake dependencies
* I had to apply a few patches to build the linaro toolchain the OE
way (mostly gcc configury)
* successfully built the sato and Qt images
* Moved on to test the February release of the linaro binary toolchain
and (probably) and hit an issue with unaligned SD card images to used
with QEMU
* the guest kernel fails with: attempt to access beyond end of device
* /proc/partitions shows different block sizes (host vs. guest)
* the image size gets calculated on the fly by OE
* patch posted that introduces allows to specify a rootfs size alignment
* not seen on trunk as they use IDE
* Started to rebase the linaro-meta layer against current OE-core
* created https://wiki.linaro.org/KenWerner/Sandbox/OEMetaLinaroCard
based on the existent card of David R.
Regards,
Ken
== GCC ==
* Fixed mainline regression causing ICE in certain outer-loop
vectorization cases.
* Merged fwprop-subreg patch into Linaro GCC 4.7.
* Completed patch to generate usat/ssat instructions
where appropriate; checked into GCC mainline.
Merge requests to Linaro GCC 4.6 and 4.7 pending.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
==Progress===
* Finished off PGO patch - sent upstream.
* Finished off the ABI tests - sent upstream.
* Investigated fixes for LP 942307 - a problem with kernel builds for
android. Backported a fix from Uli last year.
* Upstream patch review.
* Small configury done for SPEC2k as far as HC partitioning goes.
* Some Android benchmark investigations.
* Recovered from a broken upgrade on my laptop from natty to oneiric
on my laptop and then went all the way to Precise. It works
reasonably !
=== Plans ===
* Commit all approved and tested patches.
* Check on hc partitioning results from SPEC2k and make sure there is
an improvement and the feature works !
* Investigate https://bugs.launchpad.net/gcc-linaro/+bug/924726 in a
little more detail.
* Get back to partial-partial PRE.
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
