- linaro-toolchain - lists.linaro.org

by Ken Werner

Hi, OpenEmbedded: * verified that the release candidate of our 2012.03 toolchain (both source and binary) is able to build the sato and qt4e images of oe-core+meta-linaro - they are booting fine using QEMU * out sick starting from Tue :/ Regards, Ken

13 years, 8 months

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[ACTIVITY] report week 11

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-03-30 || || Historical Milestones: ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * converted crn=1; still TODO: crn=0, some loose ends; then reassess the design in the light of experience doing register conversion * I've estimated another two weeks here but this might be out, because in practice much of my time is sucked up by 'other' issues == other == * tracked down cause of LP:947888 gpg crash bug: newer glibc use /proc/self/maps to decide whether a printf format string using '%n' is in writable memory, and qemu's maps emulation wasn't good enough * fixed a thumb decoder bug where we were treating 'setend' like 'cps' * investigated whether we had any conveniently testable cores which take advantage of the ARM ARM latitude for UNDEFfing even on failed condition code checks (answer, not really but the KVM code to handle this case should be small enough not to worry about its not-yet-tested nature) * qemu-linaro 2012.03 release (lots of bug fixes, plus exynos4 and highbank models thanks to Samsung and Calxeda) * code review: imx31 board patches * rebased qemu-linaro on upstream and applied some new patches from Christoffer for ARM KVM support * LP:956799: added ppoll to QEMU arm-linux-user (a one liner...) * boot-wrapper: moved initrd load address up so we can handle large kernels (like Android!) * sent pullreqs for target-arm, arm-devs patchqueues

13 years, 8 months

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[ACTIVITY] Mar 15 - Mar 16

by Ulrich Weigand

== GCC == * Checked first part of fwprop-subreg patch into mainline. * Checked Ira's vectorizer patches into mainline. * Ongoing work on improving end-of-loop value computation. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 8 months

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Final Building at -O3 writeup

by Michael Hope

The final version of the 'Building at -O3' writeup is at: https://wiki.linaro.org/Internal/ToolChain/BuildingAtO3 This updates the SPEC 2000 results to show that there is a net win which is held back by a bad (but understood) regression in one benchmark. Thank you all for your work on this, -- Michael

13 years, 8 months

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[ANNOUNCE] Linaro QEMU 2012.03 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2012.03. Linaro QEMU 2012.03 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. Highlights in this month's release: - we now default to enabling 'reserve memory for guest' on 64 bit hosts in linux-user-mode. This significantly reduces the chances of QEMU being unable to satisfy a guest process mmap() request. - Fix for a bug that was causing spurious failures of the glibc check for "%n in a format string must be in a read-only area of memory" when running in linux-user-mode. - QEMU's built-in boot loader now supports passing a device tree blob to the kernel: if you boot with -kernel mykernel (and optionally -initrd myinitrd) you can now also use the new command line option -dtb my.dtb to pass a device tree. - This version includes an initial implementation of a model of the Samsung Exynos4210 SoC, used by board models 'nuri' and 'smdkc210' (thanks to Evgeny Voevodin, Maksim Kozlov, Igor Mitsyanko and Dmitry Solodkiy from Samsung, who submitted this work to upstream QEMU). - This version includes an initial implementation of a model of the Calxeda Highbank SoC, used by board model 'highbank' (thanks to Rob Herring and Mark Langsdorf of Calxeda, who submitted this work to upstream QEMU). - various other minor bug fixes (detailed in the Changelog.LINARO). Known issues: - Graphics do not work for OMAP3 based models (beagle, overo) with 11.10 Linaro images. The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2012.03 More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

13 years, 8 months

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Release done, branch is open

by Michael Hope

The GCC release tested up just fine. The branch is now open for commits. The next release is Thursday the 12th of April. Note that this is the week after Easter. -- Michael

13 years, 9 months

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[ANNOUNCE] Linaro GCC 4.6 and 4.5 2012.03 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the 2012.03 release of both Linaro GCC 4.6 and Linaro GCC 4.5. Linaro GCC 4.6 2012.03 is the thirteenth release in the 4.6 series. Based off the latest GCC 4.6.3 release, it contains a new scheduler pressure pass, implements new instructions, and contains a number of bug fixes. Interesting changes include: * Updates to 4.6.3. * Better performance by accounting for register pressure when scheduling instructions. * Support for the ARMv6 USAT/SSAT saturation instructions. * Support for the VFP VCVT fixed to floating point conversion instruction. Fixes: * LP: #922474 Bug in __sync_lock_release with 64 bit primitives * LP: #923397 Alignment attribute has no effect under certain conditions * LP: #926855 [ARMhf] gcc produces assembler it can't compile * LP: #936863 ICE in constprop.2 (ARM NEON related?) * LP: #942307 'asm' operand requires impossible reload * LP: #952565 Not compliant with the ABI for multi-register NEON intrinsics Linaro GCC 4.5 2012.03 is the nineteenth release in the 4.5 series. Based off the latest GCC 4.5.3+svn184976 release, this is a maintenance only update. Interesting changes include: * Updates to 4.5.3+svn184976. The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2012.03 https://launchpad.net/gcc-linaro/+milestone/4.5-2012.03 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.6/4.6-2012.03 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org -- Michael

13 years, 9 months

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EEMBC AndEBench

by Michael Hope

EEMBC have announced AndEBench, a mixed native/Java benchmark for Android. It's available on the Market. I don't know much more. It seems to be CPU bound and the test names sound a bit like CoreMark. The source is available for license and might be worth the Android guys looking into. The awesome thing is they used the 2012.01 Linaro Binary toolchain release to build the native parts - see the compiler version string in the log :) -- Michael

13 years, 9 months

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[ACTIVITY] May 5 - May 9

by Thiago Jung Bauermann

Hi, GDB for Android: * Wrote first draft of the GDB for Android card. * Found out that there actually is a libthread_db.so in /system/lib and was able to compile (after a small hack) an FSF gdbserver 7.3 which uses the libthread_db.so from Android and correctly shows all threads in the process. So the libthread_db.so from Android actually works, still have to learn why they don't use it. * Tried to compile a native GDB which uses libthread_db.so but no luck so far. There are many differences in bionic's header files which upset libiberty and gnulib which are not easy to work around. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 9 months

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SPEC shifted to ref runs

by Michael Hope

We now do a SPEC ref run when benchmarking. I've updated the linaro-toolchain-benchmarks scripts to handle the changes and spawned some historical builds to do comparisons. All earlier builds have been archived to prevent confusion. The human readable summary is now also included in the results. See: http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.6-2012.02/logs/armv7l-nat… for an example. Half an hour to build, 26 hours to run. Not too bad. -- Michael

13 years, 9 months

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Running benchmark variants

by Michael Hope

Here's brief notes on running different benchmark variants across the auto builders. Asa, could you pull these plus your notes into a wiki page? Spawn a job: http://ex.seabright.co.nz/helpers/scheduler/spawn Merge requests are automatically built. Otherwise, drop arbitrary tarballs into cbuild@orion:~/snapshots and spawn <tarball name minus extension>. For example, scp gcc-4.6.3.tar.gz cbuild@orion:~/snapshots; spawn gcc-4.6.3 into a9-builder. Jobs: * gcc-version - build and test GCC * benchmarks-gcc-version - run coremark, denbench, eembc against the already built version * benchmarks-spec2000-gcc-version - run spec2000 Queues: * a9-builders: anything that can naive build a A9 compiler * a9-ref: reference A9 boards * a8-ref: reference A8 boards Variables: * BENCHMARKS = list, such as coremark spec2000 pybench - run these benchmarks instead of the defaults Variants: * By default we build o3-neon * See http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/trunk/view/head:/l… for all names * Spawn a job with VARIANT_SRC = all and VARIANT_LIST = glob-pattern Examples: * VARIANT_LIST = o3-neon o3-vfpv3 (compare NEON with VFPv3D32) * VARIANT_LIST = o3-neon-cortexa8 o3-neon-cortexa9 (compare -mtune=cortexa8 vs -mtune=cortexa9( * VARIANT_LIST = o3-neon-novect o3-neon (compare with/without the vectoriser) -- Michael

13 years, 9 months

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Change in Linaro Toolchain announcements

by Michael Hope

I'd like to announce a change in how the Linaro Toolchain group notify about our monthly releases. In the past we've sent one email per product to the linaro-announce list. From this week forward a summary of all products will be included in the main, end of month announcement instead. We'll continue to send a per product emails to the linaro-toolchain list when the mid-month release is available. If you'd like to get things two weeks early, please subscribe[1]. You can filter on the word '[ANNOUNCE]' to filter out the development chatter. A RSS feed is also available[2]. -- Michael [1] http://lists.linaro.org/mailman/listinfo/linaro-toolchain [2] http://feeds.launchpad.net/linaro-toolchain/announcements.atom

13 years, 9 months

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Bare metal toolchain for A15

by William Mills

All, I need to supply a Linaro toolchain "aligned" (same source code) bare-metal compiler to a group doing benchmarking on A15. First off my assumption is that we will write our own boot and semi hosting code. (semi-hosting for TI emulators/simulators is different than ARM RDI semi-hosting.) I was planning on looking at the two toolchains here[1] and here [2]: [1] https://launchpad.net/linaro-toolchain-binaries [2] https://launchpad.net/gcc-arm-embedded I was then going to build a hybrid that was newlib based but appropriate for armv7-a (instead of cortext-m3) and maybe even -mtune'ed for A15. However looking at the gcc-arm-embedded release more[3] I see that it supports ARMv7-R. It supports both thumb and non-thumb modes, both softfp and hardfp ABIs. What would I really gain by building my own? For app code the user should be able to add -mtune=cortex-a15 and still be compatible with the pre-built R4/R5 libraries. The only performance difference should be in the library code and that should be only pipeline tuning if I understand the difference between armv7-a and armv7-r correctly. Am I missing something? Should I build my hybrid anyway? [1] https://launchpadlibrarian.net/88152755/readme.txt [BTW: has the below project been obsoleted by the gcc-arm-embedded one? Perhaps gcc-arm-embedded should be referenced in the description of the page below. https://launchpad.net/linaro-toolchain-unsupported ] Thanks, Bill

13 years, 9 months

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[ACTIVITY] 5th - 9th March

by Andrew Stubbs

Committed the 4.6.3 merge to Linaro GCC 4.6. Merged from FSF 4.5 to Linaro GCC 4.5. Thought about how to do register-class allocation for NEON v. core registers case. Discussed the problem at the GCC performance meeting. Lots of interesting discussion was had. I have some interesting experiments to do, but the first step needs to be to get my 64-bit operator patch to work correctly. Tried to track down the problems in my NEON-immediates patch. The problem is that it's putting constants in different pools in stage 3 to what it does in stage 2. Presumably this is something to do with the pool-offset attributes in the instruction patterns? My patch has caused it to switch from using 'fldd' to using 'vmov' in some cases (the instructions are aliases, but it's indicative of a different machine description pattern in the compiler), but I don't know why the change would be different between the different bootstrap stages? I made some alterations to switch it back to `fldd` when it wasn't supposed to change, but bootstrap still fails. More investigation required...again. Rewrote the NEON one's-complement patch and posted it upstream. Tracked down the cause of the bootstrap failures in my NEON 64-bit shifts patch: out-of-range shift amounts were not handled leading to ICEs. Reworked the constant shift handling cases, and resumbitted the patch for testing. It's failed again. A job for next week.

13 years, 9 months

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[Activity] Week 10

by Zhenqiang Chen

Summary: * Multilib test for linaro toolchain. * Code size test for embedded toolchain. Details: 1. Multilib test for linaro toolchain. * Workaround the marm/march=armv5t build by setting the MULTILIB_DEFAULT to mthumb. * Investigate how to make multiarch and multilib work together. Based on current multiarch/multilib patches, it is hard to make them work together. Trying to set the default multilib dir to the multiarch dir to workaround it. Need more work to build libgcc. 2. Code size investigation for embedded toolchain. * Try to test benchmarks. * Run gcc regression test with –mthumb/-mcpu=cortex=m3/-Os and analyze the new failed cases. After skipping the cases based on scan-assembler, warning/error message, etc, there are 5 new failed cases in three categories: (1) gcc.target/arm/neon/vst1_lanes64.c: known issue http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51631 (2) Wrong optimization for gcc.dg/atomic-lockfree.c, gcc.dg/atomic-noinline.c and gcc.dg/pr30951.c. (3) g++.dg/eh/filter1.C abort in libsupc++. Plans: * Root cause the new failed cases. * Continue to investigate the multilib/multiarch issue. Best regards! -Zhenqiang

13 years, 9 months

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Draft release notes for 2012.03

by Michael Hope

I've put the draft release notes at: https://wiki.linaro.org/MichaelHope/Sandbox/GCC2012.03ReleaseNotes Feel free to edit. -- Michael

13 years, 9 months

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Spec2000

by Andrew Stubbs

Hi Michael, Spec2000 is now running successfully: there are results at http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.7%2bbzr114965/logs/armv7l… However, they seem to have been run in 'train' mode, and none of the runs are long enough for comparison. I thought the a9-ref queue was supposed to run in full 'ref' mode? Andrew

13 years, 9 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, OpenEmbedded: * removed the recipe for building the linux-linaro-3.1 kernel * add support for the default OE-core kernel * allows to build the linux-yocto_3.2 kernel for the qemuarmv7a MACHINE using a vexpress defconfig * updated the wiki on how to build OE-core with meta-linaro https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core * worked OEMetaLinaroCard * started to talk to CI folks about automating the oe-core+meta-linaro * wrote a script that automates the process * ran it on tcserver01 to build the qt4e and sato images against the source gcc-linaro-4.6-2012.02 Regards, Ken

13 years, 9 months

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OpenEmbbedded as a test suite next steps

by Michael Hope

Hi Ken. In follow up to our 1-on-1 yesterday, here's what I'd like done next. The goal is to use OE Core as a release test suite. The releases are tarballs so we can keep the current recipe format and punt bzr support for later. The first step is to be able to reliably build a release in the cloud or validation lab. In all cases keep the other teams in mind. Much of this is related to Validation. Platform will be involved later. Ping them early. Kernel: We're starting with GCC and need a kernel to supply headers and to boot some type of ARMv7 image. I don't want a linux-linaro recipe as people will use it and it's too early for that. Find a kernel, preferably from OE Core, that is recent, ARMv7, >= 512 MB RAM, and works well with qemu-linaro. Prefer vexpress-a9, else OMAP? Talking: Say Hi to Validation re: EC2 and plans Say Hi to the ARM landing team re: vexpress upstream support Say Hi to Beth Flanagan re: Yocto's existing auto builders and any hints Cloud builds: Find out who is already doing OE builds in the cloud and how Run a build locally and time Push ~/downloads into the cloud, build, and time[1] Figure how much this build will cost in dollars [1] c1.xlarge might be best. Builds are normally I/O bound and the cloud is I/O poor. Put /tmp and other chunks in a tmpfs? EC2 rounds up to the nearest hour as well. If the cloud is too expensive then we'll get a machine installed. S3 for storage: (only proceed if affordable) Use S3 for storing the input tarballs Use S3 either as a pre-mirror by serving over HTTP, or use s3cmd to sync down the tarballs before starting the build Scripting: Re-use existing scripts if feasible. Integrate with LAVA providing we can run exactly the same scripts on a laptop for debugging. Script the bitbake, OE meta layer, and Linaro meta layer setup. Script the configuration including setting the release tarball URL and GCC preferred version. Script the build and result capture, especially the log, any ICEs, and the final sizes Future: OE can grab a repository seed then update based on that. Check if the bzr backend supports this. If so, play with seeding to do tip builds. Let me know what you think then we'll spawn blueprints. Let's keep an eye on this as it's sounding expensive. -- Michael

13 years, 9 months

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Cards

by Michael Hope

Hi Ken, Thiago. Could you try your hand at writing cards for the OpenEmbedded Core meta-layer and GDB and Android? Here are some past cards: https://linaro-public.papyrs.com/TCWG2011-GCC-O3 https://linaro-public.papyrs.com/TCWG2011-OPENOCD-SUPPORT https://linaro-public.papyrs.com/TCWG2011-WINDOWS-TOOLCHAIN They cover: * An introduction * The why/advantages * The what/features * The how/steps * Dependencies * Acceptance criteria (which is a post-tense version of the body) A card should cover three calendar months. Check the unknowns - we need to investigate the acceptance criteria and make sure there is no unexpected side work in there. We use roadmap cards as the highest level of organising our work. Cards are the interface between working groups and the TSC and sit at the project brief / deep but concise level. Draft them on the wiki (cf https://wiki.linaro.org/KenWerner/Sandbox) and we'll go from there. -- Michael

13 years, 9 months

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[Activity] Week 10

by Ramana Radhakrishnan

== Issues == It would be nice to have perf installed on the porter boxes in the canonical data center as well if we are allowed to run benchmarks there. Filed RT request. ==Progress=== * Understood STB_GNU_UNIQUE_NOTE - Helped fix a problem with compiz crashing but then it was a very nice testcase to investigate the toolchain issue with. Thanks Alexandros. * Merged pending patches. * ABI fix * Fix for ICE - LP bug 942307 * Off sick on Monday. * Did some work to improve code generation for addressing modes in VFP registers. * Did some work in setting up SPEC2k for running hc partitioning patches. Still needs to be completed. === Plans === * Ping configure.ac changes. * Complete pending benchmark run with hc partitioning and look at results with hc partitioning and run things. Was unable to run the vfp benchmarks today as ex.seabright.co.nz was down. * Resurrect partial-partial PRE Absences. * 1 week holiday sometime before that - to be booked. * Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.

13 years, 9 months

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Using OpenEmbedded Core to check this month's release

by Michael Hope

Hi Ken. This month's release is next week. Let's be aggressive and see if we can use your meta-linaro layer to check the source release. I want to use tcserver01 in the validation lab instead of the cloud until we know how much it costs. I've added you an account and done a test build to check that the dependencies are there. There's a shared directory in /home/shared that includes downloads and a sstate-cache. The machine seems fast enough for the job. The tarball should be ready around Tuesday next week. Once ready, could you mix it in with the meta-linaro layer, do a build, boot the rootfs in qemu, and document as you go? Anything past that is welcome. It's all manual but a nice proof of concept. Can we check the binary build as well? -- Michael

13 years, 9 months

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[ACTIVITY] report week 10

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-??-?? || || (new blueprints & reestimate for this one pending still; will try to do this early next week) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * converted cp15 crn={6,7,9}, still TODO just crn={0,1}. These take longer than I was expecting because to find some useful compromise between QEMU's previous (usually broken) behaviour and reality I have to cross reference half a dozen different TRMs and several revisions of the ARM ARM. == other == * getting qemu-linaro into shape for next week's release: applying patches, writing changelog, etc * patch review for more exynos4 devices * tracked down a regression in the spitz (zaurus) model, sent patch * first pass comments on blueprints for this quarter * investigating LP:947888 (gpg crashes under qemu) -- PMM

13 years, 9 months

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Re: Problem running updated compiz branches on ARM

by Andrew Stubbs

Hi Alexandros, Could you use the linaro-toolchain list for stuff like this please? You're more likely to find somebody who knows the answer that way. I'm pretty sure the problem is not the compiler because, as far as I can see, both architectures' compilers emit ".weak" directives. If there is a problem, I'd say it's in the linker. Your test case gives two different addresses on Lucid x86, and on ARM (so you say, I've not tested it), but the same address twice on Precise. This is a surprising result. *I* would have expected that static values in different dlopen'd libraries would not be unified, but apparently they are ... somtimes. I'm afraid I don't really have any insight here. :( Anyway, regardless of whether one is correct, or not, I'd suggest *not* relying on this behaviour - it's clearly not portable. I say leave it at arm's length in production software for a few years. Andrew On 06/03/12 14:27, Alexandros Frantzis wrote: > On Tue, Mar 06, 2012 at 09:51:01AM +0800, Sam Spilsbury wrote: >> On Mon, Mar 5, 2012 at 11:50 PM, Alexandros Frantzis >> <alexandros.frantzis(a)linaro.org> wrote: >>> Hi all, >>> >>> this is an update on my progress with the updated compiz branches. >>> >>> I have been trying to run our update compiz branches >>> (compiz-*/linaro-gles2-update) on ARM (precise armhf), but I have stumbled onto >>> the same issue Marc reported some days ago. In particular, I get: >>> >>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeWindow_index_4" already stored in screen. >>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeScreen_index_4" already stored in screen. >>> >>> and then a segfault when I try to run compiz. >>> >>> Note that I *don't* have this problem when running on x86_64 precise. >>> >>> The issue can be recreated with: >>> >>> $ compiz composite opengl >>> >>> I added some debugging messages to pluginclasshandler.h to get a better >>> feeling of what is going on, and ran on both my desktop and on ARM. >>> This is the output near the point when GLScreen get initialized: >>> >>> ... >>> >>> compiz (core) - Info: get(): mIndex.initiated for "8GLScreen_index_4" : 0 >>> compiz (core) - Info: initializeIndex(): Initializining index value "8GLScreen_index_4" >>> compiz (core) - Info: initializeIndex(): Private index value added for "8GLScreen_index_4" >>> compiz (core) - Info: getInstance(): Get instance for "8GLScreen_index_4" >>> compiz (core) - Info: getInstance(): Spawning new class for "8GLScreen_index_4" >>> compiz (core) - Info: ctor(): mIndex.initiated for "8GLScreen_index_4" : 1 >>> compiz (core) - Info: ctor(): Increasing reference count for "8GLScreen_index_4": 1 >>> >>> --- x86_64 --- >>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 1 >>> --- armhf --- >>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 0 >>> compiz (core) - Info: initializeIndex(): Initializining index value "15CompositeScreen_index_4" >>> compiz (core) - Fatal: initializeIndex(): Private index value "15CompositeScreen_index_4" already stored in screen. >> >> After the composite plugin loads and mIndex.initiated is set to 1, >> place a watchpoint on mIndex.initiated (it should be a separate >> template instantiation for each different class) and check if it >> changes, or check if we are reading mIndex.initiated from a different >> address, and if so, check the addresses of this for each constructor >> and destructor being called. (could be a compiler bug, I've hit these >> on this part of the code before). >> >>> ------------- >>> >>> In the armhf case, CompositeScreen is erroneously considered not >>> initialized, and is initialiazed again, therefore messing up the plugin system. >>> >>> I am trying to figure out if this is a manifestation of some kind of memory >>> corruption that doesn't affect us on x86_64 for whatever reason (alignment, >>> integer size etc), or something completely different. >>> >>> Thoughts? >>> >>> Thanks, >>> Alexandros >> >> >> >> -- >> Sam Spilsbury >> > > Hi all, > > (I have also added Michael, Andrew and Ulrich from the Linaro toolchain group > to the recipients. Hi!) > > Checking the addresses, as Sam suggested, I found that there are two different > PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex and > PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex objects. > > After a bit of investigation, objdump gave an explanation: > > objdump -t /usr/lib/compiz/libcomposite.so | c++filt | grep mIndex > > -- x86_64 -- > 0000000000277a80 u O .bss 0000000000000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex > 0000000000277a70 u O .bss 0000000000000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex > -- armhf -- > 00065648 w O .bss 00000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex > 00065658 w O .bss 00000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex > ------------ > > And the same kind of output for libopengl.so > > On x86_64 the symbols are marked 'u': 'unique global', whereas on armhf > they are marked 'w': 'weak'. This seems to be causing our troubles. > > I have produced a small test case for this: > > http://people.linaro.org/~afrantzis/cpp_unique_global.tar.gz > > Building and running 'LD_LIBRARY_PATH=. ./main' on x86_64 prints out f1 and f2 > with the same address, whereas on armhf the addresses are different (i.e. two > different objects). On x86_64 the symbol A<int>::a is 'u', on armhf it is 'w'. > > For completeness, when running without templates (edit a.h to change) the two > printed addresses are different on both x86_64 and armhf. Also A::a is 'g': > 'normal global' for both. > > Michael, Andrew, Ulrich can you please give us some insight into the situation? > Does this seem like a compiler or linker bug on ARM, or is the code depending > on undefined behavior, or something different? I have pasted the used g++ > versions at the end of the email. > > Thanks, > Alexandros > > --- g++ x86_64 -- > Using built-in specs. > COLLECT_GCC=g++ > COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.6/lto-wrapper > Target: x86_64-linux-gnu > Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++,go --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --disable-werror --with-arch-32=i686 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu > Thread model: posix > gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2) > > --- g++ armhf -- > Using built-in specs. > COLLECT_GCC=g++ > COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/4.6/lto-wrapper > Target: arm-linux-gnueabihf > Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --enable-multilib --disable-sjlj-exceptions --with-arch=armv7-a --with-float=hard --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabihf --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf > Thread model: posix > gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2) >

13 years, 9 months

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Fwd: [ACTIVITY] w10

by Asa Sandahl

Hi! * Bug reports Made an effort clean up among the remaining not-triaged bug. Michael will help out with 941676, where the failure is on power-pc. * Wiki Created a wiki page for running benchmarks in cbuild: https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/RunningBenchmark… * V8 Build system has changed in V8 from SCones to GYP. With GYP I can pass the normal flags like CXXFLAGS to control the build, so this looks like a good change. I have created a cbuild make file, patterned after the other benchmark make files. Working on x86 sofar, will go for arm next week. Will also add a parser for the results. Regards Åsa

13 years, 9 months

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[ACTIVITY] Mar 5 - Mar 8

by Ulrich Weigand

== GCC == * Checked patch to generate usat/ssat instructions into Linaro GCC 4.6 and 4.7. * Submitted (first part of) fwprop-subreg patch for mainline. * Submitted Ira's vectorizer patches for mainline. * Ongoing work on improving end-of-loop value computation. * Patch review week. == Misc == * On leave 3/9 - 3/14. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

1
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Updates sysroots for binary toolchain

by Marcin Juszkiewicz

Hi Updated sysroots for binary toolchain are available at [1]. This time I split -dev and -dbg sysroots so as long as dbgsym are not needed less disk space is used. Please take a look at them and report any issues. 1. http://people.linaro.org/~hrw/generic-linux/sysroots/20120301/

13 years, 9 months

3
8
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Linaro toolchain and ARMv6

by ezjd

Hello, My name is Jiandong Zheng and am working on a few ARM specific projects. I have been using Linaro toolchain coming with Ubuntu to do Cortext-A9 building. I also need to maintain code for old ARM11 SoC so that Linaro toolchain is my preference and it did the job well back in Maverick days if I remember correctly. However, in Precise, I have troubles running this ARM11 u-boot and kernel built with Linaro toolchain, eventually I found that my old gcc 4.3.2 toolchain can still build workable u-boot and kernel so that Linaro toolchain (gcc 4.6.2) seems the problem. I understand that Linaro's focus has been ARMv7 or above but I am wondering if its toolchain can still be used for older ARM architectures. Thanks, JD

13 years, 9 months

4
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Bug triage of 941676

by Asa Sandahl

Hi Michael, A new bug triaging question. https://bugs.launchpad.net/ubuntu/+source/ppl/+bug/941676 This one is special too because the failure is on powerpc. This means, I cannot reproduce it easily, and scan through the toolchains (without building). Matthias has given some information and a guess of what is failing. My idea was to just summarize this, and let the person who takes on the bug make the powerpc investigation. How do we handle bugs on other architectures in general? Best regards Åsa

13 years, 9 months

2
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Bug triaging of 945503

by Asa Sandahl

Hi! I need a little help with triaging of this bug, it is a little different from the ones I have triaged so far: https://bugs.launchpad.net/launchpad/+bug/945503 - gcc-4.7 branch imports fail (timeouts) It is already set to Confirmed, my question is what is needed to go to the triaged stage? Also, the comments from wgrant and jelmer somewhat indicates that there is no problem. Best regards Åsa

13 years, 9 months

2
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Test failures due to directory names in the test farm

by Ulrich Weigand

Hello, since this long-standing problem just hit me again, I had a quick look at test failures in our farm that appear to occur whenever the directory name contains a string that is being checked for via a "scan-assembler" test, e.g.: +FAIL: gcc.target/arm/sat-1.c scan-assembler-times ssat 4 +FAIL: gcc.target/arm/sat-1.c scan-assembler-times usat 4 I had been assuming this happens because the directory name somehow finds its name into the assembler file, e.g. via a .file directive or DWARF data, and therefore an additional instance of the search string is being detected erroneously. However, when I attemted to re-create the scenario by building myself within a directory that has the same name, but on my local machine, the tests when through fine. And indeed, inspecting the assembler source shows that that there is no debug info at all; while there is a .file directive, it contains just the file base name without any directory name; and in fact the directory name does not show up at all within the assembler file. Something must still be different in the runs that take place on the build farm; but I currently do not understand what that might be. Michael, is there a way to interact with the build process on the build farm machines themselves to try and find out what's going on here? Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

3
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Bombing U-Boot on ARMv4, any hints?

by Linus Walleij

Hi toolchain folks, I have a problem with U-boot compiled for an ARMv4 system (Integrator) using Linaro 2012.02-20120222, it just crashes. Compiling the same U-Boot with CodeSourcery 2010-q1 works fine. Symptom: Resetting CPU ... undefined instruction pc : [<07fdecd4>] lr : [<07fdeb34>] sp : 07f91380 ip : 00000000 fp : 00000001 r10: 010258fc r9 : 00000000 r8 : 07f94f64 r7 : 07f94eb0 r6 : 00989680 r5 : 000186a0 r4 : 000186a0 r3 : 000003e8 r2 : 000f423f r1 : 000f4240 r0 : 05f5e100 Flags: nzCv IRQs on FIQs on Mode SVC_32 (repeated ad nauseam) The only hint I have is the constant 000186a0, which appears here in the put_dec() routine from U-boots vsprintf(), which is nothing special, it's Douglas Jones' binary to decimal conversion code from the Linux kernel, but the compiles objects DOES contain calls to __aeabi_uidivmod, __udivsi3, __div64_32. Do we know of any potential trouble in these helpers on ARMv4? The file containing these functions is compiled like this: arm-linux-gnueabi-gcc -M -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x01000000 -I/var/linus/u-boot/build-integrator/include2 -I/var/linus/u-boot/build-integrator/include -I/var/linus/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /home/linus/src/gcc-linaro-arm-linux-gnueabi-2012.02-20120222_linux/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv4 -MQ /var/linus/u-boot/build-integrator/lib/vsprintf.o vsprintf.c >/var/linus/u-boot/build-integrator/lib/.depend.vsprintf Yours, Linus Walleij

13 years, 9 months

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4.6 branch does not build

by Khem Raj

Hi FWIW the backport from trunk in r106872 breaks the gcc build Something like attached is missing from backport -- -Khem

13 years, 9 months

2
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[ACTIVITY] Feb 27 - Mar 2

by Thiago Jung Bauermann

Hi, GDB on Android: * Spent some time understanding the intricate build process used to compile NDK's gdbserver. * After a lot of tinkering and trial and error I was finally able to produce a gdbserver binary which when running on the Android emulator and talking to a GDB (also compiled by me) on the host is able to show all threads and provide a useful backtrace. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 9 months

1
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Launchpad tricks

by Michael Hope

Hi there. When you do a commit that fixes a bug, try adding a '--fixes lp:123456' to the bzr commit. Launchpad recognises these and automatically link the branch and merge request to the bug report. This makes it easier for the reporter to see progress. If you forget to update the bug status (such as bumping it from 'Triaged' to 'In progress') then it's obvious that it's being worked on. See https://bugs.launchpad.net/gcc-linaro/+bug/942307 for an example. The status was 'Triaged' but there's an approved merge request which shows work is being done. -- Michael

13 years, 9 months

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New conference call numbers

by Michael Hope

The new conference call numbers have arrived. Let's use them for today's call. The toll free numbers are: * Australia: 1 800 804 786 * China: +400 120 05 90 * Germany: 01801 003 899 * New Zealand: 0800 452 947 * Sweden: 0200 125 588 * UK: 0845 351 2782 * USA: 1-866-398-2885 Alternates, including cheaper (for Linaro) local numbers are: * International toll free - Germany: 0800 588 9170 * International toll free - UK: 0800 358 6385 * Local - Australia, Sydney: +61 (0) 2 8017 6064 * Local - Brazil, Rio de Janeiro: +55 21 4063 8292 * Local - Brazil, Sao Paulo: +55 11 3351 7036 * Local - China, Beijing: +86 10 5904 5041 * Local - Germany, Frankfurt: +49 (0) 69 2222 10612 * Local - Germany, Munich: +49 (0) 89 2030 31207 * Local - Sweden, Stockholm: +46 (0) 8 5065 3956 * Local - UK, London: +44 (0) 20 3481 0123 * Local - UK, Reading: +44 (0) 11 8370 0116 * USA Toll: 1-719-457-6209 A temporary full list is at: https://wiki.linaro.org/MichaelHope/Sandbox/ZipNumbers I'll update the invite. -- Michael

13 years, 9 months

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[ACTIVITY] 27th February - 2nd March

by Andrew Stubbs

Merged FSF GCC 4.7 to the Linaro GCC 4.7 branch. Merged from GCC 4.6.3 release to Linaro GCC 4.6 branch. Wrote and posted a patch to load DImode immediate constant into NEON registers properly. Unfortunately, testing showed a bootstrap stage 2 vs. 3 miscompare, so there's something not quite right. However, disassembly of the binaries hasn't revealed any problems, so this failure is still a mystery. More investigation required. Wrote and posted a patch to do DImode negation in NEON. Realised that I had forgotten to do the core-register fall-back case; posted a new version. Again, there's something annoyingly subtle that prevents bootstrap. This time it looks like some sort of wrong code bug. Investigating. Wrote and posted a patch to do DImode one's complement in NEON. Richard E questioned how it was written though. The tests passed successfully, so that's a novelty this week! Looked for other NEON instructions missing support. Didn't find any ... but the machine description isn't exactly straight forward. Considered the problems with choosing whether or not to do an operation in NEON, or not. Discussed the existing state and possible solutions with Ramana and Benrd (thanks Guys). Thought about it some more. Posted a vague description of what might fix it to the linaro-toolchain list. Awaiting replies.

13 years, 9 months

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[ACTIVITY] w09

by Asa Sandahl

Hi! * Development benchmarks: Finished the first implementation, sent to Michael for review. * This became a very short week because of sickness. Plans for week 10 is to triage existing bugs, and to get going again with the SunSpider benchmark. Regards Åsa

13 years, 9 months

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[Activity ] Week 9

by Zhenqiang Chen

Summary: * Multilib on linaro toolchain. Details: 1. Multilib test for linaro toolchain. * Fix the multilib build issue when multiarch patch is applied. * Fix a bug in crosstool-ng upstream to build multilib for glibc/eglibc. * Successfully build multilib toolchain for armv6t2, cortex-a8 and cortex-a9. And tests show it can link the correct libraries. 2. Still issues: * Multilib and multiarch uses different directory structures. Multilib build can not find the correct directories in the prebuilt oneiric-sysroot. * Build armv5t arm mode lib when default mode is thumb for armv7-a. Annual leaves: * Mar. 1-2. Plans: * Finalize the multilib solution for linaro binary toolchain. * Work on code size optimization for the embedded toolchain. Best regards! -Zhenqiang

13 years, 9 months

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Re: [RFC] NEON vs. ARM register selection

by Steven Bosscher

> The basic idea is that we add a new RTL optimization pass (or two) that > assesses the usage of pseudo registers, and makes recommendations about > what register class each should end up in, if there's a choice. These > recommendations would then be used by later passes to get a better use > of NEON. I might call this the "prealloc" pass, or something. That sounds very much like the pre-reload that "new-ra" had at one point (http://gcc.gnu.org/viewcvs/branches/new-regalloc-branch/gcc/pre-reload.c). The problem with pre-reload for new-ra was that it was basically reload instead of something nicer and cleaner. It also only ran just before the register allocator, which is too late for the problem you are trying to solve. > Firstly, for each pseudo-register in a function, the pass would look at > the insn constraints for each "def" and "use", and see how the registers > relate to one another. This might determine things like "if rN is in > class A, then rM must be also in class A". At SUSE I tried to do this with the webizer pass (web.c). I wrote down the ideas we implemented at the time (see http://gcc.gnu.org/ml/gcc/2005-01/msg00179.html): - web class, to replace regclass and choose register classes webs instead of pseudos. This also includes splitting webs if a register in a web really wants to be in two different classes to satisfy constraints in two different insns. Right now, as far as I understand, regclass just picks one and lets reload figure out how to fix up that mistake. - A semi-strict RTL mode. Right now there is just strict and non-strict. On the branch there is a semi-strict mode which is the same as strict RTL except that pseudo-registers are still allowed. - pre-reload (which is related to web class) to make sure as many insn constraints as possible are satisfied before the register allocator goes to work. Basically, after pre-reload the insns stream should be in semi-strict RTL form. I used the webizer to unify defs and uses. I would split a web if it needed multiple register classes (I inserted a mov, without checking that a move existed from the source to the target register class), and I put pseudos r1 and r2 in the same register class if there was an insn (set (r1) (r2)) somewhere. The selection of the register classes had a cost function, but I used rtx_cost, which is not very effective, really. But I never took this experiment very far because for x86-64 the plan didn't work as well as I had hoped. I don't remember the details, but the biggest problem I had with the experimental implementation of these ideas (apart from lots of trouble with recog for semi-strict RTL) was that there is a bit of an ordering problem between combine on the one hand, and web-based register classes. If you assign classes too early and don't allow things to change, then combine fails too often. If you assign register classes after combine, you may not get the instructions selected the way you want them to be. This was when GCC still had the old local-alloc.c and global.c allocators. Things may be different (better) with IRA and the upcoming LRA stuff. If you plan to work on this, I would suggest you discuss the plan on the GCC mailing list also, with Jeff Law and Vladimir Makarov in CC because they are working on a reload rewrite (LRA). Ciao! Steven

13 years, 9 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, OpenEmbedded: * Worked on the meta-linaro layer and added libgcc and crosssdk recipes to satisfy some bitbake dependencies * I had to apply a few patches to build the linaro toolchain the OE way (mostly gcc configury) * successfully built the sato and Qt images * Moved on to test the February release of the linaro binary toolchain and (probably) and hit an issue with unaligned SD card images to used with QEMU * the guest kernel fails with: attempt to access beyond end of device * /proc/partitions shows different block sizes (host vs. guest) * the image size gets calculated on the fly by OE * patch posted that introduces allows to specify a rootfs size alignment * not seen on trunk as they use IDE * Started to rebase the linaro-meta layer against current OE-core * created https://wiki.linaro.org/KenWerner/Sandbox/OEMetaLinaroCard based on the existent card of David R. Regards, Ken

13 years, 9 months

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[ACTIVITY] Feb 27 - Mar 2

by Ulrich Weigand

== GCC == * Fixed mainline regression causing ICE in certain outer-loop vectorization cases. * Merged fwprop-subreg patch into Linaro GCC 4.7. * Completed patch to generate usat/ssat instructions where appropriate; checked into GCC mainline. Merge requests to Linaro GCC 4.6 and 4.7 pending. * Ongoing work on improving end-of-loop value computation. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

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[Activity ] Week 9

by Ramana Radhakrishnan

==Progress=== * Finished off PGO patch - sent upstream. * Finished off the ABI tests - sent upstream. * Investigated fixes for LP 942307 - a problem with kernel builds for android. Backported a fix from Uli last year. * Upstream patch review. * Small configury done for SPEC2k as far as HC partitioning goes. * Some Android benchmark investigations. * Recovered from a broken upgrade on my laptop from natty to oneiric on my laptop and then went all the way to Precise. It works reasonably ! === Plans === * Commit all approved and tested patches. * Check on hc partitioning results from SPEC2k and make sure there is an improvement and the feature works ! * Investigate https://bugs.launchpad.net/gcc-linaro/+bug/924726 in a little more detail. * Get back to partial-partial PRE. Absences. * 1 week holiday sometime before that - to be booked. * Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.

13 years, 9 months

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Agenda for next performance call

by Ramana Radhakrishnan

is now here https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-03-06 Please add any topics that you might consider interesting for next time. Ramana

13 years, 9 months

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[ACTIVITY] report week 09

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-??-?? || || (new blueprints & reestimate for this one pending) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * ploughing through conversion of cp15 registers to new design: patchset now 20 patches long, still TODO crn={0,1,6,7,9} == other == * reviewed more Xilinx Zynq model patches * looking at BE8 support: Paul Brook has posted some patches to support this in user mode * LP:944645: fixed bug where we weren't clearing the IT bits when entering an M profile exception handler * sent out an arm-devs.next pullreq * trying to track down why linux-user is failing brk() and thus causing bash segfaults

13 years, 9 months

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[RFC] NEON vs. ARM register selection

by Andrew Stubbs

Hi All, As you know, the compiler currently has difficulties choosing between whether to do an operation in NEON or not. As I see it there are three problems: 1. Simply, is it profitable? NEON can do many DImode operations in one or two instructions where 2 to 10 normal ARM/Thumb instructions would be required (not to mention the added register pressure), but there is a cost associated with moving the inputs to NEON, and the results back. If the data can stay in NEON for more than one operation, then that's even better. If the data must be loaded from memory, and the result stored back to memory, then it's only a question of whether the register space is available, or not. Currently these decisions are made in the IRA/reload passes. 2. Values that originate in hard-registers stay there. This applies to function parameters, mostly, but also in general where the result of an operation is allocated first. If there is no instruction that can use the value there then the value is 'reloaded' to a more suitable register. If there is any alternative that avoids the move then the register allocator will use it, regardless of the relatives costs of the other alternatives. This problem is reduced where an operation and move can happen in one instruction, but NEON instructions do not do this much. We can write insns that appear to do it, but these output multiple instructions (see my recent core-SI=>NEON-DI extend patch). 3. It all happens too late. The decision whether to use NEON or not is not made until register allocation time. Naturally this means that most of the optimization passes are already completed. Part of the problem is that the operation almost certainly needs splitting (into whatever form was chosen) and this might not be straight forward, post-reload. (However, the split1 pass is already quite late, so perhaps this isn't such a big deal.) Another part of the problem is that passes such as the two lower-subreg passes make assumptions about the register width which are not accurate if the operation is to end up in NEON. There are other, lesser problems, such as it being hard to adjust the costs for different cores (A8 in particular) and the cost of generating an immediate constant can't be known until it's known what instructions will be used to generate it. These problems are not specific to NEON, of course. I believe IWMMXT suffers from the same issues. Likewise the C6X port, and also the i386 MMX to some degree. Anything that has instructions that only operate on a subset of registers, basically. So, Bernd has suggested an outline of a solution. I've quizzed him on this, added a few of my own ideas, and probably a good selection of misunderstandings, bad assumptions, and general cock ups, and come up with something I can write here for comment. I can post something to upstream later if it doesn't get totally shot down now. The basic idea is that we add a new RTL optimization pass (or two) that assesses the usage of pseudo registers, and makes recommendations about what register class each should end up in, if there's a choice. These recommendations would then be used by later passes to get a better use of NEON. I might call this the "prealloc" pass, or something. Firstly, for each pseudo-register in a function, the pass would look at the insn constraints for each "def" and "use", and see how the registers relate to one another. This might determine things like "if rN is in class A, then rM must be also in class A". E.g. if you have two registers with constraints like this: "r,w" "r,w" .. (and 'r' and 'w' do not overlap) then you know that there is a choice between one mode or another, whereas this: "r,w,r,w" "r,w,w,r" .. would impose no restrictions and we can carry on as normal. Having done that we'd end up with sets of pseudo-registers that must make a decision one way or the other, and we'd know where the operations are that would force a move from one class to the other. There's a fair amount of handwavium in there at present, because I've not worked out what to do with overlapping register classes (think VFP_LO_REGS) and all the other complications. Secondly, the pass would consider the costs of each alternative, and store a recommended register class for each pseudo-register in a table somewhere. It would also create new pseudos and insert extra move instructions at the register file boundaries where an existing register would have had split recommendations (this would solve problem 2 above). Again, there's handwavium in "consider the costs". This isn't too hard for size-optimization (assuming the "length" attributes on the insn is correct), but more difficult for speed optimization. Factors to include would be the move costs (here the A8 issues would be addresses) and the relative speeds of the operations in both alternatives. Also, the various possible transition points between the two modes might need some comparisons. Thirdly, the subsequent passes would need to be modified, as would some of the back-end bits and bobs. 1. Lower-subreg would need to detect 'word_mode' based on the recommended register class, not the global value. 2. The many split patterns in the machine description could be adjusted so that, instead of simply conditionalizing on "reload_completed", they split at split1 if that's the best option. (Maybe it would be profitable to insert a new, earlier split pass specifically for this case to take advantage of the likes of combine? I mean, ideally this decision would have been made at expand time, if it could have been?) It might be useful to *not* split too soon, in some cases, so that the register allocator can still make the final decision based on register pressure, and whatever other factors it uses. Of course, the existing late-split option would need to be retained in case the prealloc pass is disabled, in any case. 3. Various passes would have to be taught not to remove seemingly superfluous register moves where they actually move between register classes. 4. Pretty much nothing would need doing to register allocation! The extra moves should make allocation a register pressure management issue, rather than a question of making it work. DImode operations preallocated to core-registers may already have been lowered, one way or the other (by split1) so there's no decision left there, and if no lowering was necessary then that option ought to be obviously cheaper. If it insists on making contrary decisions then it can be taught to use the recommendation as a hint, perhaps? In specific problem cases it would also be possible to use instruction attributes to disable (or strongly discourage) certain alternatives based on the recommended class. 5. The existing 'onlya8'/'nota8' nonsense can be removed. 6. The register move cost can be set correctly for each core. 7. If a constant is destined for a NEON register, most likely, arm_gen_constant can use the NEON immediate rules to determine the cost. There's clearly a lot of thought that needs to go into the pseudo-register scan and decision making logic, but the whole thing doesn't look like it'll boil down to very much code in the end. There's also the question of where to put the pass? Too early and you'd need to put a second one in to reassess the much changed RTL later, and too late and lower-subreg won't be able to use it. It's possible that it might be better to treat it more like the data-flow analysis where it's not actually a stand-alone pass, but rather a tool other passes can use? That might depend how computationally expensive it is. Any thoughts anyone? Might something like this actually work? Would it be worth spending the time on this? Andrew

13 years, 9 months

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lp:gcc/4.7

by Andrew Stubbs

Hi Matthias, GCC 4.7.0 has branched upstream. SVN trunk is now 4.8. Could you please create lp:gcc/4.7 from the release branch. Thanks Andrew

13 years, 9 months

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Please pull upstream rev. 184603 into gcc-linaro 4.7

by Bernhard Rosenkränzer

Hi, 184603 fixes an ICE we're running into with Android test builds. Please pull it in ASAP so I don't have to mess with the CFLAGS as a workaround. ttyl bero

13 years, 9 months

2
2
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Cross toolchain for lucid updated

by Marcin Juszkiewicz

Linaro cross toolchain backport PPA [1] got updated to recent Ubuntu 12.04 versions: - gcc 4.5.3 - gcc 4.6.2 - binutils 2.22 - eglibc 2.15 - linux 3.2 I tested both compiler versions against few packages, U-Boot and Linux 2.6.32. Those packages may also work under Ubuntu 10.10 'maverick' and 11.04 'natty' but it was not tested. Users of Ubuntu 11.10 'oneiric' may install libmpfr1ldbl package [2] and then use 'lucid' repository to install cross compiler while I will prepare packages for their version of Ubuntu. Please report any problems with those backported packages in launchpad [3][4][5]. 1. https://launchpad.net/~linaro-maintainers/+archive/toolchain 2. http://packages.ubuntu.com/lucid/libmpfr1ldbl 3. https://launchpad.net/ubuntu/+source/gcc-4.5-armel-cross/+bugs 4. https://launchpad.net/ubuntu/+source/gcc-4.5-armel-cross/+bugs 5. https://launchpad.net/ubuntu/+source/armel-cross-toolchain-base/+bugs

13 years, 9 months

1
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Status call number is unchanged

by Michael Hope

No news yet on the new conference call numbers. Let's see if the old numbers still work. -- Michael

13 years, 9 months

1
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Spec 2000 broken?

by Andrew Stubbs

Hi Michael, I ran the benchmark tests on GCC 4.7, but the spec2000 run seems to have failed. This is both on the baseline, and on my patch. See here: http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.7%2bbzr114968~ams-codesou… Andrew

13 years, 9 months

2
2
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Saturated operations

by Michael Hope

Hi Ulrich. The saturated work you're doing at the moment - is it the saturated add/subtract QADD/QSUB/QDADD/QDSUB or the ARMv6 saturate-word-with-shift SSAT/USAT? I've updated the old blueprint and added a new one for SSAT/USAT: https://blueprints.launchpad.net/gcc-linaro/+spec/armv6-saturation-instruct… https://blueprints.launchpad.net/gcc-linaro/+spec/armv5-saturated-ops and was wondering which to put against your name. -- Michael

13 years, 9 months

2
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Fleshing out the QEMU blueprints

by Michael Hope

Hi Peter, Rusty. I've fleshed out the KVM blueprints a bit more at: https://wiki.linaro.org/MichaelHope/Sandbox/Q1.12ToDo Notable is adding validation and de-PENDING a few things. I need to know the following things before talking to Validation and Platforms about things that are in their queue: * What's the host kernel? Christoffers, or a linux-linaro-kvm based off his plus work in progress? * What's the guest kernel? * Anything special that needs to be in the host rootfs outside qemu and libvirt? Do you have a host and guest kernel .config that I can pass on to Platforms? -- Michael

13 years, 9 months

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[ACTIVITY] Feb 20 - Feb 24

by Thiago Jung Bauermann

Hi, GDB on Android: * Set up cross compiling environment using both the Android toolchain and the Linaro toolchain. * Tested Android and Mozilla GDB running as a native binary on the Linaro Android image on qemu. None of them were able to see all threads in a multi-threaded process. The same happens with a native binary on Android talking to a gdbserver on localhost. * I was able to produce an Android GDB 7.1.x binary which when running on an i386 host talking to the Android SDK emulator sees all threads. It is not able to generate a backtrace though. * Carnival holidays. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 9 months

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[ACTIVITY] 20th - 24th February

by Andrew Stubbs

Investigated and produced and patch for bug lp936863. Continued work on 64-bit shifts. I updated my neon shifts patch twice: once to take -Os optimization into account, and once because I noticed that the CC clobbers were being retained even after they were known to be not required, and presumably this could be a bad thing. Posted a patch to improve SI->DImode sign- and zero-extends that also move values from core registers to neon registers. Wrote a patch to implement negation in neon register, albeit at the cost of a scratch register to hold the constant zero. This worked, but insisted on loading the zero from memory, despite the fact that NEON has a suitable instruction for loading zero. Attempted to get "vmov dN, #0" to work. The problem appears to be that DImode loads are handled by the VFP load pattern in vfp.md and that that doesn't seem to DTRT for integer constants. I've got as far as trying to figure out what it does do, but there's more to be done to get to the bottom of the problem. Tried to get the benchmarking going for 64-bit shifts. Unfortunately ursa1 has been experiencing outages. Michael has been trying to fix it, but so far I've not been able to run anything there. Instead, I've launched benchmark runs via Michael's normal test infrastructure. Hopefully this can replace the manual ones anyway. That would be more convenient.

13 years, 9 months

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Running pre-built linaro toolchain failed on Ubuntu 11.04, 64bit server

by Lv Terry-R65388

Hi, I'm trying to use pre-built version of linaro toolchain for cross-compiler in Ubuntu 11.04 on our 64bit server. I got it from http://people.linaro.org/~michaelh/incoming/binaries/. When I run arm-linux-gnueabi-gcc to compile a c source, it says "No such file or directory". The steps are as below: 1. Unpack gcc-linaro-arm-linux-gnueabi-2011.12-20111219+bzr2309~linux.tar.bz2. 2. Rename gcc-linaro-arm-linux-gnueabi-2011.12-20111219+bzr2309~linux to arm-fsl-linux-gnueabi. 3. Copy to ~/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/ 2. Use arm-linux-gnueabi-gcc to compile my code. The output is: r65388@shlinux3:~/MEMCPYBM$ ~/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/arm-fsl-linux-gnueabi/bin/arm-linux-gnueabi-gcc -bash: /home/r65388/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/arm-fsl-linux-gnueabi/bin/arm-linux-gnueabi-gcc: No such file or directory I have installed lsb 4.0 and libc6 2.13. r65388@shlinux3:~/MEMCPYBM$ dpkg -s lsb Package: lsb Status: install ok installed Priority: extra Section: misc Installed-Size: 48 Maintainer: Ubuntu Developers <ubuntu-devel-discuss(a)lists.ubuntu.com> Architecture: all Version: 4.0-0ubuntu16 ... r65388@shlinux3:~/MEMCPYBM$ dpkg -s libc6-dev Package: libc6-dev Status: install ok installed Multi-Arch: same Priority: optional Section: libdevel Installed-Size: 11888 Maintainer: Ubuntu Developers <ubuntu-devel-discuss(a)lists.ubuntu.com> Architecture: amd64 Source: eglibc Version: 2.13-20ubuntu5 Provides: libc-dev Depends: libc6 (= 2.13-20ubuntu5), libc-dev-bin (= 2.13-20ubuntu5), linux-libc-dev Recommends: gcc | c-compiler Suggests: glibc-doc, manpages-dev Breaks: binutils (<< 2.20.1-1), binutils-gold (<< 2.20.1-11), cmake (<< 2.8.4+dfsg.1-5), gcc-4.4 (<< 4.4.6-3ubuntu1), gcc-4.4-base (<< 4.4.6-3ubuntu1), gcc-4.5 (<< 4.5.3-1ubuntu2), gcc-4.5-base (<< 4.5.3-1ubuntu2), gcc-4.6 (<< 4.6.0-12), gcj-4.4-base (<< 4.4.6-2ubuntu2), gcj-4.5-base (<< 4.5.3-1ubuntu2), gnat-4.4-base (<< 4.4.6-1ubuntu3), libhwloc-dev (<< 1.2-3), libjna-java (<< 3.2.7-4), liblouis-dev (<< 2.3.0-2), liblouisxml-dev (<< 2.4.0-2), make (<< 3.81-8.1), pkg-config (<< 0.26-1) ... Do you know why? How can I fix this issue? Thanks~~ Yours Terry

13 years, 9 months

3
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[Activity] Week 8

by Zhenqiang Chen

Summary: * Linaro binary toolchain 2012.02 release. * Try the Multilib patch on linaro toolchain. Details: 1. Linaro binary toolchain 2012.02 release. * Create linaro license file based on embedded toolchain, add crosstool-ng and sysroot (eglibc) license. * Tests on win7, oneiric and RHEL5. 2. Try to apply the multilib patch used in embedded toolchain to linaro toolchain. * The multilib solution can not work together with the multiarch patch. (1) With both patches, "gcc -print-multi-lib" can only print one option. (2) With only multilib patch, "gcc -print-multi-lib" can print the multilib list. * Successfully build a multilib toolchain (Based on the prebuilt oneiric-sysroot with directory structure change for include and lib.) without the multiarch patch and c++ support. Plans: 1. Try crosstool-ng 1.14 to build multilib eglibc. 2. Investigate how to make multiarch and multilib work together. Planed leaves: * Mar. 1-2. Best regards! -Zhenqiang

13 years, 9 months

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KVM blueprints

by Michael Hope

Hi Peter, Rusty. I've written down my notes from Connect and drafted the blueprints at: https://wiki.linaro.org/MichaelHope/Sandbox/Q1.12ToDo I've put my priories on things and sorted them by relative importance. I'll check tomorrow if there's a good match between this, the KVMEpic spec, and the older task spreadsheet. Most of these are too short. I don't know what's involved with the CP15 work. Some still have big PENDINGS. Please edit and correct. There's a lot of work there. Some is on other teams but I'm concerned. -- Michael

13 years, 9 months

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[ACTIVITY] Feb 20 - Feb 24

by Ulrich Weigand

== GCC == * Merged Ira's remaining vectorizer patches into Linaro GCC 4.7. * Merged Richard's sched-pressure patch (enabled by default on ARM) into Linaro GCC 4.7. Asked IBM colleagues for benchmark results on s390 and rs6000 as well. * Committed patch to enable vect_condition tests in FSF mainline, FSF 4.6, and Linaro GCC 4.7. * Verified that Linaro GCC 4.7 now contains every feature that was present in Linaro GCC 4.6. * Rebased and re-benchmarked fwprop-subreg patch. * Ongoing work on a patch to generate usat/ssat instructions where appropriate. * Worked on improving end-of-loop value computation. * Fixed mainline .init_array/.fini_array regression on certain newlib targets. * Reviewed several merge requests. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

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[Activity] Week 8

by Ramana Radhakrishnan

On holiday last week and at connect week before that. ==Progress=== * Recovered from jet-lag and started to catch up on email. * Patch review week. * Cleared out a bit of my patch backlog. * Helped Asa with some bug triaging. * Read up a bit about ssat and usat and what we should be doing with other tuning for them. * Looked up some performance profiles with v8 benchmarks . Reviewed the Android benchmark numbers. * Booked tickets for connect 2012.q2 * Wrote up connect week discussions on libav regressions . === Plans === * Clear out more pending patches ( PGO next on the hit list and the vmla investigation) * Investigate partial-partial PRE results. * Finish off the ABI tests. Absences. * 1 week holiday sometime before that - to be booked. * Linaro Connect Q2.12 - May 28 - June 1

13 years, 9 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, OpenEmbedded: * added initial support for the Linaro GCC 4.6 based toolchain to the meta-linaro layer. * allows to build the Linaro toolchain the OE way * successfully built the core-image-sato but when running inside QEMU the GUI isn't usable (needs investigation) glibc: * built glibc+glibc-ports natively on ARM * the upstream glibc testsuite isn't aware of the multiarch paths and therefore it won't find some libs (libgcc_s, libstdc++) * workaround using symlinks; wiki updated: https://wiki.linaro.org/KenWerner/Sandbox/HowToBuildToolchainComponents#gli… Regards, Ken

13 years, 9 months

1
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Re: gcc: Thumb interworking and weakly linked functions

by V, Aneesh

+ linaro-toolchain Hello Ulrich, I want to revisit this old thread. Sorry for the sloppy follow-up. But, this time around I have more data. On Tue, Mar 15, 2011 at 9:00 PM, Ulrich Weigand <Ulrich.Weigand(a)de.ibm.com> wrote: > Aneesh V <aneesh(a)ti.com> wrote: > >> I was trying to build u-boot in Thumb2 for OMAP4. Everything was fine >> until I added some patches recently. One of these patches introduced an >> API (let's say foo()) that has a weakly linked alias(let's say >> __foo()) and a strongly linked implementation(the real foo()) in an >> assembly file. >> >> Although I give -mthumb and -mthumb-interwork for all the files, >> apparently GCC generates ARM code for assembly files. In the final >> image foobar() calls foo() using a BL. Since foobar() is in Thumb and >> foo() in ARM, it ends up crashing. Looks like foobar() assumed foo() >> to be Thumb because __foo() is Thumb. > > I'm unable to reproduce this. Do you have a complete test case? > > I've tried with the following small example: > > foo1.c: > > extern void foo (void) __attribute__ ((weak, alias ("__foo"))); > > void __foo (void) > { > } > > int main (void) > { > foo (); > } > > foo2.S: > .text > .align 2 > .global foo > .type foo, %function > foo: > push {r7} > add r7, sp, #0 > mov sp, r7 > pop {r7} > bx lr > .size foo, .-foo > > When building just "gcc foo1.c", I get: > > 0000835c <__foo>: > 835c: b480 push {r7} > 835e: af00 add r7, sp, #0 > 8360: 46bd mov sp, r7 > 8362: bc80 pop {r7} > 8364: 4770 bx lr > 8366: bf00 nop > > 00008368 <main>: > 8368: b580 push {r7, lr} > 836a: af00 add r7, sp, #0 > 836c: f7ff fff6 bl 835c <__foo> > 8370: 4618 mov r0, r3 > 8372: bd80 pop {r7, pc} > > When building both files "gcc foo1.c foo2.S", I get instead: > > 00008368 <main>: > 8368: b580 push {r7, lr} > 836a: af00 add r7, sp, #0 > 836c: f000 e802 blx 8374 <foo> > 8370: 4618 mov r0, r3 > 8372: bd80 pop {r7, pc} > > 00008374 <foo>: > 8374: e92d0080 push {r7} > 8378: e28d7000 add r7, sp, #0 > 837c: e1a0d007 mov sp, r7 > 8380: e8bd0080 pop {r7} > 8384: e12fff1e bx lr > > > So it seems to me the linker is handling this correctly ... > > (This is on Ubuntu Natty using system gcc and binutils.) I could reproduce the problem on older tool-chain(Sourcery G++ Lite 2010q1-202) [1] with a modified version of your sample code: a.c: ==== extern void foo (void) __attribute__ ((weak, alias ("__foo"))); void __foo (void) { } extern void call_foo(void); int main (void) { call_foo (); } b.S: ==== .text .align 2 .global foo foo: push {r7} add r7, sp, #0 mov sp, r7 pop {r7} bx lr .size foo, .-foo c.S .text .align 2 .global call_foo call_foo: bl foo bx lr .global __aeabi_unwind_cpp_pr0 __aeabi_unwind_cpp_pr0: bx lr Now, I build them using the following commands, which is similar to what U-Boot does: arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c a.c arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c b.S arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c c.S arm-none-linux-gnueabi-ld -r a.o -o alib.o arm-none-linux-gnueabi-ld -r b.o -o blib.o arm-none-linux-gnueabi-ld -r c.o -o clib.o arm-none-linux-gnueabi-ld --start-group clib.o alib.o blib.o --end-group -o a.out armobjdump -S --reloc a.out You will get something like: 00008094 <call_foo>: 8094: fa000006 blx 80b4 <foo> 8098: e12fff1e bx lr Please note that that the 'blx' is not correct. Now, do the following change: diff --git a/b.S b/b.S index e0f2de9..96dba1f 100644 --- a/b.S +++ b/b.S @@ -1,5 +1,6 @@ .text .align 2 +.type foo, %function .global foo foo: push {r7} And build it again the same way and you will see: 00008094 <call_foo>: 8094: eb000006 bl 80b4 <foo> 8098: e12fff1e bx lr I can't reproduce this on Linaro GCC 2012.01, so looks like the problem is solved in recent tool-chains. However, sadly I could reproduce a different but similar problem with Linaro GCC 2012.01. This time the call is from C(Thumb) to assembly(ARM) and no weakly linked symbols are involved. a.c: ==== int main (void) { foo (); } b.S: ==== .text .align 2 .global foo foo: push {r7} add r7, sp, #0 mov sp, r7 pop {r7} bx lr .size foo, .-foo .global __aeabi_unwind_cpp_pr0 __aeabi_unwind_cpp_pr0: bx lr arm-linux-gnueabi-gcc -mthumb -mthumb-interwork -c a.c arm-linux-gnueabi-gcc -mthumb -mthumb-interwork -c b.S arm-linux-gnueabi-ld -r a.o -o alib.o arm-linux-gnueabi-ld -r b.o -o blib.o arm-linux-gnueabi-ld --start-group alib.o blib.o --end-group -o a.out arm-linux-gnueabi-objdump -S --reloc a.out gives: 8076: af00 add r7, sp, #0 8078: f000 f802 bl 8080 <foo> 807c: 4618 mov r0, r3 It should have been "blx 8080 <foo>", isn't it? Again, %function solves it. I agree that not marking the assembly functions ' %function' is a problem in the code, so it's not a critical bug. But I would've been happier if the linker refused to link it rather than branching with the wrong instruction. Isn't that a problem? Problem No:2 ************* Linaro GCC 2012.01 is giving a new problem w.r.to Thumb build that is not existing in Sourcery G++ Lite 2010q1-202. However, I couldn't reproduce this problem with a small program like above. So, let me give you reference to the original u-boot code that shows the problem and steps to reproduce it. tree: git://github.com/aneeshv/u-boot.git branch: thumb The above branch has mainline u-boot with 4 additional patches from me for enabling Thumb build. You can build it like this: make CROSS_COMPILE=arm-linux-gnueabi- ARCH=arm distclean make CROSS_COMPILE=arm-linux-gnueabi- ARCH=arm omap4_sdp4430 This builds two images u-boot and u-boot-spl. SPL is a tiny u-boot that runs from internal RAM and loads the u-boot to SDRAM. Now, please have a look at the map file of u-boot-spl which is at: spl/u-boot-spl.map I see the following in my map file: /spl/u-boot-spl.map: ================= .rodata.wkup_padconf_array_essential_4460 0x40309583 0x4 board/ti/sdp4430/libsdp4430.o 0x40309583 wkup_padconf_array_essential_4460 .rodata.wkup_padconf_array_essential 0x40309587 0xc board/ti/sdp4430/libsdp4430.o 0x40309587 wkup_padconf_array_essential .rodata.core_padconf_array_essential 0x40309593 0x60 board/ti/sdp4430/libsdp4430.o 0x40309593 core_padconf_array_essential Please note that the .rodata symbols have odd addresses. These arrays actually need to be aligned at least to half-word boundary. In fact, in the image I verified that they are put at even addresses. So, the symbols have been kept as real address +1. I understand that this is the convention for Thumb functions. I guess the tool-chain did it for data too?? And I am getting unaligned access aborts on accessing them. I notice that this doesn't happen with all .rodata. symbols in the image. I couldn't see any difference between working and non-working files nor any difference in the command used to build them! Well, this doesn't happen if I don't use "-fdata-sections" in gcc options. So, apply the following patch and you will see that those symbols have even addresses now. diff --git a/config.mk b/config.mk index ddaa477..723286a 100644 --- a/config.mk +++ b/config.mk @@ -190,7 +190,7 @@ CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ # Enable garbage collection of un-used sections for SPL ifeq ($(CONFIG_SPL_BUILD),y) -CPPFLAGS += -ffunction-sections -fdata-sections +CPPFLAGS += -ffunction-sections LDFLAGS_FINAL += --gc-sections endif /spl/u-boot-spl.map: ================= .rodata 0x40309204 0x38c board/ti/sdp4430/libsdp4430.o 0x40309204 core_padconf_array_essential 0x40309264 wkup_padconf_array_essential 0x40309270 wkup_padconf_array_essential_4460 0x40309274 core_padconf_array_non_essential 0x40309540 wkup_padconf_array_non_essential 0x40309588 wkup_padconf_array_non_essential_4430 Will you be able to look into these? Thanks, Aneesh [1] Sourcery G++ Lite 2010q1-202 arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2010q1-202) 4.4.1 GNU ld (Sourcery G++ Lite 2010q1-202) - binutils 2.19.51.20090709 [2] Linaro 4.6-2012.01 arm-linux-gnueabi-gcc (crosstool-NG linaro-1.13.1-2012.01-20120125 - Linaro GCC 2012.01) 4.6.3 20120105 (prerelease) GNU ld (crosstool-NG linaro-1.13.1-2012.01-20120125 - Linaro GCC 2012.01) 2.22

13 years, 9 months

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[ACTIVITY] w08

by Asa Sandahl

Hi! * Development benchmarks: Focused on the implementation of development benchmarks in the cbuild system. Discussed with Michael about how the comments should look. I am now testing my solution in the launchpad staging area. You can see a link to an example of a benchmark result comment below. (Should not be a double comment of course, and the actual result files are only stored on my machine for now.) https://code.staging.launchpad.net/~ramana/gcc-linaro/partial_partial_pre_t… The real benchmark names are not mentioned, since that might be sensitive. * Bug reports I got an action on Monday's meeting to investigate if https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/926855 is the same as PR52294. Investigated with help from Ramana and updated the ticket. Regards Åsa

13 years, 9 months

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[ACTIVITY] report week 08

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-??-?? || || (new blueprints & reestimate for this one pending Michael H's writeup/etc) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * figuring out how various suggestions/conversations on this from Connect ought to fit together == other == * LP:928580 recent u-boot not booting on QEMU beagle: tracked this down to a u-boot bug and passed to John Rigby * investigated a linux-user segfault deadlock which turns out to be because the guest program is using setrlimit to restrict memory usage and one of qemu's internal memory allocations then fails. Not clear how best to fix but was able to nack the suggested patch... * most of the patches for passing a device tree to the kernel from qemu (via -dtb option) are now upstream; rebased the final patch which should now go in soon I think * LP885239 qemu-linaro broke booting of zaurus models: fixed a bug where a trustzone support patch had broken some cp15 registers for xscale cpus * minor patch: fixed formatting of list of supported machines help text * fix an embarrassing segfault bug in a patch of mine committed last week * it turns out that we can detect at compile time whether glibc's makecontext() is an always-fails stub : sent configure patch to do this * travel mostly set up for connect Q2.12 * lots of meetings/training: toolchain call; standup; 1-2-1; project management training; comms meeting

13 years, 9 months

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Cortex-A8 benchmark machine

by Michael Hope

I've added a Cortex-A8 benchmark machine to my home office. The machine is called 'nova1' and is part of the cbuild a8-ref queue. Feel free to give it jobs: http://ex.seabright.co.nz/helpers/scheduler/spawn -- Michael

13 years, 9 months

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[ACTIVITY] Feb 13 - Feb 17

by Thiago Jung Bauermann

Hi, GDB on Android exploration: * Familiarizing myself with the Android SDK and NDK, and the Android runtime environment. * Set up a Linaro Android Versatile Express image running on Linaro qemu. Updated the wiki page [1] with instructions on how to prepare its initrd to make it palatable to qemu. * Trying to figure out if there's a way to get the SDK and NDK to talk to that image. * Studied AOSP's patches to gdbserver, and also Mozilla's patches to AOSP's GDB and gdbserver. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group [1] https://wiki.linaro.org/PeterMaydell/QemuVersatileExpress

13 years, 9 months

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Bounce host changes

by Michael Hope

I've changed the bounce host used to gain access to the boards at my home office. The ports and configuration are the same but you will get a scary error due to the SSH host key changing. Let me know if there are any problems, -- Michael

13 years, 9 months

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Agenda for tomorrow's performance call.

by Ramana Radhakrishnan

Hi , This is now at : https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-02-07 Please add any topics that need to be added in the wiki page. Thanks, Ramana

13 years, 9 months

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[ACTIVITY] 13th - 19th February

by Andrew Stubbs

* Linaro GCC Discovered that part of my conditional execution problems were caused by some over-zealous peephole optimizations adding CC register clobbers to arithmetic operations in order to take advantage of the 16-bit encoding. This is a problem because they can't be converted to conditional execution so freely because overwriting the CC register prevents any further conditional execution (and forces a 32-bit encoding unnecessarily). I wrote a patch to help ifcvt unpick all this and DTRT, and posted it upstream. It turns out that Benrd (I think) already reimplemented the peephole optimization in the reorg pass, so all that is really needed is to delete the now obsolete peepholes. Richard E has approved the revised patch. Unfortunately I've now discovered that that exposed a bug in the machine description, so that'll have to be fixed also. Tried to update the gcc-linaro/4.7 branch, but found the build broken. In fact, Matthias had already reported it to Bugzilla. I did a binary search, identified the problem commit, posted the info to bugzilla, and pushed a merge request for the last working commit for testing. This tested ok, so I've merged it to the Linaro 4.7 trunk. Brought the Linaro GCC patch tracker up to date to aid identification of patches we will need to forward port to 4.7. The remaining 'red' patches are either not committed upstream, or I wasn't sure. Attempted to benchmark the 64-bit shift improvements, but the target board (ursa1) has developed an I/O error. * Other Joe Seymour and I went to HP Bristol to attend one of their science lectures. Professor Jim Al-Khalili gave a talk about the recent "faster-than-light" neutrinos experiments, and explained why it can't possibly be true. http://www.jimal-khalili.com/blog/faster-than-the-speed-of-light.html

13 years, 9 months

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[ACTIVITY] Week 07

by Zhenqiang Chen

Summary: * crosstool-ng patches for linaro 2012.02 binary toolchain release Details: 1. Revise the gdb lsb build patches based on gdb-7.4. 2. Clean up old patches and only keep the latest version, since we only keep the latest version in config for linaro. 3. Window installer patch. * Scripts to use installjammer to create the win32 install package. * Apply linaro logo to the install package. * Sync up the install directory and Start-menu layout with embedded toolchain. * Test the package on win7. Plans: * Finalize 2012.02 binary toolchain release. Best regards! -Zhenqiang

13 years, 9 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, libunwind * discussions about local unwinding on Android * problem: dl_iterate_phdr isn't available * idea: parse proc/<pid>/maps but to find the ELF file for a given IP and get to the ARM specific unwind info from there * assisted an Android game developer who is using clang to compile the native parts of the app, the ndk to link it and wondered why the debuggerd doesn't catch any crashes OpenEmbedded * mainly worked on the linaro meta layer * got the external binary toolchain recipe working * added the Linaro 3.1 Kernel to the layer * updated documentation: https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core Regards, Ken

13 years, 9 months

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[ACTIVITY] report week 07

by Peter Maydell

RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-02-20 || || (for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == other == * post-Connect miscellany: * got boot-wrapper into an official location in linaro git repo * Exynos4 patchset finally made it through a review and is upstream * vexpress-a15 model also now upstream * put together arm-devs pullreq and got it committed * LP:932856 : fix broken omap3 bootrom emulation of raw boot mode * LP:931940 : fix failure to raise interrupts in PL031 realtime clock model * reviewed some qemu gdbstub patches that should fix a problem with semihosting-via-gdb * rebased qemu-linaro: another nasty one after upstream QOM patches landing * spent some time finishing up cleanup of the omap_i2c patches in qemu-linaro (a job started and left unfinished a few months back)

13 years, 9 months

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[ACTIVITY] Feb 14 - Feb 17

by Ulrich Weigand

== GCC == * Verified status of patches in Linaro 4.6 that might not yet be in mainline / Linaro 4.7. Ported two of Ira's vectorizer patches and created merge request. * Successfully tested and benchmarked 4.7 version of Richard's sched-pressure patch, with similar results as seen on 4.6. Rebased branch due to conflicts with recent mainline merge; will commit after retesting. * Investigated LP #923397 (Broken alignment attribute). Now fixed in FSF mainline and 4.6 branch, will get merged into Linaro GCC 4.6 automatically for next release. * Ongoing work on a patch to allow memory operands with vec_set and vec_extract to avoid excessive vmov generation in the PR 51819 test case. * Started working on a patch to generate usat/ssat instructions where appropriate. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

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Status of Linaro GCC 4.7 patches

by Ulrich Weigand

Hi Andrew, thanks for bringing the 4.6 patch tracker up to date. I've had a look over everything that's marked red to see what we need to do to bring Linaro 4.7 up to date: 106869 Add -fsched-pressure-algorithm=model and enable it by default on ARM. My recent commit of Richard's patch. I've tested a forward-port to the Linaro 4.7 branch already, but had to rebase it due to merge conflicts with the recent upstream merge, so I'll commit after retesting: lp:~uweigand/gcc-linaro/sched-pressure-v2-4.7 106846 Handle non-constants in mixed size condition 106844 Support pattern detection for basic blocks. Two of Ira's patches that have not yet landed upstream due to stage 3. I've created a forward-port branch and will merge into Linaro 4.7: lp:~uweigand/gcc-linaro/vect-patches-4.7 106789 Fix rs6000 vector expansion. 106768 Merge fix for lp721513. These are actually already upstream (modulo minor cosmetic changes) and present in Linaro 4.7. All in all, once the two branches mentioned above are merged, Linaro 4.7 will have everything that's today in Linaro 4.6. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 9 months

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[ACTIVITY] w07

by Asa Sandahl

Hi! * Finished gcc-4.7 benchmarking: https://wiki.linaro.org/Internal/ToolChain/Benchmarks/gcc-4.7_benchmarking Results uploaded to lp:~linaro-toolchain-wg/linaro-toolchain-benchmarks/private-runs * Development benchmarks: Continued the work started at connect. Got stuck for a while with a problem with the launchpad staging area. I could no longer log in. Seems the staging area is reset at weekends. The user credentials has to be given again, but you first have to remove them manually from the GNOME keyring (or whatever place they are stored). * Bug triaging: Triaged these bugs: https://launchpad.net/bugs/926855, https://launchpad.net/bugs/925991, https://launchpad.net/bugs/924726. Regards Åsa

13 years, 9 months

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No meetings except standup

by Michael Hope

Hi there. I've cancelled the Monday and stand up calls for this week. Andrew, could you run the standup call on Thursday please? The moderator details are at: https://wiki.linaro.org/Internal/ToolChain -- Michael

13 years, 10 months

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[ACTIVITY] 6th - 10th February

by Andrew Stubbs

* Linaro GCC Continued work on 64-bit shifts. My patch for shifts in core registers was rejected because I used conditional-execution before it's safe, apparently, so I've spent some time looking at the alternatives. First, conditional move instructions were unsatisfactory - the final instruction sequence was longer and therefore less efficient. Second, if_then_else instructions (basically conditional execution expressed a different way) was to limited - there were no patterns compatible with "or with shifted input" available in ARM mode, and no patterns available at all in Thumb mode. I solved that easily enough, of course, but the result was still unsatisfactory. In Thumb mode the result was roughly equivalent (conditional-execution is constrained by IT blocks), but in ARM mode it uses patterns that output two opposing instructions at once, without allowing for the possibility of scheduling or other optimization. Third, I've tried putting in ordinary branches and relying on the if-conversion pass to transform that to conditional execution. I had not done this initially, partially because I didn't know how, but mostly because the original implementation I was trying to replace resulted in branches in the output code, and I was trying to improve on that. Anyway, I've now figured out how to do that, and initial testing suggests that the if-conversion really is working this time. Even if it doesn't always, the other improvements to the shift sequence should still give a boost. My other patch, to do 64-bits shifts in NEON (and fall back to the above code when register allocation sees fit) has not yet been reviewed. * Linaro Connect This week was Linaro Connect week. I could not attend the event in San Francisco in person this time, so I took part in some of the morning sessions remotely. Linaro have switched to using Google Hangouts for the remote participation, and it went really rather well. In the old system there was an audio stream to listen to (on a 20 second delay or so, usually), and an IRC room projected onto a large screen for remote attendees to respond. The new Hangout system is effectively a simple in-browser video-conference system that allowed us to not only see the room, but also respond verbally in real time. The only disadvantage is the 10-person limit, but I never saw any room get near that all week. I successfully attended several sessions and one regular meeting remotely by these means. And no jet lag or eating so much!

13 years, 10 months

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[ACTIVITY] Feb 6 - Feb 10

by Thiago Jung Bauermann

Hi, Made the GDB 7.4-2012.02 release: * Learned about cbuild and how to use its services. * Prepared a GDB Linaro 7.4-2012.02~rc1 tarball and ran on cbuild. * Compared test results on ARM and i686 with the ones from 7.3-2011.12. Investigated new failures, determining that all come from new testcases added since the last release. One seemed important but when investigated it turned out to be a bug in the hand-written debug info for the testcase, which is wrong on ARM. I opened bug reports on Launchpad for the new failures which are worth being investigated for future releases. There are no regressions in 7.4-2012.02 compared to 7.3-2011.12. * Executed the release process for Linaro GDB. * Started exploring GDB on Android. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 10 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, OpenEmbedded-Core: * tested the external-toolchain branch from C. Larson * changes now upstream * rebased my changes to the current oe-core trunk * startet to setup a proper external layer at: git://git.linaro.org/people/kwerner/meta-linaro.git * got the minimal, sato and Qt image built again (only two patches required on the oe-core tree) Misc: * remotely attended some Linaro Connect sessions Regards, Ken

13 years, 10 months

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Linaro GDB 7.4 2012.02 released

by Thiago Jung Bauermann

The Linaro Toolchain Working Group is pleased to announce the release of Linaro GDB 7.4 2012.02. Linaro GDB 7.4 2012.02 is the first release in the 7.4 series. Based off the latest GDB 7.4, it includes a number of ARM-focused bug fixes and enhancements. Interesting changes include: * Update to GDB 7.4 code base. * The "info proc" and "generate-core-file" commands will now also work on remote targets connected to GDBserver on Linux. The source tarball is available at: https://launchpad.net/gdb-linaro/+milestone/7.4-2012.02 More information on Linaro GDB is available at: https://launchpad.net/gdb-linaro -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 10 months

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Linaro QEMU 2012-02 released

by Rusty Russell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2012-02. Linaro QEMU 2012.02 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. New in this month's release: - A simplified A15 model (non-LPAE) which is sufficent to boot a carefully-configured Linux kernel. Known issues: - Graphics do not work for OMAP3 based models (beagle, overo) with 11.10 Linaro images. The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2012.02 More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

13 years, 10 months

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Linaro GCC 4.5 and Linaro GCC 4.6 2012.02 released.

by Ramana Radhakrishnan

The Linaro Toolchain Working Group is pleased to announce the 2012.02 release of Linaro GCC 4.6 and Linaro GCC 4.5. Linaro GCC 4.6 2012.02 is the twelfth release in the 4.6 series. Based off the latest GCC 4.6.2+svn183786, it contains a few bug fixes and backports Cortex-A7 and Cortex-A15 support from FSF trunk. Interesting changes include: * Updates to 4.6.2+svn183786. * Add initial Cortex-A7 support. * Backport Cortex-A15 tuning improvements from upstream. * Backport improvements to 64 bit unsigned comparisons. Fixes: * LP: #917967 Backport the fix for PR51799. * LP: #836588 armel FTBFS with gcc 4.5 org 4.6 O2 and fPIC. * LP: #879725 ICE in int_mode_for_mode, at stor-layout.c:490. Linaro GCC 4.5 2012.02 is the eighteenth release in the 4.5 series. Based off the latest GCC 4.5.3+svn183785, it is a maintenance only release. Interesting changes include: * Updates to 4.5.3+svn183785. The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2012.02 https://launchpad.net/gcc-linaro/+milestone/4.5-2012.02 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.6/4.6-2012.02 https://launchpad.net/gcc-linaro/4.5/4.5-2012.02 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? inquire at support at linaro.org -- Ramana

13 years, 10 months

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Qemu atags passing in register.

by dpc＠ucore.info

Hi, I'm doing some tricks with Linux kernel and I'm dependent on bootloader atags passing. On PandaBoard the u-boot is always passing DTF/Atags pointer in r2 register, and I'm kind of depending on it. I need to emulate this behavior by -initrd qemu's argument. However it seems that qemu-system-arm zeros the registers on the start, and places atags in some hardcoded memory address no matter what. Is this behaviour really OK? Isn't r2 register a proper way to pass atags on ARM platform? If so, would you merge into mainline a patch that implement this? I could write it, but I don't want end-users of my work to have to patch and compile Qemu manually. Please CC me, I'm not following actively these mailinglists. Regards, -- Dawid Ciężarkiewicz

13 years, 10 months

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Fwd: [RFC] Upcoming work view for individual engineers

by Mounir Bsaibes

Please take the time to comment on this mockup, would it be useful for you? what other info you like to see to make your job easier, know what you have on your plate, your WIs progress, what is next in priority .... BR, Mounir ---------- Forwarded message ---------- From: Guilherme Salgado <guilherme.salgado(a)linaro.org> Date: Wed, Feb 1, 2012 at 9:54 AM Subject: [RFC] Upcoming work view for individual engineers To: linaro-dev(a)lists.linaro.org Hi folks, We're trying to make status.l.o more useful to engineers and the first thing we're planning to do is a new page listing the upcoming work assigned to a given person. I'm attaching a mockup of that view here and we'd like to know what you think of it... Do you think that would be useful to you? Is there any other information you'd like to see there, or maybe a different way to present/group them? Cheers, -- Guilherme Salgado <https://launchpad.net/~salgado> _______________________________________________ linaro-dev mailing list linaro-dev(a)lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev -- Mounir Bsaibes Project Manager Follow Linaro.org: facebook.com/pages/Linaro/155974581091106 http://twitter.com/#!/linaroorg http://www.linaro.org/linaro-blog <http://www.linaro.org/linaro-blog>

13 years, 10 months

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[ACTIVITY] 30th January - 3rd February

by Andrew Stubbs

Adjusted my 64-bit shifts patch to address Richard Earnshaw's concerns, tested it, and posted the new one upstream. Continued trying to figure out how ira-costs.c works, and in particular, why it doesn't choose to do 64-bit stuff in NEON when I think it should. Basically, the problem seems to be that when hard regs are *already* assigned, prior to IRA (say because they are function parameters or return values), then the allocator does not even consider the possibility of moving that value to another register unless it absolutely has to. It will merrily choose the worst possible option just because it's the easiest decision. Merged FSF GCC 4.5 into Linaro GCC 4.5. Likewise for 4.6. Pushed the branches to Launchpad for testing. The 4.5 testing did not come back totally clear, so this may delay the release a little. Hmmm. Updated my FSF GCC 4.7 checkout and rebuilt it. This time the build succeeded, so I've used it as the basis for a shiny new launchpad branch "lp:gcc-linaro/4.7". I've created the release series to go with it. Applied my new 64-bit shifts patch to the new GCC 4.7 Linaro branch and submitted a merge request. This is mostly for the purposes of getting the test results at this point.

13 years, 10 months

1
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native gdb for Android

by Barry Song

Hi guys, I compile a native gdb using linaro 2011.10 by “./configure --host=arm-none-linux-gnueabi --target=arm-none-linux-gnueabi”, and the gdb runs on arm target boards directly. # gdb GNU gdb (Linaro GDB) 7.3-2011.10 Copyright (C) 2011 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "arm-none-linux-gnueabi". For bug reporting instructions, please see: <http://bugs.launchpad.net/gdb-linaro/>. (gdb) I can use it to debug native programs on target boards directly. For example, attach process, set breakpoints, check registers and memory. One issue is I can't see multi-threads, for example: PID 646 is system_server by ps "646 1000 159m S system_server" Then I use gdb to attach it: # gdb attach 646 (gdb) info threads Id Target Id Frame * 1 process 646 "system_server" __ioctl () at bionic/libc/arch-arm/syscalls/__ioctl.S:15 as you see, “info threads” only shows one thread but there are several threads in system_server. But if I compile a new program based on glibc and gnu libthread, I can see multi-threads by the gdb. So my questions are: 1. Should I compile the native gdb using android toolchain and android bionic/libthread libraries? 2. Why can’t the current gdb capture multithreads for android processes? This question is actually about the theory for gdb to know multi-threads. In my opinion, both gnu and android use clone() to fork threads and threads in one process have same tgid in kernel and all threads return same getpid() value. Why not gdb just travel process lists to find multi-threads? Thanks Barry

13 years, 10 months

3
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[ACTIVITY] Jan 30 - Feb 3

by Thiago Jung Bauermann

Hi, * Learned the basics of bzr and examined the gdb-linaro repository. * Went through Michael Hope's steps to import upstream's 7.4 branch into bzr. * Explored gdb-linaro bugs and blueprints in Launchpad to familiarize myself with what has been done and is planned or proposed to be done. * Went through the gdb-linaro/7.3 branch to verify what needs to be forward-ported to gdb-linaro/7.4. Forward-ported 10 patches. * Checked which Linaro Connect sessions would be of interest for me to attend remotely, but found out that only one will be available for remote participation. * Worked very little on Wednesday since my laptop refused to turn on again after I hibernated it. I found out on the next day that plugging in an external monitor makes it happy again (I didn't have a monitor on Wed to try this out so I was stuck). Apparently the LCD screen died. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 10 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, libunwind * reviewed small patch from T. R. of Nokia who provided a bugfix when searching for unwind table entry for an IP OpenEmbedded * build the OE-core images (minimal, sato and qt4e) with -O1 and -O0 * collected the ELF size and memory footprint and updated the charts * encountered an issue when compiling Qt 4.8.0 using -O0. It causes qdbusviewer fail to link because an .LTHUNK symbol survives * tested various compilers and optimization levels and noticed that the .LTHUNK symbols do also survive with higher optimization levels * only the Linaro and ARM CSL toolchains seem to be affected (FSF trunk, 46branch and 46release seem to work) * provided a reduced testcase and opened lp #924726 * Linaro cc1 emits undefined label when using -fPIC -Os (lp #924889) * already fixed upstream, Ramana is backporting to Linaro GCC * look into the external-toolchain branch from C. Larson: https://github.com/kergoth/oe-core/tree/external-toolchain and tested it against CSL 2011.03 -> works fine * started to document: https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core Regards, Ken

13 years, 10 months

1
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[ACTIVITY] Jan 30 - Feb 3

by Ulrich Weigand

== GCC == * Benchmarking the 4.6 backport of subreg forward-propagation confirmed that this is a net loss. On 4.7, microbenchmarks suggest a different outcome (due to register allocator enhancements), so I've created a 4.7 Bazaar branch including the patch and submitted it for benchmarking. * Implemented a patch to allow memory operands with vec_set and vec_extract to avoid excessive vmov generation in the PR 51819 test case. Patch shows no regression on microbenchmarks; full testing and benchmarking still outstanding. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 10 months

1
0
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[ACTIVITY] report week 05

by Peter Maydell

RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-02-20 || || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?||2012-02-01 || (for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || == cp15-rework == * Since this isn't in the critical path any more we'll work on it next quarter, and adjust its priority/due dates post Connect. == qemu-kvm-getting-started == * finished writing up HowTo documents for reproducing the KVM prototype and running it on a Fast Model: https://wiki.linaro.org/PeterMaydell/KVM/HowTo * did the last bits of testing enough to be able to say we've done the initial prototype work for TCWG2011-A15-KVM, which means we can close out the qemu-kvm-getting-started blueprint. == other == * more upstream patch review, etc * LP:926012: patches to support prctl(PR_SET_NAME, ...) in linux-user mode, for the benefit of perl 5.14.

13 years, 10 months

1
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[ACTIVITY] w05

by Asa Sandahl

Hi! * -o2/-o3 benchmarking: Did some final work on the charts for the -O3 write up. * gcc-4.7 benchmarking: Worked on the charts for gcc-4.7 benchmarking. The Fortran tests in Spec2000 were missing from my runs. The reason was that I had mixed with the LD_LIBRARY_PATH in the cbuild make file on a previous occasion. :-( Created an internal wiki page for the results, modeled after Michael's page about -O3: https://wiki.linaro.org/Internal/ToolChain/Benchmarks/gcc-4.7_benchmarking * v8: No progress for JavaScript benchmarks this weak. https://wiki.linaro.org/AsaSandahl/Sandbox/JavaScriptBenchmarks * Bug triaging: Had a look at this bug. https://bugs.launchpad.net/gcc-linaro/+bug/923397 Regards Åsa

13 years, 10 months

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[Activity] Week 05

by Zhenqiang Chen

Summary: * Analyze PATH issues for win32 binary toolchain. Details: 1. Analyze PATH issues for win32 binary toolchain. * gcc can not find the install dir if user set PATH="INSTALL_DIR\bin" in dos cmdline, which leads to compile fail since gcc can not find ../lib, ../libexec, etc. * Root cause: in dos, " is taken as part of dirs during set PATH, which is different from cygwin or linux. And dir with " is invalid in dos. * Work out a patch to filter " in function make_relative_prefix_1 and discuss it with Michael. * Create an windows install package, so users do not need to set PATH. Will discuss more detail with Michael for the following releases. 2. Read document to ramp-up on gcc. Plans: * Feb 6-10: Linaro Connect Q1.12 Best regards! -Zhenqiang

13 years, 10 months

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Benchmark investigation at Connect

by Michael Hope

I've set up a new user on my laptop that we can use for experimenting with benchmarks during Connect. Here's what we've got: * A user called 'connect' * Ramana, Ulrich, Åsa, and myself can log in via SSH * bzr repo for trunk, 4.6, and gcc-linaro 4.6 * Tarballs of all gcc-linaro 4.4, 4.5, and 4.6 releases * Tarballs of the recent CSL, Google 4.6, and Android 4.4 compilers * A sysroot in ~/sysroot * Cross-binutils etch in ~/cross * A shared ccache in ~/ccache primed with these * A ~/env.sh that sets up the right paths etc * A ~/builds/doconfigure.sh that configures for our standard ARMv7-A C/C++/Fortran configuration * EEMBC, DENBench, and SPEC 2000 under ~/benchmarks The trees under build/ build into build/$ver/build and install into build/$ver/install. The benchmarks are set up to cross build and cross run. I've pulled ursa2 out of the farm and nuked it, so we can do something like: make CROSS_COMPILE=arm-linux-gnueabi- RUN="$PWD/sshrun ursa2" to run the benchmarks. I'll see about perf. We still need to re-baseline the benchmarks and get perf traces. Anything else needed? You can log in and try things if you want. Go through the bounce host and try connecting as connect@crucis. -- Michael

13 years, 10 months

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Improved use of vst1 via vec_extract (PR 51819 test case)

by Ulrich Weigand

Hi Ramana, as you pointed out, in the gcc.dg/vect/vect-double-reduc-6.c test case, using compiler options as described in PR 51819, we see the following inefficient code generation: vmov.32 r2, d28[0] @ 57 vec_extractv4si [length = 4] vmov.32 r1, d22[0] @ 84 vec_extractv4si [length = 4] str r2, [r0, #4] @ 58 *thumb2_movsi_vfp/7 [length = 4] vmov.32 r3, d0[0] @ 111 vec_extractv4si [length = 4] str r1, [r0, #8] @ 85 *thumb2_movsi_vfp/7 [length = 4] vst1.32 {d2[0]}, [r0:64] @ 31 neon_vst1_lanev4si [length = 4] str r3, [r0, #12] @ 112 *thumb2_movsi_vfp/7 [length = 4] bx lr @ 120 *thumb2_return [length = 12] (The :64 alignment in vst1.32 is incorrect; that is that actual problem in PR 51819, which is now fixed.) The reason for this particular code sequence turns out to be as follows: The middle end tries to store the LSB vector lane to memory, and uses the vec_extract named pattern to do so. This pattern currently only supports an "s_register_operand" destination, and is implemented via vmov to a core register. The contents of that register are then stored to memory. Now why does any vst1 instruction show up? This is because combine is able to merge the vec_extract back into the store pattern and ends up with a pattern that matches neon_vst1_lanev4si. Note that the latter pattern is actually intended to implement NEON built-ins (vst1_lane_... etc). Now there seem to be two problems with this scenario: First of all, the neon_vst1_lane<mode> patterns seem to be actually incorrect on big-endian systems due to lane-numbering problems. As I understand it, all NEON intrinsics are supposed to take lane numbers according to the NEON ordering scheme, while the vec_select RTX pattern is defined to take lane numbers according to the in-memory order. Those disagree in the big-endian case. All other patterns implementing NEON intrinsics therefore avoid using vec_select, and instead resort to using special UNSPEC codes -- the sole exception to this happens to be neon_vst1_lane<mode>. It would appear that this is actually incorrect, and the pattern ought to use a UNSPEC_VST1_LANE unspec instead (that UNSPEC code is already defined, but nowhere used). Now if we make that change, then the above code sequence will contain no vst1 any more. But in any case, expanding first into a vec_extract followed by a store pattern, only to rely on combine to merge them back together, is a suboptimal approach. One obvious drawback is that the auto-inc-dec pass runs before reload, and therefore only sees plain stores -- with no reason whatsoever to attempt to introduce post-inc operations. Also, just in general it normally works out best to allow the final choice between register and memory operands to be make in reload ... Therefore, I think the vec_extract patterns ought to support *both* register and memory destination operands, and implement those via vmov or vst1 in final code generation, as appropriate. This means that we can make the choice in reload, guided as usual by alternative ordering and/or penalties -- for example, we can choose to reload the address and still use vst1 over reloading the contents to a core register and then using an offsetted store. Finally, this sequence will also allow the auto-inc-dec pass to do a better job. The current in-tree pass doesn't manage unfortunately, but with Richard's proposed replacement, assisted by a tweak to the cost function to make sure the (future) address reload is "priced in" correctly, I'm now seeing what appears to be the optimal code sequence: vst1.32 {d6[0]}, [r0:64]! @ 30 vec_extractv4si/1 [length = 4] vst1.32 {d22[0]}, [r0]! @ 56 vec_extractv4si/1 [length = 4] vst1.32 {d2[0]}, [r0:64]! @ 82 vec_extractv4si/1 [length = 4] vst1.32 {d4[0]}, [r0] @ 108 vec_extractv4si/1 [length = 4] bx lr @ 116 *thumb2_return [length = 12] (Again the :64 is wrong; it's already fixed on mainline but I haven't pulled that change in yet.) The attached patch implements the above-mentioned changes. Any comments? I'll try to get some performance numbers as well before moving forward with the patch ... (As an aside, it might likewise be helpful to update the vec_set patterns to allow for memory operands, implemented via vld1.) (See attached file: diff-gcc-arm-vecextractmem) B.t.w. I'm wondering how I can properly test: - that the NEON intrinsics still work - that everything works on big-endian Any suggestions would be appreciated! Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 10 months

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Building at -O3 write up

by Michael Hope

One of our cards this quarter was -O3 as a performance theme which included doing a write up on the advantages and usability of -O3. This write up is at: https://wiki.linaro.org/Internal/ToolChain/BuildingAtO3 A sanitised version with non-sharable benchmark data is at: https://wiki.linaro.org/Internal/ToolChain/BuildingAtO3 Could someone review it for me please? Both facts and style. Peter, care to nit it? -- Michael

13 years, 10 months

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Android SMP Session - request for participation

by Mounir Bsaibes

The Linaro Android team has scheduled an SMP session and is requesting some participation from the Toolchain WG. The session's blueprint to subscribe to: https://blueprints.launchpad.net/linaro-android/+spec/linaro-platforms-q112… Zach, If this is not the correct session, please let the team know. Thanks, Mounir -- Mounir Bsaibes Project Manager Follow Linaro.org: facebook.com/pages/Linaro/155974581091106 http://twitter.com/#!/linaroorg http://www.linaro.org/linaro-blog <http://www.linaro.org/linaro-blog>

13 years, 10 months

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GCC 4.7 import

by Michael Hope

Hi Andrew. gcc-4.7~svn183693 just finished running through the auto builders and builds and tests in the ARM, Cortex-A9, i686, and x86_64 configurations. You could base the Linaro 4.7 branch off that. It's r114897 in bzr and, suitably, Sandra is the author. -- Michael

13 years, 10 months

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bzr, quick pulls, and new branches

by Michael Hope

For your records: Loïc wrote a script that pushes the revisions from a GCC branch into the current development focus. This makes branching on a shared repository much faster. The script is here: http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/tools/view/head:/e… and it runs daily on a cronjob as the cbuild user on the 'apus' EC2 instance (phew). We'll need to update this when 4.7 comes along. -- Michael

13 years, 10 months

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KVM/Fast Models howto wiki pages updated

by Peter Maydell

I've gone through the documentation on the wiki about how to get going with KVM on Fast Models, to clean it up and reorganise it and add some of the missing bits (notably how to set up a KVM guest kernel and filesystem). It's now at: https://wiki.linaro.org/PeterMaydell/KVM/HowTo The only minor point I'd still like to address is that at the moment we document the old-style "build your kernel and arguments into an .axf file" boot-wrapper, because my changes to support specifying them at model runtime haven't yet gone into the boot-wrapper git repo. When they do land I'll update the wiki. (Yes, technically TCWG2011-A15-KVM says "one page summary" but I thought splitting it into four pages was much clearer :-)) -- PMM

13 years, 10 months

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Adding lower optimisations into the mix

by Michael Hope

Ken, Åsa: could you add a -O0 and -O1 build to the size and benchmark results? I'm looking at the writeup and it would be interesting to contrast the speed/size of -O0 with -O2. Ta, -- Michael

13 years, 10 months

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