Hi toolchain folks,
I have a problem with U-boot compiled for an ARMv4 system (Integrator)
using Linaro 2012.02-20120222, it just crashes. Compiling the same
U-Boot with CodeSourcery 2010-q1 works fine.
Symptom:
Resetting CPU ...
undefined instruction
pc : [<07fdecd4>] lr : [<07fdeb34>]
sp : 07f91380 ip : 00000000 fp : 00000001
r10: 010258fc r9 : 00000000 r8 : 07f94f64
r7 : 07f94eb0 r6 : 00989680 r5 : 000186a0 r4 : 000186a0
r3 : 000003e8 r2 : 000f423f r1 : 000f4240 r0 : 05f5e100
Flags: nzCv IRQs on FIQs on Mode SVC_32
(repeated ad nauseam)
The only hint I have is the constant 000186a0, which appears
here in the put_dec() routine from U-boots vsprintf(), which is
nothing special, it's Douglas Jones' binary to decimal conversion
code from the Linux kernel, but the compiles objects DOES
contain calls to __aeabi_uidivmod, __udivsi3, __div64_32.
Do we know of any potential trouble in these helpers on ARMv4?
The file containing these functions is compiled like this:
arm-linux-gnueabi-gcc -M -g -Os -fno-common -ffixed-r8 -msoft-float
-D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x01000000
-I/var/linus/u-boot/build-integrator/include2
-I/var/linus/u-boot/build-integrator/include
-I/var/linus/u-boot/include -fno-builtin -ffreestanding -nostdinc
-isystem /home/linus/src/gcc-linaro-arm-linux-gnueabi-2012.02-20120222_linux/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux
-mno-thumb-interwork -march=armv4 -MQ
/var/linus/u-boot/build-integrator/lib/vsprintf.o vsprintf.c
>/var/linus/u-boot/build-integrator/lib/.depend.vsprintf
Yours,
Linus Walleij
Hi,
GDB on Android:
* Spent some time understanding the intricate build process used
to compile NDK's gdbserver.
* After a lot of tinkering and trial and error I was finally able
to produce a gdbserver binary which when running on the Android
emulator and talking to a GDB (also compiled by me) on the host
is able to show all threads and provide a useful backtrace.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi there. When you do a commit that fixes a bug, try adding a
'--fixes lp:123456' to the bzr commit. Launchpad recognises these and
automatically link the branch and merge request to the bug report.
This makes it easier for the reporter to see progress. If you forget
to update the bug status (such as bumping it from 'Triaged' to 'In
progress') then it's obvious that it's being worked on.
See https://bugs.launchpad.net/gcc-linaro/+bug/942307 for an example.
The status was 'Triaged' but there's an approved merge request which
shows work is being done.
-- Michael
Merged FSF GCC 4.7 to the Linaro GCC 4.7 branch.
Merged from GCC 4.6.3 release to Linaro GCC 4.6 branch.
Wrote and posted a patch to load DImode immediate constant into NEON
registers properly. Unfortunately, testing showed a bootstrap stage 2
vs. 3 miscompare, so there's something not quite right. However,
disassembly of the binaries hasn't revealed any problems, so this
failure is still a mystery. More investigation required.
Wrote and posted a patch to do DImode negation in NEON. Realised that I
had forgotten to do the core-register fall-back case; posted a new
version. Again, there's something annoyingly subtle that prevents
bootstrap. This time it looks like some sort of wrong code bug.
Investigating.
Wrote and posted a patch to do DImode one's complement in NEON. Richard
E questioned how it was written though. The tests passed successfully,
so that's a novelty this week!
Looked for other NEON instructions missing support. Didn't find any ...
but the machine description isn't exactly straight forward.
Considered the problems with choosing whether or not to do an operation
in NEON, or not. Discussed the existing state and possible solutions
with Ramana and Benrd (thanks Guys). Thought about it some more. Posted
a vague description of what might fix it to the linaro-toolchain list.
Awaiting replies.
Hi!
* Development benchmarks:
Finished the first implementation, sent to Michael for review.
* This became a very short week because of sickness.
Plans for week 10 is to triage existing bugs, and to get going again with
the SunSpider benchmark.
Regards
Åsa
Summary:
* Multilib on linaro toolchain.
Details:
1. Multilib test for linaro toolchain.
* Fix the multilib build issue when multiarch patch is applied.
* Fix a bug in crosstool-ng upstream to build multilib for glibc/eglibc.
* Successfully build multilib toolchain for armv6t2, cortex-a8 and
cortex-a9. And tests show it can link the correct libraries.
2. Still issues:
* Multilib and multiarch uses different directory structures.
Multilib build can not find the correct directories in the prebuilt
oneiric-sysroot.
* Build armv5t arm mode lib when default mode is thumb for armv7-a.
Annual leaves:
* Mar. 1-2.
Plans:
* Finalize the multilib solution for linaro binary toolchain.
* Work on code size optimization for the embedded toolchain.
Best regards!
-Zhenqiang
> The basic idea is that we add a new RTL optimization pass (or two) that
> assesses the usage of pseudo registers, and makes recommendations about
> what register class each should end up in, if there's a choice. These
> recommendations would then be used by later passes to get a better use
> of NEON. I might call this the "prealloc" pass, or something.
That sounds very much like the pre-reload that "new-ra" had at one
point (http://gcc.gnu.org/viewcvs/branches/new-regalloc-branch/gcc/pre-reload.c).
The problem with pre-reload for new-ra was that it was basically
reload instead of something nicer and cleaner. It also only ran just
before the register allocator, which is too late for the problem you
are trying to solve.
> Firstly, for each pseudo-register in a function, the pass would look at
> the insn constraints for each "def" and "use", and see how the registers
> relate to one another. This might determine things like "if rN is in
> class A, then rM must be also in class A".
At SUSE I tried to do this with the webizer pass (web.c). I wrote down
the ideas we implemented at the time (see
http://gcc.gnu.org/ml/gcc/2005-01/msg00179.html):
- web class, to replace regclass and choose register classes webs
instead of pseudos. This also includes splitting webs if a register
in a web really wants to be in two different classes to satisfy
constraints in two different insns. Right now, as far as I
understand, regclass just picks one and lets reload figure out how to
fix up that mistake.
- A semi-strict RTL mode. Right now there is just strict and
non-strict. On the branch there is a semi-strict mode which is the
same as strict RTL except that pseudo-registers are still allowed.
- pre-reload (which is related to web class) to make sure as many insn
constraints as possible are satisfied before the register allocator
goes to work. Basically, after pre-reload the insns stream should be
in semi-strict RTL form.
I used the webizer to unify defs and uses. I would split a web if it
needed multiple register classes (I inserted a mov, without checking
that a move existed from the source to the target register class), and
I put pseudos r1 and r2 in the same register class if there was an
insn (set (r1) (r2)) somewhere. The selection of the register classes
had a cost function, but I used rtx_cost, which is not very effective,
really. But I never took this experiment very far because for x86-64
the plan didn't work as well as I had hoped. I don't remember the
details, but the biggest problem I had with the experimental
implementation of these ideas (apart from lots of trouble with recog
for semi-strict RTL) was that there is a bit of an ordering problem
between combine on the one hand, and web-based register classes. If
you assign classes too early and don't allow things to change, then
combine fails too often. If you assign register classes after combine,
you may not get the instructions selected the way you want them to be.
This was when GCC still had the old local-alloc.c and global.c
allocators. Things may be different (better) with IRA and the upcoming
LRA stuff.
If you plan to work on this, I would suggest you discuss the plan on
the GCC mailing list also, with Jeff Law and Vladimir Makarov in CC
because they are working on a reload rewrite (LRA).
Ciao!
Steven
Hi,
OpenEmbedded:
* Worked on the meta-linaro layer and added libgcc and crosssdk
recipes to satisfy some bitbake dependencies
* I had to apply a few patches to build the linaro toolchain the OE
way (mostly gcc configury)
* successfully built the sato and Qt images
* Moved on to test the February release of the linaro binary toolchain
and (probably) and hit an issue with unaligned SD card images to used
with QEMU
* the guest kernel fails with: attempt to access beyond end of device
* /proc/partitions shows different block sizes (host vs. guest)
* the image size gets calculated on the fly by OE
* patch posted that introduces allows to specify a rootfs size alignment
* not seen on trunk as they use IDE
* Started to rebase the linaro-meta layer against current OE-core
* created https://wiki.linaro.org/KenWerner/Sandbox/OEMetaLinaroCard
based on the existent card of David R.
Regards,
Ken
== GCC ==
* Fixed mainline regression causing ICE in certain outer-loop
vectorization cases.
* Merged fwprop-subreg patch into Linaro GCC 4.7.
* Completed patch to generate usat/ssat instructions
where appropriate; checked into GCC mainline.
Merge requests to Linaro GCC 4.6 and 4.7 pending.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
==Progress===
* Finished off PGO patch - sent upstream.
* Finished off the ABI tests - sent upstream.
* Investigated fixes for LP 942307 - a problem with kernel builds for
android. Backported a fix from Uli last year.
* Upstream patch review.
* Small configury done for SPEC2k as far as HC partitioning goes.
* Some Android benchmark investigations.
* Recovered from a broken upgrade on my laptop from natty to oneiric
on my laptop and then went all the way to Precise. It works
reasonably !
=== Plans ===
* Commit all approved and tested patches.
* Check on hc partitioning results from SPEC2k and make sure there is
an improvement and the feature works !
* Investigate https://bugs.launchpad.net/gcc-linaro/+bug/924726 in a
little more detail.
* Get back to partial-partial PRE.
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-??-?? || ||
(new blueprints & reestimate for this one pending)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* ploughing through conversion of cp15 registers to new design:
patchset now 20 patches long, still TODO crn={0,1,6,7,9}
== other ==
* reviewed more Xilinx Zynq model patches
* looking at BE8 support: Paul Brook has posted some patches
to support this in user mode
* LP:944645: fixed bug where we weren't clearing the IT bits when
entering an M profile exception handler
* sent out an arm-devs.next pullreq
* trying to track down why linux-user is failing brk() and thus
causing bash segfaults
Hi All,
As you know, the compiler currently has difficulties choosing between
whether to do an operation in NEON or not.
As I see it there are three problems:
1. Simply, is it profitable?
NEON can do many DImode operations in one or two instructions
where 2 to 10 normal ARM/Thumb instructions would be required
(not to mention the added register pressure), but there is a
cost associated with moving the inputs to NEON, and the results
back.
If the data can stay in NEON for more than one operation,
then that's even better.
If the data must be loaded from memory, and the result stored back
to memory, then it's only a question of whether the register space
is available, or not.
Currently these decisions are made in the IRA/reload passes.
2. Values that originate in hard-registers stay there.
This applies to function parameters, mostly, but also in general
where the result of an operation is allocated first.
If there is no instruction that can use the value there then the
value is 'reloaded' to a more suitable register. If there is any
alternative that avoids the move then the register allocator will
use it, regardless of the relatives costs of the other
alternatives.
This problem is reduced where an operation and move can happen in
one instruction, but NEON instructions do not do this much. We can
write insns that appear to do it, but these output multiple
instructions (see my recent core-SI=>NEON-DI extend patch).
3. It all happens too late.
The decision whether to use NEON or not is not made until register
allocation time. Naturally this means that most of the optimization
passes are already completed.
Part of the problem is that the operation almost certainly needs
splitting (into whatever form was chosen) and this might not be
straight forward, post-reload. (However, the split1 pass is
already quite late, so perhaps this isn't such a big deal.)
Another part of the problem is that passes such as the two
lower-subreg passes make assumptions about the register width which
are not accurate if the operation is to end up in NEON.
There are other, lesser problems, such as it being hard to adjust the
costs for different cores (A8 in particular) and the cost of generating
an immediate constant can't be known until it's known what instructions
will be used to generate it.
These problems are not specific to NEON, of course. I believe IWMMXT
suffers from the same issues. Likewise the C6X port, and also the i386
MMX to some degree. Anything that has instructions that only operate on
a subset of registers, basically.
So, Bernd has suggested an outline of a solution. I've quizzed him on
this, added a few of my own ideas, and probably a good selection of
misunderstandings, bad assumptions, and general cock ups, and come up
with something I can write here for comment. I can post something to
upstream later if it doesn't get totally shot down now.
The basic idea is that we add a new RTL optimization pass (or two) that
assesses the usage of pseudo registers, and makes recommendations about
what register class each should end up in, if there's a choice. These
recommendations would then be used by later passes to get a better use
of NEON. I might call this the "prealloc" pass, or something.
Firstly, for each pseudo-register in a function, the pass would look at
the insn constraints for each "def" and "use", and see how the registers
relate to one another. This might determine things like "if rN is in
class A, then rM must be also in class A".
E.g. if you have two registers with constraints like this:
"r,w"
"r,w"
.. (and 'r' and 'w' do not overlap) then you know that there is a choice
between one mode or another, whereas this:
"r,w,r,w"
"r,w,w,r"
.. would impose no restrictions and we can carry on as normal.
Having done that we'd end up with sets of pseudo-registers that must
make a decision one way or the other, and we'd know where the operations
are that would force a move from one class to the other.
There's a fair amount of handwavium in there at present, because I've
not worked out what to do with overlapping register classes (think
VFP_LO_REGS) and all the other complications.
Secondly, the pass would consider the costs of each alternative, and
store a recommended register class for each pseudo-register in a table
somewhere. It would also create new pseudos and insert extra move
instructions at the register file boundaries where an existing register
would have had split recommendations (this would solve problem 2 above).
Again, there's handwavium in "consider the costs". This isn't too hard
for size-optimization (assuming the "length" attributes on the insn is
correct), but more difficult for speed optimization. Factors to include
would be the move costs (here the A8 issues would be addresses) and the
relative speeds of the operations in both alternatives. Also, the
various possible transition points between the two modes might need some
comparisons.
Thirdly, the subsequent passes would need to be modified, as would some
of the back-end bits and bobs.
1. Lower-subreg would need to detect 'word_mode' based on the
recommended register class, not the global value.
2. The many split patterns in the machine description could be adjusted
so that, instead of simply conditionalizing on "reload_completed", they
split at split1 if that's the best option. (Maybe it would be profitable
to insert a new, earlier split pass specifically for this case to take
advantage of the likes of combine? I mean, ideally this decision would
have been made at expand time, if it could have been?) It might be
useful to *not* split too soon, in some cases, so that the register
allocator can still make the final decision based on register pressure,
and whatever other factors it uses. Of course, the existing late-split
option would need to be retained in case the prealloc pass is disabled,
in any case.
3. Various passes would have to be taught not to remove seemingly
superfluous register moves where they actually move between register
classes.
4. Pretty much nothing would need doing to register allocation! The
extra moves should make allocation a register pressure management issue,
rather than a question of making it work. DImode operations preallocated
to core-registers may already have been lowered, one way or the other
(by split1) so there's no decision left there, and if no lowering was
necessary then that option ought to be obviously cheaper. If it insists
on making contrary decisions then it can be taught to use the
recommendation as a hint, perhaps? In specific problem cases it would
also be possible to use instruction attributes to disable (or strongly
discourage) certain alternatives based on the recommended class.
5. The existing 'onlya8'/'nota8' nonsense can be removed.
6. The register move cost can be set correctly for each core.
7. If a constant is destined for a NEON register, most likely,
arm_gen_constant can use the NEON immediate rules to determine the cost.
There's clearly a lot of thought that needs to go into the
pseudo-register scan and decision making logic, but the whole thing
doesn't look like it'll boil down to very much code in the end.
There's also the question of where to put the pass? Too early and you'd
need to put a second one in to reassess the much changed RTL later, and
too late and lower-subreg won't be able to use it.
It's possible that it might be better to treat it more like the
data-flow analysis where it's not actually a stand-alone pass, but
rather a tool other passes can use? That might depend how
computationally expensive it is.
Any thoughts anyone? Might something like this actually work? Would it
be worth spending the time on this?
Andrew
Hi,
184603 fixes an ICE we're running into with Android test builds.
Please pull it in ASAP so I don't have to mess with the CFLAGS as a workaround.
ttyl
bero
Hi Peter, Rusty. I've fleshed out the KVM blueprints a bit more at:
https://wiki.linaro.org/MichaelHope/Sandbox/Q1.12ToDo
Notable is adding validation and de-PENDING a few things.
I need to know the following things before talking to Validation and
Platforms about things that are in their queue:
* What's the host kernel? Christoffers, or a linux-linaro-kvm based
off his plus work in progress?
* What's the guest kernel?
* Anything special that needs to be in the host rootfs outside qemu
and libvirt?
Do you have a host and guest kernel .config that I can pass on to Platforms?
-- Michael
Hi,
GDB on Android:
* Set up cross compiling environment using both the Android toolchain
and
the Linaro toolchain.
* Tested Android and Mozilla GDB running as a native binary on the
Linaro Android image on qemu. None of them were able to see all
threads in a multi-threaded process. The same happens with a native
binary on Android talking to a gdbserver on localhost.
* I was able to produce an Android GDB 7.1.x binary which when running
on an i386 host talking to the Android SDK emulator sees all threads.
It is not able to generate a backtrace though.
* Carnival holidays.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Investigated and produced and patch for bug lp936863.
Continued work on 64-bit shifts. I updated my neon shifts patch twice:
once to take -Os optimization into account, and once because I noticed
that the CC clobbers were being retained even after they were known to
be not required, and presumably this could be a bad thing.
Posted a patch to improve SI->DImode sign- and zero-extends that also
move values from core registers to neon registers.
Wrote a patch to implement negation in neon register, albeit at the cost
of a scratch register to hold the constant zero. This worked, but
insisted on loading the zero from memory, despite the fact that NEON has
a suitable instruction for loading zero.
Attempted to get "vmov dN, #0" to work. The problem appears to be that
DImode loads are handled by the VFP load pattern in vfp.md and that that
doesn't seem to DTRT for integer constants. I've got as far as trying to
figure out what it does do, but there's more to be done to get to the
bottom of the problem.
Tried to get the benchmarking going for 64-bit shifts. Unfortunately
ursa1 has been experiencing outages. Michael has been trying to fix it,
but so far I've not been able to run anything there. Instead, I've
launched benchmark runs via Michael's normal test infrastructure.
Hopefully this can replace the manual ones anyway. That would be more
convenient.
Hi,
I'm trying to use pre-built version of linaro toolchain for cross-compiler in Ubuntu 11.04 on our 64bit server.
I got it from http://people.linaro.org/~michaelh/incoming/binaries/.
When I run arm-linux-gnueabi-gcc to compile a c source, it says "No such file or directory".
The steps are as below:
1. Unpack gcc-linaro-arm-linux-gnueabi-2011.12-20111219+bzr2309~linux.tar.bz2.
2. Rename gcc-linaro-arm-linux-gnueabi-2011.12-20111219+bzr2309~linux to arm-fsl-linux-gnueabi.
3. Copy to ~/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/
2. Use arm-linux-gnueabi-gcc to compile my code.
The output is:
r65388@shlinux3:~/MEMCPYBM$ ~/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/arm-fsl-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-bash: /home/r65388/toolchain_ltib/gcc-linaro-4.6.3-glibc-2.13-singlelib-2011.12/arm-fsl-linux-gnueabi/bin/arm-linux-gnueabi-gcc: No such file or directory
I have installed lsb 4.0 and libc6 2.13.
r65388@shlinux3:~/MEMCPYBM$ dpkg -s lsb
Package: lsb
Status: install ok installed
Priority: extra
Section: misc
Installed-Size: 48
Maintainer: Ubuntu Developers <ubuntu-devel-discuss(a)lists.ubuntu.com>
Architecture: all
Version: 4.0-0ubuntu16
...
r65388@shlinux3:~/MEMCPYBM$ dpkg -s libc6-dev
Package: libc6-dev
Status: install ok installed
Multi-Arch: same
Priority: optional
Section: libdevel
Installed-Size: 11888
Maintainer: Ubuntu Developers <ubuntu-devel-discuss(a)lists.ubuntu.com>
Architecture: amd64
Source: eglibc
Version: 2.13-20ubuntu5
Provides: libc-dev
Depends: libc6 (= 2.13-20ubuntu5), libc-dev-bin (= 2.13-20ubuntu5), linux-libc-dev
Recommends: gcc | c-compiler
Suggests: glibc-doc, manpages-dev
Breaks: binutils (<< 2.20.1-1), binutils-gold (<< 2.20.1-11), cmake (<< 2.8.4+dfsg.1-5), gcc-4.4 (<< 4.4.6-3ubuntu1), gcc-4.4-base (<< 4.4.6-3ubuntu1), gcc-4.5 (<< 4.5.3-1ubuntu2), gcc-4.5-base (<< 4.5.3-1ubuntu2), gcc-4.6 (<< 4.6.0-12), gcj-4.4-base (<< 4.4.6-2ubuntu2), gcj-4.5-base (<< 4.5.3-1ubuntu2), gnat-4.4-base (<< 4.4.6-1ubuntu3), libhwloc-dev (<< 1.2-3), libjna-java (<< 3.2.7-4), liblouis-dev (<< 2.3.0-2), liblouisxml-dev (<< 2.4.0-2), make (<< 3.81-8.1), pkg-config (<< 0.26-1)
...
Do you know why?
How can I fix this issue?
Thanks~~
Yours
Terry
Summary:
* Linaro binary toolchain 2012.02 release.
* Try the Multilib patch on linaro toolchain.
Details:
1. Linaro binary toolchain 2012.02 release.
* Create linaro license file based on embedded toolchain, add
crosstool-ng and sysroot (eglibc) license.
* Tests on win7, oneiric and RHEL5.
2. Try to apply the multilib patch used in embedded toolchain to
linaro toolchain.
* The multilib solution can not work together with the multiarch patch.
(1) With both patches, "gcc -print-multi-lib" can only print one option.
(2) With only multilib patch, "gcc -print-multi-lib" can print the
multilib list.
* Successfully build a multilib toolchain (Based on the prebuilt
oneiric-sysroot with directory structure change for include and lib.)
without the multiarch patch and c++ support.
Plans:
1. Try crosstool-ng 1.14 to build multilib eglibc.
2. Investigate how to make multiarch and multilib work together.
Planed leaves:
* Mar. 1-2.
Best regards!
-Zhenqiang
Hi Peter, Rusty. I've written down my notes from Connect and drafted
the blueprints at:
https://wiki.linaro.org/MichaelHope/Sandbox/Q1.12ToDo
I've put my priories on things and sorted them by relative importance.
I'll check tomorrow if there's a good match between this, the KVMEpic
spec, and the older task spreadsheet.
Most of these are too short. I don't know what's involved with the
CP15 work. Some still have big PENDINGS. Please edit and correct.
There's a lot of work there. Some is on other teams but I'm concerned.
-- Michael
== GCC ==
* Merged Ira's remaining vectorizer patches into Linaro GCC 4.7.
* Merged Richard's sched-pressure patch (enabled by default
on ARM) into Linaro GCC 4.7. Asked IBM colleagues for
benchmark results on s390 and rs6000 as well.
* Committed patch to enable vect_condition tests in FSF mainline,
FSF 4.6, and Linaro GCC 4.7.
* Verified that Linaro GCC 4.7 now contains every feature that
was present in Linaro GCC 4.6.
* Rebased and re-benchmarked fwprop-subreg patch.
* Ongoing work on a patch to generate usat/ssat instructions
where appropriate.
* Worked on improving end-of-loop value computation.
* Fixed mainline .init_array/.fini_array regression on certain
newlib targets.
* Reviewed several merge requests.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
On holiday last week and at connect week before that.
==Progress===
* Recovered from jet-lag and started to catch up on email.
* Patch review week.
* Cleared out a bit of my patch backlog.
* Helped Asa with some bug triaging.
* Read up a bit about ssat and usat and what we should be doing with
other tuning for them.
* Looked up some performance profiles with v8 benchmarks . Reviewed the Android
benchmark numbers.
* Booked tickets for connect 2012.q2
* Wrote up connect week discussions on libav regressions .
=== Plans ===
* Clear out more pending patches ( PGO next on the hit list and the
vmla investigation)
* Investigate partial-partial PRE results.
* Finish off the ABI tests.
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1
Hi,
OpenEmbedded:
* added initial support for the Linaro GCC 4.6 based toolchain to
the meta-linaro layer.
* allows to build the Linaro toolchain the OE way
* successfully built the core-image-sato
but when running inside QEMU the GUI isn't usable
(needs investigation)
glibc:
* built glibc+glibc-ports natively on ARM
* the upstream glibc testsuite isn't aware of the multiarch paths
and therefore it won't find some libs (libgcc_s, libstdc++)
* workaround using symlinks; wiki updated:
https://wiki.linaro.org/KenWerner/Sandbox/HowToBuildToolchainComponents#gli…
Regards,
Ken
+ linaro-toolchain
Hello Ulrich,
I want to revisit this old thread. Sorry for the sloppy follow-up. But,
this time around I have more data.
On Tue, Mar 15, 2011 at 9:00 PM, Ulrich Weigand
<Ulrich.Weigand(a)de.ibm.com> wrote:
> Aneesh V <aneesh(a)ti.com> wrote:
>
>> I was trying to build u-boot in Thumb2 for OMAP4. Everything was fine
>> until I added some patches recently. One of these patches introduced an
>> API (let's say foo()) that has a weakly linked alias(let's say
>> __foo()) and a strongly linked implementation(the real foo()) in an
>> assembly file.
>>
>> Although I give -mthumb and -mthumb-interwork for all the files,
>> apparently GCC generates ARM code for assembly files. In the final
>> image foobar() calls foo() using a BL. Since foobar() is in Thumb and
>> foo() in ARM, it ends up crashing. Looks like foobar() assumed foo()
>> to be Thumb because __foo() is Thumb.
>
> I'm unable to reproduce this. Do you have a complete test case?
>
> I've tried with the following small example:
>
> foo1.c:
>
> extern void foo (void) __attribute__ ((weak, alias ("__foo")));
>
> void __foo (void)
> {
> }
>
> int main (void)
> {
> foo ();
> }
>
> foo2.S:
> .text
> .align 2
> .global foo
> .type foo, %function
> foo:
> push {r7}
> add r7, sp, #0
> mov sp, r7
> pop {r7}
> bx lr
> .size foo, .-foo
>
> When building just "gcc foo1.c", I get:
>
> 0000835c <__foo>:
> 835c: b480 push {r7}
> 835e: af00 add r7, sp, #0
> 8360: 46bd mov sp, r7
> 8362: bc80 pop {r7}
> 8364: 4770 bx lr
> 8366: bf00 nop
>
> 00008368 <main>:
> 8368: b580 push {r7, lr}
> 836a: af00 add r7, sp, #0
> 836c: f7ff fff6 bl 835c <__foo>
> 8370: 4618 mov r0, r3
> 8372: bd80 pop {r7, pc}
>
> When building both files "gcc foo1.c foo2.S", I get instead:
>
> 00008368 <main>:
> 8368: b580 push {r7, lr}
> 836a: af00 add r7, sp, #0
> 836c: f000 e802 blx 8374 <foo>
> 8370: 4618 mov r0, r3
> 8372: bd80 pop {r7, pc}
>
> 00008374 <foo>:
> 8374: e92d0080 push {r7}
> 8378: e28d7000 add r7, sp, #0
> 837c: e1a0d007 mov sp, r7
> 8380: e8bd0080 pop {r7}
> 8384: e12fff1e bx lr
>
>
> So it seems to me the linker is handling this correctly ...
>
> (This is on Ubuntu Natty using system gcc and binutils.)
I could reproduce the problem on older tool-chain(Sourcery G++ Lite
2010q1-202) [1] with a modified version of your sample code:
a.c:
====
extern void foo (void) __attribute__ ((weak, alias ("__foo")));
void __foo (void)
{
}
extern void call_foo(void);
int main (void)
{
call_foo ();
}
b.S:
====
.text
.align 2
.global foo
foo:
push {r7}
add r7, sp, #0
mov sp, r7
pop {r7}
bx lr
.size foo, .-foo
c.S
.text
.align 2
.global call_foo
call_foo:
bl foo
bx lr
.global __aeabi_unwind_cpp_pr0
__aeabi_unwind_cpp_pr0:
bx lr
Now, I build them using the following commands, which is similar to
what U-Boot does:
arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c a.c
arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c b.S
arm-none-linux-gnueabi-gcc -mthumb -mthumb-interwork -c c.S
arm-none-linux-gnueabi-ld -r a.o -o alib.o
arm-none-linux-gnueabi-ld -r b.o -o blib.o
arm-none-linux-gnueabi-ld -r c.o -o clib.o
arm-none-linux-gnueabi-ld --start-group clib.o alib.o blib.o
--end-group -o a.out
armobjdump -S --reloc a.out
You will get something like:
00008094 <call_foo>:
8094: fa000006 blx 80b4 <foo>
8098: e12fff1e bx lr
Please note that that the 'blx' is not correct. Now, do the following change:
diff --git a/b.S b/b.S
index e0f2de9..96dba1f 100644
--- a/b.S
+++ b/b.S
@@ -1,5 +1,6 @@
.text
.align 2
+.type foo, %function
.global foo
foo:
push {r7}
And build it again the same way and you will see:
00008094 <call_foo>:
8094: eb000006 bl 80b4 <foo>
8098: e12fff1e bx lr
I can't reproduce this on Linaro GCC 2012.01, so looks like the problem
is solved in recent tool-chains. However, sadly I could reproduce a
different but similar problem with Linaro GCC 2012.01. This time the
call is from C(Thumb) to assembly(ARM) and no weakly linked symbols are
involved.
a.c:
====
int main (void)
{
foo ();
}
b.S:
====
.text
.align 2
.global foo
foo:
push {r7}
add r7, sp, #0
mov sp, r7
pop {r7}
bx lr
.size foo, .-foo
.global __aeabi_unwind_cpp_pr0
__aeabi_unwind_cpp_pr0:
bx lr
arm-linux-gnueabi-gcc -mthumb -mthumb-interwork -c a.c
arm-linux-gnueabi-gcc -mthumb -mthumb-interwork -c b.S
arm-linux-gnueabi-ld -r a.o -o alib.o
arm-linux-gnueabi-ld -r b.o -o blib.o
arm-linux-gnueabi-ld --start-group alib.o blib.o --end-group -o a.out
arm-linux-gnueabi-objdump -S --reloc a.out
gives:
8076: af00 add r7, sp, #0
8078: f000 f802 bl 8080 <foo>
807c: 4618 mov r0, r3
It should have been "blx 8080 <foo>", isn't it? Again, %function
solves it.
I agree that not marking the assembly functions ' %function' is a problem
in the code, so it's not a critical bug. But I would've been happier if
the linker refused to link it rather than branching with the wrong
instruction. Isn't that a problem?
Problem No:2
*************
Linaro GCC 2012.01 is giving a new problem w.r.to Thumb build
that is not existing in Sourcery G++ Lite 2010q1-202. However, I
couldn't reproduce this problem with a small program like above. So,
let me give you reference to the original u-boot code that shows the
problem and steps to reproduce it.
tree: git://github.com/aneeshv/u-boot.git
branch: thumb
The above branch has mainline u-boot with 4 additional patches from me
for enabling Thumb build. You can build it like this:
make CROSS_COMPILE=arm-linux-gnueabi- ARCH=arm distclean
make CROSS_COMPILE=arm-linux-gnueabi- ARCH=arm omap4_sdp4430
This builds two images u-boot and u-boot-spl. SPL is a tiny u-boot that
runs from internal RAM and loads the u-boot to SDRAM. Now, please have
a look at the map file of u-boot-spl which is at: spl/u-boot-spl.map
I see the following in my map file:
/spl/u-boot-spl.map:
=================
.rodata.wkup_padconf_array_essential_4460
0x40309583 0x4 board/ti/sdp4430/libsdp4430.o
0x40309583 wkup_padconf_array_essential_4460
.rodata.wkup_padconf_array_essential
0x40309587 0xc board/ti/sdp4430/libsdp4430.o
0x40309587 wkup_padconf_array_essential
.rodata.core_padconf_array_essential
0x40309593 0x60 board/ti/sdp4430/libsdp4430.o
0x40309593 core_padconf_array_essential
Please note that the .rodata symbols have odd addresses. These arrays
actually need to be aligned at least to half-word boundary. In fact, in
the image I verified that they are put at even addresses. So, the
symbols have been kept as real address +1. I understand that this is
the convention for Thumb functions. I guess the tool-chain did it for
data too?? And I am getting unaligned access aborts on accessing them.
I notice that this doesn't happen with all .rodata. symbols in the
image. I couldn't see any difference between working and non-working
files nor any difference in the command used to build them!
Well, this doesn't happen if I don't use "-fdata-sections" in gcc
options. So, apply the following patch and you will see that those
symbols have even addresses now.
diff --git a/config.mk b/config.mk
index ddaa477..723286a 100644
--- a/config.mk
+++ b/config.mk
@@ -190,7 +190,7 @@ CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
# Enable garbage collection of un-used sections for SPL
ifeq ($(CONFIG_SPL_BUILD),y)
-CPPFLAGS += -ffunction-sections -fdata-sections
+CPPFLAGS += -ffunction-sections
LDFLAGS_FINAL += --gc-sections
endif
/spl/u-boot-spl.map:
=================
.rodata 0x40309204 0x38c board/ti/sdp4430/libsdp4430.o
0x40309204 core_padconf_array_essential
0x40309264 wkup_padconf_array_essential
0x40309270 wkup_padconf_array_essential_4460
0x40309274 core_padconf_array_non_essential
0x40309540 wkup_padconf_array_non_essential
0x40309588 wkup_padconf_array_non_essential_4430
Will you be able to look into these?
Thanks,
Aneesh
[1] Sourcery G++ Lite 2010q1-202
arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2010q1-202) 4.4.1
GNU ld (Sourcery G++ Lite 2010q1-202) - binutils 2.19.51.20090709
[2] Linaro 4.6-2012.01
arm-linux-gnueabi-gcc (crosstool-NG linaro-1.13.1-2012.01-20120125 -
Linaro GCC 2012.01) 4.6.3 20120105 (prerelease)
GNU ld (crosstool-NG linaro-1.13.1-2012.01-20120125 - Linaro GCC 2012.01) 2.22
Hi!
* Development benchmarks:
Focused on the implementation of development benchmarks in the cbuild
system. Discussed with Michael about how the comments should look.
I am now testing my solution in the launchpad staging area. You can see a
link to an example of a benchmark result comment below. (Should not be a
double comment of course, and the actual result files are only stored on my
machine for now.)
https://code.staging.launchpad.net/~ramana/gcc-linaro/partial_partial_pre_t…
The real benchmark names are not mentioned, since that might be sensitive.
* Bug reports
I got an action on Monday's meeting to investigate if
https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/926855
is the same as PR52294.
Investigated with help from Ramana and updated the ticket.
Regards
Åsa
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-??-?? || ||
(new blueprints & reestimate for this one pending Michael H's writeup/etc)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* figuring out how various suggestions/conversations on this from
Connect ought to fit together
== other ==
* LP:928580 recent u-boot not booting on QEMU beagle: tracked
this down to a u-boot bug and passed to John Rigby
* investigated a linux-user segfault deadlock which turns out to
be because the guest program is using setrlimit to restrict
memory usage and one of qemu's internal memory allocations then
fails. Not clear how best to fix but was able to nack the suggested
patch...
* most of the patches for passing a device tree to the kernel from
qemu (via -dtb option) are now upstream; rebased the final patch
which should now go in soon I think
* LP885239 qemu-linaro broke booting of zaurus models: fixed a bug
where a trustzone support patch had broken some cp15 registers for
xscale cpus
* minor patch: fixed formatting of list of supported machines help text
* fix an embarrassing segfault bug in a patch of mine committed last week
* it turns out that we can detect at compile time whether glibc's
makecontext() is an always-fails stub : sent configure patch to do this
* travel mostly set up for connect Q2.12
* lots of meetings/training: toolchain call; standup; 1-2-1;
project management training; comms meeting
I've added a Cortex-A8 benchmark machine to my home office. The
machine is called 'nova1' and is part of the cbuild a8-ref queue.
Feel free to give it jobs:
http://ex.seabright.co.nz/helpers/scheduler/spawn
-- Michael
Hi,
GDB on Android exploration:
* Familiarizing myself with the Android SDK and NDK, and the Android
runtime environment.
* Set up a Linaro Android Versatile Express image running on Linaro
qemu. Updated the wiki page [1] with instructions on how to prepare
its initrd to make it palatable to qemu.
* Trying to figure out if there's a way to get the SDK and NDK to talk
to that image.
* Studied AOSP's patches to gdbserver, and also Mozilla's patches to
AOSP's GDB and gdbserver.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
[1] https://wiki.linaro.org/PeterMaydell/QemuVersatileExpress
I've changed the bounce host used to gain access to the boards at my
home office. The ports and configuration are the same but you will
get a scary error due to the SSH host key changing.
Let me know if there are any problems,
-- Michael
* Linaro GCC
Discovered that part of my conditional execution problems were caused by
some over-zealous peephole optimizations adding CC register clobbers to
arithmetic operations in order to take advantage of the 16-bit encoding.
This is a problem because they can't be converted to conditional
execution so freely because overwriting the CC register prevents any
further conditional execution (and forces a 32-bit encoding
unnecessarily). I wrote a patch to help ifcvt unpick all this and DTRT,
and posted it upstream. It turns out that Benrd (I think) already
reimplemented the peephole optimization in the reorg pass, so all that
is really needed is to delete the now obsolete peepholes. Richard E has
approved the revised patch. Unfortunately I've now discovered that that
exposed a bug in the machine description, so that'll have to be fixed also.
Tried to update the gcc-linaro/4.7 branch, but found the build broken.
In fact, Matthias had already reported it to Bugzilla. I did a binary
search, identified the problem commit, posted the info to bugzilla, and
pushed a merge request for the last working commit for testing. This
tested ok, so I've merged it to the Linaro 4.7 trunk.
Brought the Linaro GCC patch tracker up to date to aid identification of
patches we will need to forward port to 4.7. The remaining 'red' patches
are either not committed upstream, or I wasn't sure.
Attempted to benchmark the 64-bit shift improvements, but the target
board (ursa1) has developed an I/O error.
* Other
Joe Seymour and I went to HP Bristol to attend one of their science
lectures. Professor Jim Al-Khalili gave a talk about the recent
"faster-than-light" neutrinos experiments, and explained why it can't
possibly be true.
http://www.jimal-khalili.com/blog/faster-than-the-speed-of-light.html
Summary:
* crosstool-ng patches for linaro 2012.02 binary toolchain release
Details:
1. Revise the gdb lsb build patches based on gdb-7.4.
2. Clean up old patches and only keep the latest version, since we
only keep the latest version in config for linaro.
3. Window installer patch.
* Scripts to use installjammer to create the win32 install package.
* Apply linaro logo to the install package.
* Sync up the install directory and Start-menu layout with
embedded toolchain.
* Test the package on win7.
Plans:
* Finalize 2012.02 binary toolchain release.
Best regards!
-Zhenqiang
Hi,
libunwind
* discussions about local unwinding on Android
* problem: dl_iterate_phdr isn't available
* idea: parse proc/<pid>/maps but to find the ELF file for a given IP
and get to the ARM specific unwind info from there
* assisted an Android game developer who is using clang to compile
the native parts of the app, the ndk to link it and wondered why
the debuggerd doesn't catch any crashes
OpenEmbedded
* mainly worked on the linaro meta layer
* got the external binary toolchain recipe working
* added the Linaro 3.1 Kernel to the layer
* updated documentation:
https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core
Regards,
Ken
RAG:
Red:
Amber:
Green:
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-02-20 || ||
(for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== other ==
* post-Connect miscellany:
* got boot-wrapper into an official location in linaro git repo
* Exynos4 patchset finally made it through a review and is upstream
* vexpress-a15 model also now upstream
* put together arm-devs pullreq and got it committed
* LP:932856 : fix broken omap3 bootrom emulation of raw boot mode
* LP:931940 : fix failure to raise interrupts in PL031 realtime
clock model
* reviewed some qemu gdbstub patches that should fix a problem
with semihosting-via-gdb
* rebased qemu-linaro: another nasty one after upstream QOM
patches landing
* spent some time finishing up cleanup of the omap_i2c patches
in qemu-linaro (a job started and left unfinished a few months back)
== GCC ==
* Verified status of patches in Linaro 4.6 that might not yet
be in mainline / Linaro 4.7. Ported two of Ira's vectorizer
patches and created merge request.
* Successfully tested and benchmarked 4.7 version of Richard's
sched-pressure patch, with similar results as seen on 4.6.
Rebased branch due to conflicts with recent mainline merge;
will commit after retesting.
* Investigated LP #923397 (Broken alignment attribute). Now
fixed in FSF mainline and 4.6 branch, will get merged into
Linaro GCC 4.6 automatically for next release.
* Ongoing work on a patch to allow memory operands with vec_set
and vec_extract to avoid excessive vmov generation in the
PR 51819 test case.
* Started working on a patch to generate usat/ssat instructions
where appropriate.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi Andrew,
thanks for bringing the 4.6 patch tracker up to date. I've had a look over
everything that's marked red to see what we need to do to bring Linaro 4.7
up to date:
106869 Add -fsched-pressure-algorithm=model and enable it by default on
ARM.
My recent commit of Richard's patch. I've tested a forward-port to the
Linaro 4.7 branch already, but had to rebase it due to merge conflicts
with the recent upstream merge, so I'll commit after retesting:
lp:~uweigand/gcc-linaro/sched-pressure-v2-4.7
106846 Handle non-constants in mixed size condition
106844 Support pattern detection for basic blocks.
Two of Ira's patches that have not yet landed upstream due to stage 3.
I've created a forward-port branch and will merge into Linaro 4.7:
lp:~uweigand/gcc-linaro/vect-patches-4.7
106789 Fix rs6000 vector expansion.
106768 Merge fix for lp721513.
These are actually already upstream (modulo minor cosmetic changes)
and present in Linaro 4.7.
All in all, once the two branches mentioned above are merged,
Linaro 4.7 will have everything that's today in Linaro 4.6.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi!
* Finished gcc-4.7 benchmarking:
https://wiki.linaro.org/Internal/ToolChain/Benchmarks/gcc-4.7_benchmarking
Results uploaded to
lp:~linaro-toolchain-wg/linaro-toolchain-benchmarks/private-runs
* Development benchmarks:
Continued the work started at connect.
Got stuck for a while with a problem with the launchpad staging area. I
could no longer log in. Seems the staging area is reset at weekends. The
user credentials has to be given again, but you first have to remove them
manually from the GNOME keyring (or whatever place they are stored).
* Bug triaging:
Triaged these bugs: https://launchpad.net/bugs/926855,
https://launchpad.net/bugs/925991, https://launchpad.net/bugs/924726.
Regards
Åsa
Hi there. I've cancelled the Monday and stand up calls for this week.
Andrew, could you run the standup call on Thursday please? The
moderator details are at:
https://wiki.linaro.org/Internal/ToolChain
-- Michael
* Linaro GCC
Continued work on 64-bit shifts. My patch for shifts in core registers
was rejected because I used conditional-execution before it's safe,
apparently, so I've spent some time looking at the alternatives.
First, conditional move instructions were unsatisfactory - the final
instruction sequence was longer and therefore less efficient.
Second, if_then_else instructions (basically conditional execution
expressed a different way) was to limited - there were no patterns
compatible with "or with shifted input" available in ARM mode, and no
patterns available at all in Thumb mode. I solved that easily enough, of
course, but the result was still unsatisfactory. In Thumb mode the
result was roughly equivalent (conditional-execution is constrained by
IT blocks), but in ARM mode it uses patterns that output two opposing
instructions at once, without allowing for the possibility of scheduling
or other optimization.
Third, I've tried putting in ordinary branches and relying on the
if-conversion pass to transform that to conditional execution. I had not
done this initially, partially because I didn't know how, but mostly
because the original implementation I was trying to replace resulted in
branches in the output code, and I was trying to improve on that.
Anyway, I've now figured out how to do that, and initial testing
suggests that the if-conversion really is working this time. Even if it
doesn't always, the other improvements to the shift sequence should
still give a boost.
My other patch, to do 64-bits shifts in NEON (and fall back to the above
code when register allocation sees fit) has not yet been reviewed.
* Linaro Connect
This week was Linaro Connect week. I could not attend the event in San
Francisco in person this time, so I took part in some of the morning
sessions remotely.
Linaro have switched to using Google Hangouts for the remote
participation, and it went really rather well. In the old system there
was an audio stream to listen to (on a 20 second delay or so, usually),
and an IRC room projected onto a large screen for remote attendees to
respond. The new Hangout system is effectively a simple in-browser
video-conference system that allowed us to not only see the room, but
also respond verbally in real time. The only disadvantage is the
10-person limit, but I never saw any room get near that all week.
I successfully attended several sessions and one regular meeting
remotely by these means. And no jet lag or eating so much!
Hi,
Made the GDB 7.4-2012.02 release:
* Learned about cbuild and how to use its services.
* Prepared a GDB Linaro 7.4-2012.02~rc1 tarball and ran on cbuild.
* Compared test results on ARM and i686 with the ones from 7.3-2011.12.
Investigated new failures, determining that all come from new
testcases added since the last release. One seemed important but
when investigated it turned out to be a bug in the hand-written
debug info for the testcase, which is wrong on ARM. I opened
bug reports on Launchpad for the new failures which are worth being
investigated for future releases. There are no regressions
in 7.4-2012.02 compared to 7.3-2011.12.
* Executed the release process for Linaro GDB.
* Started exploring GDB on Android.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi,
OpenEmbedded-Core:
* tested the external-toolchain branch from C. Larson
* changes now upstream
* rebased my changes to the current oe-core trunk
* startet to setup a proper external layer at:
git://git.linaro.org/people/kwerner/meta-linaro.git
* got the minimal, sato and Qt image built again
(only two patches required on the oe-core tree)
Misc:
* remotely attended some Linaro Connect sessions
Regards,
Ken
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro GDB 7.4 2012.02.
Linaro GDB 7.4 2012.02 is the first release in the 7.4 series. Based off
the latest GDB 7.4, it includes a number of ARM-focused bug fixes and
enhancements.
Interesting changes include:
* Update to GDB 7.4 code base.
* The "info proc" and "generate-core-file" commands will now also
work on remote targets connected to GDBserver on Linux.
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.4-2012.02
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2012-02.
Linaro QEMU 2012.02 is the latest monthly release of qemu-linaro. Based
off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
New in this month's release:
- A simplified A15 model (non-LPAE) which is sufficent to boot a
carefully-configured Linux kernel.
Known issues:
- Graphics do not work for OMAP3 based models (beagle, overo)
with 11.10 Linaro images.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2012.02
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The Linaro Toolchain Working Group is pleased to announce the 2012.02
release of Linaro GCC 4.6 and Linaro GCC 4.5.
Linaro GCC 4.6 2012.02 is the twelfth release in the 4.6 series. Based
off the latest GCC 4.6.2+svn183786, it contains a few bug
fixes and backports Cortex-A7 and Cortex-A15 support from FSF trunk.
Interesting changes include:
* Updates to 4.6.2+svn183786.
* Add initial Cortex-A7 support.
* Backport Cortex-A15 tuning improvements from upstream.
* Backport improvements to 64 bit unsigned comparisons.
Fixes:
* LP: #917967 Backport the fix for PR51799.
* LP: #836588 armel FTBFS with gcc 4.5 org 4.6 O2 and fPIC.
* LP: #879725 ICE in int_mode_for_mode, at stor-layout.c:490.
Linaro GCC 4.5 2012.02 is the eighteenth release in the 4.5 series. Based
off the latest GCC 4.5.3+svn183785, it is a maintenance only release.
Interesting changes include:
* Updates to 4.5.3+svn183785.
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.6-2012.02https://launchpad.net/gcc-linaro/+milestone/4.5-2012.02
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.6/4.6-2012.02https://launchpad.net/gcc-linaro/4.5/4.5-2012.02
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? inquire at support at linaro.org
-- Ramana
Hi,
I'm doing some tricks with Linux kernel and I'm dependent on
bootloader atags passing.
On PandaBoard the u-boot is always passing DTF/Atags pointer in r2
register, and I'm kind of depending on it. I need to emulate this
behavior by -initrd qemu's argument. However it seems that
qemu-system-arm zeros the registers on the start, and places atags in
some hardcoded memory address no matter what.
Is this behaviour really OK? Isn't r2 register a proper way to pass
atags on ARM platform? If so, would you merge into mainline a patch
that implement this? I could write it, but I don't want end-users of
my work to have to patch and compile Qemu manually.
Please CC me, I'm not following actively these mailinglists.
Regards,
--
Dawid Ciężarkiewicz
Please take the time to comment on this mockup, would it be useful for you?
what other info you like to see to make your job easier, know what you have
on your plate, your WIs progress, what is next in priority ....
BR,
Mounir
---------- Forwarded message ----------
From: Guilherme Salgado <guilherme.salgado(a)linaro.org>
Date: Wed, Feb 1, 2012 at 9:54 AM
Subject: [RFC] Upcoming work view for individual engineers
To: linaro-dev(a)lists.linaro.org
Hi folks,
We're trying to make status.l.o more useful to engineers and the first
thing we're planning to do is a new page listing the upcoming work
assigned to a given person. I'm attaching a mockup of that view here and
we'd like to know what you think of it... Do you think that would be
useful to you? Is there any other information you'd like to see there,
or maybe a different way to present/group them?
Cheers,
--
Guilherme Salgado <https://launchpad.net/~salgado>
_______________________________________________
linaro-dev mailing list
linaro-dev(a)lists.linaro.org
http://lists.linaro.org/mailman/listinfo/linaro-dev
--
Mounir Bsaibes
Project Manager
Follow Linaro.org:
facebook.com/pages/Linaro/155974581091106http://twitter.com/#!/linaroorghttp://www.linaro.org/linaro-blog <http://www.linaro.org/linaro-blog>
Adjusted my 64-bit shifts patch to address Richard Earnshaw's concerns,
tested it, and posted the new one upstream.
Continued trying to figure out how ira-costs.c works, and in particular,
why it doesn't choose to do 64-bit stuff in NEON when I think it should.
Basically, the problem seems to be that when hard regs are *already*
assigned, prior to IRA (say because they are function parameters or
return values), then the allocator does not even consider the
possibility of moving that value to another register unless it
absolutely has to. It will merrily choose the worst possible option just
because it's the easiest decision.
Merged FSF GCC 4.5 into Linaro GCC 4.5. Likewise for 4.6. Pushed the
branches to Launchpad for testing. The 4.5 testing did not come back
totally clear, so this may delay the release a little. Hmmm.
Updated my FSF GCC 4.7 checkout and rebuilt it. This time the build
succeeded, so I've used it as the basis for a shiny new launchpad branch
"lp:gcc-linaro/4.7". I've created the release series to go with it.
Applied my new 64-bit shifts patch to the new GCC 4.7 Linaro branch and
submitted a merge request. This is mostly for the purposes of getting
the test results at this point.
Hi guys,
I compile a native gdb using linaro 2011.10 by “./configure
--host=arm-none-linux-gnueabi --target=arm-none-linux-gnueabi”, and
the gdb runs on arm target boards directly.
# gdb
GNU gdb (Linaro GDB) 7.3-2011.10
Copyright (C) 2011 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "arm-none-linux-gnueabi".
For bug reporting instructions, please see:
<http://bugs.launchpad.net/gdb-linaro/>.
(gdb)
I can use it to debug native programs on target boards directly. For
example, attach process, set breakpoints, check registers and memory.
One issue is I can't see multi-threads, for example:
PID 646 is system_server by ps
"646 1000 159m S system_server"
Then I use gdb to attach it:
# gdb attach 646
(gdb) info threads
Id Target Id Frame
* 1 process 646 "system_server" __ioctl ()
at bionic/libc/arch-arm/syscalls/__ioctl.S:15
as you see, “info threads” only shows one thread but there are several
threads in system_server.
But if I compile a new program based on glibc and gnu libthread, I can
see multi-threads by the gdb.
So my questions are:
1. Should I compile the native gdb using android toolchain and android
bionic/libthread libraries?
2. Why can’t the current gdb capture multithreads for android
processes? This question is actually about the theory for gdb to know
multi-threads. In my opinion, both gnu and android use clone() to fork
threads and threads in one process have same tgid in kernel and all
threads return same getpid() value. Why not gdb just travel process
lists to find multi-threads?
Thanks
Barry
Hi,
* Learned the basics of bzr and examined the gdb-linaro repository.
* Went through Michael Hope's steps to import upstream's 7.4 branch into
bzr.
* Explored gdb-linaro bugs and blueprints in Launchpad to familiarize
myself with what has been done
and is planned or proposed to be done.
* Went through the gdb-linaro/7.3 branch to verify what needs to be
forward-ported to gdb-linaro/7.4.
Forward-ported 10 patches.
* Checked which Linaro Connect sessions would be of interest for me to
attend remotely, but
found out that only one will be available for remote participation.
* Worked very little on Wednesday since my laptop refused to turn on
again after I hibernated it.
I found out on the next day that plugging in an external monitor makes
it happy again (I didn't
have a monitor on Wed to try this out so I was stuck). Apparently the
LCD screen died.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi,
libunwind
* reviewed small patch from T. R. of Nokia who provided a bugfix
when searching for unwind table entry for an IP
OpenEmbedded
* build the OE-core images (minimal, sato and qt4e) with -O1 and -O0
* collected the ELF size and memory footprint and updated the charts
* encountered an issue when compiling Qt 4.8.0 using -O0. It causes
qdbusviewer fail to link
because an .LTHUNK symbol survives
* tested various compilers and optimization levels and
noticed that the .LTHUNK symbols do also survive with higher
optimization levels
* only the Linaro and ARM CSL toolchains seem to be affected
(FSF trunk, 46branch and 46release seem to work)
* provided a reduced testcase and opened lp #924726
* Linaro cc1 emits undefined label when using -fPIC -Os (lp #924889)
* already fixed upstream, Ramana is backporting to Linaro GCC
* look into the external-toolchain branch from C. Larson:
https://github.com/kergoth/oe-core/tree/external-toolchain
and tested it against CSL 2011.03 -> works fine
* started to document:
https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core
Regards,
Ken
== GCC ==
* Benchmarking the 4.6 backport of subreg forward-propagation
confirmed that this is a net loss. On 4.7, microbenchmarks
suggest a different outcome (due to register allocator
enhancements), so I've created a 4.7 Bazaar branch including
the patch and submitted it for benchmarking.
* Implemented a patch to allow memory operands with vec_set and
vec_extract to avoid excessive vmov generation in the PR 51819
test case. Patch shows no regression on microbenchmarks; full
testing and benchmarking still outstanding.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
RAG:
Red:
Amber:
Green:
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-02-20 || ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?||2012-02-01 ||
(for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
== cp15-rework ==
* Since this isn't in the critical path any more we'll work on it
next quarter, and adjust its priority/due dates post Connect.
== qemu-kvm-getting-started ==
* finished writing up HowTo documents for reproducing the KVM
prototype and running it on a Fast Model:
https://wiki.linaro.org/PeterMaydell/KVM/HowTo
* did the last bits of testing enough to be able to say we've done
the initial prototype work for TCWG2011-A15-KVM, which means we
can close out the qemu-kvm-getting-started blueprint.
== other ==
* more upstream patch review, etc
* LP:926012: patches to support prctl(PR_SET_NAME, ...) in linux-user
mode, for the benefit of perl 5.14.
Summary:
* Analyze PATH issues for win32 binary toolchain.
Details:
1. Analyze PATH issues for win32 binary toolchain.
* gcc can not find the install dir if user set
PATH="INSTALL_DIR\bin" in dos cmdline, which leads to compile fail
since gcc can not find ../lib, ../libexec, etc.
* Root cause: in dos, " is taken as part of dirs during set PATH,
which is different from cygwin or linux. And dir with " is invalid in
dos.
* Work out a patch to filter " in function make_relative_prefix_1
and discuss it with Michael.
* Create an windows install package, so users do not need to set
PATH. Will discuss more detail with Michael for the following
releases.
2. Read document to ramp-up on gcc.
Plans:
* Feb 6-10: Linaro Connect Q1.12
Best regards!
-Zhenqiang
I've set up a new user on my laptop that we can use for experimenting
with benchmarks during Connect. Here's what we've got:
* A user called 'connect'
* Ramana, Ulrich, Åsa, and myself can log in via SSH
* bzr repo for trunk, 4.6, and gcc-linaro 4.6
* Tarballs of all gcc-linaro 4.4, 4.5, and 4.6 releases
* Tarballs of the recent CSL, Google 4.6, and Android 4.4 compilers
* A sysroot in ~/sysroot
* Cross-binutils etch in ~/cross
* A shared ccache in ~/ccache primed with these
* A ~/env.sh that sets up the right paths etc
* A ~/builds/doconfigure.sh that configures for our standard ARMv7-A
C/C++/Fortran configuration
* EEMBC, DENBench, and SPEC 2000 under ~/benchmarks
The trees under build/ build into build/$ver/build and install into
build/$ver/install.
The benchmarks are set up to cross build and cross run. I've pulled
ursa2 out of the farm and nuked it, so we can do something like:
make CROSS_COMPILE=arm-linux-gnueabi- RUN="$PWD/sshrun ursa2"
to run the benchmarks.
I'll see about perf. We still need to re-baseline the benchmarks and
get perf traces.
Anything else needed?
You can log in and try things if you want. Go through the bounce host
and try connecting as connect@crucis.
-- Michael
Hi Ramana,
as you pointed out, in the gcc.dg/vect/vect-double-reduc-6.c test case,
using compiler options as described in PR 51819, we see the following
inefficient code generation:
vmov.32 r2, d28[0] @ 57 vec_extractv4si [length = 4]
vmov.32 r1, d22[0] @ 84 vec_extractv4si [length = 4]
str r2, [r0, #4] @ 58 *thumb2_movsi_vfp/7 [length =
4]
vmov.32 r3, d0[0] @ 111 vec_extractv4si [length = 4]
str r1, [r0, #8] @ 85 *thumb2_movsi_vfp/7 [length =
4]
vst1.32 {d2[0]}, [r0:64] @ 31 neon_vst1_lanev4si
[length = 4]
str r3, [r0, #12] @ 112 *thumb2_movsi_vfp/7 [length =
4]
bx lr @ 120 *thumb2_return [length = 12]
(The :64 alignment in vst1.32 is incorrect; that is that actual problem in
PR 51819, which is now fixed.)
The reason for this particular code sequence turns out to be as follows:
The middle end tries to store the LSB vector lane to memory, and uses the
vec_extract named pattern to do so. This pattern currently only supports
an "s_register_operand" destination, and is implemented via vmov to a core
register. The contents of that register are then stored to memory. Now
why does any vst1 instruction show up? This is because combine is able to
merge the vec_extract back into the store pattern and ends up with a
pattern that matches neon_vst1_lanev4si. Note that the latter pattern is
actually intended to implement NEON built-ins (vst1_lane_... etc).
Now there seem to be two problems with this scenario:
First of all, the neon_vst1_lane<mode> patterns seem to be actually
incorrect on big-endian systems due to lane-numbering problems. As I
understand it, all NEON intrinsics are supposed to take lane numbers
according to the NEON ordering scheme, while the vec_select RTX pattern is
defined to take lane numbers according to the in-memory order. Those
disagree in the big-endian case. All other patterns implementing NEON
intrinsics therefore avoid using vec_select, and instead resort to using
special UNSPEC codes -- the sole exception to this happens to be
neon_vst1_lane<mode>. It would appear that this is actually incorrect, and
the pattern ought to use a UNSPEC_VST1_LANE unspec instead (that UNSPEC
code is already defined, but nowhere used).
Now if we make that change, then the above code sequence will contain no
vst1 any more. But in any case, expanding first into a vec_extract
followed by a store pattern, only to rely on combine to merge them back
together, is a suboptimal approach. One obvious drawback is that the
auto-inc-dec pass runs before reload, and therefore only sees plain stores
-- with no reason whatsoever to attempt to introduce post-inc operations.
Also, just in general it normally works out best to allow the final choice
between register and memory operands to be make in reload ...
Therefore, I think the vec_extract patterns ought to support *both*
register and memory destination operands, and implement those via vmov or
vst1 in final code generation, as appropriate. This means that we can make
the choice in reload, guided as usual by alternative ordering and/or
penalties -- for example, we can choose to reload the address and still use
vst1 over reloading the contents to a core register and then using an
offsetted store.
Finally, this sequence will also allow the auto-inc-dec pass to do a better
job. The current in-tree pass doesn't manage unfortunately, but with
Richard's proposed replacement, assisted by a tweak to the cost function to
make sure the (future) address reload is "priced in" correctly, I'm now
seeing what appears to be the optimal code sequence:
vst1.32 {d6[0]}, [r0:64]! @ 30 vec_extractv4si/1
[length = 4]
vst1.32 {d22[0]}, [r0]! @ 56 vec_extractv4si/1 [length =
4]
vst1.32 {d2[0]}, [r0:64]! @ 82 vec_extractv4si/1
[length = 4]
vst1.32 {d4[0]}, [r0] @ 108 vec_extractv4si/1 [length =
4]
bx lr @ 116 *thumb2_return [length = 12]
(Again the :64 is wrong; it's already fixed on mainline but I haven't
pulled that change in yet.)
The attached patch implements the above-mentioned changes. Any comments?
I'll try to get some performance numbers as well before moving forward with
the patch ...
(As an aside, it might likewise be helpful to update the vec_set patterns
to allow for memory operands, implemented via vld1.)
(See attached file: diff-gcc-arm-vecextractmem)
B.t.w. I'm wondering how I can properly test:
- that the NEON intrinsics still work
- that everything works on big-endian
Any suggestions would be appreciated!
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi Andrew. gcc-4.7~svn183693 just finished running through the auto
builders and builds and tests in the ARM, Cortex-A9, i686, and x86_64
configurations.
You could base the Linaro 4.7 branch off that. It's r114897 in bzr
and, suitably, Sandra is the author.
-- Michael
For your records:
Loïc wrote a script that pushes the revisions from a GCC branch into
the current development focus. This makes branching on a shared
repository much faster. The script is here:
http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/tools/view/head:/e…
and it runs daily on a cronjob as the cbuild user on the 'apus' EC2
instance (phew).
We'll need to update this when 4.7 comes along.
-- Michael
I've gone through the documentation on the wiki about how to get
going with KVM on Fast Models, to clean it up and reorganise it
and add some of the missing bits (notably how to set up a KVM
guest kernel and filesystem). It's now at:
https://wiki.linaro.org/PeterMaydell/KVM/HowTo
The only minor point I'd still like to address is that at the
moment we document the old-style "build your kernel and arguments
into an .axf file" boot-wrapper, because my changes to support
specifying them at model runtime haven't yet gone into the
boot-wrapper git repo. When they do land I'll update the wiki.
(Yes, technically TCWG2011-A15-KVM says "one page summary" but
I thought splitting it into four pages was much clearer :-))
-- PMM
Ken, Åsa: could you add a -O0 and -O1 build to the size and benchmark
results? I'm looking at the writeup and it would be interesting to
contrast the speed/size of -O0 with -O2.
Ta,
-- Michael
Continued work on 64-bit shifts in core registers. This has now been
posted to gcc-patches, and is awaiting review.
64-bit shifts in NEON are also working correctly, but the register
allocator chooses not to use them most of the time. I've begun trying to
work out why, but it's quite involved in ira-costs.c and will take some
unpicking, I think.
Attempted to create a Linaro GCC 4.7 branch, but my test build failed,
so that'll have to wait until it's stabilized a little.
Hi Marcin, Ricardo. How is the work on pre-built sysroots coming
along? I'd like to use/reference them in the next binary toolchain
release.
I'm looking for:
* Scripts that produce the sysroots
* A README that covers what they contain and how to reproduce them
* Test plan
* An official tagged branch holding the above
* A tarball release of the above
* A tarball release of the different sysroots
* Done in a way so they easily integrate with the binary builds[1]
and are useful to others as a sysroot
* Relocatable
* Usable on win32 and Linux
all hosted somewhere. Zhenqiang and I can test and give you feedback.
For reference, here's the README for the binary builds:
http://launchpadlibrarian.net/90998258/README.txt
Here's the simple script I used to make a libc only sysroot:
http://bazaar.launchpad.net/~linaro-toolchain-dev/crosstool-ng/linaro/view/…
I used chdist as I don't know multistrap. I guessed and added
build-dep support to download the build dependencies. It also fixes
up the absolute symlinks to relative.
-- Michael
[1] https://launchpad.net/linaro-toolchain-binaries
==Progress===
* Fixed PR48308 on FSF trunk. Needs backporting to FSF GCC 4.6 branch
* Fixed a number of failing testcases on trunk.
* Read up on Partial-partial PRE . Slow progress but getting a handle
on the theory now. A couple of approaches being benchmarked . Still
slow progress.
* Debugged Andrew's issues with 64 bit shifts. Nice that skype screen
sharing works well on Ubuntu.
* Started notes for Connect 2012.q1.
* Looked into the strd / strexd failure on the testcase in trunk.
Looked at a small patch to implement sync_lock_releasedi for ARM but
needs some more time and effort. Filed issue
https://bugs.launchpad.net/gcc-linaro/+bug/922474
=== Plans ===
* Finish 1x AFDS
* Continue with partial-partial PRE .
* Finish backport of fix for PR50313 to appropriate branches
* Start preparing for Connect 2012.q1
* Do something about the PGO and ABI patches next week.
Absences.
* Feb 6-10 : Linaro Connect Q1.12.
* Feb 13- 18 : Holiday.
Hi,
* libunwind
* reviewed small patch from T. R. of Nokia who provided a
bugfix in case unwind instructions are popping VFP registers
* exchanged mails with P. W. from Bosch who encountered a crash
in case DWARF info is involved
* OpenEmbedded
* changed Qt build to respect the optimization flags
* wrote a script around QEMU to measure the memory footprint
using named pipes to communicate with the serial console of the guest
* rebuilt the minimal, sato and qt4e images using the
gcc-linaro-arm-linux-gnueabi-2012.01-20120125_linux
(optimization levels: -O2, -O3 -fno-tree-vectorize and -O3)
* collected/updated the ELF size and memory footprint results:
*
https://docs.google.com/spreadsheet/ccc?key=0AmsCLxCMnnISdDNQSEM2ZHIxd3dVNj…
*
https://docs.google.com/spreadsheet/ccc?key=0AmsCLxCMnnISdHFtZll0OWdiTlhpdj…
* uploaded the image packs to: http://people.linaro.org/~kwerner/oe-core/
* prepared the environment to build the images using -O1
Regards,
Ken
== GDB ==
* Committed follow-on patch to fix cosmetic issues resulting from
the remote "info proc" patch set.
== GCC ==
* Created 4.6 backport branch including Richard's subreg forward-
propagation branch, the modes-tieable patch, and the combine.c
regression fix, and evaluated for correctness and performance.
Investigation of performance regressions uncovered a problem in
the register allocator: tied subregs (validly) cause somewhat
larger register pressure in certain cases, and this caused the
4.6 IRA to generate spills. Note that the 4.7 IRA is still
able to allocate every pseudo in the very same code; this is
a result of Vladmir's significant IRA rewrite in 4.7 ...
* Investigated Ramana's vld1 patches, and a problem with excessive
vmov's in the PR 51819 test case pointed out by Ramana. It turns
out that when we extract a lane from a vector to memory using an
offsetted address, we move the value through a core register
instead of simply computing the address and using vst1.
I'm working on a patch to address this.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
RAG:
Red:
Amber:
Green:
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-02-20 || ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| ||
(for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
== cp15-rework ==
* discussions with Rusty
== qemu-kvm-getting-started ==
* wrote patches for the A15 Fast Models boot-wrapper that allow you
to pass the kernel/initrd/kernel command line via a parameter to
the model rather than having to hard code them into an ELF file
along with the boot-wrapper. This should make life a lot easier for
the validation folk.
* various discussions with validation/etc about what you can and
can't do with a model and what the best setup is going to be
* sorted out a Debian fs to use for KVM guest : this is needed because
the kernel module doesn't do Thumb or VFP yet.
* started on rearranging and improving the writeup/HOWTO on the wiki
== other ==
* target-arm/arm-devs queues pushed upstream [Calxeda Highbank model
is now in upstream QEMU]
* helping Will Deacon track down what looks like a race condition in
Linux's handling of VFP on SMP where signal handlers are involved
* a QEMU Object Model patch series has landed upstream -- this will
be a nasty rebase for qemu-linaro next week I think
Hi!
* -o2/-o3 benchmarking:
Worked on and shared charts for the -o2/-o3 benchmark runs with
gcc-linaro-4.6-2012.01. I have created charts for both the score of the
benchmarks and the sizes (text segment) of the executables. Making
improvements continuously as I get feedback from the team.
The charts are stored in GoogleDocs:
https://docs.google.com/a/linaro.org/leaf?id=0B1IP4dZWVaxZOGZlM2UwMGQtOGQyZ…
* gcc4.7 benchmarking:
Did benchmark runs on a late revision of gcc4.7.
Next week I will process the data and list regressions/improvements against
gcc4.6.2 and gcc-linaro-4.6-2012.01.
* v8:
Investigated possibility of running SunSpider stand-alone on the v8 engine.
Found out that there is a stand-alone driver included in WebKit.
Have built v8 on x86 and ARM (on ARM it takes ~18 min) and run SunSpider
and the v8 benchmark suite.
Next step I will try to build with another toolchain. It is not Make but
SCons that controls the build, so I am not sure how to do that.
https://wiki.linaro.org/AsaSandahl/Sandbox/JavaScriptBenchmarks
* Bug triaging:
I have triaged all "easy" ones in the list of new tickets. Michael will
help me look through the rest of new and incomplete bugs which are mostly
old ones (waiting for someone to take some action) or very tricky ones.
Regards
Åsa
On Wed, Jan 25, 2012 at 7:02 AM, Ulrich Weigand
<Ulrich.Weigand(a)de.ibm.com> wrote:
>
> Hi Michael,
>
> GDB 7.4 has finally been released. What do we need to do to get the
> 7.4-branch imported into Launchpad? I think last time (for 7.3) you did
> that somehow ...
Done as:
lp:~linaro-toolchain-dev/gdb/7.4
and documented at:
https://wiki.linaro.org/MichaelHope/Sandbox/GDBImport
-- Michael
Peter, could you review:
https://wiki.linaro.org/WorkingGroups/ToolChain/QEMUARMGuestQ411
please? I'm interesting in anything I've missed or exaggerated. The
audience is the TSC or people outside Linaro who are interested in a
summary of the changes.
-- Michael
Hi Zygmunt. I've enabled the ARM native build on the QEMU auto
builders. These are built in the validation lab on the Natty based
tcpanda boards and end up on control under
~cbuild/cbuild/build/qemu-$version/qemu-$something.tar.xz.
I've uploaded this build to
http://people.linaro.org/~michaelh/incoming/qemu-armv7l-natty-cbuild236-tcp….
There's something wrong with embedding of the version number into the
name. A quick 'does it run' test passes.
Peter, could you check the configure log at:
http://builds.linaro.org/toolchain/qemu-linaro-0~20120118+gitcc8661e/logs/a…
and see if there's anything missing.
The auto builders fire with each commit so there's always something up
to date. You can list the builds at:
http://ex.seabright.co.nz/helpers/buildlog/qemu
and see the raw results at:
http://builds.linaro.org/toolchain/qemu-linaro-0~20120118+gitcc8661e/logs/a…
(after a lag)
-- Michael
---------- Forwarded message ----------
From: Linaro Toolchain Builder <michael.hope+cbuild(a)linaro.org>
Date: Thu, Jan 26, 2012 at 11:14 AM
Subject: [cbuild] qemu-linaro-0~20120118+gitcc8661e armv7l completed
To: "linaro-toolchain-builds(a)lists.launchpad.net"
<linaro-toolchain-builds(a)lists.launchpad.net>
tcpanda05 finished running job qemu-linaro-0~20120118+gitcc8661e on
armv7l-natty-cbuild236-tcpanda05-cortexa9r1.
The results are here:
http://builds.linaro.org/toolchain/qemu-linaro-0~20120118+gitcc8661e
9 PASS 9 TEST
This email is sent from a cbuild (https://launchpad.net/cbuild) based
bot which is administered by Michael Hope <michael.hope(a)linaro.org>.
The Linaro Toolchain Working Group is pleased to announce the release
of the Linaro Toolchain Binaries, a pre-built version of Linaro GCC
and Linaro GDB that runs on generic Linux or Windows and targets the
glibc Linaro Evaluation Build.
This is the first release. Releases will be made each month shortly
after the corresponding source release.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 2012.01
* Linaro GDB 2011.12
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
The Linux version is supported on Ubuntu 10.04.3 and 11.10, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.01
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
-- Michael
On Wed, Jan 25, 2012 at 2:33 AM, Ulrich Weigand
<Ulrich.Weigand(a)de.ibm.com> wrote:
>
> Michael, Åsa,
>
> as discussed in today's performance call, the 4.6 backport of Richard's
> sched-pressure enhancements is available here:
> https://code.launchpad.net/~rsandifo/gcc-linaro/alt-sched-pressure-4.6
>
> To activate the feature, you need to use the options:
>
> -fsched-pressure -fsched-pressure-algorithm=model
Åsa, I think we're ready to spawn benchmark jobs through the build
farm. I've made a front end:
http://ex.seabright.co.nz/helpers/scheduler/spawn
to make it a little easier to use. To spawn a benchmark run, enter a
job called benchmarks-<buildname> such as
benchmarks-gcc-linaro-4.6+bzr106857~rsandifo~alt-sched-pressure-4.6
and spawn it into the 'test' queue. See the page for how to change
the flags and benchmarks that are run.
The results end up at:
http://ex.seabright.co.nz/benchmarks/
which needs the password from:
https://wiki.linaro.org/Internal/ToolChain
I've spawned Ulrich's job into the queue as a test run. Let's see how
it goes. If it works, you can spawn the ancestor
(benchmarks-gcc-linaro-4.6+bzr106856) and later do a diffbench on the
results.
-- Michael
Hi,
I am looking at ticket 739305 "[armhf] libffi variadic support"
which still has status "New" for Linaro gcc.
https://bugs.launchpad.net/ubuntu/+source/libffi/+bug/739305
If I understand correctly, David's patch is included in libffi in Oneiric,
but not yet backported to Linaro gcc?
What is the correct thing to do with this ticket for Linaro GCC?
I was thinking it could be set to "Triaged", waiting for an appropriate
time to backport.
Regards
Åsa
Spotted this in a Phoronix article today:
Overall it seems that most of the computational tests are performing
better with the newer Ubuntu 11.10 and 12.04 user-space packages,
which upgrades the GNU Compiler Collection to the 4.6 series over
the 4.5 release found in Ubuntu 11.04. The 4.6 compiler upgrade with
greater ARMv7 architecture enhancements is likely what can be
attributed to most of the performance improvements found in this
article. [...]
See the results for yourself at:
http://www.phoronix.com/scan.php?page=article&item=nvidia_tegra2_ubuntu&num…
Good job,
--
Christian Robottom Reis, Engineering VP
Brazil (GMT-3) | [+55] 16 9112 6430 | [+1] 612 216 4935
Linaro.org: Open Source Software for ARM SoCs
* Linaro
Continued work on 64-bit multiplies. Cleaned up the patches a lot.
Started testing work to check for correctness. Ironed out a few bugs.
My turn for patch review week.
* Other
Spent most of the week in San Diego attending the formerly-known-as
CodeSourcery annual meeting, now Mentor Graphics' ESD TOOLS team annual
meeting.
Mostly bug hunting week with some time on Partial partial PRE.
==Progress===
* Fixed PR50313 - backport submitted to Linaro 4.6 branch for testing
- Testing on FSF GCC 4.6 branch as well currently.
* Followed up on PR48308 fix . No reply yet.
* Triaged some of the test failures that we are currently seeing on
FSF trunk. Reported a few bugs upstream which I think are now fixed.
There are still too many vect failures for my liking ( nearly 30 odd
unique) . Some of them are testisms and some of them probably need a
bit of knowledge in the vectoriser. So could do with a hand here in
case someone has some free time and needs things to look at .
* Read up on Partial-partial PRE . Slow progress but getting a handle
on the theory now.
* Handed over the vld1 / vldm work to Uli - found another case where
the compiler could do better while fixing up PR51819. Essentially in
loop end code where we have cleanup code involving single elements
from the vector, the backend prefers to move this to an integer
register and store the value to memory which is just silly - See
https://pastebin.linaro.org/385
* Fixed PR51819. Backported fix to Linaro 4.6 branch - The FSF 4.6
branch *doesn't* show this particular problem.
=== Plans ===
* Continue with partial-partial PRE .
* Finish submitting PGO patch and ABI tests patch
* Finish backporting PR50313 fix to the correct repositories.
* Follow up on PR48308 and investigate this a bit further.
* Start preparing for Connect 2012.q1
Absences.
* Feb 6-10 : Linaro Connect Q1.12.
* Feb 13- 18 : Holiday.
== GDB ==
* Fixed some final minor issues with remote "info proc".
Committed patch set to implement remote "info proc" (LP #804411)
and remote core file generation (LP #804406) to mainline.
Backported to Linaro GDB 7.3.
== GCC ==
* Created patch to fix optimization failures on x86_64 exposed by
Richard's subreg forward-propagation patch.
* Set up Richard's loop-microbenchmarks suite and verified that the
subreg forward-propagation patch causes no regression anywhere,
and shows measurable improvements on some cases in GCC mainline.
With the Linaro GCC 4.6 backport, results don't look as good;
still investigating the cause.
* Started looking into Ramana's vld1 patches.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
* hacked the external toolchain recipe to use the latest version of the
binary toolchain
this kind of reverts the multiarch changes since oe doesn't support
it yet
* built the minimal, sato and qt images for armv7-a
in three different flavors (-O2, -O3 -fno-tree-vectorize, -O3)
using gcc-linaro-arm-linux-gnueabi-2012.01-20120112+bzr2318~linux
see: http://people.linaro.org/~kwerner/oe-core/
* encountered that binutils 2.22 (the gas) fails to build with -O3
due to a warning about an unitialized variable
I'm not convinced this is a real bug, I'll look at it as time permits
workaround: --disable-werror
* all nine of them (the images) are booting within qemu using
vexpress_defconfig!
There is one glitche with the mouse pointer:
it doesn't match to the one of the SDL/VNC window as
the guest pointer sometime accelerates faster that the host pointer
I can hardly imagine this is due to miscompiled code
* Extracted size informations about the generated ELF files:
https://docs.google.com/spreadsheet/ccc?key=0AmsCLxCMnnISdDNQSEM2ZHIxd3dVNj…
Regards,
Ken
RAG:
Red:
Amber:
Green: A15 vexpress system model sufficient for KVM guest now done
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-02-20 || ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| ||
(for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
== cp15-rework ==
* some (slow) progress on this
* made a list of the missing pieces in my current patchset and
knocked off a few of the easier ones
* fortunately this blueprint isn't really a critical blocker for
KVM work any more
== initial-a15-system-model ==
* vexpress-a15 now submitted upstream (in review) and in qemu-linaro
* ...so this blueprint is complete
* NB: doesn't boot in KVM but this is a trivial kernel-side issue
== other ==
* this category seems to take most of my time :-(
* patch review: still Calxeda, Samsung
* patch review: softfloat type fixes
* identified some bugs in softfloat and arm code that surface if a
softfloat type is 64 bits (at the moment it is 32 bits in practice
but it is being proposed to widen it)
* wrote up the issues to be solved so somebody else can do qemu-linaro
releases
* got qemu-jeos building for ARM [an attempt at making qemu testing
easier by having an automated "build toolchain/kernel/initrd" setup]
* retested QEMU fused-multiply-accumulate against an A15 FPGA
Hi Åsa. The GCC 4.7 release is coming up and the ARM testsuite shows
a lot of regressions:
http://ex.seabright.co.nz/helpers/testlog/gcc-4.7~svn183205/logs/armv7l-nat…
We've been running three builds a week:
http://ex.seabright.co.nz/helpers/buildlog/gcc-4.7~svn
and can use the result to track down the range of commits where a
fault was introduced or exposed.
Could you please look through the results and narrow down where each
failure appeared? I've uploaded all of the results to:
http://people.linaro.org/~michaelh/incoming/trunks.tar.xz
One way is to look at the testsuite-diff.txt in each build as it
should show the change in test results between one build and the next
but might be incomplete. Another way is to pull the failures out of
gcc-testsuite.txt and do a diff against the previous version.
The output should be a revision range for each of the current failures.
Script it up. Don't do it by hand. I'm not that mean.
Ta,
-- Michael
* Started with bug triaging, looked at four different bugs (including
Michael's example). Challenging, but interesting. Got great help from
Ramana and Andrew.
* -o2/-o3 benchmark runs with gcc-linaro-4.6-2012.01 done. coremark, eembc,
denbench, pybench and spec2000. Uploaded all results
~linaro-toolchain-wg/linaro-toolchain-benchmarks/private-runs. Posted
results for -o2-neon vs -o3-neon-novect. Working on charts including also
-o3-neon and -os. Got a bit too occupied with making the matplotlib charts
look pretty. I will try to get all results posted next week.
* Started the add-sunspider-as-a-benchmark blueprint in the background.
Built the v8-engine stand alone on x86 (just with default options). It has
a sample shell included. You can feed it with .js-files. Tried the v8
benchmark, which also comes with the engine.
Regards
Åsa
Hi all,
I will be out for vacation during Chinese Spring Festival (Jan
21-29, 2012). For emergency, call me at +86-13817948562.
Best regards!
-Zhenqiang
Summary:
* Enhance crosstool-ng build process.
Details:
1. Linaro crosstool-ng patches:
* Update and commit the patch to strip debug sections.
* rm *-cc.exe symblink for win32.
* enable gdb for win32 (lp:918479)
* Update README to add flip dependence for build.
2. Verify the following bugs and change status to "Fix Committed"
* lp:906729 baremetal libc headers and libraries are in inconsistent places
* lP:906077 binaries: baremetal include files are in the wrong place
* lP:894527 binaries: remove all symlinks from the Windows build
* lp:889984 binaries: should step across helper functions
* lp:906662 binaries: pgversion can get out of sync with product
3. Analyzed bugs
* lp:915137 Link failure due to absolute paths: Need more
information to reproduce.
* lp:p18478 wind32 doesn't have pkg-config: Try to build pkg-config
for mingw32 host. But failed since it required preinstalled glib2. And
configure error if cross building the glib.
* lp:894528 binaries: can't run if the patch contains whitespace.
Can not reproduce it on cygwin, but still have issue in DOS cmdline
4. Verify the prerelease binary package on windows. And find and
workaround a gdb document name issue since filename on windows is case
insensitive (lp:909195).
5. Raise the gcc trunk build fail issue to crosstool-ng mail-list. But
not confirm "-EL" is the final root cause. Need more investigation.
Planned Absence:
* Jan 21-29, 2012 Chinese Spring Festival
Best regards!
-Zhenqiang
Hello experts,
I don't know whether this is the place to ask this question.Please forgive
if i am wrong.
I am trying to cross-compile Eglibc,(which i thought is similar to the
glibc) library with Linaro tool chain.My aim is to cross-compile the
library and add it with the tool-chain( i assumed that Linaro doesn't ahve
the eglibc libraries by itself).
.
I referred to the link http://www.eglibc.org/archives/patches/msg00078.html
(README.cross-compiling of the libc) and did the following.
I thought that binutils is not required as the tool chain itself contains
the loader, assembler etc.(which are the most important in the binutils).So
i skipped that step.(i am not sure whether this is right.please correct me
if i am wrong).
I did the below steps as in the above link.
1) Copied the Linux Kernel Headers
2) EGLIBC Headers and Preliminary Objects
2.1) configuring the Eglibc headers by the below steps.
appan@oplt$ ~/cross_compile_eglibc/ppc/obj/eglibc-headers$ BUILD_CC=gcc
CC=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-gcc
CXX=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-cpp
AR=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-ar
RANLIB=/home/appaan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-ranlib
/home/appan/cross_compile_eglibc/src/libc/configure
--prefix=/home/appan/CC_EGLIBC
--with-headers=/home/appan/cross_compile_eglibc/ppc/sysroot/usr/include/
--build=i686-pc-linux-gnu --host=arm-unknown-linux-gnu --enable-add-ons
--with-tls --with-__thread
2.2) compilation
make install-headers install_root=$sysroot install-bootstrap-headers=yes
But following is the error i get.
> /home/appan/cross_compile_eglibc/ppc/obj/eglibc-headers/Versions.v.iT<http://versions.v.it/>
In file included from <stdin>:1:0:
ports/sysdeps/arm/nptl/tls.h:48:3: error: #*error "TLS support is required.*
"
make[1]: *** No rule to make target `headers_install'. Stop.
make[1]: Leaving directory `/home/appan/cross_compile_eglibc/src/libc'
make: *** [headers_install] Error 2
I tried googling, but i did not get the solution for this..
please provide me with some suggestions and that will be of great help to
me...
thanks and regards
appan
Hi there!
I need some help with how to handle this bug:
https://bugs.launchpad.net/gcc-linaro/+bug/873977
It looks like an improvement suggestion more than a bug.
Regards
Åsa
*Automatically save preprocessed source on ICE*In order to help with bug
reporting, gcc could save the preprocessed source of the unit that caused
the ICE, so one can just pick it up and attach it to bug reports instead of
trying to reproduce it manually.
Hi Peter. I've had a poke about in qemu-linaro, OpenStack, and
libvirt to get a feel for the KVM integration work. My scratch notes
are here:
https://wiki.linaro.org/MichaelHope/Sandbox/QEMUA15GuestNotes
I'm feeling happy about the integration. The parts that I've seen
have good separation, are architecture neutral, and have some ARM
support. We can prototype using virtual x86 based masters and QEMU
TCG based compute instances.
I've seen a few bugs and assumptions: OpenStack defaults to virtio,
boot=hda, and fixed kernel args; and libvirt can't parse the the
qemu-linaro version string. There will be more.
I'll feed this into the KVM 1.0 task list and share it.
-- Michael
Hi there. Starting next week we'll switch to the Zip conference line. See:
https://wiki.linaro.org/Resources/ZipConferenceLine
under 1-719-457-1414 for a list of numbers. A selected few are:
UK 0 808 101 1146
Germany 0 800 181 9019
Sweden 02 079 7556
Brazil, Sao Paulo Local +55 11 5582 6534
Australia 1 800 105 680
China +400 148 5400
NZ 0800 451 015
The code is 763 804 0680. I've updated the meeting calendar and will
update the wiki page once Monday comes around. The moderator code is
on the toolchain internal page.
Amber, could you update the public event please?
Ramana, could you update the performance call for two weeks time?
Maybe move it to linaro-events so I can edit it.
-- Michael
Hi Michael,
So, I gave my best shot at:
https://bugs.launchpad.net/gcc-linaro/+bug/914703
Kind of similar to the one in your walk-through, but I couldn't actually
reproduce on the version reported.
Could you please check if this looks OK?
Regards
Åsa