- linaro-toolchain - lists.linaro.org

Re: [Linaro-TCWG-CI] gcc-14-5032-ge3da1d7bb28: Failure on arm

by Maxim Kuvyrkov

Hi Richard, This patch also breaks profiled_bootstrap on aarch64-linux-gnu, which may be easier to reproduce, see [1]. [1] https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sh… Regards, -- Maxim Kuvyrkov https://www.linaro.org > On Nov 1, 2023, at 15:46, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In bootstrap_build master-arm-bootstrap_profiled_lto_lean after: > > | commit gcc-14-5032-ge3da1d7bb28 > | Author: Richard Biener <rguenther(a)suse.de> > | Date: Tue Oct 31 10:13:13 2023 +0100 > | > | tree-optimization/112305 - SCEV cprop and conditional undefined overflow > | > | The following adjusts final value replacement to also rewrite the > | replacement to defined overflow behavior if there's conditionally > | evaluated stmts (with possibly undefined overflow), not only when > | we "folded casts". The patch hooks into expression_expensive for > | this. > | ... 10 lines of the commit log omitted. > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe bootstrap_profiled_lto_lean: > # FAILED > # First few build errors in logs: > # 01:55:54 /home/tcwg-buildslave/workspace/tcwg_gnu_4/abe/snapshots/gcc.git~master/libiberty/regex.c:5549: internal compiler error: Segmentation fault > # 01:55:54 make[4]: *** [/tmp/ccj2LJs3.mk:380: /tmp/ccIWXeRO.ltrans126.ltrans.o] Error 1 > # 01:57:45 lto-wrapper: fatal error: make returned 2 exit status > # 01:57:46 /usr/bin/ld: error: lto-wrapper failed > # 01:57:46 collect2: error: ld returned 1 exit status > # 01:57:46 make[3]: *** [/home/tcwg-buildslave/workspace/tcwg_gnu_4/abe/snapshots/gcc.git~master/gcc/cp/Make-lang.in:145: cc1plus] Error 1 > # 01:57:46 make[2]: *** [Makefile:5260: all-stagefeedback-gcc] Error 2 > # 01:57:46 make[1]: *** [Makefile:26669: stagefeedback-bubble] Error 2 > # 01:57:46 make: *** [Makefile:26689: profiledbootstrap] Error 2 > # 00:06:15 make[3]: [Makefile:1822: armv8l-unknown-linux-gnueabihf/bits/largefile-config.h] Error 1 (ignored) > # 00:47:56 make[3]: [Makefile:1822: armv8l-unknown-linux-gnueabihf/bits/largefile-config.h] Error 1 (ignored) > # 01:09:35 make[3]: [Makefile:1822: armv8l-unknown-linux-gnueabihf/bits/largefile-config.h] Error 1 (ignored) > # 01:14:05 /home/tcwg-buildslave/workspace/tcwg_gnu_4/abe/snapshots/gcc.git~master/libiberty/regex.c:5549:1: internal compiler error: Segmentation fault > # 01:14:05 /home/tcwg-buildslave/workspace/tcwg_gnu_4/abe/snapshots/gcc.git~master/libiberty/regex.c:5549:1: internal compiler error: Segmentation fault > # 01:14:05 /home/tcwg-buildslave/workspace/tcwg_gnu_4/abe/snapshots/gcc.git~master/libiberty/regex.c:5549:1: internal compiler error: Segmentation fault > # 01:14:05 make[4]: *** [/tmp/ccCI7mJj.mk:20: /tmp/ccH1y1BV.ltrans6.ltrans.o] Error 1 > # 01:14:05 make[4]: *** [/tmp/cciXJOsB.mk:20: /tmp/ccaXf4f5.ltrans6.ltrans.o] Error 1 > # 01:14:05 make[4]: *** [/tmp/cccYndDm.mk:20: /tmp/cc6tlPuq.ltrans6.ltrans.o] Error 1 > # 01:14:07 lto-wrapper: fatal error: make returned 2 exit status > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe bootstrap_profiled_lto_lean: > 1 > > The configuration of this build is: > CI config tcwg_bootstrap_build/master-arm-bootstrap_profiled_lto_lean > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_profil… > Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_profil… > > Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sh… > > Full commit : https://github.com/gcc-mirror/gcc/commit/e3da1d7bb288c8c864f0284bc4bc5877b4… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-989 > > List of configurations that regressed due to this commit : > * tcwg_bootstrap_build > ** master-arm-bootstrap_profiled_lto_lean > *** Failure > *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sh… > *** https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_profil…

1 year, 12 months

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[ACTIVITY] Report for week #43

by Philippe Mathieu-Daudé

Progress: * QEMU-610 [Remove qemu_get_cpu() from hardware models] - Big rework of Cortex-A MPCore models. A common class is now used and various duplicated code from ARM boards got removed. Possible follow-up with QEMU-601 [Implement TYPE_CORTEXR52_PRIV].

1 year, 12 months

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[ACTIVITY] Report for week #43

by Thiago Jung Bauermann

Hello, # [GNU-981] FEAT_GCS (Guarded Control Stack) support in GDB - Started working on this feature. Currently adding ptrace and core file support for the NT_ARM_GCS regset. # Upstream community - Implemented fix for ‘--with-auto-load-dir’ and ‘--with-auto-load-safe-path’ configure options on Windows (since Eli mentioned it earlier this month) and posted “[PATCH] gdb/configure.ac: Fix auto-load options to work with Windows path separator”. -- Thiago

2 years

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[weekly][linaro] report week ending 27 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Took a prototype set of patches to add a second UART to the virt board which I'd written before going off on holiday; cleaned them up and got them into shape to send out for review. This is likely to be QEMU 9.0 material because we want to wait for the fix to EDK2 to make it handle the second uart more sensibly to get into an upstream EDK2 before landing the QEMU patches. - More code review work; sent this week's target-arm pull request * QEMU-292 [ARMv8.3 FEAT_NV, Nested Virtualization] - Started on implementation. This seems to be shaping up to be a less difficult task than our initial estimate suggested; I have code-complete patches for most of the necessary behaviour changes already. (Testing may be a more drawn-out effort :-)) -- PMM

2 years

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Re: [Linaro-TCWG-CI] 31 patches in gcc: Failure on aarch64

by Christophe Lyon

Sorry, there was a temporary breakage in our CI scripts, you can ignore this bogus report. On Tue, 24 Oct 2023 at 18:25, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In gcc_build master-aarch64 after: > > | 31 patches in gcc > | Patchwork URL: https://patchwork.sourceware.org/patch/78409 > | ecdd9931b4f libstdc++: Optimize std::is_pointer compilation performance > | 2d53274d549 c++: Implement __is_pointer built-in trait > | 9414aba0b5b libstdc++: Optimize std::remove_pointer compilation performance > | b0f04909269 c++: Implement __remove_pointer built-in trait > | f5ae5fbcc28 libstdc++: Optimize std::is_object compilation performance > | ... and 26 more patches in gcc > | ... applied on top of baseline commit: > | 326a8c047ec testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > # FAILED > # First few build errors in logs: > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > 1 > > The configuration of this build is: > CI config tcwg_gcc_build/master-aarch64 > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-precommit/3362/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-build/1263/artifac…

2 years

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[Linaro-TCWG-CI] glibc-2.38.9000-193-gb121fdc552: FAIL: 2 regressions on arm

by ci_notify＠linaro.org

Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In glibc_check master-arm after: | commit glibc-2.38.9000-193-gb121fdc552 | Author: Arjun Shankar <arjun(a)redhat.com> | Date: Mon Oct 2 14:55:15 2023 +0200 | | Remove 'grp' and merge into 'nss' and 'posix' | | The majority of grp routines are entry points for nss functionality. | This commit removes the 'grp' subdirectory and moves all nss-relevant | functionality and all tests to 'nss', and the 'setgroups' stub into | 'posix' (alongside the 'getgroups' stub). References to grp/ are | accordingly changed. In addition, compat-initgroups.c, a fallback | ... 6 lines of the commit log omitted. FAIL: 2 regressions regressions.sum: === glibc tests === Running glibc:nss ... FAIL: nss/tst-initgroups1 FAIL: nss/tst-initgroups2 === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/678/artifact/a… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/678/artifact/a… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/678/artifact/a… . The configuration of this build is: CI config tcwg_glibc_check/master-arm -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/678/artifact/a… Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/676/artifact/a… Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/… Full commit : https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=b121fdc552f392cd86b2… Latest bug report status : https://linaro.atlassian.net/browse/GNU-979 List of configurations that regressed due to this commit : * tcwg_glibc_check ** master-arm *** FAIL: 2 regressions *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/… *** https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/678/

2 years

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Re: [Linaro-TCWG-CI] gcc patch #78468: Failure on aarch64

by Christophe Lyon

Sorry, there was a temporary breakage in our CI scripts, you can ignore this bogus report. On Tue, 24 Oct 2023 at 18:41, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In gcc_build master-aarch64 after: > > | gcc patch https://patchwork.sourceware.org/patch/78468 > | Author: Daniil Frolov <exactlywb(a)ispras.ru> > | Date: Tue Oct 24 17:11:24 2023 +0300 > | > | Detecting lifetime-dse issues via Valgrind > | > | PR 66487 is asking to provide sanitizer-like detection for C++ object lifetime > | violations that are worked around with -fno-lifetime-dse in Firefox, LLVM, > | OpenJade. > | > | The discussion in the PR was centered around extending MSan, but MSan was not > | ... 33 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 326a8c047ec testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > # FAILED > # First few build errors in logs: > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > 1 > > The configuration of this build is: > CI config tcwg_gcc_build/master-aarch64 > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-precommit/3368/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-build/1263/artifac…

2 years

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Re: [Linaro-TCWG-CI] gcc patch #78433: FAIL: 1162 regressions on aarch64

by Christophe Lyon

Sorry, there was a temporary breakage in our CI scripts, you can ignore this bogus report. On Tue, 24 Oct 2023 at 18:40, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In gcc_check master-aarch64 after: > > | gcc patch https://patchwork.sourceware.org/patch/78433 > | Author: Ajit Agarwal <aagarwa1(a)linux.ibm.com> > | Date: Tue Oct 24 15:01:11 2023 +0530 > | > | ree: Improve ree pass using defined abi interfaces > | > | Hello Vineet, Jeff and Bernhard: > | > | This version 13 of the patch uses abi interfaces to remove zero and sign extension elimination. > | Bootstrapped and regtested on powerpc-linux-gnu. > | > | ... 40 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 0fc13e8c0e3 Improve factor_out_conditional_operation for conversions and constants > > FAIL: 1162 regressions > > regressions.sum: > === g++ tests === > > Running g++:g++.dg/asan/asan.exp ... > FAIL: c-c++-common/asan/alloca_big_alignment.c -O2 output pattern test > FAIL: c-c++-common/asan/alloca_big_alignment.c -O2 -flto -fno-use-linker-plugin -flto-partition=none output pattern test > FAIL: c-c++-common/asan/alloca_detect_custom_size.c -O2 output pattern test > FAIL: c-c++-common/asan/alloca_detect_custom_size.c -O2 -flto -fno-use-linker-plugin -flto-partition=none output pattern test > FAIL: c-c++-common/asan/alloca_detect_custom_size.c -O3 -g output pattern test > FAIL: c-c++-common/asan/alloca_detect_custom_size.c -Os output pattern test > FAIL: c-c++-common/asan/alloca_overflow_partial.c -O2 output pattern test > ... and 1191 more entries > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/3409/art… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/3409/art… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/3409/art… . > > The configuration of this build is: > CI config tcwg_gcc_check/master-aarch64 > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/3409/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/1093/artifac…

2 years

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Re: [Linaro-TCWG-CI] gcc patch #78469: Failure on aarch64

by Christophe Lyon

Sorry, there was a temporary breakage in our CI scripts, you can ignore this bogus report. On Tue, 24 Oct 2023 at 18:38, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In gcc_build master-aarch64 after: > > | gcc patch https://patchwork.sourceware.org/patch/78469 > | Author: Stefan Schulze Frielinghaus <stefansf(a)linux.ibm.com> > | Date: Tue Oct 24 17:26:55 2023 +0200 > | > | testsuite: Fix _BitInt in gcc.misc-tests/godump-1.c > | > | Currently _BitInt is only supported on x86_64 which means that for other > | targets all tests fail with e.g. > | > | gcc.misc-tests/godump-1.c:237:1: sorry, unimplemented: '_BitInt(32)' is not supported on this target > | 237 | _BitInt(32) b32_v; > | ... 12 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 326a8c047ec testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > # FAILED > # First few build errors in logs: > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > 1 > > The configuration of this build is: > CI config tcwg_gcc_build/master-aarch64 > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-precommit/3369/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-build/1263/artifac…

2 years

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Re: [Linaro-TCWG-CI] gcc patch #78466: Failure on aarch64

by Christophe Lyon

Sorry, there was a temporary breakage in our CI scripts, you can ignore this bogus report. On Tue, 24 Oct 2023 at 18:35, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In gcc_build master-aarch64 after: > > | gcc patch https://patchwork.sourceware.org/patch/78466 > | Author: Jose E. Marchesi <jose.marchesi(a)oracle.com> > | Date: Tue Oct 24 14:41:13 2023 +0200 > | > | gcov-io.h: fix comment regarding length of records > | > | The length of gcov records is stored as a signed 32-bit number of bytes. > | Ok? > | ... applied on top of baseline commit: > | 326a8c047ec testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > # FAILED > # First few build errors in logs: > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > 1 > > The configuration of this build is: > CI config tcwg_gcc_build/master-aarch64 > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-precommit/3366/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_build--master-aarch64-build/1263/artifac…

2 years

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[Linaro-TCWG-CI] v8.1.0-1799-g38ee0a7dfb: FAIL: 2 regressions on aarch64

by ci_notify＠linaro.org

Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In master-aarch64 after: | commit v8.1.0-1799-g38ee0a7dfb | Author: Richard Henderson <richard.henderson(a)linaro.org> | Date: Sat Sep 30 12:05:11 2023 -0700 | | linux-user: Remap guest SIGABRT | | Distinguish host SIGABRT from guest SIGABRT by mapping | the guest signal onto one of the host RT signals. | | This prevents a cycle by which a host assertion failure | is caught and handled by host_signal_handler, queued for | ... 6 lines of the commit log omitted. FAIL: 2 regressions regressions.sum: === libstdc++ tests === Running libstdc++:libstdc++-dg/conformance.exp ... FAIL: 30_threads/condition_variable/members/103382.cc -std=gnu++17 execution test FAIL: 30_threads/thread/native_handle/cancel.cc -std=gnu++17 execution test === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10… . The configuration of this build is: CI config tcwg_gnu_cross_check_gcc/master-aarch64 -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10… Reference build : https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10… Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/qemu/s… Full commit : https://gitlab.com/qemu-project/qemu/commit/38ee0a7dfb4b15407678df26448e4a1… Latest bug report status : https://linaro.atlassian.net/browse/GNU-974 List of configurations that regressed due to this commit : * tcwg_gnu_cross_check_gcc ** master-aarch64 *** FAIL: 2 regressions *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/qemu/s… *** https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/10…

2 years

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[ACTIVITY] Report for week #42

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Implemented support for expressing variable-sized vector registers in the XML target description. Now making some changes in GDB's handling of the expedited registers in the remote protocol and adjusting of the g/G packet size. # TCWG CI - Analysed and closed LLVM code size regression GNU-963. -- Thiago

2 years

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Re: [PATCH v2] ARM: Block predication on atomics [PR111235]

by Ramana Radhakrishnan

+ linaro-toolchain as I don't understand the CI issues on patchwork. On Wed, Sep 27, 2023 at 8:40 PM Wilco Dijkstra <Wilco.Dijkstra(a)arm.com> wrote: > > Hi Ramana, > > > Hope this helps. > > Yes definitely! > > >> Passes regress/bootstrap, OK for commit? > > > > Target ? armhf ? --with-arch , -with-fpu , -with-float parameters ? > > Please be specific. > > I used --target=arm-none-linux-gnueabihf --host=arm-none-linux-gnueabihf > --build=arm-none-linux-gnueabihf --with-float=hard. However it seems that the > default armhf settings are incorrect. I shouldn't need the --with-float=hard since > that is obviously implied by armhf, and they should also imply armv7-a with vfpv3 > according to documentation. It seems to get confused and skip some tests. I tried > using --with-fpu=auto, but that doesn't work at all, so in the end I forced it like: > --with-arch=armv8-a --with-fpu=neon-fp-armv8. With this it runs a few more tests. Yeah that's a wart that I don't like. armhf just implies the hard float ABI and came into being to help distinguish from the Base PCS for some of the distros at the time (2010s). However we didn't want to set a baseline arch at that time given the imminent arrival of v8-a and thus the specification of --with-arch , --with-fpu and --with-float became second nature to many of us working on it at that time. I can see how it can be confusing. With the advent of fpu=auto , I thought this could be made better but that is a matter for another patch and another discussion. However until then do remember to baseline to --with-arch , --with-fpu and --with-float . Unfortunate but needed. If there is a bug with --with-fpu=auto , good to articulate it as I understand that to be the state of the art. Thank you for working through it. > > > Since these patterns touch armv8m.baseline can you find all the > > testcases in the testsuite and ensure no change in code for > > armv8m.baseline as that's unpredicated already and this patch brings > > this in line with the same ? Does the testsuite already cover these > > arch variants and are you satisfied that the tests in the testsuite > > can catch / don't make any additional code changes to the other > > architectures affected by this ? > > There are various v8-m(.base/.main) tests and they all pass. The generated > code is generally unchanged if there was no conditional execution. I made > the new UNSPEC_LDR/STR patterns support offsets so there is no difference > in generated code for relaxed loads/stores (since they used to use a plain > load/store which has an immediate offset). > > >> * onfig/arm/sync.md (arm_atomic_load<mode>): Add new pattern. > > > > Nit: s/onfig/config > > Fixed. Thanks > > >> (atomic_load<mode>): Always expand atomic loads explicitly. > >> (atomic_store<mode>): Always expand atomic stores explicitly. > > > > Nit: Change message to : > > Switch patterns to define_expand. > > Fixed. Thanks. > > > Largely looks ok though I cannot work out tonight if we need more v8-a > > or v8m-baseline specific tests for scan-assembler patterns. > > > > Clearly our testsuite doesn't catch it , so perhaps the OP could help > > validate this patch with their formal models to see if this fixes > > these set of issues and creates no new regressions ? Is that feasible > > to do ? > > Disabling conditional execution avoids the issue. It's trivial to verify that > atomics can no longer be conditionally executed (no "%?"). When this is > committed, we can run the random testing again to confirm the issue > is no longer present. Ok, thanks for promising to do so - I trust you to get it done. Please try out various combinations of -march v7ve, v7-a , v8-a with the tool as each of them have slightly different rules. For instance v7ve allows LDREXD and STREXD to be single copy atomic for 64 bit loads whereas v7-a did not . > > > -(define_insn "atomic_load<mode>" > > - [(set (match_operand:QHSI 0 "register_operand" "=r,r,l") > > +(define_insn "arm_atomic_load<mode>" > > + [(set (match_operand:QHSI 0 "register_operand" "=r,l") > > (unspec_volatile:QHSI > > - [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q") > > - (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model > > + [(match_operand:QHSI 1 "memory_operand" "m,m")] > > > > Remind me again why is it safe to go from the Q constraint to the m > > constraint here and everywhere else you've done this ? > > That's because the relaxed loads/stores use LDR/STR wrapped in an > UNSPEC. To avoid regressions we have to use 'm' so that an immediate > offset can be merged into the memory access. This is because the instructions used here are ldr and str and the use of the 'm' constraint is considered safe. > > >> - VUNSPEC_LDA ; Represent a store-register-acquire. > >> + VUNSPEC_LDR ; Represent a load-register-relaxed. > >> + VUNSPEC_LDA ; Represent a load-register-acquire. > > > > Nit: LDA before LDR ? Though I suspect this list can be alphabetically > > ordered at another point of time. > > Swapped. Thanks > > > There are new tests added for v7-a , what happens with the output for > > v8-a and the changes for ldacq and other such instructions ? > > v7-a and v8-a generate the same instructions for relaxed load/store. > The acquire/release versions are identical except they are no longer > predicated. Basically the new patterns are not only significantly simpler, > they are now the same between the many ARM/Thumb-2/v7-a/v8-m/v8-a > combinations, so test coverage is much higher now. This is how these > patterns should have been designed all along. > > v2 follows below. > > Cheers, > Wilco > > > [PATCH v2] ARM: Block predication on atomics [PR111235] > > The v7 memory ordering model allows reordering of conditional atomic > instructions. To avoid this, make all atomic patterns unconditional. > Expand atomic loads and stores for all architectures so the memory access > can be wrapped into an UNSPEC. > > gcc/ChangeLog/ > PR target/111235 > * config/arm/constraints.md: Remove Pf constraint. > * config/arm/sync.md (arm_atomic_load<mode>): Add new pattern. > (arm_atomic_load_acquire<mode>): Likewise. > (arm_atomic_store<mode>): Likewise. > (arm_atomic_store_release<mode>): Likewise. > (atomic_load<mode>): Switch patterns to define_expand. > (atomic_store<mode>): Likewise. > (arm_atomic_loaddi2_ldrd): Remove predication. > (arm_load_exclusive<mode>): Likewise. > (arm_load_acquire_exclusive<mode>): Likewise. > (arm_load_exclusivesi): Likewise. > (arm_load_acquire_exclusivesi: Likewise. > (arm_load_exclusivedi): Likewise. > (arm_load_acquire_exclusivedi): Likewise. > (arm_store_exclusive<mode>): Likewise. > (arm_store_release_exclusivedi): Likewise. > (arm_store_release_exclusive<mode>): Likewise. > * gcc/config/arm/unspecs.md: Add VUNSPEC_LDR and VUNSPEC_STR. > > gcc/testsuite/ChangeLog/ > PR target/111235 > * gcc.dg/rtl/arm/stl-cond.c: Remove test. > * gcc.target/arm/atomic_loaddi_7.c: Fix dmb count. > * gcc.target/arm/atomic_loaddi_8.c: Likewise. > * gcc.target/arm/pr111235.c: Add new test. > > --- > > diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md > index 05a4ebbdd67601d7b92aa44a619d17634cc69f17..d7c4a1b0cd785f276862048005e6cfa57cdcb20d 100644 > --- a/gcc/config/arm/constraints.md > +++ b/gcc/config/arm/constraints.md > @@ -36,7 +36,7 @@ > ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe > ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra, > ;; Rg, Ri > -;; in all states: Pf, Pg > +;; in all states: Pg > > ;; The following memory constraints have been used: > ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf, Ux, Ul > @@ -239,13 +239,6 @@ (define_constraint "Pe" > (and (match_code "const_int") > (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510"))) > > -(define_constraint "Pf" > - "Memory models except relaxed, consume or release ones." > - (and (match_code "const_int") > - (match_test "!is_mm_relaxed (memmodel_from_int (ival)) > - && !is_mm_consume (memmodel_from_int (ival)) > - && !is_mm_release (memmodel_from_int (ival))"))) > - > (define_constraint "Pg" > "@internal In Thumb-2 state a constant in range 1 to 32" > (and (match_code "const_int") > diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md > index 7626bf3c443285dc63b4c4367b11a879a99c93c6..2210810f67f37ce043b8fdc73b4f21b54c5b1912 100644 > --- a/gcc/config/arm/sync.md > +++ b/gcc/config/arm/sync.md > @@ -62,68 +62,110 @@ (define_insn "*memory_barrier" > (set_attr "conds" "unconditional") > (set_attr "predicable" "no")]) > > -(define_insn "atomic_load<mode>" > - [(set (match_operand:QHSI 0 "register_operand" "=r,r,l") > +(define_insn "arm_atomic_load<mode>" > + [(set (match_operand:QHSI 0 "register_operand" "=r,l") > (unspec_volatile:QHSI > - [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q") > - (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model > + [(match_operand:QHSI 1 "memory_operand" "m,m")] > + VUNSPEC_LDR))] > + "" > + "ldr<sync_sfx>\t%0, %1" > + [(set_attr "arch" "32,any")]) > + > +(define_insn "arm_atomic_load_acquire<mode>" > + [(set (match_operand:QHSI 0 "register_operand" "=r") > + (unspec_volatile:QHSI > + [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q")] > VUNSPEC_LDA))] > "TARGET_HAVE_LDACQ" > - { > - if (aarch_mm_needs_acquire (operands[2])) > - { > - if (TARGET_THUMB1) > - return "lda<sync_sfx>\t%0, %1"; > - else > - return "lda<sync_sfx>%?\t%0, %1"; > - } > - else > - { > - if (TARGET_THUMB1) > - return "ldr<sync_sfx>\t%0, %1"; > - else > - return "ldr<sync_sfx>%?\t%0, %1"; > - } > - } > - [(set_attr "arch" "32,v8mb,any") > - (set_attr "predicable" "yes")]) > + "lda<sync_sfx>\t%0, %C1" > +) > > -(define_insn "atomic_store<mode>" > - [(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q") > +(define_insn "arm_atomic_store<mode>" > + [(set (match_operand:QHSI 0 "memory_operand" "=m,m") > + (unspec_volatile:QHSI > + [(match_operand:QHSI 1 "register_operand" "r,l")] > + VUNSPEC_STR))] > + "" > + "str<sync_sfx>\t%1, %0"; > + [(set_attr "arch" "32,any")]) > + > +(define_insn "arm_atomic_store_release<mode>" > + [(set (match_operand:QHSI 0 "arm_sync_memory_operand" "=Q") > (unspec_volatile:QHSI > - [(match_operand:QHSI 1 "general_operand" "r,r,l") > - (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model > + [(match_operand:QHSI 1 "register_operand" "r")] > VUNSPEC_STL))] > "TARGET_HAVE_LDACQ" > - { > - if (aarch_mm_needs_release (operands[2])) > - { > - if (TARGET_THUMB1) > - return "stl<sync_sfx>\t%1, %0"; > - else > - return "stl<sync_sfx>%?\t%1, %0"; > - } > - else > - { > - if (TARGET_THUMB1) > - return "str<sync_sfx>\t%1, %0"; > - else > - return "str<sync_sfx>%?\t%1, %0"; > - } > - } > - [(set_attr "arch" "32,v8mb,any") > - (set_attr "predicable" "yes")]) > + "stl<sync_sfx>\t%1, %C0") > + > + > +(define_expand "atomic_load<mode>" > + [(match_operand:QHSI 0 "register_operand") ;; val out > + (match_operand:QHSI 1 "arm_sync_memory_operand") ;; memory > + (match_operand:SI 2 "const_int_operand")] ;; model > + "" > +{ > + memmodel model = memmodel_from_int (INTVAL (operands[2])); > + > + if (TARGET_HAVE_LDACQ && !is_mm_relaxed (model)) > + { > + emit_insn (gen_arm_atomic_load_acquire<mode> (operands[0], operands[1])); > + DONE; > + } > + > + /* The seq_cst model needs a barrier before the load to block reordering with > + earlier accesses. */ > + if (is_mm_seq_cst (model)) > + expand_mem_thread_fence (model); > + > + emit_insn (gen_arm_atomic_load<mode> (operands[0], operands[1])); > + > + /* All non-relaxed models need a barrier after the load when load-acquire > + instructions are not available. */ > + if (!is_mm_relaxed (model)) > + expand_mem_thread_fence (model); > + > + DONE; > +}) > + > +(define_expand "atomic_store<mode>" > + [(match_operand:QHSI 0 "arm_sync_memory_operand") ;; memory > + (match_operand:QHSI 1 "register_operand") ;; store value > + (match_operand:SI 2 "const_int_operand")] ;; model > + "" > +{ > + memmodel model = memmodel_from_int (INTVAL (operands[2])); > + > + if (TARGET_HAVE_LDACQ && !is_mm_relaxed (model)) > + { > + emit_insn (gen_arm_atomic_store_release<mode> (operands[0], operands[1])); > + DONE; > + } > + > + /* All non-relaxed models need a barrier after the load when load-acquire > + instructions are not available. */ > + if (!is_mm_relaxed (model)) > + expand_mem_thread_fence (model); > + > + emit_insn (gen_arm_atomic_store<mode> (operands[0], operands[1])); > + > + /* The seq_cst model needs a barrier after the store to block reordering with > + later accesses. */ > + if (is_mm_seq_cst (model)) > + expand_mem_thread_fence (model); > + > + DONE; > +}) > > ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets > > (define_insn "arm_atomic_loaddi2_ldrd" > [(set (match_operand:DI 0 "register_operand" "=r") > (unspec_volatile:DI > - [(match_operand:DI 1 "arm_sync_memory_operand" "Q")] > + [(match_operand:DI 1 "memory_operand" "m")] > VUNSPEC_LDRD_ATOMIC))] > "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE" > - "ldrd%?\t%0, %H0, %C1" > - [(set_attr "predicable" "yes")]) > + "ldrd\t%0, %H0, %1" > +) > > ;; There are three ways to expand this depending on the architecture > ;; features available. As for the barriers, a load needs a barrier > @@ -152,6 +194,11 @@ (define_expand "atomic_loaddi" > DONE; > } > > + /* The seq_cst model needs a barrier before the load to block reordering with > + earlier accesses. */ > + if (is_mm_seq_cst (model)) > + expand_mem_thread_fence (model); > + > /* On LPAE targets LDRD and STRD accesses to 64-bit aligned > locations are 64-bit single-copy atomic. We still need barriers in the > appropriate places to implement the ordering constraints. */ > @@ -160,7 +207,6 @@ (define_expand "atomic_loaddi" > else > emit_insn (gen_arm_load_exclusivedi (operands[0], operands[1])); > > - > /* All non-relaxed models need a barrier after the load when load-acquire > instructions are not available. */ > if (!is_mm_relaxed (model)) > @@ -446,54 +492,42 @@ (define_insn_and_split "atomic_nand_fetch<mode>" > [(set_attr "arch" "32,v8mb")]) > > (define_insn "arm_load_exclusive<mode>" > - [(set (match_operand:SI 0 "s_register_operand" "=r,r") > + [(set (match_operand:SI 0 "s_register_operand" "=r") > (zero_extend:SI > (unspec_volatile:NARROW > - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")] > + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LL)))] > "TARGET_HAVE_LDREXBH" > - "@ > - ldrex<sync_sfx>%?\t%0, %C1 > - ldrex<sync_sfx>\t%0, %C1" > - [(set_attr "arch" "32,v8mb") > - (set_attr "predicable" "yes")]) > + "ldrex<sync_sfx>\t%0, %C1" > +) > > (define_insn "arm_load_acquire_exclusive<mode>" > - [(set (match_operand:SI 0 "s_register_operand" "=r,r") > + [(set (match_operand:SI 0 "s_register_operand" "=r") > (zero_extend:SI > (unspec_volatile:NARROW > - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")] > + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LAX)))] > "TARGET_HAVE_LDACQ" > - "@ > - ldaex<sync_sfx>%?\\t%0, %C1 > - ldaex<sync_sfx>\\t%0, %C1" > - [(set_attr "arch" "32,v8mb") > - (set_attr "predicable" "yes")]) > + "ldaex<sync_sfx>\\t%0, %C1" > +) > > (define_insn "arm_load_exclusivesi" > - [(set (match_operand:SI 0 "s_register_operand" "=r,r") > + [(set (match_operand:SI 0 "s_register_operand" "=r") > (unspec_volatile:SI > - [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")] > + [(match_operand:SI 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LL))] > "TARGET_HAVE_LDREX" > - "@ > - ldrex%?\t%0, %C1 > - ldrex\t%0, %C1" > - [(set_attr "arch" "32,v8mb") > - (set_attr "predicable" "yes")]) > + "ldrex\t%0, %C1" > +) > > (define_insn "arm_load_acquire_exclusivesi" > - [(set (match_operand:SI 0 "s_register_operand" "=r,r") > + [(set (match_operand:SI 0 "s_register_operand" "=r") > (unspec_volatile:SI > - [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")] > + [(match_operand:SI 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LAX))] > "TARGET_HAVE_LDACQ" > - "@ > - ldaex%?\t%0, %C1 > - ldaex\t%0, %C1" > - [(set_attr "arch" "32,v8mb") > - (set_attr "predicable" "yes")]) > + "ldaex\t%0, %C1" > +) > > (define_insn "arm_load_exclusivedi" > [(set (match_operand:DI 0 "s_register_operand" "=r") > @@ -501,8 +535,8 @@ (define_insn "arm_load_exclusivedi" > [(match_operand:DI 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LL))] > "TARGET_HAVE_LDREXD" > - "ldrexd%?\t%0, %H0, %C1" > - [(set_attr "predicable" "yes")]) > + "ldrexd\t%0, %H0, %C1" > +) > > (define_insn "arm_load_acquire_exclusivedi" > [(set (match_operand:DI 0 "s_register_operand" "=r") > @@ -510,8 +544,8 @@ (define_insn "arm_load_acquire_exclusivedi" > [(match_operand:DI 1 "mem_noofs_operand" "Ua")] > VUNSPEC_LAX))] > "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN" > - "ldaexd%?\t%0, %H0, %C1" > - [(set_attr "predicable" "yes")]) > + "ldaexd\t%0, %H0, %C1" > +) > > (define_insn "arm_store_exclusive<mode>" > [(set (match_operand:SI 0 "s_register_operand" "=&r") > @@ -530,14 +564,11 @@ (define_insn "arm_store_exclusive<mode>" > Note that the 1st register always gets the > lowest word in memory. */ > gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); > - return "strexd%?\t%0, %2, %H2, %C1"; > + return "strexd\t%0, %2, %H2, %C1"; > } > - if (TARGET_THUMB1) > - return "strex<sync_sfx>\t%0, %2, %C1"; > - else > - return "strex<sync_sfx>%?\t%0, %2, %C1"; > + return "strex<sync_sfx>\t%0, %2, %C1"; > } > - [(set_attr "predicable" "yes")]) > +) > > (define_insn "arm_store_release_exclusivedi" > [(set (match_operand:SI 0 "s_register_operand" "=&r") > @@ -550,20 +581,16 @@ (define_insn "arm_store_release_exclusivedi" > { > /* See comment in arm_store_exclusive<mode> above. */ > gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); > - return "stlexd%?\t%0, %2, %H2, %C1"; > + return "stlexd\t%0, %2, %H2, %C1"; > } > - [(set_attr "predicable" "yes")]) > +) > > (define_insn "arm_store_release_exclusive<mode>" > - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") > + [(set (match_operand:SI 0 "s_register_operand" "=&r") > (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) > - (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua,Ua") > + (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua") > (unspec_volatile:QHSI > - [(match_operand:QHSI 2 "s_register_operand" "r,r")] > + [(match_operand:QHSI 2 "s_register_operand" "r")] > VUNSPEC_SLX))] > "TARGET_HAVE_LDACQ" > - "@ > - stlex<sync_sfx>%?\t%0, %2, %C1 > - stlex<sync_sfx>\t%0, %2, %C1" > - [(set_attr "arch" "32,v8mb") > - (set_attr "predicable" "yes")]) > + "stlex<sync_sfx>\t%0, %2, %C1") > diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md > index 6a5b1f8f623b00dc014c9f829c591477f8faa9a1..4713ec840abae48ca70f418dbc0d4028ad4ad527 100644 > --- a/gcc/config/arm/unspecs.md > +++ b/gcc/config/arm/unspecs.md > @@ -221,8 +221,10 @@ (define_c_enum "unspecv" [ > VUNSPEC_SC ; Represent a store-register-exclusive. > VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. > VUNSPEC_SLX ; Represent a store-register-release-exclusive. > - VUNSPEC_LDA ; Represent a store-register-acquire. > + VUNSPEC_LDA ; Represent a load-register-acquire. > + VUNSPEC_LDR ; Represent a load-register-relaxed. > VUNSPEC_STL ; Represent a store-register-release. > + VUNSPEC_STR ; Represent a store-register-relaxed. > VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. > VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. > VUNSPEC_SET_FPSCR_NZCVQC ; Represent assign of FPSCR_nzcvqc content. > diff --git a/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c b/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c > deleted file mode 100644 > index e47ca6bf36dac500b90d80e52e150a19c95c7219..0000000000000000000000000000000000000000 > --- a/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c > +++ /dev/null > @@ -1,61 +0,0 @@ > -/* { dg-do compile { target arm*-*-* } } */ > -/* { dg-require-effective-target arm_arm_ok } */ > -/* { dg-require-effective-target arm_arch_v8a_ok } */ > -/* { dg-options "-O2 -marm" } */ > -/* { dg-add-options arm_arch_v8a } */ > - > -/* We want to test that the STL instruction gets the conditional > - suffix when under a COND_EXEC. However, COND_EXEC is very hard to > - generate from C code because the atomic_store expansion adds a compiler > - barrier before the insn, preventing if-conversion. So test the output > - here with a hand-crafted COND_EXEC wrapped around an STL. */ > - > -void __RTL (startwith ("final")) foo (int *a, int b) > -{ > -(function "foo" > - (param "a" > - (DECL_RTL (reg/v:SI r0)) > - (DECL_RTL_INCOMING (reg:SI r0)) > - ) > - (param "b" > - (DECL_RTL (reg/v:SI r1)) > - (DECL_RTL_INCOMING (reg:SI r1)) > - ) > - (insn-chain > - (block 2 > - (edge-from entry (flags "FALLTHRU")) > - (cnote 5 [bb 2] NOTE_INSN_BASIC_BLOCK) > - > - (insn:TI 7 (parallel [ > - (set (reg:CC cc) > - (compare:CC (reg:SI r1) > - (const_int 0))) > - (set (reg/v:SI r1) > - (reg:SI r1 )) > - ]) ;; {*movsi_compare0} > - (nil)) > - > - ;; A conditional atomic store-release: STLNE for Armv8-A. > - (insn 10 (cond_exec (ne (reg:CC cc) > - (const_int 0)) > - (set (mem/v:SI (reg/v/f:SI r0) [-1 S4 A32]) > - (unspec_volatile:SI [ > - (reg/v:SI r1) > - (const_int 3) > - ] VUNSPEC_STL))) ;; {*p atomic_storesi} > - (expr_list:REG_DEAD (reg:CC cc) > - (expr_list:REG_DEAD (reg/v:SI r1) > - (expr_list:REG_DEAD (reg/v/f:SI r0) > - (nil))))) > - (edge-to exit (flags "FALLTHRU")) > - ) ;; block 2 > - ) ;; insn-chain > - (crtl > - (return_rtx > - (reg/i:SI r0) > - ) ;; return_rtx > - ) ;; crtl > -) ;; function > -} > - > -/* { dg-final { scan-assembler "stlne" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c > index 6743663f1e6831d3fc441e80fcfe3d761987970b..79e36edbb8fa86712b8d283b9a81b794610f4813 100644 > --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c > +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c > @@ -6,4 +6,4 @@ > #include "atomic_loaddi_seq_cst.x" > > /* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ > -/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ > +/* { dg-final { scan-assembler-times "dmb\tish" 2 } } */ > diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c > index f7bd3e5a2b515d91418f5f4a7a8db00336a8b594..7241d361313997b0133056c1a3a7c1b546708e43 100644 > --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c > +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c > @@ -6,4 +6,4 @@ > #include "atomic_loaddi_seq_cst.x" > > /* { dg-final { scan-assembler-times "ldrd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ > -/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ > +/* { dg-final { scan-assembler-times "dmb\tish" 2 } } */ > diff --git a/gcc/testsuite/gcc.target/arm/pr111235.c b/gcc/testsuite/gcc.target/arm/pr111235.c > new file mode 100644 > index 0000000000000000000000000000000000000000..b06a5bfb8e294edf04ec9b7b6d8fe5d1ac73b1e7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr111235.c > @@ -0,0 +1,39 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > +/* { dg-require-effective-target arm_arch_v7a_ok } */ > +/* { dg-add-options arm_arch_v7a } */ > + > +#include <stdatomic.h> > + > +int t0 (int *p, int x) > +{ > + if (x > 100) > + x = atomic_load_explicit (p, memory_order_relaxed); > + return x + 1; > +} > + > +long long t1 (long long *p, int x) > +{ > + if (x > 100) > + x = atomic_load_explicit (p, memory_order_relaxed); > + return x + 1; > +} > + > +void t2 (int *p, int x) > +{ > + if (x > 100) > + atomic_store_explicit (p, x, memory_order_relaxed); > +} > + > +void t3 (long long *p, int x) > +{ > + if (x > 100) > + atomic_store_explicit (p, x, memory_order_relaxed); > +} > + > +/* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 2 } } */ > +/* { dg-final { scan-assembler-not "ldrgt" } } */ > +/* { dg-final { scan-assembler-not "ldrdgt" } } */ > +/* { dg-final { scan-assembler-not "ldrexdgt" } } */ > +/* { dg-final { scan-assembler-not "strgt" } } */ > +/* { dg-final { scan-assembler-not "strdgt" } } */ Ok if no regressions but as you might get nagged by the post commit CI ... While it is not policy yet to look at these bots but given the enthusiasm at Cauldron for patchwork and pre-commit CI and because all my armhf boxes are boxed up, I decided to do something a bit novel ! I tried reviewing this via patchwork https://patchwork.sourceware.org/project/gcc/patch/PAWPR08MB8982A6AA40749B7… and notice that https://ci.linaro.org/job/tcwg_gcc_build--master-arm-precommit/2393/artifac… says nothing could be built. Possibly worth double checking the status for it being a false negative as to why the build failed. It was green on patchwork but remembering that Green is not Green for CI in patchwork I clicked on the afore mentioned ci.linaro.org link and see that it's actually broken. regards Ramana

2 years

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[ACTIVITY] report week ending 20 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - post-holiday catchup on email and code review - respin and resend of a patch fixing a bug in rdma code - sent a target-arm pull request * QEMU-292 [ARMv8.3 FEAT_NV, Nested Virtualization] - did an initial read-through of the relevant portions of the Arm ARM to identify the work required here thanks -- PMM

2 years

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Re: [Linaro-TCWG-CI] llvmorg-18-init-8757-gfd311126349b: Failure on aarch64

by Nick Desaulniers

Thanks for the report. Looks like Nathan has reported this, too (as have Google3 folks): https://github.com/llvm/llvm-project/commit/fd311126349b8fe1684d62154a9fa5a… On Wed, Oct 18, 2023 at 7:31 PM <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_kernel/llvm-master-aarch64-stable-defconfig after: > > | commit llvmorg-18-init-8757-gfd311126349b > | Author: Florian Hahn <flo(a)fhahn.com> > | Date: Tue Oct 17 19:17:40 2023 +0100 > | > | [VPlan] Insert Trunc/Exts for reductions directly in VPlan. > | > | Update the code to create Trunc/Ext recipes directly in > | adjustRecipesForReductions instead of fixing it up later in > | fixReductions. > | > | This explicitly models the required conversions and also makes sure they > | ... 2 lines of the commit log omitted. > > Results changed to > # reset_artifacts: > -10 > # build_abe binutils: > -9 > # build_kernel_llvm: > -5 > # build_abe qemu: > -2 > # linux_n_obj: > 8020 > # First few build errors in logs: > > # 00:12:40 clang: error: clang frontend command failed with exit code 134 (use -v to see invocation) > # 00:12:40 make[5]: *** [scripts/Makefile.build:243: drivers/platform/chrome/cros_ec_i2c.o] Error 1 > # 00:13:18 make[4]: *** [scripts/Makefile.build:480: drivers/platform/chrome] Error 2 > # 00:13:18 make[3]: *** [scripts/Makefile.build:480: drivers/platform] Error 2 > # 00:13:37 clang: error: clang frontend command failed with exit code 134 (use -v to see invocation) > # 00:13:37 make[7]: *** [scripts/Makefile.build:243: drivers/net/ethernet/intel/igb/igb_main.o] Error 1 > # 00:13:46 make[6]: *** [scripts/Makefile.build:480: drivers/net/ethernet/intel/igb] Error 2 > # 00:13:53 make[5]: *** [scripts/Makefile.build:480: drivers/net/ethernet/intel] Error 2 > # 00:16:54 make[4]: *** [scripts/Makefile.build:480: drivers/net/ethernet] Error 2 > # 00:16:54 make[3]: *** [scripts/Makefile.build:480: drivers/net] Error 2 > > From > # reset_artifacts: > -10 > # build_abe binutils: > -9 > # build_kernel_llvm: > -5 > # build_abe qemu: > -2 > # linux_n_obj: > 9166 > # linux build successful: > all > # linux boot successful: > boot > > The configuration of this build is: > CI config tcwg_kernel/llvm-master-aarch64-stable-defconfig > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-stable-defconfig… > Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-stable-defconfig… > > Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/s… > > Full commit : https://github.com/llvm/llvm-project/commit/fd311126349b8fe1684d62154a9fa5a… > > Latest bug report status : https://linaro.atlassian.net/browse/LLVM-1007 > > List of configurations that regressed due to this commit : > * tcwg_kernel > ** llvm-master-aarch64-stable-defconfig > *** Failure > *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/s… > *** https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-stable-defconfig… -- Thanks, ~Nick Desaulniers

2 years

2
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[ACTIVITY] Report for week #41

by Thiago Jung Bauermann

Hello, # TCWG CI - Flakiness in gdb.base/gdb-sigterm.exp causes false positives on tcwg_check_gdb--master-arm-precommit, so started investigating its failures. - Investigated regressions reported by the CI: - GCC regression GNU-935: Not a real regression, just already existing failures being reported for a new version of the C++ standard. - linux-next regression GNU-936: Fixed in the newest linux-next tree. - GCC regression GNU-962: Opened GCC bug 111802 ("New analyser diagram failures since commit b365e9d57ad4"). - GCC regression GNU-965: Arm already opened GCC bug 111784 ("[14 Regression] aarch64: ldp_stp_{15,16,17,18}.c test failures since r14-4579.") about this issue. - GCC regression GNU-966: This problem has been fixed in trunk. - linux-next regression GNU-967: A patch was sent to fix the error. # [GNU-767] Support changing SVE vector length in remote debugging - Working on adapting gdbserver's regcache to support registers with a variable size. - Also enabling the target description XML to express vector register sizes in terms of another register. -- Thiago

2 years

1
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Re: WoA machines in the lab

by Lina Iyer

+ linaro-toolchain(a)lists.linaro.org Could someone help with this information in Maxim's absence ? Thanks, Lina On Tue, Oct 10 2023 at 10:07 -0600, Lina Iyer wrote: >Hi Maxim, > >Do you have a list of machines and who provided us with those machines >that we use for WoA projects? I see the list in [1] but not where we got >them from. Marcus from MS was asking for a list of MS provided machines >that we have in use. > >Thanks, >Lina > >[1]. >https://linaro.atlassian.net/wiki/spaces/TCWG/pages/22395192116/Accessing+W…

2 years

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Fwd: [Linaro-TCWG-CI] llvmorg-18-init-7933-ge13bed4c5f35: slowed down by 6% - 464.h264ref on aarch64 O2

by Maxim Kuvyrkov

Hi Dmitriy, Linaro Benchmarking CI has flagged several interesting code-speed and code-size regressions for your patch -- see [1]. In particular, could you check if below regressions can be avoided: - grew in size by 21% - 473.astar:[.] _ZN7way2obj12releasepointEii - slowed down by 61% - 505.mcf_r:[.] price_out_impl Both of these are for 32-bit ARM, but AArch64 also has code-speed and code-size regressions. Let me know if you need any assistance in reproducing these problems. [1] https://linaro.atlassian.net/browse/LLVM-1001 Kind regards, -- Maxim Kuvyrkov https://www.linaro.org > Begin forwarded message: > > From: ci_notify(a)linaro.org > Subject: [Linaro-TCWG-CI] llvmorg-18-init-7933-ge13bed4c5f35: slowed down by 6% - 464.h264ref on aarch64 O2 > Date: October 8, 2023 at 04:26:39 GMT+4 > To: maxim.kuvyrkov(a)linaro.org > Reply-To: linaro-toolchain(a)lists.linaro.org > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_bmk-code_speed-spec2k6/llvm-aarch64-master-O2 after: > > | commit llvmorg-18-init-7933-ge13bed4c5f35 > | Author: Dmitriy Smirnov <dmitriy.smirnov(a)arm.com> > | Date: Fri Oct 6 11:15:00 2023 +0100 > | > | [PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP > | > | This patch tries to canonicalise add + gep to gep + gep. > | > | Co-authored-by: Paul Walker <paul.walker(a)arm.com> > | > | Reviewed By: nikic > | ... 2 lines of the commit log omitted. > > the following benchmarks slowed down by more than 3%: > - slowed down by 6% - 464.h264ref - from 11126 to 11766 perf samples > the following hot functions slowed down by more than 15% (but their benchmarks slowed down by less than 3%): > - slowed down by 44% - 464.h264ref:[.] FastFullPelBlockMotionSearch - from 1531 to 2206 perf samples > > The configuration of this build is: > Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. > > Configuration: > - Benchmark: > - Toolchain: Clang + Glibc + LLVM Linker > - Version: all components were built from their tip of trunk > - Target: aarch64-linux-gnu > - Compiler flags: O2 > - Hardware: NVidia TX1 4x Cortex-A57 > > This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--llvm-aarch64-master-… > Reference build : https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--llvm-aarch64-master-… > > Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/s… > > Full commit : https://github.com/llvm/llvm-project/commit/e13bed4c5f3544c076ce57e36d9a11e… > > Latest bug report status : https://linaro.atlassian.net/browse/LLVM-1001 > > List of configurations that regressed due to this commit : > * tcwg_bmk-code_speed-spec2k6 > ** llvm-aarch64-master-O2 > *** slowed down by 6% - 464.h264ref > *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/s… > *** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--llvm-aarch64-master-…

2 years

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[ACTIVITY] Report for weeks #37 to #40

by Thiago Jung Bauermann

Hello, Attended two events in a row in September, so had a bit of a time crunch and the weekly report fell through the cracks... # TCWG CI - Investigated and fixed a few false positives in the GDB precommit CI which were caused by random failures in gdb.threads/process-dies-while-detaching.exp. Posted upstream and later committed patch fixing the testcase to be more stable. - After conversations during GNU Tools Cauldron and following Maxim's suggestion, changed Linaro's CI to use the read1 library while running the GDB testsuite to improve the stability of its results. - After review from Tom Tromey, posted v2 and later committed a patch which adds '--with-additional-debug-dirs' configure option. - Committed a couple of changes to our CI scripts which make sure that the kernel.yama.ptrace_scope and kernel.core_pattern sysctls have correct values for running the GDB testsuite. # [GNU-767] Support changing SVE vector length in remote debugging - Now that Luis pushed his SME and SME2 patches, merged current GDB main branch into my local branch. It builds but doesn't work yet. # GDB Upstream - Reviewed patch series "[PATCH v3 0/4] Dynamic properties of pointers". - Investigated upstream bugzilla "18898 - Cannot specify non-default list of directories as argument of --with-auto-load-dir on Windows", but concluded it's an autoconf limitation that isn't easy to fix. # Misc - Prepared for Linaro's Employees Meeting. - Attended GNU Tools Cauldron. - Took a few days of vacation. -- Thiago

2 years

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Re: [Linaro-TCWG-CI] 13 patches in glibc: FAIL: 7 regressions

by Maxim Kuvyrkov

Hi Arjun, Please ignore this report. We had a new machine added to the testing pool, and it behaved differently than the others. -- Maxim Kuvyrkov https://www.linaro.org > On Oct 4, 2023, at 22:30, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_glibc_check/master-arm after: > > | 13 patches in glibc > | Patchwork URL: https://patchwork.sourceware.org/patch/76970 > | 72a0ec189c Move 'rpc' routines from 'inet' into 'nss' > | e9e10ad39b Move 'protocols' routines from 'inet' into 'nss' > | e0694af485 Move 'networks' routines from 'inet' into 'nss' > | 547bcf6d44 Move 'netgroup' routines from 'inet' into 'nss' > | 6c43eb641a Move 'hosts' routines from 'inet' into 'nss' > | ... and 8 more patches in glibc > | ... applied on top of baseline commit: > | 1056e5b4c3 tunables: Terminate if end of input is reached (CVE-2023-4911) > > FAIL: 7 regressions > > regressions.sum: > === glibc tests === > > Running glibc:io ... > FAIL: io/tst-close_range > > Running glibc:misc ... > FAIL: misc/tst-epoll > FAIL: misc/tst-epoll-time64 > FAIL: misc/tst-mount > FAIL: misc/tst-process_mrelease > ... and 6 more entries > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/802/artifa… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/802/artifa… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/802/artifa… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/802/artifa… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/650/artifact/a…

2 years

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Re: [Linaro-TCWG-CI] glibc patch #77093: FAIL: 5 regressions

by Maxim Kuvyrkov

Hi Joe, Please ignore this report. We had a new machine added to the testing pool, and it behaved differently than the others. -- Maxim Kuvyrkov https://www.linaro.org > On Oct 4, 2023, at 22:32, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_glibc_check/master-arm after: > > | glibc patch https://patchwork.sourceware.org/patch/77093 > | Author: Joe Ramsay <Joe.Ramsay(a)arm.com> > | Date: Wed Oct 4 11:58:09 2023 +0100 > | > | aarch64: Improve vecmath sin routines > | > | * Update ULP comment reflecting a new observed max in [-pi/2, pi/2] > | * Use the same polynomial in AdvSIMD and SVE, rather than FTRIG instructions > | * Improve register use near special-case branch > | > | Also use overloaded intrinsics for SVE. > | ... applied on top of baseline commit: > | 1056e5b4c3 tunables: Terminate if end of input is reached (CVE-2023-4911) > > FAIL: 5 regressions > > regressions.sum: > === glibc tests === > > Running glibc:io ... > FAIL: io/tst-close_range > > Running glibc:misc ... > FAIL: misc/tst-epoll > FAIL: misc/tst-epoll-time64 > FAIL: misc/tst-mount > FAIL: misc/tst-process_mrelease > ... and 2 more entries > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/810/artifa… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/810/artifa… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/810/artifa… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/810/artifa… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/650/artifact/a…

2 years

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Re: [Linaro-TCWG-CI] glibc patch #77054: FAIL: 5 regressions

by Maxim Kuvyrkov

Hi Siddhesh, Please ignore this report. We had a new machine added to the testing pool, and it behaved differently than the others. -- Maxim Kuvyrkov https://www.linaro.org > On Oct 4, 2023, at 22:33, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_glibc_check/master-arm after: > > | glibc patch https://patchwork.sourceware.org/patch/77054 > | Author: Siddhesh Poyarekar <siddhesh(a)sourceware.org> > | Date: Tue Oct 3 16:11:50 2023 -0400 > | > | Make all malloc tunables SXID_ERASE > | > | The malloc tunables were made SXID_IGNORE to mimic the environment > | variables they aliased, in order to maintain compatibility. This > | allowed alteration of allocator behaviour across setuid boundaries, > | where a setuid program may ignore the tunable but its non-setuid child > | can read it and adjust allocator behaviour accordingly. > | ... 10 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 1056e5b4c3 tunables: Terminate if end of input is reached (CVE-2023-4911) > > FAIL: 5 regressions > > regressions.sum: > === glibc tests === > > Running glibc:io ... > FAIL: io/tst-close_range > > Running glibc:misc ... > FAIL: misc/tst-epoll > FAIL: misc/tst-epoll-time64 > FAIL: misc/tst-mount > FAIL: misc/tst-process_mrelease > ... and 2 more entries > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/806/artifa… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/806/artifa… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/806/artifa… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/806/artifa… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/650/artifact/a…

2 years

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Regarding installation

by Ashu Jain

We are installing SDK we need some details regarding linaro toolchain

2 years

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Re: [Linaro-TCWG-CI] binutils patch #76666: FAIL: 2 regressions

by Christophe Lyon

Hi, The error reported below was in fact caused by a bug in these tests, which has now been fixed. Sorry for the false alarm. Thanks On Tue, 26 Sept 2023 at 16:42, <ci_notify(a)linaro.org> wrote: > Dear contributor, our automatic CI has detected problems related to your > patch(es). Please find some details below. If you have any questions, > please follow up on linaro-toolchain(a)lists.linaro.org mailing list, > Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain > developer on the usual project channel. > > In CI config tcwg_binutils_check/master-aarch64 after: > > | binutils patch https://patchwork.sourceware.org/patch/76666 > | Author: Arsen Arsenović <arsen(a)aarsen.me> > | Date: Tue Sep 26 02:17:33 2023 +0200 > | > | *: add modern gettext support > | > | ChangeLog: > | > | * .gitignore: Add '/gettext*'. > | * configure.ac (host_libs): Replace intl with gettext. > | (hbaseargs, bbaseargs, baseargs): Split baseargs into > {h,b}baseargs. > | ... 64 lines of the commit log omitted. > | ... applied on top of baseline commit: > | d86dbbea8a8 aarch64: Allow feature flags to occupy >64 bits > > FAIL: 2 regressions > > regressions.sum: > === binutils tests === > > Running binutils:binutils-all/ar.exp ... > FAIL: replacing non-deterministic member (wrong size, expected: 920) > FAIL: replacing SOURCE_DATE_EPOCH deterministic member (wrong size, > expected: 1096) > > === Results Summary === > > You can find the failure logs in *.log.1.xz files in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/376… > . > The full lists of regressions and progressions are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/376… > . > The list of [ignored] baseline and flaky failures are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/376… > . > > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/376… > Reference build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-build/302/art…

2 years

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Re: [Linaro-TCWG-CI] binutils patch #76704: FAIL: 2 regressions

by Christophe Lyon

Hi, The error reported below was in fact caused by a bug in these tests, which has now been fixed. Sorry for the false alarm. Thanks On Tue, 26 Sept 2023 at 16:38, <ci_notify(a)linaro.org> wrote: > Dear contributor, our automatic CI has detected problems related to your > patch(es). Please find some details below. If you have any questions, > please follow up on linaro-toolchain(a)lists.linaro.org mailing list, > Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain > developer on the usual project channel. > > In CI config tcwg_binutils_check/master-aarch64 after: > > | binutils patch https://patchwork.sourceware.org/patch/76704 > | Author: Neal Frager <neal.frager(a)amd.com> > | Date: Tue Sep 26 13:46:37 2023 +0100 > | > | gas: microblaze: fixing constant range check issue > | > | The range check should be checking for the range > | ffffffff80000000..7fffffff, not ffffffff70000000. > | > | This patch has been tested for years of AMD Xilinx Yocto > | releases as part of the following patch set: > | ... 5 lines of the commit log omitted. > | ... applied on top of baseline commit: > | d86dbbea8a8 aarch64: Allow feature flags to occupy >64 bits > > FAIL: 2 regressions > > regressions.sum: > === binutils tests === > > Running binutils:binutils-all/ar.exp ... > FAIL: replacing non-deterministic member (wrong size, expected: 920) > FAIL: replacing SOURCE_DATE_EPOCH deterministic member (wrong size, > expected: 1096) > > === Results Summary === > > You can find the failure logs in *.log.1.xz files in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/379… > . > The full lists of regressions and progressions are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/379… > . > The list of [ignored] baseline and flaky failures are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/379… > . > > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/379… > Reference build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-build/302/art…

2 years

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Re: [Linaro-TCWG-CI] binutils patch #76687: FAIL: 2 regressions

by Christophe Lyon

Hi, The error reported below was in fact caused by a bug in these tests, which has now been fixed. Sorry for the false alarm. Thanks On Tue, 26 Sept 2023 at 16:38, <ci_notify(a)linaro.org> wrote: > Dear contributor, our automatic CI has detected problems related to your > patch(es). Please find some details below. If you have any questions, > please follow up on linaro-toolchain(a)lists.linaro.org mailing list, > Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain > developer on the usual project channel. > > In CI config tcwg_binutils_check/master-aarch64 after: > > | binutils patch https://patchwork.sourceware.org/patch/76687 > | Author: YunQiang Su <yunqiang.su(a)cipunited.com> > | Date: Tue Sep 26 07:20:35 2023 -0400 > | > | GAS/MIPS: Fix testcase module-defer-warn2 for r2+ triples > | > | When gas is configured with --target=mipsisa32r2el-elf, > module-defer-warn2 > | will fail: > | > | /binutils-gdb/gas/testsuite/gas/mips/module-defer-warn2.s: > Assembler messages: > | /binutils-gdb/gas/testsuite/gas/mips/module-defer-warn2.s:2: > Error: `gp=64' used with a 32-bit processor > | ... 11 lines of the commit log omitted. > | ... applied on top of baseline commit: > | d86dbbea8a8 aarch64: Allow feature flags to occupy >64 bits > > FAIL: 2 regressions > > regressions.sum: > === binutils tests === > > Running binutils:binutils-all/ar.exp ... > FAIL: replacing non-deterministic member (wrong size, expected: 920) > FAIL: replacing SOURCE_DATE_EPOCH deterministic member (wrong size, > expected: 1096) > > === Results Summary === > > You can find the failure logs in *.log.1.xz files in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/378… > . > The full lists of regressions and progressions are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/378… > . > The list of [ignored] baseline and flaky failures are in > - > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/378… > . > > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-precommit/378… > Reference build : > https://ci.linaro.org/job/tcwg_binutils_check--master-aarch64-build/302/art…

2 years

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Re: [Linaro-TCWG-CI] gcc patch #76638: FAIL: 12 regressions

by Jonathan Wakely

The <bits/version.h> header needs to be regenerated. The changes to the generated file were not in the diff posted to the mailing list (but are committed to git). On Mon, 25 Sept 2023 at 11:55, <ci_notify(a)linaro.org> wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_gcc_check/master-arm after: > > | gcc patch https://patchwork.sourceware.org/patch/76638 > | Author: Jonathan Wakely <jwakely(a)redhat.com> > | Date: Mon Sep 25 09:53:24 2023 +0100 > | > | libstdc++: Define C++23 std::forward_like (P2445R1) > | > | Tested x86_64-linux. Pushed to trunk. > | > | -- >8 -- > | > | libstdc++-v3/ChangeLog: > | ... 8 lines of the commit log omitted. > | ... applied on top of baseline commit: > | c25d6f15211 LoongArch: doc: Update -m[no-]explicit-relocs for r14-4160 > > FAIL: 12 regressions > > regressions.sum: > === libstdc++ tests === > > Running libstdc++:libstdc++-dg/conformance.exp ... > FAIL: 20_util/forward_like/1.cc -std=gnu++23 (test for excess errors) > FAIL: 20_util/forward_like/1.cc -std=gnu++26 (test for excess errors) > FAIL: 20_util/forward_like/2_neg.cc -std=gnu++23 (test for errors, line ) > FAIL: 20_util/forward_like/2_neg.cc -std=gnu++23 (test for errors, line 5) > FAIL: 20_util/forward_like/2_neg.cc -std=gnu++23 (test for errors, line 7) > FAIL: 20_util/forward_like/2_neg.cc -std=gnu++23 (test for excess errors) > FAIL: 20_util/forward_like/2_neg.cc -std=gnu++26 (test for errors, line ) > ... and 7 more entries > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-precommit/3840/artifac… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-precommit/3840/artifac… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-precommit/3840/artifac… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-arm-precommit/3840/artifac… > Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1059/artifact/ar…

2 years, 1 month

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[ACTIVITY] report week ending 27 Sep

by Peter Maydell

Progress (short week, three days): * UM-2 [QEMU upstream maintainership] - Sent a patch to fix a bug involving QEMU's PSCI emulation when QEMU is faking being EL3 firmware for a Linux guest - Sent patch to make our handling of the UNPREDICTABLE T32 LDM-of-single-register case match real hardware (some buggy software assumes this) - Patch review - Converted some more .txt files in our docs directory to rST * QEMU-486 [Support FEAT_RME guests in a board model] - JIRA cleanup to more clearly define what this epic is for, close out some redundant other epics and issues, and create or move some subtasks to be part of this epic -- PMM

2 years, 1 month

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Re: [Linaro-TCWG-CI] gcc-14-4111-g6e92a6a2a72: 483.xalancbmk failed to build

by Maxim Kuvyrkov

Hi Patrick, Did you already get any bug reports for gcc-14-4111-g6e92a6a2a72 ? In our benchmarking we see that 483.xalancbmk (from SPEC CPU2006) fails to build on 32-bit ARM. Let me know if you need any help in reproducing and troubleshooting this. Thanks! -- Maxim Kuvyrkov https://www.linaro.org > On Sep 27, 2023, at 11:05, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_bmk-code_speed-spec2k6/gnu-arm-master-O3 after: > > | commit gcc-14-4111-g6e92a6a2a72 > | Author: Patrick Palka <ppalka(a)redhat.com> > | Date: Mon Sep 18 14:47:52 2023 -0400 > | > | c++: non-dependent assignment checking [PR63198, PR18474] > | > | This patch makes us recognize and check non-dependent simple assigments > | ahead of time, like we already do for compound assignments. This means > | the templated representation of such assignments will now usually have > | an implicit INDIRECT_REF (due to the reference return type), which the > | -Wparentheses code needs to handle. As a drive-by improvement, this > | ... 51 lines of the commit log omitted. > > the following benchmarks slowed down by more than 3%: > - 483.xalancbmk failed to build > > Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. > > Configuration: > - Benchmark: > - Toolchain: GCC + Glibc + GNU Linker > - Version: all components were built from their tip of trunk > - Target: arm-linux-gnueabihf > - Compiler flags: O3 > - Hardware: NVidia TK1 4x Cortex-A15 > > This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--gnu-arm-master-O3-bu… > Reference build : https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--gnu-arm-master-O3-bu… > > Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sh… > > Full commit : https://github.com/gcc-mirror/gcc/commit/6e92a6a2a72d3b7a5e1b29042d8a6a43fe… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-951 > > List of configurations that regressed due to this commit : > * tcwg_bmk-code_speed-spec2k6 > ** gnu-arm-master-O3 > *** 483.xalancbmk failed to build > *** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sh… > *** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6--gnu-arm-master-O3-bu…

2 years, 1 month

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Fwd: [Linaro-TCWG-CI] 2 patches in gdb: Failure

by Guinevere Larsen

Hello! I got 3 of these messages about a patch I have upstream, which seems excessive. I also just managed to grab an aarch64 box and test it and got no errors, so I'd appreciate someone double checking that those werent 3 false positives please. Thank you! Guinevere Larsen She/Her/Hers -------- Forwarded Message -------- Subject: [Linaro-TCWG-CI] 2 patches in gdb: Failure Date: Mon, 25 Sep 2023 05:37:49 +0000 (UTC) From: ci_notify(a)linaro.org Reply-To: linaro-toolchain(a)lists.linaro.org To: blarsen(a)redhat.com Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_gdb_check/master-aarch64 after: | 2 patches in gdb | Patchwork URL: https://patchwork.sourceware.org/patch/76616 | ca7351280f6 gdb/infrun: simplify process_event_stop_test | 0e77782d402 gdb/record: print frame information when exiting a recursive call | ... applied on top of baseline commit: | be8e8313099 Automatic date update in version.in Results changed to # reset_artifacts: -10 # build_abe gdb -- --prefix /usr --disable install: # FAILED # build_abe dejagnu: # build_abe check_gdb --: # First few build errors in logs: # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7012:17: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7185:14: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7185:31: error: ‘original_frame_id’ was not declared in this scope # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7615:8: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7615:25: error: ‘original_frame_id’ was not declared in this scope # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7663:11: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:10:07 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7663:28: error: ‘original_frame_id’ was not declared in this scope # 00:10:09 make[1]: *** [Makefile:1923: infrun.o] Error 1 # 00:10:09 make: *** [Makefile:12387: all-gdb] Error 2 # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7012:17: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7185:14: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7185:31: error: ‘original_frame_id’ was not declared in this scope # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7615:8: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7615:25: error: ‘original_frame_id’ was not declared in this scope # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7663:11: error: ‘curr_frame_id’ was not declared in this scope; did you mean ‘outer_frame_id’? # 00:09:18 /home/tcwg-build/workspace/tcwg_gnu_0/abe/snapshots/gdb.git~master/gdb/infrun.c:7663:28: error: ‘original_frame_id’ was not declared in this scope # 00:09:22 make[1]: *** [Makefile:1924: infrun.o] Error 1 # 00:09:43 make: *** [Makefile:12387: all-gdb] Error 2 From # reset_artifacts: -10 # build_abe gdb -- --prefix /usr --disable install: -2 # build_abe dejagnu: -1 # build_abe check_gdb --: 0 -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_gdb_check--master-aarch64-precommit/642/arti… Reference build : https://ci.linaro.org/job/tcwg_gdb_check--master-aarch64-build/326/artifact…

2 years, 1 month

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[weekly][linaro] report week ending 22 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Implemented Neoverse N2 CPU model (easy as it's very similar to the Cortex-A710 we just implemented; but because it supports 48 bit physical addresses we can use it in the sbsa-ref board, so it's worth having both) - Wrote code to wire up the NS EL2 virtual timer IRQ on the virt board. This is part of FEAT_VHE, and we implemented the timer itself in the CPU ages ago, but forgot to ever wire up the interrupt line on the board models. Unfortunately doing this runs into a bug in EDK2 where it incorrectly asserts when it sees a dtb that reports the interrupt line. Leif Lindholm wrote patches to fix this in EDK2, but we'll need to update the QEMU testsuite and figure out how to communicate the need for an updated EDK2 to users. - Looked again at a long-standing missing feature in the virt board where it only has one UART. The main blocker for adding a second one has been odd EDK2 behaviour when the dtb tells it there are two UARTs. Investigated and wrote up exactly what it does to start a discussion about improving it. - Put together a target-arm pull request - Squashed a few -Wshadow warnings - Looking at a bug involving QEMU's PSCI emulation when QEMU is faking being EL3 firmware for a Linux guest * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Implemented and sent a patch for FEAT_HPMN0 (a very easy feature that makes MDCR_EL2.HPMN==0 valid) -- PMM

2 years, 1 month

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Re: [EXT] [Linaro-TCWG-CI] basepoints/gcc-14-4038-gb975c0dc3be: Failure

by Andrew Pinski

I could not reproduce the bootstrap failure at -O3 on x86_64. I used --with-build-config=bootstrap-O3 . Maybe this is an arm (32?) only issue. Thanks, Andrew ________________________________________ From: ci_notify(a)linaro.org <ci_notify(a)linaro.org> Sent: Saturday, September 16, 2023 5:33 AM To: Andrew Pinski Cc: gcc-regression(a)gcc.gnu.org Subject: [EXT] [Linaro-TCWG-CI] basepoints/gcc-14-4038-gb975c0dc3be: Failure External Email ---------------------------------------------------------------------- Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_bootstrap_build/master-arm-bootstrap_O3 after: | commit basepoints/gcc-14-4038-gb975c0dc3be | Author: Andrew Pinski <apinski(a)marvell.com> | Date: Thu Sep 14 14:47:04 2023 -0700 | | MATCH: Improve zero_one_valued_p for cases without range information | | I noticed we sometimes lose range information in forwprop due to a few | match and simplify patterns optimizing away casts. So the easier way | to these cases is to add a match for zero_one_valued_p wich mathes | a cast from another zero_one_valued_p. | This also adds the case of `x & zero_one_valued_p` as being zero_one_valued_p | ... 13 lines of the commit log omitted. Results changed to # reset_artifacts: -10 # true: 0 # build_abe bootstrap_O3: # FAILED # First few build errors in logs: # 00:30:42 xg++: internal compiler error: Segmentation fault signal terminated program cc1plus # 00:30:42 make[3]: *** [Makefile:1184: tree-ssa-loop-niter.o] Error 4 # 00:30:42 make[2]: *** [Makefile:5051: all-stage2-gcc] Error 2 # 00:30:42 make[1]: *** [Makefile:25871: stage2-bubble] Error 2 # 00:30:42 make: *** [Makefile:1090: all] Error 2 # 00:07:25 make[3]: [Makefile:1822: armv8l-unknown-linux-gnueabihf/bits/largefile-config.h] Error 1 (ignored) # 00:25:31 xg++: internal compiler error: Segmentation fault signal terminated program cc1plus # 00:25:31 make[3]: *** [Makefile:1184: tree-ssa-loop-niter.o] Error 4 # 00:30:14 make[2]: *** [Makefile:5051: all-stage2-gcc] Error 2 # 00:30:14 make[1]: *** [Makefile:25871: stage2-bubble] Error 2 # 00:30:14 make: *** [Makefile:1090: all] Error 2 From # reset_artifacts: -10 # true: 0 # build_abe bootstrap_O3: 1 -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reproduce last good and first bad builds: https://urldefense.proofpoint.com/v2/url?u=https-3A__git.linaro.org_toolcha… Full commit : https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_gcc-2Dmirro… Latest bug report status : https://urldefense.proofpoint.com/v2/url?u=https-3A__linaro.atlassian.net_b… List of configurations that regressed due to this commit : * tcwg_bootstrap_build ** master-arm-bootstrap_O3 *** Failure *** https://urldefense.proofpoint.com/v2/url?u=https-3A__git.linaro.org_toolcha… *** https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…

2 years, 1 month

3
2
0 0

[Linaro-TCWG-CI] glibc-2.38.9000-125-g973fe93a56: FAIL: 1 regressions

by ci_notify＠linaro.org

Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_glibc_check/master-arm after: | commit glibc-2.38.9000-125-g973fe93a56 | Author: Siddhesh Poyarekar <siddhesh(a)sourceware.org> | Date: Fri Sep 15 13:51:12 2023 -0400 | | getaddrinfo: Fix use after free in getcanonname (CVE-2023-4806) | | When an NSS plugin only implements the _gethostbyname2_r and | _getcanonname_r callbacks, getaddrinfo could use memory that was freed | during tmpbuf resizing, through h_name in a previous query response. | | The backing store for res->at->name when doing a query with | ... 15 lines of the commit log omitted. FAIL: 1 regressions regressions.sum: === glibc tests === Running glibc:nss ... FAIL: nss/tst-nss-gai-hv2-canonname === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/615/artifact/a… Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/sha… Full commit : https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=973fe93a5675c42798b2… Latest bug report status : https://linaro.atlassian.net/browse/GNU-940 List of configurations that regressed due to this commit : * tcwg_glibc_check ** master-arm *** FAIL: 1 regressions *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/sha… *** https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/

2 years, 1 month

1
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[ACTIVITY] report week ending 15 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent patches that re-sync our defined set of usermode hwcap bits and ID register bitmasks with what the Linux kernel currently has - code review * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_HBC: wrote and sent patch for this very simple feature - FEAT_MOPS: rolled v2 patchset based on review feedback * QEMU-486 [Update QEMU device models for FEAT_RME] - Looked at the SMMU spec to see (a) what realm-management related changes it needs and (b) where we are on the implementation of other features. Closed a few stale JIRA issues for features we've already implemented. - sent a patchset that advertises that we support SMMUv3.1-XNX (this is a no-op for our implementation) - investigated what the "expected" setup is for enforcing GPT checks on the GIC/ITS. Current front-runner is "the SMMU that's already in the system provides 'GPC checks only' for the accesses from these devices, as well as stage1/stage2 + GPT checks for PCI etc devices" (the term in the SMMU spec rev F.a is for a GPC-checks-only client device is "NoStreamID device") -- PMM

2 years, 1 month

1
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Re: [Linaro-TCWG-CI] glibc patch #75959: FAIL: 1 regressions

by Siddhesh Poyarekar

On 2023-09-14 16:32, ci_notify(a)linaro.org wrote: > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_glibc_check/master-arm after: > > | glibc patch https://patchwork.sourceware.org/patch/75959 > | Author: Siddhesh Poyarekar <siddhesh(a)sourceware.org> > | Date: Thu Sep 14 06:13:02 2023 -0400 > | > | getaddrinfo: Fix use after free in getcanonname (CVE-2023-4806) > | > | When an NSS plugin only implements the _gethostbyname2_r and > | _getcanonname_r callbacks, getaddrinfo could use memory that was freed > | during tmpbuf resizing, through h_name in a previous query response. > | Fix this by copying h_name over and freeing it at the end. > | > | ... 3 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 803f4073cc Add MOVE_MOUNT_BENEATH from Linux 6.5 to sys/mount.h > > FAIL: 1 regressions > > regressions.sum: > === glibc tests === > > Running glibc:nss ... > FAIL: nss/tst-nss-gai-hv2-canonname > > === Results Summary === > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/612/artifact/a… Hello, I'm looking at the logs and all it has is: original exit status 127 running post-clean rsync for the new test. It looks like other NSS tests also fail in the same way. Is this a known issue on arm? Thanks, Sid

2 years, 1 month

4
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Fwd: [Linaro-TCWG-CI] gcc patch #75644: FAIL: 2 regressions

by Jonathan Wakely

I think this is because the patch changes libstdc++-v3/include/bits/version.def which requires version.h to be regenerated, by running 'make update-version' in the objdir/$target/libstdc++-v3/include directory. The patch I sent to gcc-patches (which is archived in patchwork) doesn't have the updates to the generated files, but what I committed to git does have them. ---------- Forwarded message --------- From: <ci_notify(a)linaro.org> Date: Mon, 11 Sept 2023 at 21:00 Subject: [Linaro-TCWG-CI] gcc patch #75644: FAIL: 2 regressions To: <jwakely(a)redhat.com> Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_gcc_check/master-aarch64 after: | gcc patch https://patchwork.sourceware.org/patch/75644 | Author: Jonathan Wakely <jwakely(a)redhat.com> | Date: Mon Sep 11 14:57:08 2023 +0100 | | libstdc++: Formatting std::thread::id and std::stacktrace (P2693R1) | | Tested aarch64-linux. Pushed to trunk. | | -- >8 -- | | New std::formatter specializations for C++23. | ... 18 lines of the commit log omitted. | ... applied on top of baseline commit: | 390fa3a78c8 libstdc++: Fix -Wunused-parameter warnings FAIL: 2 regressions regressions.sum: === libstdc++ tests === Running libstdc++:libstdc++-dg/conformance.exp ... FAIL: 19_diagnostics/stacktrace/output.cc (test for excess errors) FAIL: 19_diagnostics/stacktrace/version.cc (test for excess errors) === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/926/artifact…

2 years, 1 month

1
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[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continuing work on new approach to support changing SVE vector length in remote debugging. Fixed making native GDB work with the new approach using the DWARF location expression. Now porting the same approach to gdbserver, with an ad-hoc minimal location expression. # TCWG CI - Fixed GDB testsuite default timeout value, to make GDB check jobs for 32-bit ARM run in a less unreasonable time again. # Misc - Started preparation for future work on Guarded Control Stack for GDB. -- Thiago

2 years, 1 month

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[ACTIVITY] report week ending 8 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent patch fixing some regexes in our documentation - patch review and queueing up an arm pull request - Investigated the mps3-an536 Cortex-R52 FPGA image to see what work would be required to implement a QEMU model of it, wrote a draft of a jira epic issue for this * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_MOPS: * Implemented and tested the memcpy/memmove insns CPY* * Got the whole patchseries into good enough shape to send out for review -- PMM

2 years, 1 month

1
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[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Resumed working on new approach to support changing SVE vector length in remote debugging. I was able to use DWARF location expressions in the target description to express the SVE vector register sizes in terms of the VG register. Also adapted the regcache to support variable-length registers, and removed the VQ value from the target description and from aarch64_gdbarch_tdep, making GDB use one target description regardless of the vector length size. Still ironing out some bugs, and haven't tackled gdbserver yet. -- Thiago

2 years, 1 month

1
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Re: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions

by Andrew Pinski

Just FYI. This test is just bogus and fixing it might be simple as using -fsanitize=undefined to check at runtime there is no undefined behavior being hit. In this case even if we do the comparison in `signed` and do the negate in `unsigned` types. we can still remove the negate in this case since we know the only value that will be still negative in that branch is LONG_MIN. So my patch just simplifies the inner comparison to that instead of `a < 0` and then be able to remove the neg. Someone else will have to fix the testcase since it is a testcase issue ... ________________________________________ From: ci_notify(a)linaro.org <ci_notify(a)linaro.org> Sent: Friday, September 1, 2023 3:07 PM To: Andrew Pinski Subject: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions External Email ---------------------------------------------------------------------- Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list. In CI config tcwg_gcc_check/master-aarch64 after: | 2 patches in gcc | Patchwork URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.sourceware.o… | 504821491ff VR-VALUES: Rewrite test_for_singularity using range_op_handler | f6d1540c3e0 VR-VALUES: Rename op0/op1 to op1/op2 for test_for_singularity | ... applied on top of baseline commit: | b0d75f7d3bb libstdc++: Fix debug-mode tests for constexpr algorithms FAIL: 1 regressions regressions.sum: === gcc tests === Running gcc:gcc.target/aarch64/aarch64.exp ... FAIL: gcc.target/aarch64/vnegd_s64.c scan-assembler-times neg\\tx[0-9]+, x[0-9]+ 1 === Results Summary === -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…

2 years, 1 month

1
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[ACTIVITY] report week ending 1 Sep

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - code review: + RTH's linux-user ESR signal frame patchset + iMX6/7 cleanup patchset + some other minor bits and pieces * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_MOPS: * SETG* instructions (memset + MTE tag setting) implemented and given some basic testing -- PMM

2 years, 1 month

1
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[Linaro-TCWG-CI] FAIL: regressions after gcc commit 0c78240fd7d519fc27ca822f66a92f85edf43f70

by Adhemerval Zanella Netto

Hi Jan, Your patch caused a regression [1] on aarch64-linux-gnu. Would you please investigate? I am having some trouble to reproduce it outside our CI environment, but it has been hitting this issues consistently and it does seems related to your patch. Let me know if you need any assistance in reproducing these. Thanks! [1] https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_pr…

2 years, 2 months

1
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Re: [Linaro-TCWG-CI] FAIL: 2 regressions after gcc commit 27de9aa152141e7f3ee66372647d0f2cd94c4b90

by Adhemerval Zanella Netto

Hi Richard, Your patch caused a regression [1] on aarch64-linux-gnu. Would you please investigate? I did a quick analysis and it seems that for test_copy_lane_f32, test_copy_lane_s32, test_copy_lane_u32, gcc is now generating zip1 instead of a ins; which does not seem fully correct. Let me know if you need any assistance in reproducing these. Thanks! [1] https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/91…

2 years, 2 months

2
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Re: [Linaro-TCWG-CI] FAIL: 1 regressions after glibc-2.38.9000-71-g7086332e06 elf: Check that --list-diagnostics output has the expected syntax

by Maxim Kuvyrkov

> On Aug 25, 2023, at 19:18, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch. > Please find below some details about it. If you have any questions, please > follow up on linaro-toolchain(a)lists.linaro.org mailing list. > > In CI config tcwg_glibc_check/master-aarch64 after: > > | Patchwork URL: https://patchwork.sourceware.org/project/glibc/patch/871qfr9te6.fsf@oldenbu… > | commit 7086332e068cbe778cb47a9baf23cd1d2401444a > | Author: Florian Weimer <fweimer(a)redhat.com> > | Date: Fri Aug 25 14:52:01 2023 +0200 > | > | elf: Check that --list-diagnostics output has the expected syntax > | > | Parts of elf/tst-rtld-list-diagnostics.py have been copied from > | scripts/tst-ld-trace.py. > | > | The abnf module is entirely optional and used to verify the > | ... 3 lines of the commit log omitted. > > FAIL: 1 regressions > > regressions.sum: > === glibc tests === > > Running glibc:elf ... > FAIL: elf/tst-rtld-list-diagnostics Hi Florian, Output of failed test is in [1]. [1] https://ci.linaro.org/job/tcwg_glibc_check--master-aarch64-precommit/597/ar… . Regards, -- Maxim Kuvyrkov https://www.linaro.org > > === Results Summary === > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-aarch64-precommit/597/ar… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-aarch64-build/622/artifa… > > Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/sha… > > Full commit : https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=7086332e068cbe778cb4… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-692 > > List of configurations that regressed due to this commit : > * tcwg_glibc_check > ** master-aarch64 > *** FAIL: 1 regressions > *** https://ci.linaro.org/job/tcwg_glibc_check--master-aarch64-precommit/597/

2 years, 2 months

2
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[ACTIVITY] Report for week #34

by Thiago Jung Bauermann

Hello, # TCWG CI - GCC regression GNU-884: Prathamesh confirmed that the new generated code is better so I posted a patch adjusting the testcase. - GCC regression GNU-885: Confirmed that the problem is still present in trunk as of commit 829c0c06fe7b from yesterday, so opened bugzilla 111125 and copied the patch author. He fixed the regression. - Posted Gerrit review request to increase timeout for GDB check jobs to accommodate longer times for Armv8l builds. # GDB Upstream - Reviewed v4 of Luis' patch series adding SME support to GDB and gdbserver. -- Thiago

2 years, 2 months

1
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Re: [Linaro-TCWG-CI] FAIL: 1 regressions after gcc commit

by Adhemerval Zanella Netto

Hi Andrew, Your patch caused a regression [1] on aarch64-linux-gnu. Would you please investigate? I did a quick analysis and it seems that the expected 18 for aarch64 is now 17: $ grep "Jumps threaded" a-ssa-dom-thread-7.c.197t.thread2 Jumps threaded: 17 Let me know if you need any assistance in reproducing these. Thanks! [1] https://ci.linaro.org/job/tcwg_gnu_native_check_gcc--master-aarch64-build/5…

2 years, 2 months

2
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Re: [Linaro-TCWG-CI] FAIL: 6 regressions after basepoints/gcc-14-3441-ga1558e9ad85 tree-optimization/111115 - SLP of masked stores

by Maxim Kuvyrkov

Hi Richard, Your patch below ICEs on aarch64-linux-gnu. Should reproduce easily on native or cross aarch64-linux-gnu build. Let me know if you need any assistance in reproducing this. Thanks, -- Maxim Kuvyrkov https://www.linaro.org > On Aug 24, 2023, at 22:03, ci_notify(a)linaro.org wrote: > > Dear contributor, our automatic CI has detected problems related to your patch. > Please find below some details about it. If you have any questions, please > follow up on linaro-toolchain(a)lists.linaro.org mailing list. > > In CI config tcwg_gcc_check/master-aarch64 after: > > | commit a1558e9ad856938f165f838733955b331ebbec09 > | Author: Richard Biener <rguenther(a)suse.de> > | Date: Wed Aug 23 14:28:26 2023 +0200 > | > | tree-optimization/111115 - SLP of masked stores > | > | The following adds the capability to do SLP on .MASK_STORE, I do not > | plan to add interleaving support. > | > | PR tree-optimization/111115 > | ... 21 lines of the commit log omitted. > > FAIL: 6 regressions > > regressions.sum: > === gcc tests === > > Running gcc:gcc.target/aarch64/sve/aarch64-sve.exp ... > FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (internal compiler error: in get_group_load_store_type, at tree-vect-stmts.cc:2121) > FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (test for excess errors) > UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2b\\t.z[0-9] > UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2d\\t.z[0-9] > UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2h\\t.z[0-9] > UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2w\\t.z[0-9] > > ... and 1 more entries > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/artifact… > Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/856/artifact… > > Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/… > > Full commit : https://github.com/gcc-mirror/gcc/commit/a1558e9ad856938f165f838733955b331e… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-893 > > List of configurations that regressed due to this commit : > * tcwg_gcc_check > ** master-aarch64 > *** FAIL: 6 regressions > *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/

2 years, 2 months

2
1
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[ACTIVITY] report week ending 24 Aug

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - code review: + Xilinx Versal CFI support series + v2 of RTH's Cortex-A710 series - a few more -Wvla patches - put together and sent the first arm pullreq for the 8.2 cycle * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_MOPS: + updated to use a refactoring suggested by RTH + started looking at SETG operation (memset with MTE tag setting) -- PMM

2 years, 2 months

1
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Re: [Linaro-TCWG-CI] FAIL: 10 regressions after gcc commit: 5 commits in gcc

by Maxim Kuvyrkov

Hi Julian, Your patch series causes regressions on aarch64-linux-gnu. Would you please investigate? Let me know if you need any assistance in reproducing these. Thanks! -- Maxim Kuvyrkov https://www.linaro.org > On Aug 19, 2023, at 09:32, ci_notify(a)linaro.org wrote: > > [Linaro-TCWG-CI] FAIL: 10 regressions after gcc commit: 5 commits in gcc > > Dear contributor, our automatic CI has detected problems related to your patch. > Please find below some details about it. > > In CI config tcwg_gcc_check/master-aarch64 after: > > | gcc commits: > | dce6c135fb52fd631c2fc82d8048d32ce41ece21 OpenMP/OpenACC: Reorganise OMP map clause handling in gimplify.cc > | dd49dd178e3eac8e9925baa3d71325d8d5f69215 OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic > | bd5a53e6b47907d05672cbb603af363a665b45a4 OpenMP: Pointers and member mappings > | 4e0359d8a659c8abdca3297fc9b0e20ff89f7f82 OpenMP/OpenACC: Rework clause expansion and nested struct handling > | a855174e5461d2b423af7f892fd31dfb10ce09ec OpenMP/OpenACC: Reindent TO/FROM/_CACHE_ stanza in {c_}finish_omp_clause > > FAIL: 10 regressions > > regressions.sum: > === libgomp tests === > > Running libgomp:libgomp.c++/c++.exp ... > FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test > FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test > > Running libgomp:libgomp.c/c.exp ... > FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test > FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test > > ... and 9 more entries > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1593/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact…

2 years, 2 months

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Re: [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp policies with test-cases.

by Manos Anagnostakis

Sorry, forgot cc. On Sat, Aug 19, 2023 at 10:24 PM Manos Anagnostakis < manos.anagnostakis(a)vrull.eu> wrote: > Hello Maxim, > > I've found out why this happens. It is a test problem having to do with > -mcpu and should be trivial to address. I should have followed up with a V2 > by next week. > > Thank you for your report! > > Manos. > > On Sat, Aug 19, 2023 at 9:54 AM Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> > wrote: > >> Hi Manos, >> >> New tests in your patch [1] fail on aarch64-linux-gnu build in our CI. >> Would you please investigate why? Testing logs are at [2]. >> >> [1] >> https://patchwork.sourceware.org/project/gcc/patch/20230818074943.41754-1-m… >> [2] >> https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art… >> >> -- >> Maxim Kuvyrkov >> https://www.linaro.org >> >> > On Aug 19, 2023, at 08:37, ci_notify(a)linaro.org wrote: >> > >> > [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: >> basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp >> policies with test-cases. >> > >> > Dear contributor, our automatic CI has detected problems related to >> your patch. >> > Please find below some details about it. >> > >> > In CI config tcwg_gcc_check/master-aarch64 after: >> > >> > | commit cddc26e0274b51e775929e497f89d203211689d2 >> > | Author: Manos Anagnostakis <manos.anagnostakis(a)vrull.eu> >> > | Date: Fri Aug 18 10:49:43 2023 +0300 >> > | >> > | aarch64: Fine-grained ldp and stp policies with test-cases. >> > | >> > | This patch implements the following TODO in >> gcc/config/aarch64/aarch64.cc >> > | to provide the requested behaviour for handling ldp and stp: >> > | >> > | /* Allow the tuning structure to disable LDP instruction >> formation >> > | ... 47 lines of the commit log omitted. >> > >> > FAIL: 6 regressions >> > >> > regressions.sum: >> > === gcc tests === >> > >> > Running gcc:gcc.target/aarch64/aarch64.exp ... >> > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times >> ldp\tq[0-9]+, q[0-9] 1 >> > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times >> ldp\tw[0-9]+, w[0-9] 3 >> > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times >> ldp\tx[0-9]+, x[0-9] 3 >> > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times >> ldp\tq[0-9]+, q[0-9] 2 >> > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times >> ldp\tw[0-9]+, w[0-9] 6 >> > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times >> ldp\tx[0-9]+, x[0-9] 6 >> > >> > ... and 1 more entries >> > >> > >> > >> > >> -----------------8<--------------------------8<--------------------------8<-------------------------- >> > The information below can be used to reproduce a debug environment: >> > >> > Current build : >> https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art… >> > Reference build : >> https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact… >> > >> > Reproduce last good and first bad builds: >> https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/… >> > >> > Full commit : >> https://github.com/gcc-mirror/gcc/commit/cddc26e0274b51e775929e497f89d20321… >> > >> > Latest bug report status : https://linaro.atlassian.net/browse/GNU-692 >> > >> > List of configurations that regressed due to this commit : >> > * tcwg_gcc_check >> > ** master-aarch64 >> > *** FAIL: 6 regressions >> > *** >> https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/ >> >> >> > > -- > *Manos Anagnostakis | Compiler Engineer |* > E: manos.anagnostakis(a)vrull.eu <makeljana.shkurti(a)vrull.eu> > > *VRULL GmbH *| Beatrixgasse 32 1030 Vienna | > W: www.vrull.eu | LinkedIn <https://www.linkedin.com/company/vrull/> > -- *Manos Anagnostakis | Compiler Engineer |* E: manos.anagnostakis(a)vrull.eu <makeljana.shkurti(a)vrull.eu> *VRULL GmbH *| Beatrixgasse 32 1030 Vienna | W: www.vrull.eu | LinkedIn <https://www.linkedin.com/company/vrull/>

2 years, 2 months

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Re: [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp policies with test-cases.

by Maxim Kuvyrkov

Hi Manos, New tests in your patch [1] fail on aarch64-linux-gnu build in our CI. Would you please investigate why? Testing logs are at [2]. [1] https://patchwork.sourceware.org/project/gcc/patch/20230818074943.41754-1-m… [2] https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art… -- Maxim Kuvyrkov https://www.linaro.org > On Aug 19, 2023, at 08:37, ci_notify(a)linaro.org wrote: > > [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp policies with test-cases. > > Dear contributor, our automatic CI has detected problems related to your patch. > Please find below some details about it. > > In CI config tcwg_gcc_check/master-aarch64 after: > > | commit cddc26e0274b51e775929e497f89d203211689d2 > | Author: Manos Anagnostakis <manos.anagnostakis(a)vrull.eu> > | Date: Fri Aug 18 10:49:43 2023 +0300 > | > | aarch64: Fine-grained ldp and stp policies with test-cases. > | > | This patch implements the following TODO in gcc/config/aarch64/aarch64.cc > | to provide the requested behaviour for handling ldp and stp: > | > | /* Allow the tuning structure to disable LDP instruction formation > | ... 47 lines of the commit log omitted. > > FAIL: 6 regressions > > regressions.sum: > === gcc tests === > > Running gcc:gcc.target/aarch64/aarch64.exp ... > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 1 > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 3 > FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 3 > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 2 > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 6 > FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 6 > > ... and 1 more entries > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art… > Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact… > > Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/… > > Full commit : https://github.com/gcc-mirror/gcc/commit/cddc26e0274b51e775929e497f89d20321… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-692 > > List of configurations that regressed due to this commit : > * tcwg_gcc_check > ** master-aarch64 > *** FAIL: 6 regressions > *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/

2 years, 2 months

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[ACTIVITY] Report for week #33

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued working on new approach to support changing SVE vector length in remote debugging. # TCWG CI - Analysed GCC regression GNU-880 which is actually an XFAIL → XPASS so I sent a patch removing the xfail annotation. - Analysed GCC regression GNU-881. The problem is that we don't have Python in the ABE sysroot so a new Python GCC plugin testcase fails to build. Sent a patch to detect that situation and mark the test as unsupported. It was committed upstream. - Tested a couple of new versions of a GDB mailing list patch to see if it fixed the failure reported by the precommit CI. Reported results to patch author. - Fixed silly mistake spotted by Laurent in ABE Gerrit requests to use TIMEOUTFACTOR for DejaGnu testsuites. Adjusted it to not use the factor in GDB on armhf and sent new version for review. - Reviewed a couple of Gerrit requests. -- Thiago

2 years, 2 months

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[ACTIVITY] report week ending 18 Aug

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - sent out another couple of "avoid VLA" patches * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - managed to write some first-pass code for the MTE checks for FEAT_MOPS memset operations. Got something together enough to send to RTH for some pre-review before I roll the approach out to the other insns. -- PMM

2 years, 2 months

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Re: [Linaro-TCWG-CI] Failure after gcc commit: basepoints/gcc-14-3309-g360cabf45a0 arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

by Maxim Kuvyrkov

Hi Stamatis, Let us know if you need any help in troubleshooting the failures in https://patchwork.sourceware.org/project/gcc/list/?series=23558 . Kind regards, -- Maxim Kuvyrkov https://www.linaro.org > On Aug 18, 2023, at 01:13, ci_notify(a)linaro.org wrote: > > [Linaro-TCWG-CI] Failure after gcc commit: basepoints/gcc-14-3309-g360cabf45a0 arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns > > Dear contributor, our automatic CI has detected problems related to your patch. > Please find below some details about it. > > In CI config tcwg_gcc_build/master-arm after: > > | commit 360cabf45a05d5d2d5a98f0e081cb8f53e01e8aa > | Author: Stamatis Markianos-Wright <stam.markianos-wright(a)arm.com> > | Date: Thu Aug 17 11:30:58 2023 +0100 > | > | arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns > | > | Hi all, > | > | I'd like to submit two patches that add support for Arm's MVE > | Tail Predicated Low Overhead Loop feature. > > Results changed to > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > # FAILED > # First few build errors in logs: > # 00:02:46 /home/tcwg-build/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/config/arm/mve.md:7018:8: error: invalid decimal constant > # 00:02:46 make[2]: *** [Makefile:2647: s-preds-h] Error 1 > # 00:02:46 make[1]: *** [Makefile:4655: all-gcc] Error 2 > # 00:02:46 make: *** [Makefile:1051: all] Error 2 > # 00:02:28 /home/tcwg-build/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/config/arm/mve.md:7018:8: error: invalid decimal constant > # 00:02:28 make[2]: *** [Makefile:2586: s-conditions] Error 1 > # 00:02:28 /home/tcwg-build/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/config/arm/mve.md:7018:8: error: invalid decimal constant > # 00:02:28 /home/tcwg-build/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/config/arm/mve.md:7018:8: error: invalid decimal constant > # 00:02:28 make[2]: *** [Makefile:2647: s-preds-h] Error 1 > # 00:02:28 make[2]: *** [Makefile:2652: s-constrs-h] Error 1 > # 00:02:28 /home/tcwg-build/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/config/arm/mve.md:7018:8: error: invalid decimal constant > # 00:02:28 make[2]: *** [Makefile:2642: s-preds] Error 1 > # 00:02:35 make[1]: *** [Makefile:4655: all-gcc] Error 2 > # 00:02:35 make: *** [Makefile:1051: all] Error 2 > > From > # reset_artifacts: > -10 > # true: > 0 > # build_abe gcc: > 1 > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_gcc_build--master-arm-precommit/1787/artifac… > Reference build : https://ci.linaro.org/job/tcwg_gcc_build--master-arm-build/1060/artifact/ar… > > Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/… > > Full commit : https://github.com/gcc-mirror/gcc/commit/360cabf45a05d5d2d5a98f0e081cb8f53e… > > Latest bug report status : https://linaro.atlassian.net/browse/GNU-692 > > List of configurations that regressed due to this commit : > * tcwg_gcc_build > ** master-arm > *** Failure > *** https://ci.linaro.org/job/tcwg_gcc_build--master-arm-precommit/1787/

2 years, 2 months

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LLVM bots down for extended period

by Aaron Ballman

Hello! You are the point of contact for some build bots in the LLVM build lab that have been down for an extended period of time. If you're not the correct point of contact, can you please CC the right individual (if you know who they are)? The following bot(s) appear to have been down for multiple weeks: https://lab.llvm.org/buildbot/#/builders/clang-armv7-global-isel https://lab.llvm.org/buildbot/#/builders/clang-native-arm-lnt-perf https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vla-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls https://lab.llvm.org/buildbot/#/builders/clang-armv7-vfpv3-full-2stage https://lab.llvm.org/buildbot/#/builders/clang-thumbv7-full-2stage Do you have plans to bring the bot back online? If not, that's okay -- just let me know and I can remove the bots from the lab for you. Thank you! ~Aaron

2 years, 2 months

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CMake requirements LLVM buildbots

by Mark de Wever

Hi, As discussed in [1] I just committed [2] to update the minimum CMake version in LLVM to 3.20.0. Unfortunately it seems the ARM builders in the libc++ precommit CI are running CMake 3.16.3 [3]. Would it be possible to update these builders? [1] https://discourse.llvm.org/t/rfc-upgrading-llvms-minimum-required-cmake-ver… [2] https://reviews.llvm.org/D144509a [3] https://buildkite.com/llvm-project/libcxx-ci/builds/19366#0186756a-1599-46e… Thanks, Mark

2 years, 2 months

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[ACTIVITY] Report for week #32

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Returned to implementing support for changing SVE vector length in remote debugging. The patch series I sent earlier this year used an approach that some maintainers weren't enthusiastic about (modifying the Remote Serial Protocol to request XML target descriptions). Now trying the approach they suggested, which is to extend target descriptions to support expressing vector registers whose length is given by the contents of another register. # TCWG CI - Following Maxim's suggestion, sent and merged Gerrit review requests to increase chance of tcwg_gdb_check jobs to be faster at detecting new or newly expired flaky tests: - 45151: tcwg_gdb: Increase job frequency - 45152: round-robin.sh (build_abe): Increase time to re-detect GDB flaky tests - Implemented change in ABE to support glibc's TIMEOUTFACTOR environment variable for DejaGnu testsuites. Testing on armv8l and aarch64. -- Thiago

2 years, 2 months

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[ACTIVITY] week ending Aug. 13 2023

by Alex Bennée

QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH 0/8] some testing and gdbstub fixes Message-Id: <20230810153640.1879717-1-alex.bennee(a)linaro.org> for 8.1 release - posted [RFC PATCH 0/2] linux-user: extend -dfilter to accept paths Message-Id: <20230811162830.2278032-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> [plugin patch] <https://patchew.org/QEMU/CADc=-s5RwGViNTR-h5cq3np673W3RRFfhr4vCGJp0EoDUxvho…> Completed Reviews [3/3] ======================= [PATCH v3 0/3] Add VIRTIO sound card Message-Id: <cover.1689692765.git.manos.pitsidianakis(a)linaro.org> [RFC v4 00/11] Native Library Calls Message-Id: <20230808141739.3110740-1-fufuyqqqqqq(a)gmail.com> Absences ======== - Birthday long weekend next week Current Review Queue ==================== TODO [PATCH v3 0/9] gfxstream + rutabaga_gfx Message-Id: <20230803235502.373-1-gurchetansingh(a)google.com> ======================================================================================================== TODO [PATCH 0/4] chardev/char-fe: Document FEWatchFunc and use G_SOURCE_CONTINUE/REMOVE Message-Id: <20230705133139.54419-1-philmd(a)linaro.org> ============================================================================================================================================= TODO [PATCH v2 0/3] util/fifo8: Introduce fifo8_peek_buf() Message-Id: <20230705131859.53970-1-philmd(a)linaro.org> ================================================================================================================ -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 2 months

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[ACTIVITY] report week ending 11 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - code review, notably: + RTH's setnegcond series + Jean-Philippe's fixes for various FEAT_RME bugs + Akihiko's series to make KVM '-machine none' not default to 40 bits of IPA space if the host doesn't supoprt that (like the Apple CPUs) - sent a patch to catch the illegal exception return case from EL3 with bad SCR_EL3.{NSE,NS} - respin and resend of ptw cleanup patchset - tidied another 'BiteSizedTask' entry into a gitlab issue - went back to an old minor cleanup task: getting rid of the last dozen or so uses of variable-length arrays in the codebase (so we can enforce not using them in the compiler, and avoid unchecked-on-stack-allocation security bugs). Sent patches to zap a few more. * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - thinking a bit more about FEAT_MOPS and MTE checks, but ultimately not much progress: didn't find enough hours with a sufficiently alert mind... -- PMM

2 years, 2 months

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[ACTIVITY] Report for week #31

by Thiago Jung Bauermann

Hello, # TCWG CI - Implemented increasing testsuite timeout for each testsuite try in GDB check jobs. Sent a Gerrit review request for it but then found out that it makes armhf jobs take a lot longer, so abandoned it. # Community - Finished reviewing SME patches for GDB and gdbserver. -- Thiago

2 years, 2 months

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[ACTIVITY] report week ending 4 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - some bits and pieces for release - code review, notably: + raspberry pi 4 support patchseries (a big 44-patch set) + Xilinx Versal CFI support patches * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - more work on FEAT_MOPS: tested my memset implementation, and fixed various bugs. Still no MTE tag checking support. -- PMM

2 years, 2 months

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[ACTIVITY] Report for week #30

by Thiago Jung Bauermann

Hello, # TCWG CI - CI Babysitting: Worked on two regressions detected at the end of last week. - Enabled precommit testing for GDB patches. # Misc - Reviewing SME patches for GDB and gdbserver. -- Thiago

2 years, 3 months

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[ACTIVITY] report week ending 28 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - release related stuff: handling merge requests, etc (now passed back to RTH again) - sent some patches for a few easy coverity issues - worked through some code review (in particular some patches from new contributors) - created a gitlab "bite sized task" issue that better explains and has more detail on the "convert from malloc to g_malloc" suggested task for new contributors * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - a little more progress with FEAT_MOPS. I now have an untested implementation of the memset insns which I think is complete except for MTE tag checking -- PMM

2 years, 3 months

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[ACTIVITY] Report for week #29

by Thiago Jung Bauermann

Hello, # TCWG CI - Babysat the CI: Investigated 9 regressions in GCC, 2 in GDB, 1 in LLVM and 1 in glibc. Reported 4 in GCC (GNU-855, GNU-857, GNU-858 and GNU-859). 3 of which are fixed and another has a tentative fix. - Reviewed a couple of Gerrit requests. -- Thiago

2 years, 3 months

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[ACTIVITY] report week ending Jul 21

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - fixed some places in our RTC device models where we were putting a time_t or time_t offset into a 32-bit variable - took over from RTH briefly for pullreq merge handling - sent some patches fixing minor Coverity issues - investigated a couple of "test case fails on big-endian host" errors: sent patches for Sparc FPRS handling and for the Arm SMMUv3 model - Investigated report that our MPS2/3 M-profile models don't have the same number of MPU regions configured as the real FPGA images, and so you can't run the same Zephyr binary on both. Have some preliminary patches to correct the number of regions. * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - finally got back to FEAT_MOPS work; wrote a skeleton of code for the memset operations that's about right up to the point where it needs to actually do the memset... -- PMM

2 years, 3 months

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[ACTIVITY] week ending Jul. 23 2023

by Alex Bennée

Project Orko ============ - Hosted sprint planning, syncs with EPAM and Xilinx [roadmap] <https://linaro.atlassian.net/wiki/spaces/ORKO/overview> Generic vhost-user-device ([ORKO-19]) ===================================== - spent some time improving coverage for CI on standaline PoC - syncing with RedHat on virtio-sound [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [QEMU bits] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [vhost bits] <https://github.com/stsquad/vhost/tree/standalone/get-specs> [vhost-device bits] <https://github.com/stsquad/vhost-device/pull/new/standalone/vrng-experiment> Enable Arm Architecture in QEMU =============================== [slides] <https://www.bennee.com/~alex/presentations/kvm23-qemu-keynote.html> [live stream feed] <https://www.youtube.com/live/vy-3oYEDKCQ?feature=share&t=3531> QEMU Upstream Work ([UM-2]) =========================== - started collecting stray fixes, ran into issue with [plugin patch] - has a poor interaction with the SH4 gUSA sequence [UM-2] <https://linaro.atlassian.net/browse/UM-2> [plugin patch] <https://patchew.org/QEMU/CADc=-s5RwGViNTR-h5cq3np673W3RRFfhr4vCGJp0EoDUxvho…> Completed Reviews [1/1] ======================= [PATCH v3 0/3] Add VIRTIO sound card Message-Id: <cover.1689692765.git.manos.pitsidianakis(a)linaro.org> Absences ======== - Summer holidays until 2nd week of August Current Review Queue ==================== TODO [PATCH 0/4] chardev/char-fe: Document FEWatchFunc and use G_SOURCE_CONTINUE/REMOVE Message-Id: <20230705133139.54419-1-philmd(a)linaro.org> ============================================================================================================================================= TODO [PATCH v2 0/3] util/fifo8: Introduce fifo8_peek_buf() Message-Id: <20230705131859.53970-1-philmd(a)linaro.org> ================================================================================================================ TODO [PATCH v3 0/4] Virtio shared dma-buf Message-Id: <20230524091333.201767-1-aesteve(a)redhat.com> ================================================================================================= -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

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'(...)Applications/ClamAV/clamscan' is missing

by Andrzej Warzynski

Hi everyone, I'm not 100% sure whether this is a bot misconfiguration issue, but couldn't find any other source of this failure: ``` ******************** TEST 'test-suite :: MultiSource/Applications/ClamAV/clamscan.test' FAILED ******************** Executable '/home/tcwg-buildbot/worker/clang-aarch64-sve-vla/test/sandbox/build/MultiSource/Applications/ClamAV/clamscan' is missing ******************** ``` Link: https://lab.llvm.org/buildbot/#/builders/197/builds/8209 Would anyone be able to take a look? Thank you :) -Andrzej IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

2 years, 3 months

3
4
0 0

[ACTIVITY] report week ending 14 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - investigated and fixed a bug in page-table-walk handling of debug accesses that was introduced by the FEAT_RME changes - that prompted me to look at a cleanup of some of the ptw code so that we consistently look at "which space is this walk for" and don't carry around a parallel boolean "secure/non-secure" that duplicates that information - found and fixed a few other ptw bugs along the way -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Jul. 9 2023

by Alex Bennée

Project Orko ============ - held kick-off with the EPAM guys [roadmap] <https://linaro.atlassian.net/wiki/spaces/ORKO/overview> Generic vhost-user-device ([ORKO-19]) ===================================== - PoC for standaline vhost-user daemons - [QEMU bits] - [vhost bits] - [vhost-device bits] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [QEMU bits] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [vhost bits] <https://github.com/stsquad/vhost/tree/standalone/get-specs> [vhost-device bits] <https://github.com/stsquad/vhost-device/pull/new/standalone/vrng-experiment> Enable Arm Architecture in QEMU =============================== - Delivered talk at KVM Forum - See [slides] and [live stream feed] (dodgy audio) [slides] <https://www.bennee.com/~alex/presentations/kvm23-qemu-keynote.html> [live stream feed] <https://www.youtube.com/live/vy-3oYEDKCQ?feature=share&t=3531> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH 0/5] docs/devel: improve API documentation for QOM Message-Id: <20230619171437.357374-1-alex.bennee(a)linaro.org> - posted [PULL 00/38] maintainer updates for 8.1: testing, fuzz, plugins, docs, gdbstub Message-Id: <20230703134427.1389440-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH 0/2] tests: lcitool: Refresh to latest lcitool changes Message-Id: <cover.1685528076.git.eskultet(a)redhat.com> [PATCH v3 0/8] gdbstub: Add support for info proc mappings Message-Id: <20230606132743.1386003-1-iii(a)linux.ibm.com> [PATCH] contrib/plugins: add meson build file Message-Id: <20230615141315.961315-1-anton.kochkov(a)proton.me> [RFC v3 00/10] Native Library Calls Message-Id: <20230625212707.1078951-1-fufuyqqqqqq(a)gmail.com> Other ===== - various syncs Current Review Queue ==================== TODO [PATCH 0/4] chardev/char-fe: Document FEWatchFunc and use G_SOURCE_CONTINUE/REMOVE Message-Id: <20230705133139.54419-1-philmd(a)linaro.org> ============================================================================================================================================= TODO [PATCH v2 0/3] util/fifo8: Introduce fifo8_peek_buf() Message-Id: <20230705131859.53970-1-philmd(a)linaro.org> ================================================================================================================ TODO [PATCH v3 0/4] Virtio shared dma-buf Message-Id: <20230524091333.201767-1-aesteve(a)redhat.com> ================================================================================================= -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #27

by Thiago Jung Bauermann

Hello, # TCWG CI - Changed tcwg_gnu-build.sh to apply GDB patch adding '--with-additional-debug-dirs' option, and ABE's gdb.conf to use it. Also changed both to add '--prefix /usr' option to GDB's configure. Both changes to fix ld.so debug info issues in GDB testsuite runs on armhf. - Testing changes to validate_failures.py and jenkins-scripts to handle empty gdb.sum. - Reviewed a few Gerrit requests. -- Thiago

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 6 Jul

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - softfreeze is next week, so spent some time putting together a pull request, fixing the bugs which the CI tests found in it, etc * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - now that we implement all the necessary features (excluding some trace/profiling type stuff that is out-of-scope for QEMU, and also FEAT_NV that we might come back to later), sent out the patchset to define a 'neoverse-v1' CPU type for QEMU -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #26

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Investigated why the CI didn't recover from empty gdb.sum, since it was supposed to. - Fixing validate_failures.py and tcwg_gnu-build.sh to correctly handle empty gdb.sum. - Fixing GDB armhf CI jobs to find distro's debug info. # CI Babysitting - Verified that a couple of regressions I reported last week were fixed in trunk. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #25

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Investigated why the GDB check jobs stopped succeeding, as reported by Maxim. It turns there was an upstream commit (which was soon reverted) that broke generation of the gdb.sum file and consequently our baseline results became empty. Theoretically the CI should recover from that but we don't deal well with this corner case. With Maxim's help, restored the baseline and now things should be back to normal. Will improve our scripts to avoid this trap. # CI Babysitting This week was my turn to baby sit the CI. - Investigated 12 regressions in GCC and reported 3. The others were already fixed. - Investigated 1 regression in GDB but it wasn't actually one. - Investigated 1 regression in QEMU but it was already fixed. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 23 Jun (inc. KVM Forum trip report)

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - catch up on email after a week away - Put together some arm pull requests - sent out draft QEMU summit minutes for review - sent patch to avoid using the buggy __builtin_subcll in Apple Clang 14 - sent patch fixing build error with newer xkeyboard-data - some gardening of Coverity issue reports Last week was KVM Forum in Brno -- here's a quick trip summary: This year KVM Forum was a slightly smaller conference (2 days, single-track), as we are now organizing it independently of the Linux Foundation. The independent organization went pretty well this year (despite the slightly awkward short notice) and the conference was very useful both for the talks and for the hallway track. Interesting talks (just a sampling biased to my interests): * KVM: Arm Confidential Compute Architecture Support Suzuki Poulose presented a summary of FEAT_RME and the CCA hardware and software architecture, and how it's intended to fit into KVM * KVM/arm64: Episode V - The Blob Strikes Back Immediately following was Marc Zyngier and Oliver Upton from Google: their talk was a pretty strong critique of the CCA software stack architecture. Their central point is that having the RMM be "part of the firmware" rather than "part of the hypervisor" is going to cause a rerun of all the issues we've seen with dubious and non-upgradable vendor code in EL3. Secondly, having the fixed API between the hypervisor and the RMM restricts to least-common-denominator and provides no room for experimentation and optimizations. They want an architected way to deploy an RMM at boot time. * Handling complex guest exits with eBPF Will Deacon presented what he described as "conference driven development" -- an interesting prototype of having device models in the host kernel that are implemented in eBPF. This (in theory) gives you the performance gains of an in-kernel device without it putting a lot of C code onto the security boundary between the guest and host. * Challenges Revisited in Supporting Virt CPU Hotplug on architectures that don't Support CPU Hotplug (like ARM64) James Morse (Arm) and Salil Mehta (Huawei) presented on CPU hotplug. The underlying problem here remains that Arm has no hardware hotplug handling, so there's no clear model for what hotplug on a VM should look like. Cloud vendors have an obvious desire for the x86-style tooling to Just Work on Arm too. The gap between "we have a prototype that seems to work" and "upstreamable maintainable code" has not yet been bridged, though... * QEMU Arm CPU models and KVM Cornelia Huck (RedHat) had a talk that was intended as a statement of the problem rather than a proposed solution. At the moment we only let a KVM guest see the same CPU type as the host and don't have a mechanism for presenting a subset of features to it. KVM is about to get support for letting the VMM define what the guest should see in the ID registers, but how should we expose that to QEMU users without ending up with a thousand command line sub-options to turn on and off every architectural FEAT_FOO? And how do we deal with errata workarounds, which the guest currently selects based on the MIDR value? As usual, we held the QEMU Summit (an hour-long maintainer discussion mostly about process and organizational issues) during KVM Forum. I still need to write up the minutes for this, but they'll be published on the qemu-devel list shortly. thanks -- PMM

2 years, 4 months

1
0
0 0

Need emit_expr to write right shifted value.

by zac.walker＠linaro.org

Hi, In binutils I need to write an offset between two symbols shifted right by 2 bits. This offset is written to the xdata section. My code currently looks like this: exp.X_op = O_subtract; exp.X_add_symbol = symbol1; exp.X_op_symbol = symbol2; emit_expr (&exp, 2); This works fine but obviously the result value is not shifted. Anyone have a good option is to shift the output of emit_expr at write time? I cannot use resolve_expression because the symbols do not have correct addresses at the time this code executes. Any help appreciated, Zac

2 years, 4 months

2
2
0 0

[ACTIVITY] Report for week #24

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Changed tcwg_gnu-build.sh to apply GDB testsuite patch to avoid infinite loop in tcwg_gdb_check--master-arm jobs, while it isn't committed upstream. - Started investigating corrupt gdb.sum.1 file in tcwg_gdb_check--master-arm jobs. I can't reproduce it by manually running the CI's "make check-gdb" command line, nor by using ABE. I can reproduce it with tcwg_gnu-build.sh though. - Came up with validate_failures.py change to make it cope with the corrupt gdb.sum.1 file, while the underlying cause isn't known. Submitted the change upstream. # TCWG Infrastructure - Reviewed some Gerrit requests for our CI scripts. # Misc - Did some travel planning for Linaro Employee Meeting and GNU Tools Cauldron. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] week ending Jun. 11 2023

by Alex Bennée

Project Orko ============ - more virtio-gpu discussion, blog post soon Enable Arm Architecture in QEMU =============================== - prep for KVM Forum talk Other ===== - various syncs Absences ======== - KVM Forum next week Current Review Queue ==================== TODO [RFC v2 0/6] Native Library Calls Message-Id: <20230607164750.829586-1-fufuyqqqqqq(a)gmail.com> ================================================================================================= TODO [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> ============================================================================================================================== TODO [PATCH v2 00/10] hw/virtio: Build various target-agnostic objects just once Message-Id: <20230524093744.88442-1-philmd(a)linaro.org> ====================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 9 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - code review (including a new board-and-devices patchseries for a TI Tiva C devboard) - Put together an arm pull request - Investigated some bug reports, sent patches: * regression in Allwinner A10 interrupt controller * hang in icount mode on microbit with Zephyr guest * LDG doesn't return the right values when ATA==0 - prep for next week's KVM Forum trip * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - handling review comments and rebasing of decodetree load/store conversion - investigating a few issues I noticed in the process -- PMM

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #23

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Addressed review comments and sent v2 and v3 of the patch fixing loop in gdb.reverse/step-reverse.exp. The testcase's original author gave his Reviewed-by, now waiting for approval by a maintainer. In the meantime, set up our CI to apply the patch locally. - Sent patch to the GDB mailing list implementing configure option '--with-additional-debug-dirs' to allow building a GDB binary with a custom install prefix but which also looks for debug info in /usr/lib/debug. This should solve the SIGILL issue on armhf-linux in our CI, and allow a few more tests to run on aarch64-linux. # TCWG Infrastructure - Reviewed some Gerrit requests related to notification and baseline updating. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] week ending Jun. 4 2023

by Alex Bennée

Project Orko ============ - added date for initial [roadmap] [roadmap] <https://linaro.atlassian.net/wiki/spaces/ORKO/overview> Generic vhost-user-device ([ORKO-19]) ===================================== - posted [PATCH v2 00/13] virtio: add vhost-user-generic and reduce copy and paste Message-Id: <20230418162140.373219-1-alex.bennee(a)linaro.org> [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [pull req for gpio simulated device support] <https://github.com/rust-vmm/vhost-device/pull/313> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] softmmu/vl: fix typo for PHASE_MACHINE_INITIALIZED Message-Id: <20230413090310.1197548-1-alex.bennee(a)linaro.org> - posted [PATCH 00/10] tracing: remove dynamic vcpu state Message-Id: <20230420150009.1675181-1-alex.bennee(a)linaro.org> - posted [PATCH 0/9] docs: various (style, punctuation and typo fixes) Message-Id: <20230420155723.1711048-1-alex.bennee(a)linaro.org> - posted [PATCH v4 0/6] testing/next: avocado, docs, gitlab Message-Id: <20230417134321.3627231-1-alex.bennee(a)linaro.org> - posted [PATCH v6 00/11] tracing: remove dynamic vcpu state Message-Id: <20230526165401.574474-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining Message-Id: <20230523131107.3680641-1-alex.bennee(a)linaro.org> - posted [PATCH 0/8] testing/next: avocado logging, docs, gitlab Message-Id: <20230518162034.1277885-1-alex.bennee(a)linaro.org> - started prepping for KVM Forum Keynote [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [10/10] ========================= [QEMU][PATCH] gitlab-ci.d/crossbuilds: Drop the '--disable-tcg' configuration for xen Message-Id: <20230411210422.24255-1-vikram.garhwal(a)amd.com> [RFC 0/1] add support of `--initrd` for ELF-ARM kernels Message-Id: <20230414073432.36000-1-slankes(a)eonerc.rwth-aachen.de> [PATCH 0/2] accel/tcg/plugin: host insn size for plugin Message-Id: <20230406022751.757980-1-fei2.wu(a)intel.com> [PATCH v2 0/8] iotests: make meson aware of individual I/O tests Message-Id: <20230303160727.3977246-1-berrange(a)redhat.com> [PATCH v2] tests/vm/freebsd: Update to FreeBSD 13.2 Message-Id: <20230419144553.719749-1-thuth(a)redhat.com> [PATCH v4 0/2] Improve code coverage for ppc64 Message-Id: <20230421042322.684093-1-kconsul(a)linux.vnet.ibm.com> [PATCH 0/2] gitlab: improve artifact handling Message-Id: <20230503145535.91325-1-berrange(a)redhat.com> [PATCH v2 0/3] tests/tcg/s390x: Enable the multiarch system tests Message-Id: <20230424114533.1937153-1-iii(a)linux.ibm.com> [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> [RFC] Native Library Calls Message-Id: <20230530142430.45834-1-fufuyqqqqqq(a)gmail.com> Other ===== - Sorting out logistics for KVM Forum Absences ======== - Bank holidays Current Review Queue ==================== TODO [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> ============================================================================================================================== TODO [PATCH v2 00/10] hw/virtio: Build various target-agnostic objects just once Message-Id: <20230524093744.88442-1-philmd(a)linaro.org> ====================================================================================================================================== TODO [PATCH 0/8] Tiva C Implementation Message-Id: <20230517081204.30333-1-m.elsayed4420(a)gmail.com> ================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #22

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Continued investigating issue with GDB on armhf-linux about getting SIGILL when trying to detect shared library loading/unloading. Noticed that the problem happens only in tests that use the distro's toolchain (either because they're for a language we don't build in ABE gcc, or because GDB itself is built with the distro toolchain), so the impact isn't as widespread as I initially thought. It still frequently causes trouble for our CI loop though. Working on a fix. - Investigated and fixed loop in gdb.reverse/step-reverse.exp that was causing tcwg_gdb_check--master-arm-build jobs to get stuck, as reported by Maxim. Posted patch to the GDB mailing list. # TCWG Infrastructure - Reviewed Gerrit requests about testing mailing list patches in our CI. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 2 Jun

by Peter Maydell

Progress (another short week, May is great this year): * UM-2 [QEMU upstream maintainership] - More review on some of RTH's atomics related patchsets - Put together an arm pull request - Sent out a call for agenda items for QEMU Summit * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - decodetree load/store conversion done, patches sent out for review. After this I plan to go back to the FEAT_MOPS implementation (and then do the last part of the integer A64 decodetree conversion later in this release cycle). -- PMM

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #21

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Investigating issue in CI jobs where touching all C files causes GDB to show a warning about the source being newer than the executable. This interferes with a few GDB tests. - Continued investigating issue with GDB on armhf-linux about getting SIGILL when trying to detect shared library loading/unloading. Found out that the GDB testsuite binaries are using the distro's ld.so rather than the one built by ABE and which is the one expected to be used. Because we don't have debuginfo installed for the distro's ld.so, we hit the GDB bug in armhf-linux. The ld.so built by ABE has debuginfo and would avoid hitting the issue. # TCWG Infrastructure - Reworked CI job to sanity check tcwg_gnu_fast_check_{gcc,gdb} and posted new version for review. - Reviewed some Gerrit requests for jenkins-scripts and ABE. -- Thiago

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 25 May

by Peter Maydell

Progress (short week, three days): * UM-2 [QEMU upstream maintainership] - Sent a patch fixing a bug where we broke some M-profile uses (resulting in assertion failures) when we added v8R support * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Implemented support for a new feature in the decodetree generator that I need for the A64 decodetree conversion, sent patches out for review - More progress on A64 decodetree: loads and stores -- PMM

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #20

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Analysed a number of potential regressions found by our CI on aarch64-linux and armhf-linux. They aren't exactly regressions but bug fixes or new features that work on other arches (or perhaps whose testcases correctly detect PASSes on other arches) but not on aarch64-linux or armhf-linux. - armhf-linux has an important problem where a bug with detecting shared library loading/unloading is causing many tests to fail. The result is that every new GDB commit that adds a test is flagged by the bisect job. This was caused by a GDB commit from November 2022. Luis reported it at the time and the patch author was going to look into it, but this probably fell through the cracks. I'm investigating to understand the problem better and provide a fix. -- Thiago

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 19 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Reviewed another round of RTH's patchset overhauling atomics - Sent an arm pullreq * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Continued with the conversion of the A64 decoder to decodetree: have converted hints, barriers, system register insns, exception generation, and am halfway through the loads and stores. -- PMM

2 years, 5 months

1
0
0 0

LLVM buildbot timing out

by Andrzej Warzynski

Hi, Has anyone noticed that https://lab.llvm.org/buildbot/#/builders/198 (clang-aarch64-sve-vla-2stage<https://lab.llvm.org/buildbot/#/builders/198>) has been timing out for the past few days? "Duration" is often less than 1hr, so that's odd. And all Flang buildbots are green, so it's unlikely caused by changes to that sub-project (https://lab.llvm.org/buildbot/#/builders/198/builds/1804). Would anyone be able to take a look? Best regards, Andrzej IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

2 years, 5 months

4
6
0 0

[ACTIVITY] Report for week #19

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Reviewed a bunch of Gerrit requests for our CI scripts. - Finished job definition to run fast_check_{gcc,gdb} jobs triggered by new Gerrit review requests for jenkins-scripts, benchmark scripts and ABE. Sent Gerrit review request and now working on 2nd version. - Rebased our DejaGNU debug patches to upstream dejagnu-1.6.3, tested result and sent Gerrit review request for it. # TCWG CI — GDB - Confirmed regression found by CI job¹ and mentioned by Maxim. Found out that it was fixed upstream already². -- Thiago ¹ https://ci.linaro.org/job/tcwg_gnu_native_check_gdb--master-aarch64-bisect/… ² https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5a6ad5c775a58367…

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending May 12

by Peter Maydell

Progress (another short week, May is full of bank holidays :-)): * UM-2 [QEMU upstream maintainership] - usual background level of code review etc - investigated a bug reported by Mozilla where people running x86 Firefox on QEMU on Arm hardware were seeing crashes; narrowed down the cause (aided by Mozilla kindly providing a minimal repro test case), and Paolo produced a fix. * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Started looking at what is required for FEAT_MOPS (the memcpy/memset/memmove insns), what they do and how QEMU ought to implement them. - The new insns are in the load/store part of the A64 instruction space. To make this easier to do, we should really convert at least the integer parts of the A64 decoder to decodetree (a refactoring we've been putting off for a long time). Started on the conversion: sent out a first 20-patch patchset that converts the dp-immediate and branch insns. -- PMM

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 5 May

by Peter Maydell

Progress (combines two weeks): * UM-2 [QEMU upstream maintainership] - investigated various failures of avocado tests on s390x host. These are at least four different unrelated endianness bugs in different device, board or CPU models. Sent out a set of patches fixing at most of these. - TCWG / Arm syncup meeting - Linaro Connect - caught up on code review and sent a target-arm pull request - sent patch fixing a bug where our PNG screenshots have the pixel colour channels in the wrong order - while I had a conversation from Connect fresh in my mind, went back and re-looked at the page-table-walk bug with handling the NSW/SW bits that I sent patches for a couple of weeks ago. Re-did the code to consistently handle these bits in the right place and sent out another version of the patchset - reviewed a very large patchset from RTH that changes how TCG handles atomic accesses so we can implement FEAT_LSE2 - investigated a bug report about a regression with AArch32 EL1 under an AArch64 EL2; wrote patch -- PMM

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #16

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Reviewed a bunch of Gerrit requests for our CI scripts. - Learning Jenkins job builder syntax and working on a job definition to run fast_check_{gcc,gdb} jobs on Gerrit review requests for jenkins-scripts and ABE. - Changed CI scripts to save ABE and component testsuite logs when the ABE build or check step fails. This should help debug a case where a GDB CI job failed due to (probably) a corruption of the gdb.sum testsuite result file. # Misc - Some preparations for the trip to Linaro Connect. -- Thiago

2 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 21 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out v3 of the 'deprecate singlestep option' patchset - sorted out the draft QEMU Summit invite list and invitation text - spent some time trying to understand how the imx SoCs arrange their ethernet controllers and PHYs so I can review a patchset - sent patch fixing minor configure nit where it wasn't honouring --cross-prefix for the ObjC compiler - got the 8.0 release out of the door and handed over merge handling to rth - sent some patchsets updating a few old .txt files to reStructuredText - still thinking about our page-table-walk code -- I'm not convinced it's doing the right thing with NSW/SW bits, even after last week's patchset... -- PMM

2 years, 6 months

1
0
0 0

[ACTIVITY] Report for week #15

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Fixed problem in ABE with MinGW build of GDB's master branch. - Fixed problem in upstream GDB with MinGW build of GDB's master branch. - Analysed backlog of failed check_gdb jobs. - A couple of "misbisected" commits, including one pointing to a glibc commit. - One detected regression also noticed by Christophe, and fixed by the community. - One Arm failure that passes on QEMU TCG. - Reviewed a number of Gerrit requests about improving ABE and CI scripts. -- Thiago

2 years, 6 months

1
0
0 0

[ACTIVITY] week ending Apr. 16 2023

by Alex Bennée

Project Orko ============ Generic vhost-user-device ([ORKO-19]) ===================================== - posted [PATCH 00/12] virtio: add vhost-user-generic and reduce copy and paste Message-Id: <20230414160433.2096866-1-alex.bennee(a)linaro.org> - sent [pull req for gpio simulated device support] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [pull req for gpio simulated device support] <https://github.com/rust-vmm/vhost-device/pull/313> Enable Arm Architecture in QEMU =============================== QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] softmmu/vl: fix typo for PHASE_MACHINE_INITIALIZED Message-Id: <20230413090310.1197548-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [QEMU][PATCH] gitlab-ci.d/crossbuilds: Drop the '--disable-tcg' configuration for xen Message-Id: <20230411210422.24255-1-vikram.garhwal(a)amd.com> [RFC 0/1] add support of `--initrd` for ELF-ARM kernels Message-Id: <20230414073432.36000-1-slankes(a)eonerc.rwth-aachen.de> [PATCH 0/2] accel/tcg/plugin: host insn size for plugin Message-Id: <20230406022751.757980-1-fei2.wu(a)intel.com> Other ===== Absences ======== - Easter holidays Current Review Queue ==================== TODO [PATCH for-8.1 0/3] Make softmmu/qtest.c target independent Message-Id: <20230411183418.1640500-1-thuth(a)redhat.com> ======================================================================================================================= TODO [QEMU][PATCH v6 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230411224746.16152-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 6 months

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[ACTIVITY] report week ending 14 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * trying to get a release out of the door -- due among other things to the Easter holiday weekend, rc4 is a bit late and has rather more changes than I would prefer * more triaging of Coverity issues * sent a few trivial bug fix patches * started reviewing and queueing arm patches for 8.1 * investigated a FEAT_SEL2 bug that showed up with some proposed changes to TF-A/Hafnium. The architecture and QEMU's code are pretty hairy in this area but I think I have identified the correct fix... -- PMM

2 years, 6 months

1
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LLVM bots down for extended period

by Aaron Ballman

Hello! I noticed that some of the build bots in the LLVM build lab have been down for an extended period of time. I tried emailing the Linaro Toolchain Working Group address as they're listed as the admin for the machine, but I've not heard a response in a week. Renato mentioned you might be a good person to contact instead. The following bot(s) appear to have been down for multiple weeks: https://lab.llvm.org/buildbot/#/builders/clang-armv7-global-isel https://lab.llvm.org/buildbot/#/builders/clang-native-arm-lnt-perf https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vla-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls https://lab.llvm.org/buildbot/#/builders/clang-armv7-vfpv3-full-2stage https://lab.llvm.org/buildbot/#/builders/clang-thumbv7-full-2stage Do you have plans to bring the bots back online? If not, that's okay -- just let me know and I can remove the bots from the lab for you. Thank you! ~Aaron

2 years, 6 months

2
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[ACTIVITY] Report for week #14

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Submitted to GDB mailing list and committed patches fixing the gdb.asm/asm-source.exp regression found by the check_gdb job. Turned out to be a small bug in the stabs debug format support. - Committed Gerrit review request disabling Python on MinGW cross builds. [GNU-767] Support changing SVE vector length in remote debugging - Investigating a follow-up question Simon asked during review of the patch series fixing a corner case when reading auxv from multi-threaded inferiors. -- Thiago

2 years, 6 months

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[ACTIVITY] report week ending 6 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * rc3 this week * reworked my "deprecate the misleading -singlestep option" patchset to deal with review feedback, sent out v2 * KVM Forum programme committee work * investigated a regression where the mps3-an547 board asserts on startup; for 8.0 we will just revert the change that introduced the failure, since it was only an optimization * some triage of Coverity issue reports; sent some patches for some easy ones, queried original code submitter for others -- PMM

2 years, 6 months

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[TCWG CI] 602.gcc_s fails to run after llvmorg-17-init-4880-gf242291f59bf

by Maxim Kuvyrkov

Hi Alexandros, Linaro benchmarking CI flagged this patch. After it clang seems to miscompile 602.gcc_s from SPEC CPU2017 for "-O3 -flto" on aarch64-linux-gnu. Also, it appears that 600.perlbench_s slows down by 9%. Could you investigate, please? Let me know if you need any assistance in reproducing the problem. Our Benchmarking CI is still in active development, and there are false positives, but this report seems to be legit [1]. Kind regards, [1] https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017speed--llvm-aarch64-ma… -- Maxim Kuvyrkov https://www.linaro.org

2 years, 6 months

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[ACTIVITY] Report for week #13

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Committed ABE change suggested by Maxim to mention failures that cause additional testsuite runs. - Tried to update Python MinGW build to 3.x, but it's a rabbit hole. Proposing to disable Python support when cross-building GDB with MinGW instead. - First regression detected by the tcwg_gnu_native_check_gdb CI job reported upstream¹. Started investigating it. [GNU-767] Support changing SVE vector length in remote debugging - Created a testcase to exercise the corner case mentioned by Pedro. Found out that GDB is also susceptible to it. Fixed both GDB and gdbserver. Posted patch series upstream². -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/871ql6dhf4.fsf@linaro.org/ ² https://inbox.sourceware.org/gdb-patches/20230331034432.3037148-1-thiago.ba…

2 years, 7 months

1
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