- linaro-toolchain - lists.linaro.org

Need emit_expr to write right shifted value.

by zac.walker＠linaro.org

Hi, In binutils I need to write an offset between two symbols shifted right by 2 bits. This offset is written to the xdata section. My code currently looks like this: exp.X_op = O_subtract; exp.X_add_symbol = symbol1; exp.X_op_symbol = symbol2; emit_expr (&exp, 2); This works fine but obviously the result value is not shifted. Anyone have a good option is to shift the output of emit_expr at write time? I cannot use resolve_expression because the symbols do not have correct addresses at the time this code executes. Any help appreciated, Zac

1 year, 10 months

2
2
0 0

[ACTIVITY] Report for week #24

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Changed tcwg_gnu-build.sh to apply GDB testsuite patch to avoid infinite loop in tcwg_gdb_check--master-arm jobs, while it isn't committed upstream. - Started investigating corrupt gdb.sum.1 file in tcwg_gdb_check--master-arm jobs. I can't reproduce it by manually running the CI's "make check-gdb" command line, nor by using ABE. I can reproduce it with tcwg_gnu-build.sh though. - Came up with validate_failures.py change to make it cope with the corrupt gdb.sum.1 file, while the underlying cause isn't known. Submitted the change upstream. # TCWG Infrastructure - Reviewed some Gerrit requests for our CI scripts. # Misc - Did some travel planning for Linaro Employee Meeting and GNU Tools Cauldron. -- Thiago

1 year, 11 months

1
0
0 0

[ACTIVITY] week ending Jun. 11 2023

by Alex Bennée

Project Orko ============ - more virtio-gpu discussion, blog post soon Enable Arm Architecture in QEMU =============================== - prep for KVM Forum talk Other ===== - various syncs Absences ======== - KVM Forum next week Current Review Queue ==================== TODO [RFC v2 0/6] Native Library Calls Message-Id: <20230607164750.829586-1-fufuyqqqqqq(a)gmail.com> ================================================================================================= TODO [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> ============================================================================================================================== TODO [PATCH v2 00/10] hw/virtio: Build various target-agnostic objects just once Message-Id: <20230524093744.88442-1-philmd(a)linaro.org> ====================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

1 year, 11 months

1
0
0 0

[ACTIVITY] report week ending 9 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - code review (including a new board-and-devices patchseries for a TI Tiva C devboard) - Put together an arm pull request - Investigated some bug reports, sent patches: * regression in Allwinner A10 interrupt controller * hang in icount mode on microbit with Zephyr guest * LDG doesn't return the right values when ATA==0 - prep for next week's KVM Forum trip * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - handling review comments and rebasing of decodetree load/store conversion - investigating a few issues I noticed in the process -- PMM

1 year, 11 months

1
0
0 0

[ACTIVITY] Report for week #23

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Addressed review comments and sent v2 and v3 of the patch fixing loop in gdb.reverse/step-reverse.exp. The testcase's original author gave his Reviewed-by, now waiting for approval by a maintainer. In the meantime, set up our CI to apply the patch locally. - Sent patch to the GDB mailing list implementing configure option '--with-additional-debug-dirs' to allow building a GDB binary with a custom install prefix but which also looks for debug info in /usr/lib/debug. This should solve the SIGILL issue on armhf-linux in our CI, and allow a few more tests to run on aarch64-linux. # TCWG Infrastructure - Reviewed some Gerrit requests related to notification and baseline updating. -- Thiago

1 year, 11 months

1
0
0 0

[ACTIVITY] week ending Jun. 4 2023

by Alex Bennée

Project Orko ============ - added date for initial [roadmap] [roadmap] <https://linaro.atlassian.net/wiki/spaces/ORKO/overview> Generic vhost-user-device ([ORKO-19]) ===================================== - posted [PATCH v2 00/13] virtio: add vhost-user-generic and reduce copy and paste Message-Id: <20230418162140.373219-1-alex.bennee(a)linaro.org> [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [pull req for gpio simulated device support] <https://github.com/rust-vmm/vhost-device/pull/313> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] softmmu/vl: fix typo for PHASE_MACHINE_INITIALIZED Message-Id: <20230413090310.1197548-1-alex.bennee(a)linaro.org> - posted [PATCH 00/10] tracing: remove dynamic vcpu state Message-Id: <20230420150009.1675181-1-alex.bennee(a)linaro.org> - posted [PATCH 0/9] docs: various (style, punctuation and typo fixes) Message-Id: <20230420155723.1711048-1-alex.bennee(a)linaro.org> - posted [PATCH v4 0/6] testing/next: avocado, docs, gitlab Message-Id: <20230417134321.3627231-1-alex.bennee(a)linaro.org> - posted [PATCH v6 00/11] tracing: remove dynamic vcpu state Message-Id: <20230526165401.574474-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining Message-Id: <20230523131107.3680641-1-alex.bennee(a)linaro.org> - posted [PATCH 0/8] testing/next: avocado logging, docs, gitlab Message-Id: <20230518162034.1277885-1-alex.bennee(a)linaro.org> - started prepping for KVM Forum Keynote [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [10/10] ========================= [QEMU][PATCH] gitlab-ci.d/crossbuilds: Drop the '--disable-tcg' configuration for xen Message-Id: <20230411210422.24255-1-vikram.garhwal(a)amd.com> [RFC 0/1] add support of `--initrd` for ELF-ARM kernels Message-Id: <20230414073432.36000-1-slankes(a)eonerc.rwth-aachen.de> [PATCH 0/2] accel/tcg/plugin: host insn size for plugin Message-Id: <20230406022751.757980-1-fei2.wu(a)intel.com> [PATCH v2 0/8] iotests: make meson aware of individual I/O tests Message-Id: <20230303160727.3977246-1-berrange(a)redhat.com> [PATCH v2] tests/vm/freebsd: Update to FreeBSD 13.2 Message-Id: <20230419144553.719749-1-thuth(a)redhat.com> [PATCH v4 0/2] Improve code coverage for ppc64 Message-Id: <20230421042322.684093-1-kconsul(a)linux.vnet.ibm.com> [PATCH 0/2] gitlab: improve artifact handling Message-Id: <20230503145535.91325-1-berrange(a)redhat.com> [PATCH v2 0/3] tests/tcg/s390x: Enable the multiarch system tests Message-Id: <20230424114533.1937153-1-iii(a)linux.ibm.com> [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> [RFC] Native Library Calls Message-Id: <20230530142430.45834-1-fufuyqqqqqq(a)gmail.com> Other ===== - Sorting out logistics for KVM Forum Absences ======== - Bank holidays Current Review Queue ==================== TODO [PATCH] Add virtio-sound and virtio-sound-pci devices Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org> ============================================================================================================================== TODO [PATCH v2 00/10] hw/virtio: Build various target-agnostic objects just once Message-Id: <20230524093744.88442-1-philmd(a)linaro.org> ====================================================================================================================================== TODO [PATCH 0/8] Tiva C Implementation Message-Id: <20230517081204.30333-1-m.elsayed4420(a)gmail.com> ================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

1 year, 11 months

1
0
0 0

[ACTIVITY] Report for week #22

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Continued investigating issue with GDB on armhf-linux about getting SIGILL when trying to detect shared library loading/unloading. Noticed that the problem happens only in tests that use the distro's toolchain (either because they're for a language we don't build in ABE gcc, or because GDB itself is built with the distro toolchain), so the impact isn't as widespread as I initially thought. It still frequently causes trouble for our CI loop though. Working on a fix. - Investigated and fixed loop in gdb.reverse/step-reverse.exp that was causing tcwg_gdb_check--master-arm-build jobs to get stuck, as reported by Maxim. Posted patch to the GDB mailing list. # TCWG Infrastructure - Reviewed Gerrit requests about testing mailing list patches in our CI. -- Thiago

1 year, 11 months

1
0
0 0

[ACTIVITY] report week ending 2 Jun

by Peter Maydell

Progress (another short week, May is great this year): * UM-2 [QEMU upstream maintainership] - More review on some of RTH's atomics related patchsets - Put together an arm pull request - Sent out a call for agenda items for QEMU Summit * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - decodetree load/store conversion done, patches sent out for review. After this I plan to go back to the FEAT_MOPS implementation (and then do the last part of the integer A64 decodetree conversion later in this release cycle). -- PMM

1 year, 11 months

1
0
0 0

[ACTIVITY] Report for week #21

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Investigating issue in CI jobs where touching all C files causes GDB to show a warning about the source being newer than the executable. This interferes with a few GDB tests. - Continued investigating issue with GDB on armhf-linux about getting SIGILL when trying to detect shared library loading/unloading. Found out that the GDB testsuite binaries are using the distro's ld.so rather than the one built by ABE and which is the one expected to be used. Because we don't have debuginfo installed for the distro's ld.so, we hit the GDB bug in armhf-linux. The ld.so built by ABE has debuginfo and would avoid hitting the issue. # TCWG Infrastructure - Reworked CI job to sanity check tcwg_gnu_fast_check_{gcc,gdb} and posted new version for review. - Reviewed some Gerrit requests for jenkins-scripts and ABE. -- Thiago

1 year, 11 months

1
0
0 0

[ACTIVITY] report week ending 25 May

by Peter Maydell

Progress (short week, three days): * UM-2 [QEMU upstream maintainership] - Sent a patch fixing a bug where we broke some M-profile uses (resulting in assertion failures) when we added v8R support * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Implemented support for a new feature in the decodetree generator that I need for the A64 decodetree conversion, sent patches out for review - More progress on A64 decodetree: loads and stores -- PMM

1 year, 11 months

1
0
0 0

[ACTIVITY] Report for week #20

by Thiago Jung Bauermann

Hello, # TCWG CI — GDB - Analysed a number of potential regressions found by our CI on aarch64-linux and armhf-linux. They aren't exactly regressions but bug fixes or new features that work on other arches (or perhaps whose testcases correctly detect PASSes on other arches) but not on aarch64-linux or armhf-linux. - armhf-linux has an important problem where a bug with detecting shared library loading/unloading is causing many tests to fail. The result is that every new GDB commit that adds a test is flagged by the bisect job. This was caused by a GDB commit from November 2022. Luis reported it at the time and the patch author was going to look into it, but this probably fell through the cracks. I'm investigating to understand the problem better and provide a fix. -- Thiago

1 year, 12 months

1
0
0 0

[ACTIVITY] report week ending 19 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Reviewed another round of RTH's patchset overhauling atomics - Sent an arm pullreq * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Continued with the conversion of the A64 decoder to decodetree: have converted hints, barriers, system register insns, exception generation, and am halfway through the loads and stores. -- PMM

1 year, 12 months

1
0
0 0

LLVM buildbot timing out

by Andrzej Warzynski

Hi, Has anyone noticed that https://lab.llvm.org/buildbot/#/builders/198 (clang-aarch64-sve-vla-2stage<https://lab.llvm.org/buildbot/#/builders/198>) has been timing out for the past few days? "Duration" is often less than 1hr, so that's odd. And all Flang buildbots are green, so it's unlikely caused by changes to that sub-project (https://lab.llvm.org/buildbot/#/builders/198/builds/1804). Would anyone be able to take a look? Best regards, Andrzej IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

1 year, 12 months

4
6
0 0

[ACTIVITY] Report for week #19

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Reviewed a bunch of Gerrit requests for our CI scripts. - Finished job definition to run fast_check_{gcc,gdb} jobs triggered by new Gerrit review requests for jenkins-scripts, benchmark scripts and ABE. Sent Gerrit review request and now working on 2nd version. - Rebased our DejaGNU debug patches to upstream dejagnu-1.6.3, tested result and sent Gerrit review request for it. # TCWG CI — GDB - Confirmed regression found by CI job¹ and mentioned by Maxim. Found out that it was fixed upstream already². -- Thiago ¹ https://ci.linaro.org/job/tcwg_gnu_native_check_gdb--master-aarch64-bisect/… ² https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5a6ad5c775a58367…

2 years

1
0
0 0

[ACTIVITY] report week ending May 12

by Peter Maydell

Progress (another short week, May is full of bank holidays :-)): * UM-2 [QEMU upstream maintainership] - usual background level of code review etc - investigated a bug reported by Mozilla where people running x86 Firefox on QEMU on Arm hardware were seeing crashes; narrowed down the cause (aided by Mozilla kindly providing a minimal repro test case), and Paolo produced a fix. * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Started looking at what is required for FEAT_MOPS (the memcpy/memset/memmove insns), what they do and how QEMU ought to implement them. - The new insns are in the load/store part of the A64 instruction space. To make this easier to do, we should really convert at least the integer parts of the A64 decoder to decodetree (a refactoring we've been putting off for a long time). Started on the conversion: sent out a first 20-patch patchset that converts the dp-immediate and branch insns. -- PMM

2 years

1
0
0 0

[ACTIVITY] report week ending 5 May

by Peter Maydell

Progress (combines two weeks): * UM-2 [QEMU upstream maintainership] - investigated various failures of avocado tests on s390x host. These are at least four different unrelated endianness bugs in different device, board or CPU models. Sent out a set of patches fixing at most of these. - TCWG / Arm syncup meeting - Linaro Connect - caught up on code review and sent a target-arm pull request - sent patch fixing a bug where our PNG screenshots have the pixel colour channels in the wrong order - while I had a conversation from Connect fresh in my mind, went back and re-looked at the page-table-walk bug with handling the NSW/SW bits that I sent patches for a couple of weeks ago. Re-did the code to consistently handle these bits in the right place and sent out another version of the patchset - reviewed a very large patchset from RTH that changes how TCG handles atomic accesses so we can implement FEAT_LSE2 - investigated a bug report about a regression with AArch32 EL1 under an AArch64 EL2; wrote patch -- PMM

2 years

1
0
0 0

[ACTIVITY] Report for week #16

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Reviewed a bunch of Gerrit requests for our CI scripts. - Learning Jenkins job builder syntax and working on a job definition to run fast_check_{gcc,gdb} jobs on Gerrit review requests for jenkins-scripts and ABE. - Changed CI scripts to save ABE and component testsuite logs when the ABE build or check step fails. This should help debug a case where a GDB CI job failed due to (probably) a corruption of the gdb.sum testsuite result file. # Misc - Some preparations for the trip to Linaro Connect. -- Thiago

2 years

1
0
0 0

[ACTIVITY] report week ending 21 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out v3 of the 'deprecate singlestep option' patchset - sorted out the draft QEMU Summit invite list and invitation text - spent some time trying to understand how the imx SoCs arrange their ethernet controllers and PHYs so I can review a patchset - sent patch fixing minor configure nit where it wasn't honouring --cross-prefix for the ObjC compiler - got the 8.0 release out of the door and handed over merge handling to rth - sent some patchsets updating a few old .txt files to reStructuredText - still thinking about our page-table-walk code -- I'm not convinced it's doing the right thing with NSW/SW bits, even after last week's patchset... -- PMM

2 years

1
0
0 0

[ACTIVITY] Report for week #15

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Fixed problem in ABE with MinGW build of GDB's master branch. - Fixed problem in upstream GDB with MinGW build of GDB's master branch. - Analysed backlog of failed check_gdb jobs. - A couple of "misbisected" commits, including one pointing to a glibc commit. - One detected regression also noticed by Christophe, and fixed by the community. - One Arm failure that passes on QEMU TCG. - Reviewed a number of Gerrit requests about improving ABE and CI scripts. -- Thiago

2 years, 1 month

1
0
0 0

[ACTIVITY] week ending Apr. 16 2023

by Alex Bennée

Project Orko ============ Generic vhost-user-device ([ORKO-19]) ===================================== - posted [PATCH 00/12] virtio: add vhost-user-generic and reduce copy and paste Message-Id: <20230414160433.2096866-1-alex.bennee(a)linaro.org> - sent [pull req for gpio simulated device support] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [pull req for gpio simulated device support] <https://github.com/rust-vmm/vhost-device/pull/313> Enable Arm Architecture in QEMU =============================== QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] softmmu/vl: fix typo for PHASE_MACHINE_INITIALIZED Message-Id: <20230413090310.1197548-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [QEMU][PATCH] gitlab-ci.d/crossbuilds: Drop the '--disable-tcg' configuration for xen Message-Id: <20230411210422.24255-1-vikram.garhwal(a)amd.com> [RFC 0/1] add support of `--initrd` for ELF-ARM kernels Message-Id: <20230414073432.36000-1-slankes(a)eonerc.rwth-aachen.de> [PATCH 0/2] accel/tcg/plugin: host insn size for plugin Message-Id: <20230406022751.757980-1-fei2.wu(a)intel.com> Other ===== Absences ======== - Easter holidays Current Review Queue ==================== TODO [PATCH for-8.1 0/3] Make softmmu/qtest.c target independent Message-Id: <20230411183418.1640500-1-thuth(a)redhat.com> ======================================================================================================================= TODO [QEMU][PATCH v6 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230411224746.16152-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 1 month

1
0
0 0

[ACTIVITY] report week ending 14 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * trying to get a release out of the door -- due among other things to the Easter holiday weekend, rc4 is a bit late and has rather more changes than I would prefer * more triaging of Coverity issues * sent a few trivial bug fix patches * started reviewing and queueing arm patches for 8.1 * investigated a FEAT_SEL2 bug that showed up with some proposed changes to TF-A/Hafnium. The architecture and QEMU's code are pretty hairy in this area but I think I have identified the correct fix... -- PMM

2 years, 1 month

1
0
0 0

LLVM bots down for extended period

by Aaron Ballman

Hello! I noticed that some of the build bots in the LLVM build lab have been down for an extended period of time. I tried emailing the Linaro Toolchain Working Group address as they're listed as the admin for the machine, but I've not heard a response in a week. Renato mentioned you might be a good person to contact instead. The following bot(s) appear to have been down for multiple weeks: https://lab.llvm.org/buildbot/#/builders/clang-armv7-global-isel https://lab.llvm.org/buildbot/#/builders/clang-native-arm-lnt-perf https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vla-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls https://lab.llvm.org/buildbot/#/builders/clang-armv7-vfpv3-full-2stage https://lab.llvm.org/buildbot/#/builders/clang-thumbv7-full-2stage Do you have plans to bring the bots back online? If not, that's okay -- just let me know and I can remove the bots from the lab for you. Thank you! ~Aaron

2 years, 1 month

2
2
0 0

[ACTIVITY] Report for week #14

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Submitted to GDB mailing list and committed patches fixing the gdb.asm/asm-source.exp regression found by the check_gdb job. Turned out to be a small bug in the stabs debug format support. - Committed Gerrit review request disabling Python on MinGW cross builds. [GNU-767] Support changing SVE vector length in remote debugging - Investigating a follow-up question Simon asked during review of the patch series fixing a corner case when reading auxv from multi-threaded inferiors. -- Thiago

2 years, 1 month

1
0
0 0

[ACTIVITY] report week ending 6 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * rc3 this week * reworked my "deprecate the misleading -singlestep option" patchset to deal with review feedback, sent out v2 * KVM Forum programme committee work * investigated a regression where the mps3-an547 board asserts on startup; for 8.0 we will just revert the change that introduced the failure, since it was only an optimization * some triage of Coverity issue reports; sent some patches for some easy ones, queried original code submitter for others -- PMM

2 years, 1 month

1
0
0 0

[TCWG CI] 602.gcc_s fails to run after llvmorg-17-init-4880-gf242291f59bf

by Maxim Kuvyrkov

Hi Alexandros, Linaro benchmarking CI flagged this patch. After it clang seems to miscompile 602.gcc_s from SPEC CPU2017 for "-O3 -flto" on aarch64-linux-gnu. Also, it appears that 600.perlbench_s slows down by 9%. Could you investigate, please? Let me know if you need any assistance in reproducing the problem. Our Benchmarking CI is still in active development, and there are false positives, but this report seems to be legit [1]. Kind regards, [1] https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017speed--llvm-aarch64-ma… -- Maxim Kuvyrkov https://www.linaro.org

2 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #13

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Committed ABE change suggested by Maxim to mention failures that cause additional testsuite runs. - Tried to update Python MinGW build to 3.x, but it's a rabbit hole. Proposing to disable Python support when cross-building GDB with MinGW instead. - First regression detected by the tcwg_gnu_native_check_gdb CI job reported upstream¹. Started investigating it. [GNU-767] Support changing SVE vector length in remote debugging - Created a testcase to exercise the corner case mentioned by Pedro. Found out that GDB is also susceptible to it. Fixed both GDB and gdbserver. Posted patch series upstream². -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/871ql6dhf4.fsf@linaro.org/ ² https://inbox.sourceware.org/gdb-patches/20230331034432.3037148-1-thiago.ba…

2 years, 1 month

1
0
0 0

[ACTIVITY] week ending Apr. 2 2023

by Alex Bennée

Project Orko ============ - more card generation for GPU tasks - started on virtio-gpu blog post - posted [RFC PATCH] tests/avocado: Test Xen guest support under KVM Message-Id: <20230324160719.1790792-1-alex.bennee(a)linaro.org> [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Generic vhost-user-device ([ORKO-19]) ===================================== - got an initial working [branch for generic and rng] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH 00/10] accel/tcg: refactor the cpu-exec loop Message-Id: <20230320101035.2214196-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] more misc fixes for 8.0 (tests, gdbstub, meta, docs) Message-Id: <20230330101141.30199-1-alex.bennee(a)linaro.org> - preparing for next week's GSoC assessments [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Other ===== Absences ======== - Travelling Weds afternoon Current Review Queue ==================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [RFC QEMU PATCH 00/18] Add VirtIO GPU and Passthrough GPU support on Xen Message-Id: <20230312092244.451465-1-ray.huang(a)amd.com> ==================================================================================================================================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 1 month

1
0
0 0

[ACTIVITY] report week ending 31 Mar

by Peter Maydell

Progress (short week, holiday and recovering from covid...): * UM-2 [QEMU upstream maintainership] * 8.0 release related work rumbles on * debugged and fixed a regression caused by my work on HSTR_EL2 traps * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] * implemented FEAT_PAN3 (and fixed a minor bug in syndrome reporting that I noticed in the process) -- PMM

2 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #12

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Enabled gdb.gdb/unittest.exp in fast_check_gdb job. It should be stable now that tcwg-jade-02's kernel has been upgraded. - Enabled bisections for check_gdb jobs. - Implemented Maxim's idea to handle GDB testsuite's tests that can FAIL but are silent when they pass (i.e., the "gdb_test -nopass" statements). [GNU-767] Support changing SVE vector length in remote debugging - Back in February I upstreamed a couple of preparation patches and Pedro noticed an unintended change in behaviour that can affect a corner case, so I am working on a fix for that now. -- Thiago

2 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #11

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Finished implementing ABE's support for rerunning failed tests using Maxim's idea of leveraging validate_failures.py to determine which tests need to be rerun. Submitted v3 and v4 versions, and committed v4. - Investigated why tcwg-abet-tested jobs have been failing in the CI. Found out that Jenkins sets a bogus core.hooksPath in the git repo config. Submitted and merged a gerrit request fixing the problem. - Investigated why cross-build gdbserver needs GMP and MPFR (and is thus failing to build) in tcwg-gnu-build jobs. Submitted Gerrit review request to fix it. - Started looking into why re-enabling GDB testsuite parallelism makes it run fewer tests. -- Thiago

2 years, 1 month

2
2
0 0

[ACTIVITY] report week ending 17 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - went through and made estimates for a pile of JIRA tasks relating to implementing features we're missing to get to ARMv9.4 - diagnosed why --enable-werror wasn't affecting warnings from the kerneldoc docs generator, and sent a patch fixing it - some bug triage, looking for issues that ought to be fixed for 8.0 - fixed a division-by-zero bug in the cadence UART model - fixed a documentation markup mistake that made the docs look odd - investigating/fixing some more CI failures - minor bits of travel/conference related admin -- PMM

2 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #10

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Submitted and merged a couple of review requests removing obsolete CI jobs related to release automation and release regression detection - Finished version of scripts that have most of the logic for rerunning testsuites in ABE. Submitted as a review request. Addressed review comments and submitted v2. - Maxim found out a way to simplify the logic of determining whether a new testsuite run is warranted by using validate_failures.py, which I'm now implementing. -- Thiago

2 years, 2 months

1
0
0 0

[ACTIVITY] week ending Mar. 12 2023

by Alex Bennée

Project Orko ============ - various syncs and lining up for resources [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of sync meetings with various partners and members QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/30] gdbstub refactor for smaller build Message-Id: <20230307212139.883112-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] tweaks and fixes for 8.0-rc1 (tests, plugins, docs) Message-Id: <20230310103123.2118519-1-alex.bennee(a)linaro.org> - posted [PULL 0/5] gitdm updates Message-Id: <20230310155726.2222233-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/10] gitdm metadata updates Message-Id: <20230310180332.2274827-1-alex.bennee(a)linaro.org> - posted [kvm-unit-tests PATCH v10 0/7] MTTCG sanity tests for ARM Message-Id: <20230307112845.452053-1-alex.bennee(a)linaro.org> - various GSoC and Outreachy wranglings Completed Reviews [6/6] ======================= [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> [PATCH] plugin: fix clearing of plugin_mem_cbs before TB exit Message-Id: <20230222043204.941336-1-cota(a)braap.org> [PATCH 0/8] Inter-plugin interactions with QPP Message-Id: <20221213213757.4123265-1-fasano(a)mit.edu> [PATCH v4.5 00/29] gdbstub/next: re-organise and split build Message-Id: <20230303025805.625589-1-richard.henderson(a)linaro.org> [PATCH 0/3] softfloat: FloatRelation cleanups Message-Id: <20220401132240.79730-1-richard.henderson(a)linaro.org> [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Absences ======== - Away on Tuesday Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [RFC PATCH] hw: arm: Support direct boot for Linux/arm64 EFI zboot images Message-Id: <20230223105308.559632-1-ardb(a)kernel.org> =================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 2 months

1
0
0 0

[ACTIVITY] report week ending Mar 10

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Softfreeze was this Tuesday; lots of wrangling of pull requests - Code review; last arm pullreq before softfreeze - various admin type bits and pieces -- PMM

2 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #9

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Moved most of logic to rerun failed tests from tcwg_gnu-build.sh to Abe and a new script based on the sum file parser of compare_dg_tests.pl. The new script creates a "merged" sum file from all the runs. Currently changing Abe to make use of it. - Did a few cleanups in compare_dg_tests.pl as I was going through its code. Also added KFAIL status support to it, which the GDB testsuite needs. - Removed a few obsolete CI jobs which came out of the woodwork when I merged the compare_dg_tests.pl cleanups. -- Thiago

2 years, 2 months

1
0
0 0

[ACTIVITY] week ending Mar. 5 2023

by Alex Bennée

Project Orko ============ - did [launch presentation] for SOAFEE and LEDGE SC [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of planning for FEAT_GCS, see [QEMU-517] and related - spoke to Lauterbach on behalf of QC, gave pointers on debug [QEMU-517] <https://linaro.atlassian.net/browse/QEMU-517> FEAT_RME, CCA Realms ([QEMU-466]) ================================= - did a bit of review of rth's precursor patches [QEMU-466] <https://linaro.atlassian.net/browse/QEMU-466> QEMU Upstream Work ([UM-2]) =========================== - finished up [MR for using locally built QEMU in TuxRun] - posted [PATCH v4 00/26] gdbstub/next: re-organise and split build Message-Id: <20230302190846.2593720-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/24] testing updates (gitlab, cirrus, docker, avocado, windows) Message-Id: <20230301151604.1948813-1-alex.bennee(a)linaro.org> - these help address the CI minutes we are burning through monthly now [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [MR for using locally built QEMU in TuxRun] <https://gitlab.com/Linaro/tuxrun/-/merge_requests/179> Completed Reviews [6/6] ======================= [PATCH v2 0/4] Fix deadlock when dying because of a signal Message-Id: <20230213125238.331881-1-iii(a)linux.ibm.com> [PATCH 0/8] hw/arm: Cleanups around QOM style Message-Id: <20230220115114.25237-1-philmd(a)linaro.org> [PATCH v2 00/24] hw/ide: QOM/QDev housekeeping Message-Id: <20230220091358.17038-1-philmd(a)linaro.org> [PATCH v2] gdbstub: move update guest debug to accel ops Message-Id: <20230207131721.49233-1-mads(a)ynddal.dk> [PATCH 0/5] iotests: make meson aware of individual I/O tests Message-Id: <20230302184606.418541-1-berrange(a)redhat.com> [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> Other ===== Absences ======== Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [PATCH v2 00/28] tcg: Simplify temporary usage Message-Id: <20230222232715.15034-1-richard.henderson(a)linaro.org> ==================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 2 months

1
0
0 0

[TCWG CI] Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3240-g02828abd0845 commit for tcwg_aosp-code_size-surfaceflinger: commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC * oriole-master ** Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c cd investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC --- .../Transforms/InstCombine/vec_demanded_elts.ll | 317 ++++++++++++++++++++- 1 file changed, 313 insertions(+), 4 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll index e18865f9b95f..0f33eb58f080 100644 --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -2,6 +2,9 @@ ; RUN: opt < %s -passes=instcombine -S | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +declare void @use(<2 x i4>) +declare void @use_fp(<2 x float>) + define i32 @test2(float %f) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[T5:%.*]] = fmul float [[F:%.*]], [[F]] @@ -76,8 +79,8 @@ define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind { define <2 x float> @test_fptrunc(double %f) { ; CHECK-LABEL: @test_fptrunc( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> +; CHECK-NEXT: ret <2 x float> [[RET]] ; %t9 = insertelement <4 x double> undef, double %f, i32 0 %t10 = insertelement <4 x double> %t9, double 0.000000e+00, i32 1 @@ -91,8 +94,8 @@ define <2 x float> @test_fptrunc(double %f) { define <2 x double> @test_fpext(float %f) { ; CHECK-LABEL: @test_fpext( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> -; CHECK-NEXT: ret <2 x double> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> +; CHECK-NEXT: ret <2 x double> [[RET]] ; %t9 = insertelement <4 x float> undef, float %f, i32 0 %t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1 @@ -842,3 +845,309 @@ define <8 x i4> @ins_of_ext_undef_elts_propagation2(<8 x i4> %v, <8 x i4> %v2, i %i21 = shufflevector <8 x i4> %i20, <8 x i4> %v, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> ret <8 x i4> %i21 } + +define void @common_binop_demand_via_splat_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op1(<2 x i4> %p, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = mul <2 x i4> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_X_YSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_x_yshuf = mul <2 x i4> %x, %yshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_x_yshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 1, i4 2>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 1, i4 2>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %y, %xshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %yshuf, %x + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define i4 @common_binop_demand_via_extelt_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define float @common_binop_demand_via_extelt_op1(<2 x float> %p, <2 x float> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = fdiv <2 x float> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fdiv <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_X_YSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x float> %y, <2 x float> poison, <2 x i32> zeroinitializer + %b_x_yshuf = fdiv <2 x float> %x, %yshuf + %b_xy = fdiv <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_x_yshuf) + ret float %b_xy0 +} + +define float @common_binop_demand_via_extelt_op0_commute(<2 x float> %p, <2 x float> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_commute( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = fsub <2 x float> <float 3.000000e+00, float 2.000000e+00>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = fmul nnan <2 x float> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fmul ninf <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %y = fsub <2 x float> <float 3.0, float 2.0>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer + %b_y_xshuf = fmul nnan <2 x float> %y, %xshuf + %b_xy = fmul ninf <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_y_xshuf) + ret float %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = or <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = or <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = or <2 x i4> %yshuf, %x + %b_xy = or <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = xor <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = xor <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = xor <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = xor <2 x i4> %xshuf, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = mul <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> <i32 1, i32 1> +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> <i32 1, i32 1> + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt1( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 1 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 1 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} </cut>

2 years, 2 months

1
0
0 0

[TCWG CI] Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3239-g025952b00e0d commit for tcwg_aosp-code_size-surfaceflinger: commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this * oriole-master ** Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a cd investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this --- llvm/test/CodeGen/X86/bitselect.ll | 202 +++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/llvm/test/CodeGen/X86/bitselect.ll b/llvm/test/CodeGen/X86/bitselect.ll new file mode 100644 index 000000000000..5f1f6bd83a9a --- /dev/null +++ b/llvm/test/CodeGen/X86/bitselect.ll @@ -0,0 +1,202 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-bmi | FileCheck %s --check-prefixes=X64,X64-NOBMI +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefixes=X64,X64-BMI + +; PR46472 +; bitselect(a,b,m) == or(and(a,not(m)),and(b,m)) +; bitselect(a,b,m) == xor(and(xor(a,b),m),a) + +define i8 @bitselect_i8(i8 %a, i8 %b, i8 %m) nounwind { +; X86-LABEL: bitselect_i8: +; X86: # %bb.0: +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorb %cl, %al +; X86-NEXT: andb {{[0-9]+}}(%esp), %al +; X86-NEXT: xorb %cl, %al +; X86-NEXT: retl +; +; X64-LABEL: bitselect_i8: +; X64: # %bb.0: +; X64-NEXT: andl %edx, %esi +; X64-NEXT: movl %edx, %eax +; X64-NEXT: notb %al +; X64-NEXT: andb %dil, %al +; X64-NEXT: orb %sil, %al +; X64-NEXT: retq + %not = xor i8 %m, -1 + %ma = and i8 %a, %not + %mb = and i8 %b, %m + %or = or i8 %ma, %mb + ret i8 %or +} + +define i16 @bitselect_i16(i16 %a, i16 %b, i16 %m) nounwind { +; X86-LABEL: bitselect_i16: +; X86: # %bb.0: +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorw %ax, %cx +; X86-NEXT: andw {{[0-9]+}}(%esp), %cx +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %eax +; X64-NOBMI-NEXT: andl %edx, %esi +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: orl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq + %not = xor i16 %m, -1 + %ma = and i16 %a, %not + %mb = and i16 %b, %m + %or = or i16 %ma, %mb + ret i16 %or +} + +define i32 @bitselect_i32(i32 %a, i32 %b, i32 %m) nounwind { +; X86-LABEL: bitselect_i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: andl %edx, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: retq + %not = xor i32 %m, -1 + %ma = and i32 %a, %not + %mb = and i32 %b, %m + %or = or i32 %ma, %mb + ret i32 %or +} + +define i64 @bitselect_i64(i64 %a, i64 %b, i64 %m) nounwind { +; X86-LABEL: bitselect_i64: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: popl %esi +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rdi, %rdx, %rax +; X64-BMI-NEXT: andq %rdx, %rsi +; X64-BMI-NEXT: orq %rsi, %rax +; X64-BMI-NEXT: retq + %not = xor i64 %m, -1 + %ma = and i64 %a, %not + %mb = and i64 %b, %m + %or = or i64 %ma, %mb + ret i64 %or +} + +define i128 @bitselect_i128(i128 %a, i128 %b, i128 %m) nounwind { +; X86-LABEL: bitselect_i128: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: andl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: andl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl %esi, 12(%eax) +; X86-NEXT: movl %ebx, 8(%eax) +; X86-NEXT: movl %edi, 4(%eax) +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl $4 +; +; X64-NOBMI-LABEL: bitselect_i128: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %r8, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: andq %r9, %rcx +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: movq %rcx, %rdx +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i128: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rsi, %r9, %rsi +; X64-BMI-NEXT: andnq %rdi, %r8, %rax +; X64-BMI-NEXT: andq %r9, %rcx +; X64-BMI-NEXT: orq %rcx, %rsi +; X64-BMI-NEXT: andq %r8, %rdx +; X64-BMI-NEXT: orq %rdx, %rax +; X64-BMI-NEXT: movq %rsi, %rdx +; X64-BMI-NEXT: retq + %not = xor i128 %m, -1 + %ma = and i128 %a, %not + %mb = and i128 %b, %m + %or = or i128 %ma, %mb + ret i128 %or +} </cut>

2 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #8

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilize GDB testsuite results in the CI - Cleaned up change in tcwg_gnu-build.sh that reruns failed tests and created Gerrit review request¹. - Based on Laurent's and Maxim's suggestions, decided to put the code which retries the failed tests in Abe, so now I'm working on that. -- Thiago ¹ https://review.linaro.org/c/toolchain/jenkins-scripts/+/43265

2 years, 2 months

1
0
0 0

[ACTIVITY] report week ending 24 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review: big FEAT_LSE2 support series, 8.3 pointer auth, gdbstub support for M-profile sysregs, another round of FEAT_RME, and more - discussions about how to handle the fact that QEMU has run out of gitlab CI minutes, and some tweaking of my scripts to work around the lack of minutes -- PMM

2 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #7

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilize GDB testsuite results in the CI - Merged Gerrit review requests removing unsupported and flaky tests from the fast_check_gdb CI job, and also one that makes it flag regressions in the stable tests. - Implemented change in Abe to build glibc with SystemTap probes enabled, but there's a kludge I still need to cleanup before submitting it for review. - Working on change to tcwg_gnu-build.sh to make it run failed tests again to see if they change to passing status. I have a working prototype. Now running further tests and cleaning up the code. -- Thiago

2 years, 2 months

1
0
0 0

Re: Seeking toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi

by Maxim Kuvyrkov

Hi Bryan, > On Feb 7, 2023, at 9:13 PM, Bryan Phillippe <bp(a)darkforest.org> wrote: > ... > -rwxr-xr-x 1 config root 2765178 Dec 9 2018 /lib/libuClibc-1.0.14.so > /root # strings /lib/libuClibc-1.0.14.so |grep -i linaro|head -n 1 > GCC: (OpenWrt/Linaro GCC 4.8-2014.04 r35193) 4.8.3 This indicates that it was built with an OpenWRT toolchain, and OpenWRT project maintainers used Linaro GCC 4.8 source release, instead of FSF GCC 4.8 source release. In the days of GCC 4.8 it was very common to use Linaro GCC source release instead of FSF ones for building compilers for 32-bit and 64-bit ARM. Try searching in OpenWRT archives for a copy of GCC 4.8-based toolchain. > /root # strings /lib/libuClibc-1.0.14.so |grep -i gcc-4.8|head -n 1 > /home/test/work/sudhan-qsdk/qsdk/build_dir/toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi/uClibc-ng-1.0.14 > /root # > > I only need to rebuild a single binary on this platform, and I don't have the source or the toolchain for the existing binaries. If I have to recreate a toolchain based on the versions only, it should be possible, but will be a good deal of work and effort. If you know where I can find this toolchain - or have any advice on how I can build my own compatible version - I would be very grateful. If you want to rebuild a single executable, then it may be easier to use a modern toolchain for arm-linux-gnueabihf [1] and build the static binary of your package (add "-static" to compiler flags). This was the binary will include all necessary bits of system libraries. This is a good approach if your package does not have dependencies outside of C library; otherwise you would need to find static versions of all other libraries. -- Maxim Kuvyrkov https://www.linaro.org > > Thank you so much! > > -- > -bp > >> On Feb 7, 2023, at 04:24, Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> wrote: >> >> [CC: linaro-toolchain@] >> >> Hi Bryan, >> >> I don't think that Linaro has ever released a toolchain with uClibc, but I may be wrong. Could you provide additional information about the target, rootfs and your setup? >> >> -- >> Maxim Kuvyrkov >> https://www.linaro.org >> >> >> >> >>> On Feb 7, 2023, at 10:31 AM, Bryan Phillippe <bp(a)darkforest.org> wrote: >>> >>> >>> Hello! I know this is a long shot, but I have a few devices with code that was built using this toolchain: toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi >>> >>> I'm trying to find a copy of that so I can rebuild 1 binary/package on the system without blowing everything up. Do you have any idea where I can find this toolchain? Thank you so much in advance! >>> >>> -- >>> -bp >>> >> >

2 years, 2 months

1
0
0 0

Clang C++ linkage problem

by Bartosz Golaszewski

Hey! I'm the author and maintainer of libgpiod. I'm currently getting ready to do a new major release. After giving some exposure to the release candidate, I noticed that when using clang, I can't link against the C++ bindings, while it works just fine in GCC. The tree in question is here: https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/log/ You can trigger the linking program by trying to build the C++ tests with clang like that: CC=clang CXX=clang++ ./autogen.sh --enable-bindings-cxx --enable-tests && make -j16 You'll get the following error: /usr/bin/ld: tests-chip.o:(.data+0x0): undefined reference to `typeinfo for gpiod::chip_closed' /usr/bin/ld: tests-line-request.o:(.data+0x0): undefined reference to `typeinfo for gpiod::request_released' /usr/bin/ld: .libs/gpiod-cxx-test: hidden symbol `_ZTIN5gpiod11chip_closedE' isn't defined /usr/bin/ld: final link failed: bad value The typoinfo is missing for exception types that should be visible to users of the library. The culprit is here: https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/tree/bindings/cxx… I added the GPIOD_CXX_BUILD macro in order to not re-export the visible symbols if any user of the library would include the gpiod.hpp header. When the library is being built, the symbols are visible, when someone includes the header, the symbols are hidden. If I make the symbols unconditionally visible here, clang starts to work but I have no idea why and would like to avoid re-exporting the symbols if I can. I'm using the following version: Ubuntu clang version 15.0.6 Target: x86_64-pc-linux-gnu Thread model: posix InstalledDir: /usr/bin Host is: x86_64 GNU/Linux It's not like gcc links fine but then fails to obtain typeid - I can catch exceptions coming out from libgpiod just fine in external apps linked using gcc and see their type. Any hints? Thanks Bart

2 years, 3 months

2
12
0 0

[ACTIVITY] Report for week #6

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued addressing review comments on v3 of the patches. Implemented some of the suggestions in my local branch, and also engaged in discussions. # [GNU-796] Stabilize GDB testsuite results in the CI - Fixed the problem in tcwg_gnu-build.sh noticed by Maxim where no_regression_p ignored regressions in the fast_check_gdb CI job. - Removed gdb.gdb/unittest.exp and gdb.server/unittest.exp from the fast_check_gdb stable tests list. The former only temporarily while its flakiness isn't fixed, and the latter because we don't run remote CI jobs. - Found out why gdb.base/break-probes.exp is unsupported in the fast_check_gdb CI job: we don't build glibc with SystemTap static probes. I have local changes to add them — and which do fix the GDB test — but I need to clean them up a bit before pushing them. -- Thiago

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 10 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review. In particular: reviewed RTH's FEAT_RME series - Wrote and sent an RFC patchset proposing renaming of the badly misnamed '-singlestep' command line option (it actually does "put only one guest instruction in each JIT basic block") -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 12 2023

by Alex Bennée

Project Stratos =============== - more prep work for Project Orko FEAT_RME, CCA Realms ([QEMU-466]) ================================= - sync up meeting with Huawei - see QEMU, FEAT_RME/CCA and next steps Message-Id: <87mt5ln2t6.fsf(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> - continued working on [testing/next] with tuxrun tests - hacked up [PoC to use local QEMU in TuxRun] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [PoC to use local QEMU in TuxRun] <https://gitlab.com/stsquad/tuxrun/-/commit/0f9711c18b7e723e1c50c8a8fd116b93…> Completed Reviews [3/3] ======================= [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> [PATCH] gdbstub: move update guest debug to accel ops Message-Id: <20221123121712.72817-1-mads(a)ynddal.dk> [PATCH v2 0/3] Add gdbstub support to HVF Message-Id: <20221116174749.65175-1-fcagnin(a)quarkslab.com> Current Review Queue ==================== TODO [PATCH 00/22] target/arm: Implement FEAT_RME Message-Id: <20230124000027.3565716-1-richard.henderson(a)linaro.org> ==================================================================================================================== TODO [RFC PATCH 00/16] Add stage-2 translation for SMMUv3 Message-Id: <20230205094411.793816-1-smostafa(a)google.com> ================================================================================================================== TODO [PATCH v2 0/2] fix for #285 Message-Id: <20230205163758.416992-1-cota(a)braap.org> ==================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

Re: Seeking toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi

by Maxim Kuvyrkov

[CC: linaro-toolchain@] Hi Bryan, I don't think that Linaro has ever released a toolchain with uClibc, but I may be wrong. Could you provide additional information about the target, rootfs and your setup? -- Maxim Kuvyrkov https://www.linaro.org > On Feb 7, 2023, at 10:31 AM, Bryan Phillippe <bp(a)darkforest.org> wrote: > > > Hello! I know this is a long shot, but I have a few devices with code that was built using this toolchain: toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi > > I'm trying to find a copy of that so I can rebuild 1 binary/package on the system without blowing everything up. Do you have any idea where I can find this toolchain? Thank you so much in advance! > > -- > -bp >

2 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #5

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - The patches were already reviewed by 3 maintainers, so started addressing their review comments and answering questions. - Committed first two patches in the series, which were self-contained code improvements. -- Thiago

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 5 2023

by Alex Bennée

Project Stratos =============== - posted [PATCH v2] backends/vhost-user: remove the ioeventfd check Message-Id: <20230130124728.175610-1-alex.bennee(a)linaro.org> - bunch of sync and planning for Project Orko - see Project Orko requirements from TRS Message-Id: <87sffmke2i.fsf(a)linaro.org> - also debugging some TRS <-> QEMU interactions - posted [RFC PATCH] target/arm: disable FEAT_SME if we turn off SVE Message-Id: <20230203100551.2445547-1-alex.bennee(a)linaro.org> [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL v2 00/36] Testing, docs, semihosting and plugin updates Message-Id: <20230202160109.2061994-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> Other ===== - Did some investigation into LKFT regressions - posted Initial investigation of slowness kselftest job Message-Id: <1ba91912e18492c7dafedc5fbd5aef817f109d53fdc95554870edf077a6e21dc(a)mu.id> - posted Candidate patches for Debian's 7.2 release (and backports) Message-Id: <87edr8kqqq.fsf(a)linaro.org> Completed Reviews [4/4] ======================= [PATCH v6 00/36] tcg: Support for Int128 with helpers Message-Id: <20230130214844.1158612-1-richard.henderson(a)linaro.org> [PATCH] vhost-user-gpio: Configure vhost_dev when connecting Message-Id: <20230130140320.77999-1-akihiko.odaki(a)daynix.com> [PATCH] configure: Bump minimum Clang version to 10.0 Message-Id: <20230131180239.1582302-1-thuth(a)redhat.com> [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> Current Review Queue ==================== TODO [PATCH 0/4] Fix deadlock when dying because of a signal Message-Id: <20230201004609.3005029-1-iii(a)linux.ibm.com> ==================================================================================================================== TODO [RFC PATCH v1 0/8] Look Ma! We made a XenStore Message-Id: <20230201144358.1744876-1-dwmw2(a)infradead.org> ============================================================================================================= TODO [QEMU][PATCH v5 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230131225149.14764-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 3 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks - the CI/tests have got rather flaky of late: trying to find out why... * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT: is now upstream -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #4

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued preparing patches for upstream submission. Did some final code and testcase cleanups, updated/rewrote patch descriptions, wrote the cover letter and the list of changes from v2. - Posted the patches upstream¹. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20230130044518.3322695-1-thiago.ba…

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Jan. 29 2023

by Alex Bennée

Project Stratos =============== - reading up on the linux-mm subsystem - learning about struct vma_area [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> FEAT_RME, CCA Realms ([QEMU-466]) ================================= - more review of [PATCH v5 00/36] tcg: Support for Int128 with helpers Message-Id: <20230126043824.54819-1-richard.henderson(a)linaro.org> [QEMU-466] <https://linaro.atlassian.net/browse/QEMU-466> QEMU Upstream Work ([UM-2]) =========================== - updated maintainer trees, running [CI over weekend] - posted [PULL 00/35] Testing, docs, semihosting and plugin updates Message-Id: <20230126112250.2584701-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> [CI over weekend] <https://gitlab.com/stsquad/qemu/-/pipelines/753447926> Current Review Queue ==================== TODO [RFC PATCH 00/16] arm: Run Arm CCA VMs with KVM Message-Id: <20230127150727.612594-1-jean-philippe(a)linaro.org> ================================================================================================================== TODO [QEMU][PATCH v4 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230125085407.7144-1-vikram.garhwal(a)amd.com> =================================================================================================================================== TODO [PATCH v3 0/3] tcg: add perfmap and jitdump Message-Id: <20230111014705.2275040-1-iii(a)linux.ibm.com> ======================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 27 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT: finished coding, did some testing, sent patches for review -- PMM

2 years, 3 months

1
0
0 0

[TCWG CI] [TCWG CI] 465.tonto failed to build after gdb-13-branchpoint-527-g46758593515: Rename to allow_ifunc_tests

by ci_notify＠linaro.org

After gdb-13-branchpoint-527-g46758593515 commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Rename to allow_ifunc_tests the following benchmarks slowed down by more than 3%: - 465.tonto failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of gdb-13-branchpoint-527-g46758593515 commit for tcwg_bmk-code_speed-spec2k6: commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Date: Sun Jan 8 11:41:19 2023 -0700 Rename to allow_ifunc_tests This changes skip_ifunc_tests to invert the sense, and renames it to allow_ifunc_tests. * gnu-aarch64-master-O3 ** After gdb-13-branchpoint-527-g46758593515 commit 4675859351582f017b495ff13fb2ea72a99834af ** Author: Tom Tromey <tom(a)tromey.com> ** ** Rename to allow_ifunc_tests ** ** the following benchmarks slowed down by more than 3%: ** - 465.tonto failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Reproduce current build: <cut> mkdir -p investigate-binutils-4675859351582f017b495ff13fb2ea72a99834af cd investigate-binutils-4675859351582f017b495ff13fb2ea72a99834af # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Date: Sun Jan 8 11:41:19 2023 -0700 Rename to allow_ifunc_tests This changes skip_ifunc_tests to invert the sense, and renames it to allow_ifunc_tests. --- gdb/testsuite/gdb.base/gnu-ifunc.exp | 2 +- gdb/testsuite/gdb.compile/compile-ifunc.exp | 2 +- gdb/testsuite/lib/gdb.exp | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gdb/testsuite/gdb.base/gnu-ifunc.exp b/gdb/testsuite/gdb.base/gnu-ifunc.exp index 967d1e053e7..81119f764b8 100644 --- a/gdb/testsuite/gdb.base/gnu-ifunc.exp +++ b/gdb/testsuite/gdb.base/gnu-ifunc.exp @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. -require !skip_shlib_tests !skip_ifunc_tests +require !skip_shlib_tests allow_ifunc_tests standard_testfile .c set staticexecutable ${testfile}-static diff --git a/gdb/testsuite/gdb.compile/compile-ifunc.exp b/gdb/testsuite/gdb.compile/compile-ifunc.exp index bfbe65a503b..990d35a53f6 100644 --- a/gdb/testsuite/gdb.compile/compile-ifunc.exp +++ b/gdb/testsuite/gdb.compile/compile-ifunc.exp @@ -15,7 +15,7 @@ load_lib compile-support.exp -require !skip_ifunc_tests +require allow_ifunc_tests standard_testfile diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index 7143908bbc2..3a1936ffc82 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -3972,17 +3972,17 @@ gdb_caching_proc has_int128_cxx { return [gdb_int128_helper c++] } -# Return true if the IFUNC feature is unsupported. -gdb_caching_proc skip_ifunc_tests { +# Return true if the IFUNC feature is supported. +gdb_caching_proc allow_ifunc_tests { if [gdb_can_simple_compile ifunc { extern void f_ (); typedef void F (void); F* g (void) { return &f_; } void f () __attribute__ ((ifunc ("g"))); } object] { - return 0 - } else { return 1 + } else { + return 0 } } </cut>

2 years, 3 months

3
3
0 0

[ACTIVITY] Report for week #3

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued preparing patches for upstream submission. Realised I had to document my changes to the remote protocol in the GDB manual, so did that. Also making small code cleanups and updating/rewriting patch descriptions. - Noticed I could to a small optimisation in one patch, but it would involve a lot of refactoring to move GDB-specific code so that it could also be used by gdbserver, so saved the WIP branch for later. # TCWG CI - Investigated failure report from yesterday's email. Reproduced on tcwg-jade-03 with a slightly different build failure, but wasn't able to make much progress¹. -- Thiago ¹ https://lists.linaro.org/archives/list/linaro-toolchain@lists.linaro.org/th…

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 20 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT getting closer towards being done: I just have to mark up the ARMCPRegInfo structs for HDFGRTR traps, and write the code to handle traps on ERET and SVC -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Jan. 22 2023

by Alex Bennée

Project Stratos =============== - finished draft of [proposal for Unprivilaged VirtIO API] - sent out for comment [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - a few version bump reviews [UM-196] <https://linaro.atlassian.net/browse/UM-196> Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> - posted [PATCH 00/18] testing/next updates (gitlab, docker, check-tcg) Message-Id: <20230119180419.30304-1-alex.bennee(a)linaro.org> - updated maintainer trees, running [CI over weekend] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [CI over weekend] <https://gitlab.com/stsquad/qemu/-/pipelines/753447926> Completed Reviews [7/7] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> [PATCH v2 00/22] tcg: exit_tb tidy, goto_tb reorg Message-Id: <20230109014248.2894281-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] Fix win32/msys2 shader compilation & update lcitool deps Message-Id: <20230110080246.536056-1-marcandre.lureau(a)redhat.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [PATCH 0/3] various aarch64 fixes for running Hyper-V on TCG Message-Id: <20230105221251.17896-1-eiakovlev(a)linux.microsoft.com> =================================================================================================================================== TODO [PATCH 0/4] tsan fixes Message-Id: <20230108163905.59601-1-cota(a)braap.org> ============================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

[TCWG CI] [TCWG CI] 481.wrf failed to build after gdb-13-branchpoint-388-g71fa8692930: sim: cris: move arch-specific file compilation to top-level

by ci_notify＠linaro.org

After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> sim: cris: move arch-specific file compilation to top-level the following benchmarks slowed down by more than 3%: - 481.wrf failed to build - 416.gamess failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of gdb-13-branchpoint-388-g71fa8692930 commit for tcwg_bmk-code_speed-spec2k6: commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level * gnu-arm-master-O3_LTO ** After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 ** Author: Mike Frysinger <vapier(a)gentoo.org> ** ** sim: cris: move arch-specific file compilation to top-level ** ** the following benchmarks slowed down by more than 3%: ** - 481.wrf failed to build ** - 416.gamess failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Reproduce current build: <cut> mkdir -p investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 cd investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level --- sim/Makefile.in | 3 --- sim/cris/local.mk | 3 --- 2 files changed, 6 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 435c36b2b83..0ad692126e7 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -4801,9 +4801,6 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@ @SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h -@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: cris/%.c -@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - @SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c @SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS) diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 912ca12a32f..3950baed7a1 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -47,9 +47,6 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h noinst_LIBRARIES += %D%/libsim.a -%D%/%.o: %D%/%.c - $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - %D%/%.o: common/%.c $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) </cut>

2 years, 3 months

1
0
0 0

[TCWG CI] [TCWG CI] 459.GemsFDTD failed to build after glibc-2.36.9000-435-g569cfcc6bf: hurd: Fix _NOFLSH value

by ci_notify＠linaro.org

After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> hurd: Fix _NOFLSH value the following benchmarks slowed down by more than 3%: - 459.GemsFDTD failed to build - 436.cactusADM failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. For your convenience, we have uploaded tarballs with pre-processed source and assembly files at: - First_bad save-temps: $FIRST_BAD_ARTIFACTS/save-temps/ - Last_good save-temps: $LAST_GOOD_ARTIFACTS/save-temps/ - Baseline save-temps: $BASELINE_ARTIFACTS/save-temps/ Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of glibc-2.36.9000-435-g569cfcc6bf commit for tcwg_bmk-code_speed-spec2k6: commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). * gnu-aarch64-master-O3_LTO ** After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 ** Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> ** ** hurd: Fix _NOFLSH value ** ** the following benchmarks slowed down by more than 3%: ** - 459.GemsFDTD failed to build ** - 436.cactusADM failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Reproduce current build: <cut> mkdir -p investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 cd investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). --- bits/termios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bits/termios.h b/bits/termios.h index ae62d00853..4439c2f14e 100644 --- a/bits/termios.h +++ b/bits/termios.h @@ -246,7 +246,7 @@ struct termios # define NOKERNINFO (1 << 25) /* Disable VSTATUS. */ # define PENDIN (1 << 29) /* Retype pending input (state). */ #endif -#define _NOFLSH (1 << 31) /* Disable flush after interrupt. */ +#define _NOFLSH (1U << 31) /* Disable flush after interrupt. */ #define NOFLSH _NOFLSH /* Control characters. */ </cut>

2 years, 3 months

1
0
0 0

[TCWG CI] [TCWG CI] 521.wrf_r slowed down by 5% after basepoints/gcc-13-5062-gcb93c5f8008: Subject: [committed, pushed, Modula2] Added missing dependency.

by ci_notify＠linaro.org

[Error replacing 'FILE' - Error processing tokens]

2 years, 4 months

1
0
0 0

[TCWG CI] [TCWG CI] 445.gobmk slowed down by 6% after llvmorg-16-init-16383-g9b5f62685ab4: [SLP]Fix cost of the broadcast buildvector/gather.

by ci_notify＠linaro.org

After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> [SLP]Fix cost of the broadcast buildvector/gather. the following benchmarks slowed down by more than 3%: - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-16-init-16383-g9b5f62685ab4 commit for tcwg_bmk-code_speed-spec2k6: commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 * llvm-arm-master-O3_LTO ** After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b ** Author: Alexey Bataev <a.bataev(a)outlook.com> ** ** [SLP]Fix cost of the broadcast buildvector/gather. ** ** the following benchmarks slowed down by more than 3%: ** - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Reproduce current build: <cut> mkdir -p investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b cd investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 --- llvm/include/llvm/Analysis/TargetTransformInfo.h | 12 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 4 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 54 +-- llvm/lib/Analysis/TargetTransformInfo.cpp | 8 +- .../Target/AArch64/AArch64TargetTransformInfo.cpp | 7 +- .../Target/AArch64/AArch64TargetTransformInfo.h | 4 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 4 +- .../Target/Hexagon/HexagonTargetTransformInfo.cpp | 6 +- .../Target/Hexagon/HexagonTargetTransformInfo.h | 4 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 9 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 4 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 7 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 5 +- .../Target/SystemZ/SystemZTargetTransformInfo.h | 4 +- .../WebAssembly/WebAssemblyTargetTransformInfo.cpp | 5 +- .../WebAssembly/WebAssemblyTargetTransformInfo.h | 4 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 42 ++- llvm/lib/Target/X86/X86TargetTransformInfo.h | 4 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 21 +- .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll | 2 +- llvm/test/Analysis/CostModel/X86/loop_v2.ll | 2 +- .../X86/masked-intrinsic-cost-inseltpoison.ll | 4 +- .../CostModel/X86/masked-intrinsic-cost.ll | 4 +- .../CostModel/X86/vector-insert-inseltpoison.ll | 120 +++---- llvm/test/Analysis/CostModel/X86/vector-insert.ll | 120 +++---- .../Analysis/CostModel/X86/vshift-ashr-codesize.ll | 50 +-- .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-latency.ll | 18 +- .../CostModel/X86/vshift-ashr-sizelatency.ll | 50 +-- .../Analysis/CostModel/X86/vshift-lshr-codesize.ll | 82 +---- .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-latency.ll | 102 ++---- .../CostModel/X86/vshift-lshr-sizelatency.ll | 82 +---- .../Analysis/CostModel/X86/vshift-shl-codesize.ll | 82 +---- .../CostModel/X86/vshift-shl-cost-inseltpoison.ll | 138 ++----- .../test/Analysis/CostModel/X86/vshift-shl-cost.ll | 138 ++----- .../Analysis/CostModel/X86/vshift-shl-latency.ll | 102 ++---- .../CostModel/X86/vshift-shl-sizelatency.ll | 174 ++------- llvm/test/Transforms/SLPVectorizer/X86/cse.ll | 7 +- .../Transforms/SLPVectorizer/X86/malformed_phis.ll | 140 ++++---- .../X86/remark_gather-load-redux-cost.ll | 2 +- .../SLPVectorizer/X86/used-reduced-op.ll | 399 +++++++++++---------- 50 files changed, 941 insertions(+), 1522 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 6200af73842c..a9cb8717ffa8 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1193,7 +1193,8 @@ public: /// case is to provision the cost of vectorization/scalarization in /// vectorizer passes. InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index = -1) const; + unsigned Index = -1, Value *Op0 = nullptr, + Value *Op1 = nullptr) const; /// \return The expected cost of vector Insert and Extract. /// This is used when instruction is available, and implementation @@ -1786,7 +1787,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I) = 0; virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) = 0; + unsigned Index, Value *Op0, + Value *Op1) = 0; virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) = 0; @@ -2358,9 +2360,9 @@ public: const Instruction *I) override { return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) override { - return Impl.getVectorInstrCost(Opcode, Val, Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) override { + return Impl.getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) override { diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index e81e430f6624..262b42a05d99 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -585,8 +585,8 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) const { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) const { return 1; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index aabb94d82c4b..f27c6899d757 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -90,10 +90,12 @@ private: InstructionCost Cost = 0; // Broadcast cost is equal to the cost of extracting the zero'th element // plus the cost of inserting it into every element of the result vector. - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0, + nullptr, nullptr); for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -110,8 +112,10 @@ private: // vector and finally index 3 of second vector and insert them at index // <0,1,2,3> of result vector. for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -134,9 +138,9 @@ private: // type. for (int i = 0; i != NumSubElts; ++i) { Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, - i + Index); - Cost += - thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i); + i + Index, nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i, + nullptr, nullptr); } return Cost; } @@ -158,10 +162,10 @@ private: // the source type plus the cost of inserting them into the result vector // type. for (int i = 0; i != NumSubElts; ++i) { - Cost += - thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, + i, nullptr, nullptr); Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, - i + Index); + i + Index, nullptr, nullptr); } return Cost; } @@ -212,7 +216,7 @@ private: FixedVectorType::get( PointerType::get(VT->getElementType(), 0), VT->getNumElements()), - -1) + -1, nullptr, nullptr) : 0; InstructionCost LoadCost = VT->getNumElements() * @@ -237,7 +241,7 @@ private: Instruction::ExtractElement, FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VT->getNumElements()), - -1) + + -1, nullptr, nullptr) + getCFInstrCost(Instruction::Br, CostKind) + getCFInstrCost(Instruction::PHI, CostKind)); } @@ -722,9 +726,11 @@ public: if (!DemandedElts[i]) continue; if (Insert) - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i, + nullptr, nullptr); if (Extract) - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i, + nullptr, nullptr); } return Cost; @@ -1123,7 +1129,7 @@ public: InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) { return thisT()->getVectorInstrCost(Instruction::ExtractElement, VecTy, - Index) + + Index, nullptr, nullptr) + thisT()->getCastInstrCost(Opcode, Dst, VecTy->getElementType(), TTI::CastContextHint::None, TTI::TCK_RecipThroughput); @@ -1184,14 +1190,20 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) { return getRegUsageForType(Val->getScalarType()); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) { - return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index); + Value *Op0 = nullptr; + Value *Op1 = nullptr; + if (auto *IE = dyn_cast<InsertElementInst>(&I)) { + Op0 = IE->getOperand(0); + Op1 = IE->getOperand(1); + } + return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index, Op0, Op1); } InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, @@ -2246,7 +2258,8 @@ public: ArithCost += NumReduxLevels * thisT()->getArithmeticInstrCost(Opcode, Ty, CostKind); return ShuffleCost + ArithCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Try to calculate the cost of performing strict (in-order) reductions, @@ -2353,7 +2366,8 @@ public: // The last min/max should be in vector registers and we counted it above. // So just need a single extractelement. return ShuffleCost + MinMaxCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 7459ce18c3cf..d03a8cf14172 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -897,13 +897,13 @@ InstructionCost TargetTransformInfo::getCmpSelInstrCost( return Cost; } -InstructionCost TargetTransformInfo::getVectorInstrCost(unsigned Opcode, - Type *Val, - unsigned Index) const { +InstructionCost TargetTransformInfo::getVectorInstrCost( + unsigned Opcode, Type *Val, unsigned Index, Value *Op0, Value *Op1) const { // FIXME: Assert that Opcode is either InsertElement or ExtractElement. // This is mentioned in the interface description and respected by all // callers, but never asserted upon. - InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + TTIImpl->getVectorInstrCost(Opcode, Val, Index, Op0, Op1); assert(Cost >= 0 && "TTI should not produce negative costs!"); return Cost; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index ae12ae951d75..f5f6c07f766a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -2034,8 +2034,8 @@ InstructionCost AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, // Get the cost for the extract. We compute the cost (if any) for the extend // below. - InstructionCost Cost = - getVectorInstrCost(Instruction::ExtractElement, VecTy, Index); + InstructionCost Cost = getVectorInstrCost(Instruction::ExtractElement, VecTy, + Index, nullptr, nullptr); // Legalize the types. auto VecLT = getTypeLegalizationCost(VecTy); @@ -2128,7 +2128,8 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(Type *Val, } InstructionCost AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { return getVectorInstrCostHelper(Val, Index, false /* HasRealUse */); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index e309117a885b..6eaff9566b8c 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -169,8 +169,8 @@ public: InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index af72ba2daa2d..00e6970291bf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -790,7 +790,8 @@ GCNTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, } InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { @@ -799,7 +800,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (EltSize < 32) { if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) return 0; - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -810,7 +811,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 347ce87acd26..4a1137dcf2e2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -162,7 +162,7 @@ public: using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const; bool isSourceOfDivergence(const Value *V) const; diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp index 365c005b2503..c3dd321a7b9c 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp @@ -108,14 +108,15 @@ InstructionCost R600TTIImpl::getCFInstrCost(unsigned Opcode, } InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { unsigned EltSize = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType()); if (EltSize < 32) { - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -126,7 +127,7 @@ InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h index f1a198fd14e4..9045cc773189 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h @@ -62,7 +62,7 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); }; } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 8eec432a4a66..07786ea82738 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -874,7 +874,8 @@ InstructionCost ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, } InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // Penalize inserting into an D-subregister. We end up with a three times // lower estimated throughput on swift. if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement && @@ -893,7 +894,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32) return std::max<InstructionCost>( - BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U); + BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1), 2U); } if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || @@ -906,7 +907,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return LT.first * (ValTy->getScalarType()->isIntegerTy() ? 4 : 1); } - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } InstructionCost ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index db96c3da54cf..6b1e6444c516 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -240,8 +240,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 779577816fb9..6089c865cedf 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -329,7 +329,8 @@ InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, } InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType() : Val; if (Opcode == Instruction::InsertElement) { @@ -338,7 +339,8 @@ InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ElemTy->isIntegerTy(32)) return Cost; // If it's not a 32-bit value, there will need to be an extract. - return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index); + return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index, + Op0, Op1); } if (Opcode == Instruction::ExtractElement) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 49d9520b8323..d41299ff6413 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -154,8 +154,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr) { diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 3b952f11be34..328a70ec43f6 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -675,7 +675,8 @@ InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); int ISD = TLI->InstructionOpcodeToISD(Opcode); @@ -685,7 +686,8 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (!CostFactor.isValid()) return InstructionCost::getMax(); - InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); Cost *= CostFactor; if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { @@ -827,7 +829,8 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, if (Src->isVectorTy() && Opcode == Instruction::Store) for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; ++i) - Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); + Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i, nullptr, + nullptr); return Cost; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index 9db903baf407..810a7d0d62ef 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -126,8 +126,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 02ce1b135f7f..ed8af25998b0 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1216,12 +1216,13 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); if (Opcode != Instruction::ExtractElement && Opcode != Instruction::InsertElement) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // Legalize the type. std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Val); @@ -1235,7 +1236,7 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return LT.first; if (!isTypeLegal(Val)) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // In RVV, we could use vslidedown + vmv.x.s to extract element from vector // and vslideup + vmv.s.x to insert element to vector. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 80c7ca3564d7..5df266ba35b5 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -157,8 +157,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 5d00e56ae347..d6736319a404 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -996,7 +996,8 @@ InstructionCost SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // vlvgp will insert two grs into a vector register, so only count half the // number of instructions. if (Opcode == Instruction::InsertElement && Val->isIntOrIntVectorTy(64)) @@ -1012,7 +1013,7 @@ InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return Cost; } - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } // Check if a load may be folded as a memory operand in its user. diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 5ac3d8149a1d..33c3778d572c 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -107,8 +107,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); bool isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp index 38464627e742..b94dcd63ad8b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -82,9 +82,10 @@ InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost( InstructionCost WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, + Value *Op0, Value *Op1) { InstructionCost Cost = - BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); + BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // SIMD128's insert/extract currently only take constant indices. if (Index == -1u) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index 7eed7ef44af7..4f54a762042f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -66,8 +66,8 @@ public: ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); /// @} diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 7d08a1654be7..5b6c7d86cebe 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -4257,7 +4257,8 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { static const CostTblEntry SLMCostTbl[] = { { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, @@ -4330,6 +4331,14 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, } } + MVT MScalarTy = LT.second.getScalarType(); + auto IsCheapPInsrPExtrInsertPS = [&]() { + return (MScalarTy == MVT::i16 && ST->hasSSE2()) || + (MScalarTy.isInteger() && ST->hasSSE41()) || + (MScalarTy == MVT::f32 && ST->hasSSE41() && + Opcode == Instruction::InsertElement); + }; + if (Index == 0) { // Floating point scalars are already located in index #0. // Many insertions to #0 can fold away for scalar fp-ops, so let's assume @@ -4337,6 +4346,20 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ScalarType->isFloatingPointTy()) return RegisterFileMoveCost; + if (Opcode == Instruction::InsertElement && + isa_and_nonnull<UndefValue>(Op0)) { + // Consider the gather cost to be cheap. + if (isa_and_nonnull<LoadInst>(Op1)) + return RegisterFileMoveCost; + if (!IsCheapPInsrPExtrInsertPS()) { + // mov constant-to-GPR + movd/movq GPR -> XMM. + if (isa_and_nonnull<Constant>(Op1) && Op1->getType()->isIntegerTy()) + return 2 + RegisterFileMoveCost; + // Assume movd/movq GPR -> XMM is relatively cheap on all targets. + return 1 + RegisterFileMoveCost; + } + } + // Assume movd/movq XMM -> GPR is relatively cheap on all targets. if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) return 1 + RegisterFileMoveCost; @@ -4344,19 +4367,13 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, int ISD = TLI->InstructionOpcodeToISD(Opcode); assert(ISD && "Unexpected vector opcode"); - MVT MScalarTy = LT.second.getScalarType(); if (ST->useSLMArithCosts()) if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) return Entry->Cost + RegisterFileMoveCost; // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. - if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || - (MScalarTy.isInteger() && ST->hasSSE41())) - return 1 + RegisterFileMoveCost; - // Assume insertps is relatively cheap on all targets. - if (MScalarTy == MVT::f32 && ST->hasSSE41() && - Opcode == Instruction::InsertElement) + if (IsCheapPInsrPExtrInsertPS()) return 1 + RegisterFileMoveCost; // For extractions we just need to shuffle the element to index 0, which @@ -4383,7 +4400,8 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) RegisterFileMoveCost += 1; - return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1) + + RegisterFileMoveCost; } InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, @@ -5155,7 +5173,8 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, } // Add the final extract element to the cost. - return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, @@ -5455,7 +5474,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, } // Add the final extract element to the cost. - return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Calculate the cost of materializing a 64-bit value. This helper diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 666789e160dc..c189e503f4e8 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -147,8 +147,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index e1b52aa2f80e..8ca422cfab9f 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6745,9 +6745,24 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, // broadcast. assert(VecTy == FinalVecTy && "No reused scalars expected for broadcast."); - return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, - /*Mask=*/std::nullopt, CostKind, /*Index=*/0, - /*SubTp=*/nullptr, /*Args=*/VL[0]); + const auto *It = + find_if(VL, [](Value *V) { return !isa<UndefValue>(V); }); + // If all values are undefs - consider cost free. + if (It == VL.end()) + return TTI::TCC_Free; + // Add broadcast for non-identity shuffle only. + bool NeedShuffle = + VL.front() != *It || !all_of(VL.drop_front(), UndefValue::classof); + InstructionCost InsertCost = + TTI->getVectorInstrCost(Instruction::InsertElement, VecTy, + /*Index=*/0, PoisonValue::get(VecTy), *It); + return InsertCost + (NeedShuffle + ? TTI->getShuffleCost( + TargetTransformInfo::SK_Broadcast, VecTy, + /*Mask=*/std::nullopt, CostKind, + /*Index=*/0, + /*SubTp=*/nullptr, /*Args=*/VL[0]) + : TTI::TCC_Free); } InstructionCost ReuseShuffleCost = 0; if (NeedToShuffleReuses) diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll index 3e0f4c11aadf..1e96f97f16e9 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> poison, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2.ll b/llvm/test/Analysis/CostModel/X86/loop_v2.ll index a9cbaaf2fd63..8f67b365ca9b 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> undef, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll index 381e5b630812..897344d622d0 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll index 2fa41968e807..5f22b2e39f94 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll index 2296b3d5b0c4..e6a4de688186 100644 --- a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll @@ -382,58 +382,58 @@ define i32 @insert_i64(i32 %arg) { define i32 @insert_i32(i32 %arg) { ; SSE2-LABEL: 'insert_i32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSE3-LABEL: 'insert_i32' ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSSE3-LABEL: 'insert_i32' ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; @@ -664,100 +664,100 @@ define i32 @insert_i16(i32 %arg) { define i32 @insert_i8(i32 %arg) { ; SSE2-LABEL: 'insert_i8' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63 </cut>

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #2

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Fixed a regression found when preparing the new patches. Rebased on the current mainline branch and continued preparing patches for upstream submission. # Misc - Found a minor problem with a script in upstream GDB. Submitted and committed a quick patch¹ to fix it. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20230111174501.3699871-1-thiago.ba…

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 13 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - another round of patch review and a pull request * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Made some useful progress with the FEAT_FGT implementation -- PMM

2 years, 4 months

1
0
0 0

[ACTIVITY] week ending 8 Jan 2023

by Richard Henderson

* A couple of attempts at minimizing arm per-cpu init work. I've posted a short/medium-term solution for the lookup issue, so that we can re-apply Alex's CPUState unrealize patch. * TCG patch queue flushed, including call abi reorg. - Rebase TCGv_i128 patch set - Rebase goto_tb race condition patch set r~

2 years, 4 months

1
0
0 0

[ACTIVITY] week ending Jan. 8 2023

by Alex Bennée

Project Stratos =============== vhost-device maintainer effort ([UM-196]) - a few version bump reviews Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [RFC PATCH 00/40] Toward class init of cpu features Message-Id: <20230103181646.55711-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 6 Jan

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - Pretty much entirely trying to catch up with the code review backlog that had built up over the holidays. Got it down from 35 items to 7... Absences: * NB: I work a 4 day week, excluding Wednesdays * Apr 26 -- 28 : Linaro Connect (London) In office (provisional; let me know if you have preferences!): * week of the 9 Jan -- PMM

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #52

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Identified a regression on systems that do not support SVE. Debugged it and now working on a fix. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #51

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing the new approach of sending new XML target descriptions through the wire. - Fixed a couple of minor regressions I introduced and rebased the code on the current main branch. - Now preparing the patches for submitting upstream. # Community participation - Reviewed mailing list patch “[PATCH] [AArch64] Enable pointer authentication support for aarch64 bare metal/kernel mode addresses”. -- Thiago

2 years, 4 months

1
0
0 0

[ACTIVITY] week ending Dec. 25 2022

by Alex Bennée

Project Stratos =============== - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing - writing up a [proposal for an API] [proposal for an API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post - QEMU 7.2 shipped with stubs for virtio-gpio and virtio-i2c [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> Plugin register access ([QEMU-495]) =================================== - While experimenting with [the register API] ran into issues integrating to gdbstub - started a [re-factor] to make the process less painful - posted [PATCH v1 00/10] split user and system code in gdbstub Message-Id: <20221216112206.3171578-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> [the register API] <https://github.com/stsquad/qemu/tree/introspection/registers> [re-factor] <https://github.com/stsquad/qemu/tree/gdbstub/next> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 0/6] testing updates Message-Id: <20221221144019.2149905-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] gitdm metadata updates Message-Id: <20221219121914.851488-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [QEMU][PATCH v2 00/11] Introduce xenpv machine for arm architecture Message-Id: <20221202030003.11441-1-vikram.garhwal(a)amd.com> [PATCH] configure: Fix check-tcg not executing any tests Message-Id: <20221207082309.9966-1-quic_mthiyaga(a)quicinc.com> [PATCH v4 00/27] tcg misc patches Message-Id: <20221213212541.1820840-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221209051914.398215-1-richard.henderson(a)linaro.org> [PATCH-for-8.0 0/5] accel/tcg: Restrict page_collection structure to system TB maintainance Message-Id: <20221209093649.43738-1-philmd(a)linaro.org> Absences ======== Christmas holidays - merry Christmas! Current Review Queue ==================== TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== TODO [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221202061347.1070246-1-chao.p.peng(a)linux.intel.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 20 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - I'm now back on merging duty for the 8.0 release cycle, so some time spent on pull request processing - Sent pull requests with accumulated arm and reset-refactoring patches from the freeze period - Trying to cut down my code review backlog before the holidays -- PMM

2 years, 4 months

1
0
0 0

[ACTIVITY] Report for week #50

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: About halfway through implementing the new approach of sending new XML target descriptions through the wire. # Misc - Experimented with using a GDB wrapper to run the testsuite. Came up with a small patch that fixes the tests that fail when using the wrapper. -- Thiago

2 years, 4 months

1
0
0 0

[TCWG CI] Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 7572 # First few build errors in logs: # 00:10:43 drivers/gpu/drm/v3d/v3d_perfmon.c:57:1: internal compiler error: in decompose, at rtl.h:2288 # 00:10:44 make[5]: *** [scripts/Makefile.build:250: drivers/gpu/drm/v3d/v3d_perfmon.o] Error 1 # 00:10:53 make[4]: *** [scripts/Makefile.build:502: drivers/gpu/drm/v3d] Error 2 # 00:13:52 drivers/media/mc/mc-device.c:198:1: internal compiler error: in decompose, at rtl.h:2288 # 00:13:53 make[4]: *** [scripts/Makefile.build:250: drivers/media/mc/mc-device.o] Error 1 # 00:13:57 make[3]: *** [scripts/Makefile.build:502: drivers/media/mc] Error 2 # 00:15:27 make[2]: *** [scripts/Makefile.build:502: drivers/media] Error 2 # 00:17:50 make[3]: *** [scripts/Makefile.build:502: drivers/gpu/drm] Error 2 # 00:17:50 make[2]: *** [scripts/Makefile.build:502: drivers/gpu] Error 2 # 00:17:50 make[1]: *** [scripts/Makefile.build:502: drivers] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 8625 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-4618-g17ae956c0fa commit for tcwg_kernel: commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. * gnu-master-aarch64-mainline-defconfig ** Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Reproduce current build: <cut> mkdir -p investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 cd investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. --- gcc/config/aarch64/aarch64.md | 33 ++++++++--- gcc/config/aarch64/iterators.md | 2 + gcc/testsuite/gcc.target/aarch64/tbz_1.c | 95 ++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 896b6a8ac79..d749c98eef6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -947,12 +947,29 @@ (const_int 1)))] ) -(define_insn "*tb<optab><mode>1" +(define_expand "tbranch_<code><mode>3" [(set (pc) (if_then_else - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 - "aarch64_simd_shift_imm_<mode>" "n")) + (EQL (match_operand:ALLI 0 "register_operand") + (match_operand 1 "aarch64_simd_shift_imm_<mode>")) + (label_ref (match_operand 2 "")) + (pc)))] + "" +{ + rtx bitvalue = gen_reg_rtx (<ZEROM>mode); + rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); + rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); + operands[1] = const0_rtx; + operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue, + operands[1]); +}) + +(define_insn "*tb<optab><ALLI:mode><GPI:mode>1" + [(set (pc) (if_then_else + (EQL (zero_extract:GPI (match_operand:ALLI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 + "aarch64_simd_shift_imm_<ALLI:mode>" "n")) (const_int 0)) (label_ref (match_operand 2 "" "")) (pc))) @@ -963,15 +980,15 @@ { if (get_attr_far_branch (insn) == 1) return aarch64_gen_far_branch (operands, 2, "Ltb", - "<inv_tb>\\t%<w>0, %1, "); + "<inv_tb>\\t%<ALLI:w>0, %1, "); else { operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1])); - return "tst\t%<w>0, %1\;<bcond>\t%l2"; + return "tst\t%<ALLI:w>0, %1\;<bcond>\t%l2"; } } else - return "<tbz>\t%<w>0, %1, %l2"; + return "<tbz>\t%<ALLI:w>0, %1, %l2"; } [(set_attr "type" "branch") (set (attr "length") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d10cf93572e..a521dbde1ec 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1107,6 +1107,8 @@ ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) +(define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")]) +(define_mode_attr zerom [(QI "si") (HI "si") (SI "si") (DI "di")]) ;; Give the ordinal of the MSB in the mode (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_1.c b/gcc/testsuite/gcc.target/aarch64/tbz_1.c new file mode 100644 index 00000000000..39deb58e278 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tbz_1.c @@ -0,0 +1,95 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include <stdbool.h> + +void h(void); + +/* +** g1: +** tbnz w[0-9]+, #?0, .L([0-9]+) +** ret +** ... +*/ +void g1(bool x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g2: +** tbz w[0-9]+, #?0, .L([0-9]+) +** b h +** ... +*/ +void g2(bool x) +{ + if (__builtin_expect (x, 1)) + h (); +} + +/* +** g3_ge: +** tbnz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_ge(int x) +{ + if (__builtin_expect (x >= 0, 1)) + h (); +} + +/* +** g3_gt: +** cmp w[0-9]+, 0 +** ble .L[0-9]+ +** b h +** ... +*/ +void g3_gt(int x) +{ + if (__builtin_expect (x > 0, 1)) + h (); +} + +/* +** g3_lt: +** tbz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_lt(int x) +{ + if (__builtin_expect (x < 0, 1)) + h (); +} + +/* +** g3_le: +** cmp w[0-9]+, 0 +** bgt .L[0-9]+ +** b h +** ... +*/ +void g3_le(int x) +{ + if (__builtin_expect (x <= 0, 1)) + h (); +} + +/* +** g5: +** mov w[0-9]+, 65279 +** tst w[0-9]+, w[0-9]+ +** beq .L[0-9]+ +** b h +** ... +*/ +void g5(int x) +{ + if (__builtin_expect (x & 0xfeff, 1)) + h (); +} </cut>

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #49

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: There was an upstream discussion about whether changing the implementation from relying on expedited registers to relying on sending target descriptions over the wire was a better approach. Simon Marchi detailed his idea on how to do that and it does seem better. - Started implementing Simon's approach of sending target descriptions over the wire for each thread. # Misc - Sent and later committed a couple of patches¹ fixing whitespace issues in a Python script that generates a GDB source file. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #48

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the gdbserver patches to support changing the SVE vector length was quickly reviewed by both Luis and Simon Marchi. I applied their review suggestions and I'm now working on fixing a bug with multi-threaded programs that they spotted. - Submitted a couple of small patches¹ fixing tab vs spaces issues in the gdbarch.py script that generates some source code in GDB. # Misc - Fixed problem in the tcwg-dev/start.sh script where asking docker to expose /dev/kvm to a dev container on a host which doesn't have KVM support causes docker to error out (reported by David Spickett). Sent Gerrit change request “42669: tcwg-dev: Add heuristic to check for KVM support on the host” to fix it. David reviewed and merged it. Thanks! -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #47

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Worked on v2 of the gdbserver patches improving SVE support. Found a couple of simplifications that could be made to the code. Rebased on current master branch and finished regression testing and patch preparation. Wrote the cover letter. - Finally posted the patch series upstream¹. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221126020452.1686509-1-thiago.ba…

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 25 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - More conversions of devices to 3-phase reset in pursuit of the interim goal of getting rid of device_class_set_parent_reset() - Investigated a regression in a TF-A workload: this was due to recent pagetable walk refactoring breaking debug accesses. - code review, etc; mostly this has been of for-8.0 material, as (other than the above mentioned ptw regression) there haven't been many release-worthy issues this freeze cycle. -- PMM

2 years, 5 months

1
0
0 0

[TCWG CI] 403.gcc failed to run after working-3971-g5f7f484ee54e: [AArch64] Add GPR rr instructions to isAssociativeAndCommutative

by Maxim Kuvyrkov

Hi David, Our CI flagged your commit; it seems it miscompiles 403.gcc from SPEC CPU2006 at -O3 -flto for aarch64-linux-gnu. Would you please investigate? Let me know if you need any assistance in reproducing this. Thanks! === After working-3971-g5f7f484ee54e commit 5f7f484ee54ebbf702ee4c5fe9852502dc237121 Author: David Green <david.green(a)arm.com> [AArch64] Add GPR rr instructions to isAssociativeAndCommutative the following benchmarks slowed down by more than 3%: - 403.gcc failed to run Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: NVidia TX1 4x Cortex-A57 -- Maxim Kuvyrkov https://www.linaro.org

2 years, 5 months

2
2
0 0

[ACTIVITY] Report for week #46

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Found and fixed a memory leak in my code while preparing patches for upstream submission. Continuing preparing the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Analysed failures of “fast_check_gdb” CI jobs over the weekend. They were caused by unrelated build issues in GCC and libstdc++. -- Thiago

2 years, 5 months

1
0
0 0

[ACTIVITY] week ending Nov. 20 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - now live [on web site] - did a review of [virtio-loopback] - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [on web site] <https://www.linaro.org/blog/the-challenges-of-abstracting-virtio/> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PULL for 7.2 00/10] testing and doc updates Message-Id: <20221115133439.2348929-1-alex.bennee(a)linaro.org> - did a bunch of follow-up testing to shake out other console bugs - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PATCH for 7.2? v1 0/2] Arm GICv2 patches Message-Id: <20221115134048.2352715-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [1/1] ======================= [PATCH] ci: replace x86_64 macos-11 with aarch64 macos-12 Message-Id: <20221116175023.80627-1-berrange(a)redhat.com> Absences ======== Current Review Queue ==================== TODO [PATCH v6 00/21] Drivers for gunyah hypervisor Message-Id: <20221026185846.3983888-1-quic_eberman(a)quicinc.com> ================================================================================================================== TODO [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> ======================================================================================================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== -- Alex Bennée

2 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 18 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- the usual release cycle work. Looks relatively quiet this time around. -- taking the opportunity to try to catch up on some of the for-8.0 code review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] -- started thinking about how to implement FEAT_FGT. Looking at the code where this ought to go, I found a minor bug with how we implement the existing HSTR_EL2 traps, and a case where we trap AArch32 ATS12NSO* with the wrong syndrome. -- PMM

2 years, 5 months

1
0
0 0

[ACTIVITY] Report for week #45

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Tested new code for regressions in different systems and configurations and found none. Preparing new version of the patches for upstream submission. Will likely post them early next week. -- Thiago

2 years, 6 months

1
0
0 0

[ACTIVITY] week ending Nov. 13 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - did a review of [virtio-loopback] [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - review work Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [7/7] ======================= [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-1-richard.henderson(a)linaro.org> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH] Run docker probe only if docker or podman are available Message-Id: <20221030083510.310584-1-sw(a)weilnetz.de> [PULL 3/3] linux-test (tests/tcg/multiarch/linux-test.c) add check Message-Id: <1626902375-7002-4-git-send-email-tsimpson(a)quicinc.com> [PATCH v5 00/18] tests/qtest: Enable running qtest on Windows Message-Id: <20221006151927.2079583-3-bmeng.cn(a)gmail.com> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH RFC 0/1] tcg: add perfmap and jitdump Message-Id: <20221012051846.1432050-1-iii(a)linux.ibm.com> Absences ======== Current Review Queue ==================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== TODO [PATCH v3 0/7] memory: prevent dma-reentracy issues Message-Id: <20221028191648.964076-1-alxndr(a)bu.edu> =========================================================================================================== TODO [QEMU][PATCH v2 0/5] Introduce Xilinx Versal CANFD Message-Id: <20221022054746.28217-1-vikram.garhwal(a)amd.com> ================================================================================================================== -- Alex Bennée

2 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 10 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- identified another piece of the reset mechanics that can be tractably cleaned up: I think we should be able to get everything (effectively) moved over to the 3-phase reset system -- sent out various for-8.0 patchsets that convert devices that were using device_class_set_parent_reset(), since getting rid of that function is step 1 of that cleanup -- code review etc -- PMM

2 years, 6 months

1
0
0 0

[ACTIVITY] Report for week #44

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Confirmed that gdbserver doesn't send a new XML target description over the wire when the vector length changes, so there's no impact of these patches on the amount of remote protocol traffic, which was a concern for GDB maintainers. - Started doing some up code cleanup and regression tests to prepare for submitting v2 of the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Committed Gerrit change request adding the new CI job¹ to run fast subset of GDB tests, which also has stable results. The list of tests comes from Sourceware's builder project. -- Thiago ¹ https://ci.linaro.org/view/tcwg_gnu_native/job/tcwg_gnu_native_fast_check_g…

2 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 4 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- investigated and thought a bit more about a race condition involving display devices. I know think I understand the problem but the best idea I could come up with for a solution is pretty painful... (Still hoping for feedback on whether I've missed something.) -- collated and sent out a pull request with various bug fixes for rc0 -- sent some more reset-cleanup patches (these will be for 8.0) -- PMM

2 years, 6 months

1
0
0 0

Virt meeting 2022-11-01

by Richard Henderson

Hi guys, I will attempt to join today, but we've been finding that connectivity is dependent on the number of rain drops and/or hail in between here and the mast. So I'm not overly hopeful for later this evening. Status report: - Fixed a failure in my x86 TARGET_TB_PCREL patches, which caused non-booting of some images (in today's tcg PR). - Revised the TCGv_i128 patch set (not yet posted). - Lots of work on accel/tcg/{cputlb,user-exec}.c, to honor atomicity requirements of FEAT_LSE2. Next up: Adding qemu_ld/st helpers and patterns for i128. r~

2 years, 6 months

1
0
0 0

[ACTIVITY] Report for week #43

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. Started checking changes for regressions. -- Thiago

2 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 28 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Cross-checked our boot.c code against the kernel's booting.rst, and sent patch fixing a few EL3 config bits we weren't setting - Sent out the minutes from QEMU Summit * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Wrote and sent out patches to implement the extra traps required for FEAT_EVT -- PMM

2 years, 6 months

1
0
0 0

[ACTIVITY] Report for week #42

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilise GDB testsuite results in the CI - Reworked and committed Gerrit change request for jenkins-scripts adding a new CI job definition in tcwg_gnu-build.sh. - Also reworked and committed another one to the same script adding a default manifest file if one isn't specified on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Implemented Luis' suggestion of assuming that if ptrace can't read the SVE state, then SVE is disabled (which is what gdbserver does before my patches). It turns out that the only situation where this happens, gdbserver doesn't actually care about the target description. - Started exploring/implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. As Luis suggests, it may simplify the code. -- Thiago

2 years, 6 months

1
0
0 0

[ACTIVITY] week ending Oct. 23 2022

by Alex Bennée

Project Stratos =============== - wrote a [draft blog post for virtio-camera] [draft blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> vhost-device maintainer effort ([UM-196]) - review work [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: don't process FCSE translations on physical TLBs Message-Id: <20221021172338.2782240-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: protect execlog's last_exec expansion Message-Id: <20221021164028.2757262-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: enable debug on CONFIG_DEBUG_TCG Message-Id: <20221021155146.2729598-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits Message-Id: <20221020123506.26363-1-ani(a)anisinha.ca> Other ===== - reviews and appraisals - members operational meeting - QEMU plans Absences ======== Current Review Queue ==================== TODO [PATCH 00/31] tcg: Support for Int128 with helpers Message-Id: <20221020115242.2301066-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [PATCH v8 0/9] target/arm: pc-relative translation blocks Message-Id: <20221020030641.2066807-1-richard.henderson(a)linaro.org> ================================================================================================================================= TODO [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> ============================================================================================================================ -- Alex Bennée

2 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 21 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Spent a couple of days investigating a long-standing intermittent test case failure booting a kernel on the raspberry pi. This turned out to be caused by two linked bugs: - the test framework unhelpfully disconnects immediately from the guest serial console when the test ends, rather than staying connected until the QEMU process exits to capture all the output - QEMU's socket chardev loses data when the remote end closes the connection if the guest UART hasn't read all of it So the test was failing because the guest sometimes only saw the 'h' of the final 'halt' command the test sent... - Investigated and fixed a regression caused by some of last week's reset patches. (Turns out the patch to fix it had been sent back in 2021 but we accidentally dropped it on the floor. Oops.) thanks -- PMM

2 years, 6 months

1
0
0 0

[ACTIVITY] Report for week #41

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued incorporating suggestions from Luis' review of the patches. Working on a few regressions I introduced in the process. # [GNU-796] Stabilise GDB testsuite results in the CI - Started addressing Maxim's comments to my change requests for jenkins-scripts. -- Thiago

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Oct. 16 2022

by Alex Bennée

Project Stratos =============== - virtio-camera discussion and prep vhost-device maintainer effort ([UM-196]) - more review, vsock merged \o/ [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - more leadership committee work - more member engagement on CCA/RME - posted [PATCH v1 0/4] testing/next hotfix (revert bios build, mingw) Message-Id: <20221011113417.794841-1-alex.bennee(a)linaro.org> - posted [PULL 0/1] testing: revert pc-bios build patch Message-Id: <20221011192858.956078-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/7] testing/next (configure, RUNC, win32|64) Message-Id: <20221013154705.1846261-1-alex.bennee(a)linaro.org> - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [2/2] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> Other ===== - reviews and appraisals - other admin Absences ======== - day off ill Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== -- Alex Bennée

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 14 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Started looking again at QEMU's rather messy set of reset related APIs. Dug out the half-a-plan I wrote up a long time back and refreshed my memory of what I was hoping we might be able to do. - As an initial step, wrote some patches to get rid of uses of several deprecated reset-related functions so that I only have to think about one set of functions and not two... -- PMM

2 years, 7 months

1
0
0 0

[TCWG CI] Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 624 # First few build errors in logs: # 00:01:42 mm/slub.c:4428:5: error: virtual use of statement not up to date # 00:01:42 mm/slub.c:4428:5: internal compiler error: verify_ssa failed # 00:01:43 make[2]: *** [scripts/Makefile.build:250: mm/slub.o] Error 1 # 00:01:44 make[1]: *** [scripts/Makefile.build:500: mm] Error 2 # 00:01:56 make: *** [Makefile:1990: .] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 629 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-3219-g25413fdb2ac commit for tcwg_kernel: commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. * gnu-master-aarch64-next-allnoconfig ** Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Reproduce current build: <cut> mkdir -p investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 cd investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. --- gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c | 40 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c | 44 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c | 45 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c | 39 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c | 42 +++ gcc/tree-if-conv.cc | 313 ++++++++++++++++++-- gcc/tree-vect-data-refs.cc | 3 +- gcc/tree-vect-patterns.cc | 330 +++++++++++++++++++++- 14 files changed, 1079 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c new file mode 100644 index 00000000000..01cf34fb444 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define ELT0 {0} +#define ELT1 {1} +#define ELT2 {2} +#define ELT3 {3} +#define N 32 +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].i; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c new file mode 100644 index 00000000000..1a4a1579c14 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 0} +#define ELT1 {0x7FFFFFFFUL, 1} +#define ELT2 {0x7FFFFFFFUL, 2} +#define ELT3 {0x7FFFFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c new file mode 100644 index 00000000000..849f4a017e1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" +#include <stdbool.h> + +extern void abort(void); + +typedef struct { + int c; + int b; + bool a : 1; + int d : 31; +} struct_t; + +#define N 16 +#define ELT_F { 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x7FFFFFFF } +#define ELT_T { 0xFFFFFFFF, 0xFFFFFFFF, 1, 0x7FFFFFFF } + +struct_t vect_false[N] = { ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +struct_t vect_true[N] = { ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +int main (void) +{ + unsigned ret = 0; + for (unsigned i = 0; i < N; i++) + { + ret |= vect_false[i].a; + } + if (ret) + abort (); + + for (unsigned i = 0; i < N; i++) + { + ret |= vect_true[i].a; + } + if (!ret) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c new file mode 100644 index 00000000000..5bc9c412e96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c @@ -0,0 +1,45 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 3, 0} +#define ELT1 {0x7FFFFFFFUL, 3, 1} +#define ELT2 {0x7FFFFFFFUL, 3, 2} +#define ELT3 {0x7FFFFFFFUL, 3, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c new file mode 100644 index 00000000000..1dc24d3eded --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 9; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c new file mode 100644 index 00000000000..7d24c299758 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 8; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c new file mode 100644 index 00000000000..19683d277b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c @@ -0,0 +1,39 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].i = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].i != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c new file mode 100644 index 00000000000..d550dd35ab7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c new file mode 100644 index 00000000000..3303d2610ff --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c new file mode 100644 index 00000000000..fae6ea3557d --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 9; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c new file mode 100644 index 00000000000..99360c2967b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 8; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index bac29fb5574..e468a4659fa 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "ssa.h" #include "expmed.h" +#include "expr.h" #include "optabs-query.h" #include "gimple-pretty-print.h" #include "alias.h" @@ -123,6 +124,9 @@ along with GCC; see the file COPYING3. If not see #include "tree-vectorizer.h" #include "tree-eh.h" +/* For lang_hooks.types.type_for_mode. */ +#include "langhooks.h" + /* Only handle PHIs with no more arguments unless we are asked to by simd pragma. */ #define MAX_PHI_ARG_NUM \ @@ -145,6 +149,12 @@ static bool need_to_rewrite_undefined; before phi_convertible_by_degenerating_args. */ static bool any_complicated_phi; +/* True if we have bitfield accesses we can lower. */ +static bool need_to_lower_bitfields; + +/* True if there is any ifcvting to be done. */ +static bool need_to_ifcvt; + /* Hash for struct innermost_loop_behavior. It depends on the user to free the memory. */ @@ -1411,15 +1421,6 @@ if_convertible_loop_p_1 (class loop *loop, vec<data_reference_p> *refs) calculate_dominance_info (CDI_DOMINATORS); - /* Allow statements that can be handled during if-conversion. */ - ifc_bbs = get_loop_body_in_if_conv_order (loop); - if (!ifc_bbs) - { - if (dump_file && (dump_flags & TDF_DETAILS)) - fprintf (dump_file, "Irreducible loop\n"); - return false; - } - for (i = 0; i < loop->num_nodes; i++) { basic_block bb = ifc_bbs[i]; @@ -2899,18 +2900,22 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) class loop *new_loop; gimple *g; gimple_stmt_iterator gsi; - unsigned int save_length; + unsigned int save_length = 0; g = gimple_build_call_internal (IFN_LOOP_VECTORIZED, 2, build_int_cst (integer_type_node, loop->num), integer_zero_node); gimple_call_set_lhs (g, cond); - /* Save BB->aux around loop_version as that uses the same field. */ - save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; - void **saved_preds = XALLOCAVEC (void *, save_length); - for (unsigned i = 0; i < save_length; i++) - saved_preds[i] = ifc_bbs[i]->aux; + void **saved_preds = NULL; + if (any_complicated_phi || need_to_predicate) + { + /* Save BB->aux around loop_version as that uses the same field. */ + save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; + saved_preds = XALLOCAVEC (void *, save_length); + for (unsigned i = 0; i < save_length; i++) + saved_preds[i] = ifc_bbs[i]->aux; + } initialize_original_copy_tables (); /* At this point we invalidate porfile confistency until IFN_LOOP_VECTORIZED @@ -2922,8 +2927,9 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) profile_probability::always (), true); free_original_copy_tables (); - for (unsigned i = 0; i < save_length; i++) - ifc_bbs[i]->aux = saved_preds[i]; + if (any_complicated_phi || need_to_predicate) + for (unsigned i = 0; i < save_length; i++) + ifc_bbs[i]->aux = saved_preds[i]; if (new_loop == NULL) return NULL; @@ -2999,7 +3005,7 @@ ifcvt_split_critical_edges (class loop *loop, bool aggressive_if_conv) auto_vec<edge> critical_edges; /* Loop is not well formed. */ - if (num <= 2 || loop->inner || !single_exit (loop)) + if (loop->inner) return false; body = get_loop_body (loop); @@ -3260,6 +3266,201 @@ ifcvt_hoist_invariants (class loop *loop, edge pe) free (body); } +/* Returns the DECL_FIELD_BIT_OFFSET of the bitfield accesse in stmt iff its + type mode is not BLKmode. If BITPOS is not NULL it will hold the poly_int64 + value of the DECL_FIELD_BIT_OFFSET of the bitfield access and STRUCT_EXPR, + if not NULL, will hold the tree representing the base struct of this + bitfield. */ + +static tree +get_bitfield_rep (gassign *stmt, bool write, tree *bitpos, + tree *struct_expr) +{ + tree comp_ref = write ? gimple_assign_lhs (stmt) + : gimple_assign_rhs1 (stmt); + + tree field_decl = TREE_OPERAND (comp_ref, 1); + tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl); + + /* Bail out if the representative is BLKmode as we will not be able to + vectorize this. */ + if (TYPE_MODE (TREE_TYPE (rep_decl)) == E_BLKmode) + return NULL_TREE; + + /* Bail out if the DECL_SIZE of the field_decl isn't the same as the BF's + precision. */ + unsigned HOST_WIDE_INT bf_prec + = TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt))); + if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0) + return NULL_TREE; + + if (struct_expr) + *struct_expr = TREE_OPERAND (comp_ref, 0); + + if (bitpos) + *bitpos + = fold_build2 (MINUS_EXPR, bitsizetype, + DECL_FIELD_BIT_OFFSET (field_decl), + DECL_FIELD_BIT_OFFSET (rep_decl)); + + return rep_decl; + +} + +/* Lowers the bitfield described by DATA. + For a write like: + + struct.bf = _1; + + lower to: + + __ifc_1 = struct.<representative>; + __ifc_2 = BIT_INSERT_EXPR (__ifc_1, _1, bitpos); + struct.<representative> = __ifc_2; + + For a read: + + _1 = struct.bf; + + lower to: + + __ifc_1 = struct.<representative>; + _1 = BIT_FIELD_REF (__ifc_1, bitsize, bitpos); + + where representative is a legal load that contains the bitfield value, + bitsize is the size of the bitfield and bitpos the offset to the start of + the bitfield within the representative. */ + +static void +lower_bitfield (gassign *stmt, bool write) +{ + tree struct_expr; + tree bitpos; + tree rep_decl = get_bitfield_rep (stmt, write, &bitpos, &struct_expr); + tree rep_type = TREE_TYPE (rep_decl); + tree bf_type = TREE_TYPE (gimple_assign_lhs (stmt)); + + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Lowering:\n"); + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + fprintf (dump_file, "to:\n"); + } + + /* REP_COMP_REF is a COMPONENT_REF for the representative. NEW_VAL is it's + defining SSA_NAME. */ + tree rep_comp_ref = build3 (COMPONENT_REF, rep_type, struct_expr, rep_decl, + NULL_TREE); + tree new_val = ifc_temp_var (rep_type, rep_comp_ref, &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + if (write) + { + new_val = ifc_temp_var (rep_type, + build3 (BIT_INSERT_EXPR, rep_type, new_val, + unshare_expr (gimple_assign_rhs1 (stmt)), + bitpos), &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + gimple *new_stmt = gimple_build_assign (unshare_expr (rep_comp_ref), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + else + { + tree bfr = build3 (BIT_FIELD_REF, bf_type, new_val, + build_int_cst (bitsizetype, TYPE_PRECISION (bf_type)), + bitpos); + new_val = ifc_temp_var (bf_type, bfr, &gsi); + + gimple *new_stmt = gimple_build_assign (gimple_assign_lhs (stmt), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + + gsi_remove (&gsi, true); +} + +/* Return TRUE if there are bitfields to lower in this LOOP. Fill TO_LOWER + with data structures representing these bitfields. */ + +static bool +bitfields_to_lower_p (class loop *loop, + vec <gassign *> &reads_to_lower, + vec <gassign *> &writes_to_lower) +{ + gimple_stmt_iterator gsi; + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Analyzing loop %d for bitfields:\n", loop->num); + } + + for (unsigned i = 0; i < loop->num_nodes; ++i) + { + basic_block bb = ifc_bbs[i]; + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gassign *stmt = dyn_cast<gassign*> (gsi_stmt (gsi)); + if (!stmt) + continue; + + tree op = gimple_assign_lhs (stmt); + bool write = TREE_CODE (op) == COMPONENT_REF; + + if (!write) + op = gimple_assign_rhs1 (stmt); + + if (TREE_CODE (op) != COMPONENT_REF) + continue; + + if (DECL_BIT_FIELD_TYPE (TREE_OPERAND (op, 1))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " field type is not Integral.\n"); + return false; + } + + if (!get_bitfield_rep (stmt, write, NULL, NULL)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NOT OK to lower," + " representative is BLKmode.\n"); + return false; + } + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\tBitfield OK to lower.\n"); + if (write) + writes_to_lower.safe_push (stmt); + else + reads_to_lower.safe_push (stmt); + } + } + } + return !reads_to_lower.is_empty () || !writes_to_lower.is_empty (); +} + + /* If-convert LOOP when it is legal. For the moment this pass has no profitability analysis. Returns non-zero todo flags when something changed. */ @@ -3270,12 +3471,16 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) unsigned int todo = 0; bool aggressive_if_conv; class loop *rloop; + auto_vec <gassign *, 4> reads_to_lower; + auto_vec <gassign *, 4> writes_to_lower; bitmap exit_bbs; edge pe; again: rloop = NULL; ifc_bbs = NULL; + need_to_lower_bitfields = false; + need_to_ifcvt = false; need_to_predicate = false; need_to_rewrite_undefined = false; any_complicated_phi = false; @@ -3291,16 +3496,42 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) aggressive_if_conv = true; } - if (!ifcvt_split_critical_edges (loop, aggressive_if_conv)) + if (!single_exit (loop)) goto cleanup; - if (!if_convertible_loop_p (loop) - || !dbg_cnt (if_conversion_tree)) + /* If there are more than two BBs in the loop then there is at least one if + to convert. */ + if (loop->num_nodes > 2 + && !ifcvt_split_critical_edges (loop, aggressive_if_conv)) goto cleanup; - if ((need_to_predicate || any_complicated_phi) - && ((!flag_tree_loop_vectorize && !loop->force_vectorize) - || loop->dont_vectorize)) + ifc_bbs = get_loop_body_in_if_conv_order (loop); + if (!ifc_bbs) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Irreducible loop\n"); + goto cleanup; + } + + if (loop->num_nodes > 2) + { + need_to_ifcvt = true; + + if (!if_convertible_loop_p (loop) || !dbg_cnt (if_conversion_tree)) + goto cleanup; + + if ((need_to_predicate || any_complicated_phi) + && ((!flag_tree_loop_vectorize && !loop->force_vectorize) + || loop->dont_vectorize)) + goto cleanup; + } + + if ((flag_tree_loop_vectorize || loop->force_vectorize) + && !loop->dont_vectorize) + need_to_lower_bitfields = bitfields_to_lower_p (loop, reads_to_lower, + writes_to_lower); + + if (!need_to_ifcvt && !need_to_lower_bitfields) goto cleanup; /* The edge to insert invariant stmts on. */ @@ -3311,7 +3542,8 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) Either version this loop, or if the pattern is right for outer-loop vectorization, version the outer loop. In the latter case we will still if-convert the original inner loop. */ - if (need_to_predicate + if (need_to_lower_bitfields + || need_to_predicate || any_complicated_phi || flag_tree_loop_if_convert != 1) { @@ -3351,10 +3583,31 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) pe = single_pred_edge (gimple_bb (preds->last ())); } - /* Now all statements are if-convertible. Combine all the basic - blocks into one huge basic block doing the if-conversion - on-the-fly. */ - combine_blocks (loop); + if (need_to_lower_bitfields) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "-------------------------\n"); + fprintf (dump_file, "Start lowering bitfields\n"); + } + while (!reads_to_lower.is_empty ()) + lower_bitfield (reads_to_lower.pop (), false); + while (!writes_to_lower.is_empty ()) + lower_bitfield (writes_to_lower.pop (), true); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Done lowering bitfields\n"); + fprintf (dump_file, "-------------------------\n"); + } + } + if (need_to_ifcvt) + { + /* Now all statements are if-convertible. Combine all the basic + blocks into one huge basic block doing the if-conversion + on-the-fly. */ + combine_blocks (loop); + } </cut>

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for weeks #37, #39 and #40

by Thiago Jung Bauermann

Hello, I haven't sent a report since week #36. For that reason, this report covers three weeks. # [GNU-796] Stabilise GDB testsuite results in the CI - Implemented CI job to run fast GDB tests based on the list from Sourceware's builder. Submitted Gerrit change requests for jenkins-scripts and ci/job/configs. - Posted Gerrit change request for jenkins-scripts with an improvement to tcwg_gnu-build.sh to use a default path for the artifacts file if one isn't given on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Started incorporating suggestions from Luis' review of the patches. # Community participation - Reviewed mailing list patch “[PATCH v3] gdb/arm: Handle lazy FPU register stacking” - Attended GNU Tools Cauldron 2022. -- Thiago

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Oct. 9 2022

by Alex Bennée

Project Stratos =============== [UM-196] <https://linaro.atlassian.net/browse/UM-196> vhost-device maintainer effort ([UM-196]) - [review of vhost-sock for vhost-device] [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/54] testing, gdbstub, plugin and gitdm updates Message-Id: <20221004130138.2299307-1-alex.bennee(a)linaro.org> - took 3 attempts [PULL v3 00/52] testing, gdbstub, plugin and gitdm updates Message-Id: <20221006105556.3319342-1-alex.bennee(a)linaro.org> - leadership committee work - member engagement on CCA/RME [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/20] Cross compilation changes for 7.2 Message-Id: <20220825222745.38779-13-pbonzini(a)redhat.com> [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Message-Id: <20221004141051.110653-4-richard.henderson(a)linaro.org> [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> Other ===== - reviews and appraisals Absences ======== Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending Oct 7

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - miscellaneous upstream patch review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - sent out patchset implementing FEAT_GTG - sent out patch implementing FEAT_E0PD - code review of RTH's FEAT_HAFDBS patchset -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 30 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls - wrote up the draft of the minutes for the QEMU Summit for review - more code review and pullrequest collation (notably the Arm v8R support patchset) * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - read up on the remaining unimplemented features under this epic; closed out one we'd already implemented, and wrote up enough detail on the others to be happy with putting them all into the current sprint (they're all small features) - started looking at FEAT_GTG thanks -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Sep. 25 2022

by Alex Bennée

Project Stratos =============== - held poll for next meeting - started planning for virtio-camera/sensor QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race - posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog) Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing updates (docker, avocado, deprecate 32bit BE MIPS) Message-Id: <20220920171533.1098094-4-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Update docs - mention -d plugin - document features of tests/plugin plugins - clean up command lines to drop builddir KVM Forum ========= - Attended KVM forum, gave a talk, helper with another Completed Reviews [3/3] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> [RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com> [RFC 0/4] Support interactions between TCG plugins Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu> Absences ======== Current Review Queue ==================== TODO [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com> ======================================================================================================================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

2 years, 7 months

1
0
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain