- linaro-toolchain - lists.linaro.org

Linaro QEMU 2011.10 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2011.10. Linaro QEMU 2011.10 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. New in this month's release: - Instructions introduced with the Cortex-A15 (ARM mode SDIV and UDIV, and the VFPv4 fused multiply-accumulate instructions VFMA, VFMS, VFNMA, VFNMS) are now supported in linux-user mode - Beagle models now support USB networking (run the model with "-usb -device usb-net,netdev=mynet -netdev user,id=mynet") Known issues: - There may be some problems with running multithreaded programs in linux-user mode (LP:823902) The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2011.10 Binary builds of this qemu-linaro release are being prepared and will be available shortly for users of Ubuntu. Packages will be in the linaro-maintainers tools ppa: https://launchpad.net/~linaro-maintainers/+archive/tools/ More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

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Linaro GCC 4.6 and 4.5 2011.10 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the 2011.10 release of both Linaro GCC 4.6 and Linaro GCC 4.5. Linaro GCC 4.6 2011.10 is the eighth release in the 4.6 series. Based off the latest GCC 4.6.1+svn179483, it contains a range of vectoriser performance improvements and general bug fixes. Interesting changes include: * Updates to 4.6.1+svn179483 * Vectorises more straight-line code with data dependencies * Now picks the best vector width when vectorising straight line code * Better handles handling auto increment addresses in SMS * Changes the default vector width from double word to quad word * Better handling extracting the top or bottom half of a quad word vector * Now supports the NEON absolute difference instruction Fixes: * LP: #689887 ICE in get_arm_condition_code * LP: #809761 oss4 version 4.2-build2004-1ubuntu1 failed to build on armel Linaro GCC 4.5 2011.10 is the fifteenth release in the 4.5 series. Based off the latest GCC 4.5.3+svn179438, this is a maintenance focused release. Interesting changes in 4.5 include: * Updates to 4.5.3+svn179438 Fixes: * LP: #689887 ICE in get_arm_condition_code The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2011.10 https://launchpad.net/gcc-linaro/+milestone/4.5-2011.10 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.6/4.6-2011.10 https://launchpad.net/gcc-linaro/4.5/4.5-2011.10 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? inquire at support(a)linaro.org -- Michael

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Linaro GDB 7.3 2011.10 released

by Ulrich Weigand

The Linaro Toolchain Working Group is pleased to announce the release of Linaro GDB 7.3. Linaro GDB 7.3 2011.10 is the third release in the 7.3 series. Based off the latest GDB 7.3, it includes a number of ARM-focused bug fixes and enhancements. This release contains: * Support for disabling address space randomization in gdbserver * Fix for GDB crashes on 3.x kernels * Fix spurious "CRC mismatch" warnings when using "remote:" sysroot The source tarball is available at: https://launchpad.net/gdb-linaro/+milestone/7.3-2011.10 More information on Linaro GDB is available at: https://launchpad.net/gdb-linaro

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[ACTIVITY] October 9-12

by Ira Rosen

Hi, * Finished a presentation for NEON forum. Revital and Richard kindly agreed to take a look and gave me some valuable comments. Thanks! * widen-shifts: - While preparing the presentation I found some room for improvement in the pattern detection, so I implemented it. It gave additional 13% to rgb24tobgr16. - Ramana suggested a solution on how to check the constant operand of vshll. Testing these two things on ARM. * SLP improvements: - Implemented a patch that swaps operands if necessary to make the operations isomorphic, and supports loads with different offsets. Testing it now. - The three relevant libav loops now get vectorized giving 42%-57% speedup. Next week holidays: half days Sunday-Wednesday and Thursday. Ira

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Binary toolchain questions summary

by Michael Hope

Here's my summary from Monday's meeting on the harder parts of binary toolchains. Using a 4.6 compiler against a 4.5 based sysroot such as Natty: * libgcc and libstdc++ are part of the compiler * The compiler expects features that are in the corresponding runtime * You can't reliably run or validate against an earlier runtime The solution is to upgrade the runtime on the sysroot to 4.6. 4.6 is backwards compatible. Ubuntu did this with Maverick and it caused no problems, although problems such as Debian #622783 have been seen. Multiarch: * The Ubuntu multiarch patch should work with a sysroot * Multiarch and multilib should work together Multilib: * The current ARM multilib rules are old and not very relevant * Multilib means you need multiple sysroots as well * Skip multilib for the first release Other: * Anything we support in cross we should support native first * Check that we don't have to directly supply the source that goes with the binary sysroot -- Michael

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How to install an ARM cross compiler

by Andrew Stubbs

Saw this, thought it might be interesting if we want to point people at it something in future .... http://playterm.org/r/install-an-arm-cross-compiler-1316950150 Maybe we could record some more detailed stuff ourselves? Andrew

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[Activity] Week ending 7th Oct. 2011

by Ramana Radhakrishnan

==Progress=== * Out of office for a day. * Wrote a quick patch to do vcvt.f32.s32 with fractional bits where we can. Tested no regressions, need to commit this after review upstream. * Desk move and packing for that. * Looked at a bug report LP 836588 appears to go away with fno-gcse. Needs more digging. === Plans === * Look at LP 836588. * Finish auto-inc-dec pipeline scheduling work. * Clear out some of the old patches (POST_MODIFY_DISP for vfp, BRANCH_COST ) * Settle into new desk. * Again a short week as I'm away for 2 days for an internal training event. Meetings: * 1-1s * TCWG calls Absences. * 5th October - out of office. * 13th - 14th October - Out of Office - Internal training event. * 31st Oct - 4th Nov - Linaro Summit Orlando - Travel booked - * 08 Nov - 11 Nov - Tentatively booked * Dec 19 - 31st Dec - Tentatively booked

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[ACTIVITY] Weekly status

by Richard Sandiford

== Last week == * Patch review. * Backported second attempt to fix get_arm_condition_code ICE. * Worked on -fsched-pressure. Experimented with various combinations of ideas. This is giving some good results (e.g. a 2x improvement in libav's put_h264_qpel8_hv_lowpass_8) but needs a bit more work to fix some outliers. I'll be away from 18th Oct to 14th Nov. Richard

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Native build performance

by Michael Hope

Random data for the day: Dave Pigott has installed some new PandaBoard build machines in the validation lab. They're identical to mine except that root is on USB Flash instead of NFS, and they have a much faster flash drive for the build area. The time taken to bootstrap and test gcc-linaro-2011.09 with C, C++, Fortran, and LTO is: * ursa3, ursa4 (Toshiba USB stick): 301 minutes build / 369 test * ursa2 (no-name USB stick): 324 minutes build / 422 test * tcpanda (fast USB stick): 274 minutes build / 265 test So the new combo gives a 1.38 x faster build. I'm surprised as I though the build was CPU bound. I'd hate to see what building on an SD card is like. Note that /tmp is in RAM, /scratch is ext4, the new boards use noatime, and the kernel doesn't have the new USB performance fix. -- Michael

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[ACTIVITY] weekly status

by Revital Eres

Continue working on estimating register pressure with SMS: - Discussed current approach with Richard which gave useful leads. - Started to implement this approach. - Doing experiments on libav microbench.

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Re: Use of memcpy() in libpng

by jbowler＠acm.org

The unaligned accesses in libpng are, for the large copies, a bug. Our attempt to align the row buffer to a 16 byte boundary was off-by-one so we end up always mis-aligning it. I've posted a patch on the png-mng-implement list: http://sourceforge.net/mailarchive/message.php?msg_id=28194444 The time spent in memcpy() is probably an illusion. The data out of zlib gets copied to one row buffer where it is unfiltered (if necessary) then a copy is made in a separate buffer that is only used for the filter handling. If you test using images with large rows (I don't know what pngbench does) the copy buffer may well get flushed out of the second level cache between each row, then the memcpy will stall bringing it back in. If you have machine level profiling you may see this as a massive time spike on some probably unrelated instruction which just happens to be in the PC when the stall stops everything. Anyway, I have several ideas of how to avoid the copy when it isn't required. John Bowler <jbowler(a)acm.org> -----Original Message----- From: Glenn Randers-Pehrson [mailto:glennrp@gmail.com] Sent: Monday, October 03, 2011 1:15 PM To: PNG/MNG implementation discussion list Subject: [png-mng-implement] Use of memcpy() in libpng [Fwd from linaro-toolchain list] Re: Use of memcpy() in libpng David Gilbert Tue, 27 Sep 2011 06:20:14 -0700 On 27 September 2011 14:16, Christian Robottom Reis <k...(a)linaro.org> wrote: > On Tue, Sep 27, 2011 at 09:47:33AM +0100, Ramana Radhakrishnan wrote: >> On 26 September 2011 21:51, Michael Hope <michael.h...(a)linaro.org> wrote: >> > Saw this on the linaro-multimedia list: >> > >> > http://lists.linaro.org/pipermail/linaro-multimedia/2011-September/ >> > 000074.html >> > >> > libpng spends a significant amount of time in memcpy(). This might >> > tie in with Ramana's investigation or the unaligned access work by >> > allowing more memcpy()s to be inlined. >> >> It's the unaligned access and the change / improvements to the memcpy >> that *might* help in this case. But that ofcourse depends on the >> compiler knowing when it can do such a thing. Ofcourse what might be >> more interesting is the kind of workload analysis that Dave's done in >> the past with memcpy to know what the alignment and size of the >> buffer being copied is. > > If you guys could take a look at this there is a potential requirement > for the MMWG around libpng optimization; we could fit this in along > with other work (possible vectorizing, etc) on that component. It wouldn't take long to analyse the memcpy calls - life would be easier if we had the test program and some details on things like what size of images were used in these benchmarks. Dave

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[ACTIVITY] 3rd - 7th October

by Andrew Stubbs

Continued work on my constant reuse optimizations. Not too much this week though. I've now fixed some issues with the ARM size-costs code that was causing it to wildly over-estimate the cost of a MOVT instruction. I'll have to post this upstream sometime soon. Took another look at the shift-amount bug. Discussed the issue with Paul Brook. I've now fixed the original bug, and fixed the new bug introduced by Paul's original fix, and committed that upstream. I still need to backport it to Linaro GCC though, and the latent bug that Richard S spotted is still being analysed. Did a merge from FSF 4.5 & 4.6 to Linaro, and pushed them the Launchpad branches for testing. Begun work benchmarking different setups for the generic tuning patches. I had a lot of trouble trying to set up SPEC2000 though. Hopefully these issues are now resolved, with some help from Michael, and I have established some baseline figures on both A8 and A9 to work from. No progress on native tuning. I'm still waiting for upstream review. In other news: Mentor's contract with Linaro has now been extended for another 6 months. :)

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[ACTIVITY] 2011-10-07

by David Gilbert

== String Routines == * Built and tested a newlib with my memchr in - ready to go with a bit of tidy up. * Followed up on my eglibc patch submission by a comment suggesting the use of --with-cpu pointing back at the previous discussion. == 64 Bit atomics == * Updated gcc patch based on Ramana's comments, retested and posted new version - Lost half a day to a failing SD card in our panda. == QEMU == * Posted a patch that made one variable thread local using __thread that fixes multi threaded user mode ARM programs (e.g. firefox); this seems to have mutated on the list into a patch for more general thread local support. Dave

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[ACTIVITY] Oct 04 - Oct 07

by Ulrich Weigand

== GDB == * Reimplemented patch to disable address space randomization in gdbserver to respect the "set disable-randomization" command, and checked it in to mainline and Linaro GDB 7.3 * Worked on support for cross-platform core file generation. == GCC == * Checked in mainline fix for PR 50305. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

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[ACTIVITY] October 2-6

by Ira Rosen

Hi, - worked on the RTL part of the widen-shift patch - backported to linaro 2/3 of the SLP patches, and proposed the third one - worked on additional SLP improvements: - swap operands to make statements isomorphic - support load with offset 1 (after load from 0) - started working on presentation for NEON forum Upcoming holidays: Oct 12, Wed - half day Oct 13, Thu Oct 16-19, Sun-Wed - half day Oct 20, Thu Ira

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[RFC ARM] Use vcvt.f32.s32 with immediate bits to do fixed to floating point conversions.

by Ramana Radhakrishnan

Hi, So one of the things Michael pointed out in today's call was that the ARM backend doesn't generate vcvt.f32.s<type> where you have an idiom conversion from fixed to floating point as in the example below. I've chosen to implement this in the following manner in the backend using these interfaces from real.c . The reason I've chosen to not allow this transformation in case flag_rounding_math is true is because this instruction always ends up rounding using round-to-nearest rather than obeying whats in the FPSCR and thus is not safe for programs that want to dynamically set their rounding modes. The benefits are quite obvious in that we eliminate a load from the constant pool and a floating point multiply and thus essentially shaving off a floating point multiply + Load latency off these sequences. This instruction can only write the output into the same register as the input register which is why I've modelled it as below by tying op1 into op0. If there's a simpler way of using the interfaces into real.c then I'm all ears ? Thoughts ? I believe such idioms are used in libav from where the original report appears to have come and thus it's a worthwhile gain where we can have it. Any other places where folks might have noticed this. I will post upstream as well once I finish testing this patch. I'm posting this here to get some feedback as well to let anyone who is really really keen about trying this out have a go given I'm out tomorrow. ( I took a quick look at the short -> f32 case as well but the fact remains that loads either zero or sign extend anyway so there's probably not much gain in modelling that right away and the win really is in getting rid of that fp mul and the constant pool load. There's probably some gain in going from i64-> f64 as well so those patterns need to be written up at some point for completeness ) cheers Ramana 2011-10-04 Ramana Radhakrishnan <ramana.radhakrishnan(a)linaro.org> * config/arm/arm.c (vfp3_const_double_for_fract_bits): Define. * config/arm/arm-protos.h (vfp3_const_double_for_fract_bits): Declare. * config/arm/constraints.md ("Dt"): New constraint. * config/arm/predicates.md (const_double_vcvt_power_of_two_reciprocal): New. * config/arm/vfp.md (*arm_combine_vcvt_f32_s32): New. (*arm_combine_vcvt_f32_u32): New. For the following testcases I see the code as follows with -mfloat-abi=hard -mfpu=vfpv3 and -mcpu=cortex-a9 float foo (int i) { float v = (float)i / (1 << 11); return v; } float foa_unsigned (unsigned int i) { float v = (float)i / (1 << 5); return v; } After patch . foo: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. fmsr s0, r0 @ int vcvt.f32.s32 s0, s0, #11 bx lr .size foo, .-foo .align 2 .global foa_unsigned .type foa_unsigned, %function foa_unsigned: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. fmsr s0, r0 @ int vcvt.f32.u32 s0, s0, #5 bx lr .size foa_unsigned, .-foa_unsigned .align 2 .global foo1 .type foo1, %function rather than .type foo, %function foo: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. fmsr s15, r0 @ int fsitos s0, s15 flds s15, .L2 fmuls s0, s0, s15 bx lr .L3: .align 2 .L2: .word 973078528 .size foo, .-foo .align 2 .global foa_unsigned .type foa_unsigned, %function foa_unsigned: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. fmsr s15, r0 @ int fuitos s0, s15 flds s15, .L5 fmuls s0, s0, s15 bx lr .L6: .align 2 .L5: .word 1023410176

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[ACTIVITY] 26th - 30th September

by Andrew Stubbs

* Vacation Monday, Tuesday, and Wednesday. * GCC Continued work on my constant reuse optimizations. Disappointingly, I've found that there are very few optimization opportunities in EEMBC (ARM/Thumb V7-A), although it's not difficult to write testcases that the optimization could improve. I also discovered that the data-flow chains don't work exactly how I thought (with respect to if-then-else cases) so I need to do a little more work. Pinged the native tuning patches; they're still waiting for upstream review. Still can't get the generic tuning work done as the CodeSourcery panda boards appear to be still offline.

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[ACTIVITY] Weekly status

by Revital Eres

Committed to mainline the patch to support instructions with auto-inc operations in SMS after addressing Ayal's comments. The patch contains two parts; one of them fixes a bug revealed during bootstrapping with the patch and SMS flags. http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01988.html http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01987.html Looking at estimating register pressure with SMS: based on previous discussion with Richard the current approach is to try and use the register pressure estimation in loop invariant pass.

14 years, 1 month

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undefined reference to __aeabi_unwind_cpp_pr0

by AJ ONeal

I'm compiling an application built with TI's DVSDK 3 *[0]. /home/user/ti/dvsdk/dvsdk_3_01_00_10/linuxutils_2_25_02_08/packages/ti/sdo/linuxutils/cmem/lib/cmem.a470MV(cmem.o470MV):(.ARM.exidx+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.5.2-5ubuntu2~ppa1) 4.5.2 arm-linux-gnueabi-ld --version GNU ld (GNU Binutils for Ubuntu) 2.21.0.20110302 More full output is here (but it isn't particularly helpful due to TI's RTSC make system's black-magic) https://gist.github.com/925674 FYI: the MV in cmem.a470MV stands for MontaVista. This name is hard-coded somewhere even though it's not being linked against a MontaVista system. I believe the 470 means that it should work with ARMv4 through ARMv7, but I'm not positive. My googling suggest that this is a toolchain bug and that the best way around the issue is to create a file which defines the function as a void dummy and include it. http://www.codesourcery.com/archives/arm-gnu/msg03604.html http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/78649 http://www.cs.fsu.edu/~baker/devices/lxr/http/ident?i=__aeabi_unwind_cpp_pr0 I have a script that I'll post shortly with instructions as to how to setup TI's DVSDK with Linaro AJ ONeal [0] I'm not using the latest DVSDK version 4 because the paths and such are so hard-coded for the 2009q3 version of codesourcery on ubuntu 10.04 LTS that I don't know where to start fixing it.

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[ACTIVITY] Week ending 30th September 2011.

by Ramana Radhakrishnan

===Progress=== * Patch review week. * Looked at bootstrap issue for a while but Richard Sandiford picked it up and sorted it out (Thanks Richard). * Fun and games with some paperwork. * Some backporting and testing patches. (50099 and 50186) underway. === Plans === * Clear out some of the old patches (POST_MODIFY_DISP for vfp, BRANCH_COST ) and finish on auto-inc-dec patch from last week. * Away for 1 day next week. Meetings: * 1-1s * TCWG calls Absences. * 5th October -Out of Office. * 13th - 14th October - Internal training. * 31st Oct - 4th Nov - Linaro Summit Orlando. * 08 Nov - 11 Nov - Tentatively booked * Dec 19 - 31st Dec - Tentatively booked

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[ACTIVITY] report week 39

by Peter Maydell

(short week: 3 days) RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||add-omap3-networking || 2011-10-13 || 2011-10-13 || || ||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || 2011-09-22 || ||a15-usermode-support || 2011-11-10 || 2011-11-10 || || ||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 || == a15-usermode-support == * completed the implementation and testing of fused-mac instructions; posted patch series with these and udiv/sdiv == other == * lightning talk for pdsw doughnut session Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Applied patch for doing NEON high/low extraction using subregs. Ramana pointed out that we do the same thing for insertion, so I wrote a patch to handle that too. Both now merged into Linaro sources. * Looked at ARM bootstrap problem on trunk. Turned out to be an aliasing problem. Submitted and applied patch. * Reworked part of my SMS register-scheduling patch after feedback from Ayal. Submitted new version upstream. * Got SPEC2006 running on the powerpc boxes and tested one part of my -fsched-pressure patch. Bit of a mixed bag. h264ref was one of the worst sufferers, which was a bit worrying. I think I'll need to make a third change too. To recap, there are two pieces now: 1) Make -fsched-pressure honour the DFA 2) Make -fsched-pressure allow values that are live across a loop to be spilled. I naively hoped that (1) would be OK on its own, but h264 shows that the current -fsched-pressure code is very conservative when it comes to large blocks. It only considers register deaths once there is a single remaining use; if there are two unscheduled uses, it assumes that the register remains live for the rest of the block. So the problem that (1) was fixing was that -fsched-pressure was too optimistic in terms of what it could schedule in a cycle. But with that fixed, we seem to have too many sources of pessimism... Richard

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[ACTIVITY] Sep 26 - Sep 30

by Ulrich Weigand

== GDB == * Worked on support for cross-platform core file generation. * Followed up on patch to support disabling address space randomization in gdbserver. == GCC == * Followed up on patch for PR 50305. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 1 month

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[ACTIVITY] w39

by Asa Sandahl

* Working on croos-compiling Firefox. Getting dependencies in place and setting up the configuration file (.mozconfig). I have had the strategy to fix one dependency at a time, picking prebuilt packages or building my self. Michael told me at yesterday's meeting about multistrap, that could possibly be used for fixing all dependencies at once. I will look into that next week. * During this process I have also spent some time reading up on cross compilation in general and also on autoconf and the GNU build system. Best Regards Åsa

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[ACTIVITY] 2011-09-28

by David Gilbert

== String routines == * Got eglibc testing setup happy at last - Note that -O3 builds generally seem to give a few more errors that are probably worth looking at - -march=armv6 -mthumb hit some non-thumb1 instructions (normally non-lo registers), again worth looking at - Cross testing to Qemu user mode often stalls, mostly on nptl tests that abort/fail when run in system/natively * Sent new version of eglibc/memchr patch upstream * Now have working newlib test setup and reference set - next step is to try adding my memchr there == Other == * Testing a QEmu patch with Peter * Looking at bug 861296 (difference in mmap layouts) * Adding a few suggestions to the set of cpu hotplug tests. * Dealing with the Manchester lab cold. Short week; back on Monday Dave

14 years, 1 month

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[ACTIVITY] September 25-28

by Ira Rosen

Hi, * change default vector size patch - merged to linaro-gcc * SLP improvements committed upstream: - allow not affine accesses - auto-detect vector size - support multiple types and promotion/demotion operations Ira

14 years, 1 month

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[ACTIVITY] Sep 19 - Sep 23

by Ulrich Weigand

== GDB == * Committed hardware watchpoint support for gdbserver to mainline, including two minor changes resulting from review comments; backported those fixes to Linaro GDB as well. * Implemented and tested support for disabling address space randomization in gdbserver; patch posted for review. * Investigated support for cross-platform core file generation. == GCC == * Patch review week. * Posted updated patch for PR 50305. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

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Re: try_to_freeze() called with IRQs disabled on ARM

by Ulrich Weigand

Arnd Bergmann <arnd(a)arndb.de> wrote on 08/26/2011 04:44:26 PM: > On Thursday 25 August 2011, Russell King - ARM Linux wrote: > > > > Arnd, can you test this to make sure your gdb test case still works, and > > Mark, can you test this to make sure it fixes your problem please? > > Hi Russell, > > The patch in question was not actually from me but from Ulrich Weigand, > so he's probably the right person to test your patch. > I'm forwarding it in full to Uli for reference. Hi Arnd, hi Russell, sorry for the late reply, I've just returned from vacation today ... I've not yet run the test, but just from reading through the patch it seems that this will at least partially re-introduce the problem my original patch was trying to fix. The situation here is about GDB performing an "inferior function call", e.g. via the GDB "call" command. To do so, GDB will: 0. [ Have gotten control of the target process via some ptrace intercept previously, and then ... ] 1. Save the register state 2. Create a dummy frame on the stack and set up registers (PC, SP, argument registers, ...) as appropriate for a function call 3. Restart via PTRACE_CONTINUE [ ... at this point, the target process runs the function until it returns to a breakpoint instruction and GDB gets control again via another ptrace intercept ... ] 4. Restore the register state saved in [1.] 5. At some later point, continue the target process [at its original location] with PTRACE_CONTINUE The problem now occurs if at point [0.] the target process just happened to be blocked in a restartable system call. For this sequence to then work as expected, two things have to happen: - at point [3.], the kernel must *not* attempt to restart a system call, even though it thinks we're stopped in a restartable system call - at point [5.], the kernel now *must* restart the originally interrupted system call, even though it thinks we're stopped at some breakpoint, and not within a system call My patch achieved both these goals, while it would seem your patch only solves the first issue, not the second one. In fact, since any interaction with ptrace will always cause the TIF_SYS_RESTART flag to be *reset*, and there is no way at all to *set* it, there doesn't appear to be any way for GDB to achive that second goal. [ With my patch, that second goal was implicitly achieved by the fact that at [1.] GDB would save a register state that already corresponds to the way things should be for restarting the system call. When that register set is then restored in [4.], restart just happens automatically without any further kernel intervention. ] One way to fix this might be to make the TIF_SYS_RESTART flag itself visible to ptrace, so the GDB could save/restore it along with the rest of the register set; this would be similar to how that problem is handled on other platforms. However, there doesn't appear to be an obvious place for the flag in the ptrace register set ... Bye, Ulrich

14 years, 1 month

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Use of memcpy() in libpng

by Michael Hope

Saw this on the linaro-multimedia list: http://lists.linaro.org/pipermail/linaro-multimedia/2011-September/000074.h… libpng spends a significant amount of time in memcpy(). This might tie in with Ramana's investigation or the unaligned access work by allowing more memcpy()s to be inlined. -- Michael

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[ACTIVITY] Weekly status

by Revital Eres

Debugging the new version of the patch to support instructions with REG_INC_NOTE in SMS which caused bootstrap failure. (http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01216.html) A fix was tested and submitted: [PATCH, SMS 1/2] Avoid generating redundant reg-moves http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01549.html [PATCH, SMS 2/2] Support instructions with REG_INC_NOTE (second try) http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01550.html Continued looking at Richard's libav micro-bench wrt the register pressure. Richard pointed on some kernels that can serve as a testcases. Participated in non linaro activities.

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[ACTIVITY] 2011-09-23

by David Gilbert

== String routines == * Having got agreement on ignoring the triplet for picking the routine, I'm just testing a patch, but fighting a qemu setup. * Found the binfmt binding for armeb was wrong (runs the le version); filed bug with fix in Dave

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[Activity] Week ending 23/09/2011

by Ramana Radhakrishnan

==GCC== Combined report for last 2 weeks - ===Progress=== * Committed conditional compares patch to Linaro GCC 4.6 * Looking at modelling auto-inc-decs better . * Tried patch for PR19599 and that broke bootstrap with a segfault. Needs some re-engineering. * Looked at the latest bootstrap failure on trunk. Still narrowing down. * Some work on some administrative stuff * Bit of patch review. * Went for LLVM dev meeting. * Release week had a few issues and helped dry-run cbuild spawns of jobs and think I now know how to do that. === Plans === * finish looking at bootstrap failure. * Finish auto-inc-dec patch. * some more patch review. * Send out LLVM dev meeting report. Absences. * 5th October - Out of office. * 13th -14th October - Internal ARM training. * 31st Oct - 4th Nov - Linaro Summit Orlando * 08 Nov - 11 Nov - Tentatively booked * Dec 19 - 31st Dec - Tentatively booked

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[ACTIVITY] report week 38

by Peter Maydell

(short week: 4 days) RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||add-omap3-networking || 2011-10-13 || 2011-10-13 || || ||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || 2011-09-22 || ||a15-usermode-support || 2011-11-10 || 2011-11-10 || || ||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 || == a15-system-mode-planning == * now complete: we have generated blueprints/roadmap cards for the TSC for the various options == a15-usermode-support == * tested udiv/sdiv implementation * fused mac: rough idea of what needs to be done, need to get all the fiddly details right == omap3 upstreaming == * rebased and sent pullreq for various outstanding patches == other == * code/design walkthrough for upstream's new memoryregion API * working on lightning talk for pdsw doughnut session next week * investigated compile failure building QEMU in thumb mode with debug enabled (we're trying to use the Thumb framepointer register as a temporary...) * meetings: toolchain, standup, 1-2-1 Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences (to end of year): Sep 29-Oct 07, Oct 17, Nov 21, Dec 15-Jan 03: leave Oct 30-Nov 04: Linaro Connect Q4.11

14 years, 1 month

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Submitted a fix for the performance regression caused by my arm_comparison_operator patch. Applied upstream after approval from Ramana (thanks). Will backport to Linaro towards the end of next week if there are no reported problems. * Went back to looking at -fsched-pressure. To recap, a colleague ran SPEC for s390 comparing: (a) normal -O3 based flags (b) (a) + -fsched-pressure without my patch (c) (a) + -fsched-pressure with my patch (c) got the best geomean result, but there were some individual tests for which (b) was significantly worse than (a), and for which (c) only partly closed the gap. Found one problem. It looks like -fsched-pressure only really operates on the issue rate and instruction latencies; it doesn't seem to use the DFA. This seems to be unintentional, and fixing it showed some nice results. Also, the -fsched-pressure patch that I wrote at Connect set the starting pressure based on the set of registers that are both live on entry to the block _and_ used within the enclosing loop, This still seems to be a bit too conservative, in that it makes the scheduler go out of its way to preserve loop invariants, even if there are too many of them. Experimented with changing "used" to "defined". This too seemed to be a win. * Got access to some PowerPC GNU/Linux machines that are suitable for running SPEC. Set up my account there and got SPEC building. The idea is to use this to get more cross-target evidence for the -fsched-pressure submission(s). * Discussion about the SMS register-scheduling patches after great feedback from Ayal. While drafting a still-unsent reply justifying the main part of the patch, I found I was also explaining why another part of the patch (specifically the prologue/epilogue part) was wrong. Thought about that a bit today. * Submitted fix for LP 641126. == Next week == * More SMS register scheduling. * More -fsched-pressure. * Hopefully remerge the arm_comparison_operator patch with this week's fix. Richard

14 years, 1 month

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[ACTIVITY] w38

by Asa Sandahl

* Working on getting everything in place for cross-compiling Firefox for ARM. Trying to understand how the configuration script and make file works. * Working on a test that will run Sunspider and extract the results. The challenging part is that results are only presented on the page, not e.g. written to stdout or to file. My approach to create an html file, embed the page with the test in an iframe, and read out the results when the test is done. * Running SPEC2K on the Snowball board. An updated kernel solved the issue with great variations in the test results. Some tests results look a bit strange, so I will look at what those tests do to see what part of the system is stressed. Best Regards Åsa

14 years, 1 month

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[ACTIVITY] September 18-22

by Ira Rosen

Hi, * widening shifts patch - submitted upstream * change default vector size patch - submitted to linaro-gcc * automatic choice of vector size for basic block vectorization - testing * vectorizer bug fixes Next week we have New Year holiday on Wednesday (half day) and Thursday. Ira

14 years, 1 month

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Linaro GCC 4.6 and 4.5 2011.09 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the 2011.09 release of both Linaro GCC 4.6 and Linaro GCC 4.5. Linaro GCC 4.6 2011.09-1 is the seventh release in the 4.6 series. Based off the latest GCC 4.6.1+svn178681, it contains a range of vectoriser and core performance improvements as well as fixing a number of bugs. Interesting changes include: * Updates to 4.6.1+svn178681 * Improves performance by making better use of conditional compares * Improves performance by properly scheduling widening multiplies * Improves size and speed by improving constant generation in Thumb-2 * Implements support for widening multiples in toe core * Improves vectorised code by reducing the over-promotion of intermediates * Improves performance by reducing redundant moves between VFP and ARM * Finishes off supporting the Android team in integrating Linaro GCC Fixes: * LP: #823548 Can't use -flto with skia * LP: #823711 libvirt version 0.9.2-4ubuntu8 failed to build on armel * LP: #827990 internal compiler error: in decode_addr_const, at varasm.c:2632 * LP: #836401 ICE on a | (b << negative-constant) * LP: #838994 ICE building perl w/ -marm * LP: #843775 ICE optimizing widening multiply-and-accumulate Linaro GCC 4.5 2011.09 is the fourteenth release in the 4.5 series. Based off the latest GCC 4.5.3+svn178560, this is a maintenance focused release. Interesting changes in 4.5 include: * Updates to 4.5.3+svn178560 Fixes: * LP: #823711 libvirt version 0.9.2-4ubuntu8 failed to build on armel The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2011.09 https://launchpad.net/gcc-linaro/+milestone/4.5-2011.09 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.6/4.6-2011.09 https://launchpad.net/gcc-linaro/4.5/4.5-2011.09 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? inquire at support(a)linaro.org -- Michael

14 years, 1 month

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Bootstrapping GCC in PGO, LTO, and SMS modes

by Michael Hope

I tried to bootstrap current GCC trunk and our latest gcc-linaro-4.6 in profile guided, link time optimisation, and SMS modes. The results are here: https://wiki.linaro.org/MichaelHope/Sandbox/PGOLTOSMSStatus1 Short story: you can't bootstrap in LTO or PGO on ARM as they run out of memory. i686 LTO is broken on trunk and gcc-linaro-4.6. SMS is fine in general. I'll run these once a week and keep an eye on them. A -fwhopr instead of -flto may help on ARM. I don't know why the PGO build runs out of memory. -- Michael

14 years, 1 month

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libav IDCT speed tests

by Michael Hope

Måns pointed me at the IDCT throughput test that's included with libav. I've written up a page on how to build and run it at: https://wiki.linaro.org/MichaelHope/Sandbox/LibAvDCT Included are results with and without the vectoriser. In all cases the vectoriser improves things, including increasing the SIMPLE-C version by 11 % and the peak by 17 %. The coefficient of variance is low so the results are consistent. I haven't investigated the benchmark itself to see if its valid - we could be vectorising the loop overhead instead of the IDCT itself. -- Michael

14 years, 1 month

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Implicit-it upstream discussion.

by Andrew Stubbs

Hi Michael, Here's the gcc-patches@ discussion you asked for: http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01339.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01351.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01353.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01354.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01355.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01356.html http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01357.html Andrew

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Re: eglibc and fun with config.sub

by Michael K. Edwards

Please coordinate with Jon Masters at RedHat/Fedora and Adam Conrad at Ubuntu/Debian on this. (Cc'ing the cross-distro list, through which the recent ARM summit at Linux Plumbers was organized.) Cheers, - Michael On Sep 16, 2011 8:41 AM, "David Gilbert" <david.gilbert(a)linaro.org> wrote: > OK, so we seem to have agreement here that what we want is autodetect > for eglibc and > forget about the triplet; well technically that probably makes my life > easier, and I don't > think it's too hard a sell. > > Dave > > _______________________________________________ > linaro-toolchain mailing list > linaro-toolchain(a)lists.linaro.org > http://lists.linaro.org/mailman/listinfo/linaro-toolchain

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[ACTIVITY] 12th - 17th September

by Andrew Stubbs

* Linaro GCC Spun 4.5 and 4.6 2011.09 GCC release tarballs. Uploaded them to Michael's server, and kicked off the tests. Continued work on my new constant optimization experiments. I now have it tracking all the constants and am looking at how to detect the optimization opportunities. So far it only calculates how exprensive it would be to generate a value by adding to an existing constant, which is a start at least. I'm having difficulties detecting whether changing an insn will make it's parent (dependency-wise) obsolete, or not (and therefore whether to count its costs - there's no problem for instructions that overwrite an entire register, but ones that write to portions of registers (such as MOVT) make more complex dependency chains, and the def-use chains don't seem to be sorted into the order of use. * Other Half day vacation on Thursday.

14 years, 1 month

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gcc segfaults when building v8 (nodejs)

by AJ ONeal

Using the Linaro prebuilt package from a few days ago I got a segfault in gcc that is not manifest in a version from a few months earlier. Details are here: https://gist.github.com/1223209 A small snippet: g++ -o obj/release/jsregexp.o -c -fno-rtti -fno-exceptions -Wall -W -Wno-unused-parameter -Wnon-virtual-dtor -Wno-abi -pedantic -mfloat-abi=softfp -O3 -fomit-frame-pointer -fdata-sections -ffunction-sections -ansi -fno-strict-aliasing -DCAN_USE_VFP_INSTRUCTIONS -DUSE_EABI_HARDFLOAT=0 -DV8_TARGET_ARCH_ARM -DENABLE_DEBUGGER_SUPPORT -I/home/user/Code/node/deps/v8/src /home/user/Code/node/deps/v8/src/jsregexp.cc g++: Internal error: Segmentation fault (program as) Please submit a full bug report. See <file:///usr/share/doc/gcc-4.5/README.Bugs> for instructions. scons: *** [obj/release/jsregexp.o] Error 1 scons: building terminated because of errors. Waf: Leaving directory `/home/user/Code/node/out' Build failed: -> task failed (err #2): {task: libv8.a SConstruct -> libv8.a} make: *** [program] Error 1 user@linaro-developer:~/Code/node$ uname -a Linux linaro-developer 3.0.0-1004-linaro-omap #5~ppa~natty-Ubuntu SMP PREEMPT Mon Aug 22 08:44:20 UTC 2011 armv7l armv7l armv7l GNU/Linux user@linaro-developer:~/Code/node$ gcc -v Using built-in specs. COLLECT_GCC=gcc COLLECT_LTO_WRAPPER=/usr/lib/arm-linux-gnueabi/gcc/arm-linux-gnueabi/4.5.2/lto-wrapper Target: arm-linux-gnueabi Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.5.2-8ubuntu4' --with-bugurl=file:///usr/share/doc/gcc-4.5/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.5 --enable-shared --enable-multiarch --with-multiarch-defaults=arm-linux-gnueabi --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib/arm-linux-gnueabi --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.5 --libdir=/usr/lib/arm-linux-gnueabi --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-gold --enable-ld=default --with-plugin-ld=ld.gold --enable-objc-gc --disable-sjlj-exceptions --with-arch=armv7-a --with-float=softfp --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabi --host=arm-linux-gnueabi --target=arm-linux-gnueabi Thread model: posix gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4) AJ ONeal

14 years, 1 month

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[ACTIVITY] Weekly status

by Revital Eres

* Added testcases to Richard's micro benchmarks taken from libav. * Discussed with Ayal the new version of the patch to support instructions with REG_INC_NOTE in SMS which causes bootstrap failure. I intend to debug the bootstrap failure in order to find the cause for it. (http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01216.html)

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[ACTIVITY] 2011-09-16

by David Gilbert

== String routines == * Tidying up bits of cortex strings for the release process * Nailing down the behaviour of config.sub and the config systems in gcc, binutils and eglibc == Other == * A discussion on synchronisation primitives on various CPUs that started on the gcc list - looking at http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html - pointing out the 64bit instructions - asking why they used isb's when neither the kernel or gcc use them (answer the DMBs should be fine as well, but there is some debate over which is quicker, oh and DMBs are converted to slower dsb's on most A9s due to an errata). * Looking for docs on the non-core bits of current SoCs * Extracting some denbench stats from a few months back for Ramana About a day of non-Linaro IBM stuff. Dave

14 years, 1 month

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[ACTIVITY] report week 37

by Peter Maydell

RAG: Red: Amber: Green: NB: since qemu-linaro releases demonstrably go out on schedule every month I'm dropping them from the milestone tables in these reports, in favour of blueprint completion dates (usually they'll be planned for dates coinciding with a qemu-linaro release). Current Milestones: || || Planned || Estimate || Actual || ||add-omap3-networking || 2011-10-13 || 2011-10-13 || || ||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || || ||a15-usermode-support || 2011-11-10 || 2011-11-10 || || ||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 || == linaro-qemu-11.11 == * completed this month's release == add-omap3-networking == * investigated why qemu's usb-net model didn't work on the beagle; this was due to a bug in the usb-ohci controller model; patches sent upstream. Fix will go into qemu-linaro 2011-10. == a15-system-mode-planning == * wrote up options and my suggestion on the wiki: https://wiki.linaro.org/PeterMaydell/QemuA15 * just need to discuss with Michael and turn this into a roadmap entry == a15-usermode-support == * complete but untested implementation of UDIV and SDIV * fused multiply-accumulate: implemented decode, and the special-cases parts of the softfloat implementation (NaN, inf, etc); the difficult bit of actually implementing the operation remains == other == * meetings: toolchain, pdsw doughnuts, AFDS Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences (to end of year): Sep 19, Sep 29-Oct 07, Oct 17, Nov 21, Dec 15-Jan 03: leave Oct 30-Nov 04: Linaro Connect Q4.11

14 years, 1 month

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eglibc and fun with config.sub

by David Gilbert

As mentioned on the standup call this morning, I've been trying to get my head around the way different parts of the toolchain using the config scripts and the triplets. I'd appreciate some thoughts on what the right thing to do is, especially since there was some unease at some of the ideas. My aim here is to add an armv7 specific set of routines to the eglibc ports and get this picked up only when eglibc is built for armv7; but it's getting a bit tricky. eglibc shares with gcc and binutils a script called config.sub (that lives in a separate repository) which munges the triplet into a $basic_machine and validates it for a set of known triplets. So for example it has the (shell) pattern: arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] to recognise triplets of the form arm- armbe- armle- armel- armbe- armv5- armv5l- or armv5b- It also knows more obscure things such as if you're configuring for a netwinder it's an armv4l- system running linux - but frankly most of that type of thing are a decade or two out of date. Note it doesn't yet know about armv6 or armv7. eglibc builds a search path that at the moment includes a path under the 'ports' directory of the form arm/eabi/$machine where $machine is typically the first part of your triplet; however at the moment eglibc doesn't have any ARM version specific subdirectories. If I just added an ports/sysdeps/arm/eabi/armv7 directory it wouldn't use it because it searches in arm/eabi/arm if configured with the triplet arm-linux-gnueabi or --with-cpu sets $submachine (NOT $machine) - so if you pass --with-cpu=armv7 it ends up searching arm/eabi/arm/armv7 if you used the triplet arm-linux-gnueabi. If you had a triplet like armel then I think it would be searching arm/eabi/armel/armv7 So my original patch ( http://old.nabble.com/-ARM--architecture-specific-subdirectories,-optimised… ) did the following: * Modified the paths searched to be arm/eabi (rather than arm/eabi/$machine) * If $submachine hadn't been set by --with-cpu then autodetect it from gcc's #defines which meant that it ignored the start of the triplet and let you specify --with-cpu=armv7 After some discussion with Joseph Myers, he's convinced me that isn't what eglibc is expecting (see later in the thread linked above); what it should be doing is that $machine should be armv7 and $submachine should be used if we wanted say a cortex-a8 or cortext-a9 specific version. My current patch: * adds armv6 and armv7 to config.sub * adds arm/eabi/armv7 and arm/eabi/armv6t2 and one assembler routine in there. * If $machine is just 'arm' then it autodetects from gcc's #defines * else if $machine is armv.... then that's still $machine So if you use: a triplet like arm-linux-gnueabi it looks at gcc and if that's configured for armv7-a it searches arm/eabi/armv7 a triplet like armv7-linux-gnueabi then it searches arm/eabi/armv7 irrespective of what gcc was configured for a triplet like armv7-linux-gnueabi and --with-cpu=cortex-a9 then it searches arm/eabi/armv7/cortex-a9 then arm/eabi/armv7 As far as I can tell gcc ignores the first part of the triplet, other than noting it's arm and spotting if it ends with b for big endian; (i.e. configuring gcc with armv4-linux-gnueabi and armv7-linux-gnueabi ends up with the same compiler). binutils also mostly ignores the 1st part of the triple - although is a bit of a mess with different parts parsing it differently (it seems to spot arm9e for some odd reason); as far as I can tell gold will accept armbe* for big endian where as ld takes arm*b ! If you're still reading, then the questions are: 1) Does the approach I've suggested make sense - in particular that the machine directory chosen is based either on the triplet or where the triplet doesn't specify the configuration of gcc; that's my interpretation of what Joseph is suggesting. 2) Doing (1) would seem to suggest I should give config.sub armv6t2 and some of the other complex names. Dave

14 years, 1 month

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Reviewed patches for the release. * ...then broke the release. Tried to spin a new one. * Worked on a "real" fix for bug 850099. Now in testing. * Looked more at auto-inc-dec stuff. Saw a case that didn't behave as I expected on the A9. The A9 TRM doesn't describe what happens for post-indexed addressing, so I asked Ramana. Apparently the behaviour is expected. Once I have more info, I'll try to update the patches. * Worked on neon-highlow-extract and neon-strided-load-extract. Posted the three patches upstream. Nicely, the one I thought was going to be the most controversial actually got positive feedback from Paolo (who wrote the affected code). Richard

14 years, 1 month

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[ACTIVITY] Sep 12 - Sep 16

by Ulrich Weigand

== GDB == * Completed hardware watchpoint support for gdbserver. * Tracked down watchpoint resource accounting regression on GDB mainline (not present in 7.3). * Created and published Linaro GDB 7.3-2011.09 release. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 1 month

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[ACTIVITY] w37

by Asa Sandahl

* Running SPEC2K on the Snowball board. A fresh kernel with HIGHMEM enabled made it possible to run the tests. Great variations in the results indicates that something strange is going on. Turning off one of the CPU:s gives stable result (but slow), so my current guess is that the variations are caused by a known bug that makes one cpu run slower. http://igloocommunity.org/bugzilla3/show_bug.cgi?id=1 The patch for this bug was not included in my kernel. Will have another go with a kernel where the patch is included, as a background activity. * Planned and started working on the "Adding browsing benchmarks to our current set of tests"-activity. I will try to keep documentation up to date here: https://wiki.linaro.org/AsaSandahl/Sandbox/BrowsingBenchmarks Experimenting with building Firefox in different ways, so far for x86. Best Regards Åsa

14 years, 1 month

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Re: [Linaro-toolchain-benchmarks] Using u-boot for perf measurements.

by Michael Hope

(bouncing to linaro-dev as it's generally interesting) On Fri, Sep 16, 2011 at 8:17 AM, Ramana Radhakrishnan <ramana.radhakrishnan(a)linaro.org> wrote: > Hi, > > I've been looking at some of the perf regressions we've been seeing > these days in an attempt to understand what's going on in these cases. > While I can use perf and get more statistics and do other things to > figure out why there are perf regressions between 2 binaries along > with perf record and report, I wonder if it is possible to use u-boot > to accurately measure what's going on. I would like to try and get the > values of the performance counters between 2 program points . > > I am aware that there are patches that are floating around that allow > users to set and reset the PMU counters by allowing user level access > to it in the kernel : while that maybe useful to some I'm not sure if > I want to take a chance with some other process getting scheduled that > ends up getting scheduled. Even if there are parts of the kernel that > save and restore PMU counters associated per process with across > context switches . I'm looking for as accurate measurements as > possible in this case and I wonder if u-boot is the best bet for this > ( in the absence of any dedicated hardware debug / trace unit) given > not all of us have one. > > > At the minimum to do this I believe we require u-boot or some start-up code to: > > * Turn on i-cache and d-cache. ( The current u-boot for panda that I > get from the linaro-uboot git repo > git://git.linaro.org/boot/u-boot-linaro-stable.git says "Warning > Caches turned off" when starting up ). Googling around I find a few > patches floating around that turn on the d-cache in August from Aneesh > at TI . We should consider getting these in at some point. > > * Looking in $(UBOOT_TOP)/examples/api I see that there are simple > printf routines and simple stand-alone applications that exist which > could be used for this purpose. The one problem with this is the fact > that u-boot appears to require use of -ffixed-r8 for it's purposes > which *might* mean we need these if we were to use API calls into > standard u-boot functions . I wonder if R8 is used in the current ARM version? There's no reason we can't cherry pick parts such as the serial I/O out into a library and make the app completely self contained. Skip all of the initialisation stuff and assume the boot loader has done it for you. > * Turn on / off speculative prefetching - I believe the kernel does > this already for a few boards, but could this be done in u-boot just > before it launches a test application ? > > * Turn on the VFP and Neon units. > > * Turn on unaligned access so that unaligned accesses are allowed in > the test applications. GCC will now move towards generating unaligned > accesses on versions of the architecture that support it, the patches > upstream have now been approved. > > * Memory map / linker scripts to make sure we are putting things in > the right places (sigh, has to be per-board). But everything goes in RAM so you have one generic linker script and a per board MEMORY definition. Similar to: http://bazaar.launchpad.net/~stm32f-dev/stm32f-dev/stm32f-startup/view/head… ...but even lighter. > We then write a set of library functions that could then look at what > performance counters are of interest to us and track them by resetting > them to 0 and making sure they haven't overflown. > > Has anyone else in the group played with u-boot before or has any > thoughts in this direction ? I am not suggesting that we do this work > right now but it sounds like an interesting thought of where we can > get to with this. My worry is that we miss turning on a feature and get results that aren't representative. That should be easy enough to check by baselineing against a Linux hosted run. We can use NFS or kermit to load the programs. u-boot has a network console which is nice when you don't have serial. This combined with an expect script (or LAVA? Paul?) should automate the whole process. -- Michael

14 years, 1 month

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[ACTIVITY] weekly status

by Ken Werner

Hi, * put the sources of the libunwind android port, the patches for debuggerd and the Android test app online * documented things at: https://wiki.linaro.org/WorkingGroups/ToolChain/Outputs/LibunwindDebuggerd * noticed differences between the old (debuggerd) and the new (debuggerd+libunwind) backtraces * I'm still not sure what's going on (maybe they are adding offsets or something) * however, the backtrace that libunwind does looks sane to me Note: I'll be on vacation till October 7th. Regards Ken

14 years, 1 month

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[ACTIVITY] September 11-15

by Ira Rosen

Hi, * testing widen-shifts patch on ARM * SLP improvements: - submitted a patch to allow not simple ivs in SLP - committed a patch to allow read-after-read dependencies in SLP Ira

14 years, 1 month

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Linaro QEMU 2011.09 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2011.09. Linaro QEMU 2011.09 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. New in this month's release: - linux-user mode now supports the 64 bit cmpxchg kernel helpers (only needed for applications compiled for ARMv6 or lower) - PL111 display controller now supported; this fixes a problem where BGR was interpreted as RGB on recent versatilepb kernels Plus a few other minor bug fixes and the usual round of upstream fixes and improvements. Known issues: - The beagle and beaglexm models still do not support USB networking; we intend to fix this for the 2011.10 release - There may be some problems with running multithreaded programs in linux-user mode (LP:823902) The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2011.09 Binary builds of this qemu-linaro release are being prepared and will be available shortly for users of Ubuntu. Packages will be in the linaro-maintainers tools ppa: https://launchpad.net/~linaro-maintainers/+archive/tools/ More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

14 years, 1 month

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Linaro GDB 7.3 2011-09 released

by Ulrich Weigand

The Linaro Toolchain Working Group is pleased to announce the release of Linaro GDB 7.3. Linaro GDB 7.3 2011.09 is the second release in the 7.3 series. Based off the latest GDB 7.3, it includes a number of ARM-focused bug fixes and enhancements. This release contains: * Support for hardware breakpoints and watchpoints in gdbserver The source tarball is available at: https://launchpad.net/gdb-linaro/+milestone/7.3-2011.09 More information on Linaro GDB is available at: https://launchpad.net/gdb-linaro

14 years, 1 month

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Branch is open

by Michael Hope

Hi there. The 2011.09 release has been spun and is testing up well. The 4.5 and 4.6 branches are now open so feel free to commit any approved patches. -- Michael

14 years, 1 month

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arm-eabi-g++: error: unrecognized option '-avoid-version'

by Asa Sandahl

Hi! When building Android with the Linaro toolchain, I encountered this link time error when going from gcc 4.4.3 to gcc 4.6. "arm-eabi-g++: error: unrecognized option '-avoid-version'" I find several posts about people encountering the same thing for different programs. Was this option removed? Anyone know the story behind it? Regards Åsa

14 years, 1 month

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Blueprints, Headline and Acceptance criteria for monthly releases

by Mounir Bsaibes

Release Management needs the list of the the blueprints that will be delivered this month. For each bp, they want a Headline and Acceptance criteria. The Headline is a statement to include in the Monthly release announcement. The acceptance criteria is a statement how to verify the work is done. I have collected this month's blueprints in the spreadsheet, please review it for accuracy. If a blueprint you are working on is missing, please add it. The Headline and Acceptance can be added into the whiteboard as follows: Headline: headline text Acceptance: acceptance text Once you add the the headline and acceptance, please modify the spreadsheet to reflect that it is done. https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AoZqvK7R1biJdGxSc… Thanks in advance, Mounir -- Mounir Bsaibes Project Manager Follow Linaro.org: facebook.com/pages/Linaro/155974581091106 http://twitter.com/#!/linaroorg http://www.linaro.org/linaro-blog <http://www.linaro.org/linaro-blog>

14 years, 1 month

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[Activity] Weekly report for w/e 2011-09-09

by Ramana Radhakrishnan

==GCC== ===Progress=== * Fixed https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/838994 . Investigated Bernd's alternate patch . Will commit mine. * Looked at PR48308 for sometime whihc might be a dup of PR50313 . * Some blueprint foo. * Committed a few of the outstanding approved patches into Linaro GCC-4.6 * Patch review week * Caught up with email after vacation. === Plans === * Commit conditional compares patch. * Commit the patch for LP838994. * Investigate some of the performance issues with strlen and some of the cases with - one of the ideas is to probably try and get the specific testcases run under u-boot or as a bare-metal binary and look at dumps of various performance monitoring counters and see what's happening. * Look at BRANCH_COST and finish that up next. * Dust off patch for PR19599 . One of them them that has fallen into the cracks. * Some patch review. Meetings: * 1-1s * TCWG calls * Thumb2 performance call. Absences. * 16th Oct (pm) - LLVM developer summit - London * 31st Oct - 4th Nov - Linaro Summit Orlando - Travel booked - hotel to be booked. * 08 Nov - 11 Nov - Tentatively booked not approved. * Dec 19 - 31st Dec - Tentatively booked not approved.

14 years, 1 month

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[ACTIVITY] 5th - 11th September

by Andrew Stubbs

Merged both GCC 4.5 and 4.6 from FSF to Linaro. Matthias requested that I avoid a particular upstream 4.6 commit, so I selected the revision before that as the merge point. The problem was then fixes upstream, and another fix was desirable, so I've redone the merge from the branch head. Another widening-multiplies bug was reported to me (I logged it as pr50318/lp843775), so I've fixed that and committed the fix upstream, and filed a merge request on Launchpad. Finished fixing the bugs in my thumb2 constants optimizations, and backported the new patches to Linaro GCC 4.6. Pushed the updated stuff to Launchpad for testing. Richard Sandiford found a flaw in my patch for pr50193/lp836401, so I've done another version of that and posted it upstream. Ramana didn't like that version. I've started again trying to fix it a different way, but I don't have it working just yet. Continued work on my new constant reuse patch. I have it detecting many constant expressions, and calculating the values for some of them. Once it does that sufficiently well, the next step is to track what constants are available where, I then I'll be in a position to find optimization opportunities. At the moment, 'sufficiently well' could just mean MOVW/MOVT pairs, as those are the most common Tried to get the CS Panda Boards up and running again after the move. No success. Ricardo is on the case. I'm still using the boards located at Canonical. Andrew

14 years, 1 month

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[ACTIVITY] Weekly status

by Revital Eres

Continue looking at Richard's micro benchmarks taken from libav w.r.t SMS and experiment with different patches that Richard wrote to improve code generation. Submitted SMS related patch for minor misc fixes http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00551.html Trying to understand why to new version of the patch to support instructions with REG_INC_NOTE in SMS causes bootstrap failure. Will email to the ml regarding it. (http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01216.html)

14 years, 1 month

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[ACTIVITY] Weekly status

by Richard Sandiford

* Looked at LP bug 736661. Sent a patch upstream. Some positive feedback, but it hasn't been approved or rejected yet. * Looked at the old R_ARM_THM_CALL linker bug, after Matthias prepared a self-contained testcase (thanks). Attached a patch to the bug. Will submit upstream next week if testing goes OK. * Looked at why the backport of lp823708-4.5 retriggered the same bootstrap failure that Chung-Lin's patch did. Haven't been able to reproduce yet. * Looked at making the neon_vget_high/low patterns use ordinary subreg moves. Found that this triggered a fair few latent bugs in the rtl optimisers. Tried to fix those. This gave some nice improvements in some of the libav loops. * Added h264 loops to the libav microbenchmarks. * Blueprints. * Upstream patch review. Richard

14 years, 1 month

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[ACTIVITY] w36

by Asa Sandahl

* Completed First-time wiki page, at least for now. Expecting to add more information as I go. * Running SPEC2K on the Snowball board. The tests are failing because I run out out of memory. This is due to too little RAM available in the default kernel configuration. (Official HW pack.) I had a go with creating a swap file on the SD-card. The tests are then running, but results are slow (which makes sense). Will try to make more memory available with changed uboot-option, or with a fresh kernel. * Discussing with Michael about benchmark candidates that will add a web browsing perspective to the benchmarks we have. I suggest Sunspider and V8 benchmark suite for the JavaScript aspect, and EEMBC Browsing Bench and perhaps ARMBBench for the load and render aspect. As for the imaging aspect we have DENBench and ConsumerBench. Best Regards Åsa

14 years, 1 month

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GCC Trunk r178719 fails to build

by Michael Hope

For reference, trunk r178719 fails to build in an A9 or ARMv5 configuration: http://builds.linaro.org/toolchain/gcc-4.7~svn178719/logs/armv7l-natty-cbui… The error is: /scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/./prev-gcc/g++ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/./prev-gcc/ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/install/armv7l-unknown-linux-gnueabi/bin/ -nostdinc++ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/src/.libs -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/libsupc++/.libs -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/include/armv7l-unknown-linux-gnueabi -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/include -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/gcc-4.7~/libstdc++-v3/libsupc++ -L/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/src/.libs -L/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/libsupc++/.libs -c -g -O2 -gtoggle -DIN_GCC -W -Wall -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Werror -fno-common -DHAVE_CONFIG_H -I. -I. -I../../../gcc-4.7~/gcc -I../../../gcc-4.7~/gcc/. -I../../../gcc-4.7~/gcc/../include -I../../../gcc-4.7~/gcc/../libcpp/include -I../../../gcc-4.7~/gcc/../libdecnumber -I../../../gcc-4.7~/gcc/../libdecnumber/dpd -I../libdecnumber insn-peep.c -o insn-peep.o ../../../gcc-4.7~/gcc/config/arm/arm.md: In function 'const char* output_319(rtx_def**, rtx)': ../../../gcc-4.7~/gcc/config/arm/arm.md:10636:78: error: unknown conversion type character '(' in format [-Werror=format] ../../../gcc-4.7~/gcc/config/arm/arm.md:10636:78: error: unknown conversion type character ')' in format [-Werror=format] /scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/./prev-gcc/g++ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/./prev-gcc/ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/install/armv7l-unknown-linux-gnueabi/bin/ -nostdinc++ -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/src/.libs -B/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/libsupc++/.libs -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/include/armv7l-unknown-linux-gnueabi -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/include -I/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/gcc-4.7~/libstdc++-v3/libsupc++ -L/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/src/.libs -L/scratch/cbuild/slave/slaves/ursa4/gcc-4.7~svn178719/gcc/default/build/prev-armv7l-unknown-linux-gnueabi/libstdc++-v3/libsupc++/.libs -c -g -O2 -gtoggle -DIN_GCC -W -Wall -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Werror -fno-common -DHAVE_CONFIG_H -I. -I. -I../../../gcc-4.7~/gcc -I../../../gcc-4.7~/gcc/. -I../../../gcc-4.7~/gcc/../include -I../../../gcc-4.7~/gcc/../libcpp/include -I../../../gcc-4.7~/gcc/../libdecnumber -I../../../gcc-4.7~/gcc/../libdecnumber/dpd -I../libdecnumber insn-preds.c -o insn-preds.o cc1plus: all warnings being treated as errors -- Michael

14 years, 1 month

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[ACTIVITY] 2011-09-09

by David Gilbert

== String routines == * Trying to understand my strlen behaviour that Michael identified - Found lots of ways of making the faster case slower, but none of making the slower case faster! - Perf not being available on Panda (bug 702999/843628) made it difficult to dig down * Fixing standards corner cases for strchr/memchr - input match needs to be truncated to char (fixes bug 842258 & 791274) * Tidying up formatting for cortex-strings release * Looking at eglibc integration again - getting confused by what has to happen in config.sub and how other users of it cope with triplets like armv7 even though it's not in config.sub == QEMU == * Testing Peter's QEMU release - All good - Lost a few hours due to the broken version of l-i-f-ui in Oneiric - PPA version works OK * A little bit of perf profiling == Other == * Managed to get hold of a nice fast build machine

14 years, 1 month

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[ACTIVITY] Sep 5 - Sep 9

by Ulrich Weigand

== GDB == * Worked on hardware watchpoint support for gdbserver. == GCC == * Analyzed root cause of three more ICEs when building Linux kernel with mainline GCC (reported by Arnd): PR target/50305: Inline asm reload failure when building Linux kernel PR middle-end/50307: SSA checking ICE when building Linux kernel PR tree-optimization/50318: ICE optimizing widening multiply-and-accumulate * Implemented proposed fix for PR target/50305 and posted for review. == Misc == * Installed updated FPGA bitfiles on my Versatile Express and verified that network stability issues (LP #673820) are now fixed. * Booked Linaro Connect Q4.11 travel. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 1 month

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[ACTIVITY] report week 36

by Peter Maydell

RAG: Red: Amber: Green: overrunning OMAP3 upstreaming work (mostly) replanned Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || == upstream-omap3-patches == * more reshuffling of patches and dropping of unnecessary changes (eg code reformatting) * we're going to divide this blueprint into four, each of which has a reasonably clearly defined submilestone and an estimated 3 engineering weeks of work in it * in order to not have work on this completely push out other items on the schedule, we're going to limit work done on this to 2 or 3 days each week * still todo: actually split the blueprint, set dates for submilestones, check that other blueprints fit reasonably in the other half-week == linaro-qemu-11.11 == * built a pre-release tarball and tested it -- looks good for next week's release * investigated whether we can reinstate the firmware blobs in our releases (bringing us back into line with upstream) -- should be possible but need to go through the license approval process since some are GPLv3 == a15-system-mode-planning == * starting to see some (gentle) pressure for A15 support * thinking about what we should do here; my current opinion is that QEMU should implement an "A15 without virtualization or LPAE" -- we have Linux kernels that will boot on this, and it is essentially what an A15-on-A15 hw virt guest would see. The device work will be needed for KVM anyway. Need to write this up. == other == * submitted TSC licensing request to add the firmware blobs back into our qemu-linaro tarballs, in line with how upstream do releases * I need to track better how much time I'm spending on things like code review on qemu-devel, minor bug fixing and other things that aren't blueprints * all holiday to the end of the year now booked (see below) Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences (to end of year): Sep 19, Sep 29-Oct 07, Oct 17, Nov 21, Dec 15-Jan 03: leave Oct 30-Nov 04: Linaro Connect Q4.11

14 years, 1 month

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[ACTIVITY] weekly status

by Ken Werner

Hi, * I've been setting up a new system because the old laptop died * finished the initial port of libunwind for Android on ARM * changed debuggerd to make use of libunwind to unwind the stack of crashing applications * it works and the output looks great :) * I plan to document these things in the wiki by next week Regards Ken

14 years, 1 month

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Added h264 loops to libav microbenchmarks

by Richard Sandiford

Just as an FYI, I've added these loops to the libav microbenchmarks avg-h264-chroma-mc8-8.txt avg-pixels8-8.txt ff-h264-idct-add-8-8.txt ff-put-pixels8x16-8.txt h264-loop-filter-luma-8.txt idct-internal-8.txt put-h264-chroma-mc8-8.txt put-h264-qpel8-h-lowpass-8.txt put-h264-qpel8-hv-lowpass-8.txt put-h264-qpel8-v-lowpass-8.txt based on Michael's h264 profile. These loops: decode_residual ff_h264_decode_mb_cavlc fill_decode_caches aren't really the kind of thing that the microbenchmark is designed for; running the whole h264 benchmark is probably a better test. Some of the functions in the profile just consist of two copies of a simpler loop, one after the other, so for those I just used the simpler loop. Usual microbenchmark caveats apply. Richard

14 years, 1 month

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SMS wiki page

by Revital Eres

Hi, Following our last performance meeting; I started a wiki page which describes how to use SMS: https://wiki.linaro.org/WorkingGroups/ToolChain/UsingSMS Thanks, Revital

14 years, 1 month

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[ACTIVITY] September 4-8

by Ira Rosen

Hi, * merged vector over-promotion patch to linaro-gcc-4.6 * committed upstream the change of the default vector size for NEON * continued working on widening shifts Ira

14 years, 2 months

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Benchmarking / justifying cortex-strings

by Michael Hope

Hi Dave. I've been hacking away and have checked in a couple of benchmarking and plotting scripts to lp:cortex-strings. The current results are at: http://people.linaro.org/~michaelh/incoming/strings-performance/ All are done on an A9. The results are very incomplete due to how long things take to run. I'll leave ursa3 doing these over the weekend which should flesh this out for the other routines. Your new memcpy() is looking good as well - as fast as GLIBC. -- Michael

14 years, 2 months

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Vectorised copy

by Michael Hope

While out benchmarking today, I ran across code similar to this: int *a; int *b; int *c; const int ad[320]; const int bd[320]; const int cd[320]; void fill() { for (int i = 0; i < 320; i++) { a[i] = ad[i]; b[i] = bd[i]; c[i] = cd[i]; } } I was surprised and happy to see the vectoriser kick in for the copy. The inner loop looks like: add r5, r3, ip adds r4, r3, r7 vldmia r2!, {d16-d17} vldmia r1!, {d18-d19} adds r0, r3, r6 vst1.32 {q9}, [r5] vst1.32 {q8}, [r4] vldmia r3, {d16-d17} adds r3, r3, #16 cmp r3, r8 vst1.32 {q8}, [r0] bne .L3 so r3 is the loop variable and {ip,r7} are the offsets from r3 to the destination pointers. Adding a __restrict doesn't change the code. Richard, will your auto-inc/dec changes combine the final vldmia r3, add r3 into a vldmia r3! ? Changing the int *a into in-file arrays like int a[320] gives: vldmia r0!, {d16-d17} vldmia r5!, {d18-d19} vstmia r4!, {d18-d19} vstmia r1!, {d16-d17} vldmia r2!, {d16-d17} vstmia r3!, {d16-d17} cmp r3, r6 bne .L2 Marking them as extern int a[320] goes back to the first form. Can we always use the second form? What optimisation is preventing it? -- Michael

14 years, 2 months

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Re: Memcpy and memset

by Michael Hope

On Fri, Sep 2, 2011 at 4:51 AM, David Gilbert <david.gilbert(a)linaro.org> wrote: > Hi Michael, > I've just committed a pair of memcpy's into src/linaro-a9 - memcpy.S > that is armv7 > and memcpy-hybrid.S that is a Neon hybrid which uses neon for non-aligned cases > and for large (128K or larger) copies. I've also (accidentally) > wired the memcpy-hybrid > one into the Makefile.am (I wasn't sure what the right way to do this > was - the neon_sources > seemed a good place for it, but there is nothing currently in there > that turns off the non-neon > version). > > I'd be interested in seeing the results for both; I've got a bit of > a soft spot for the hybrid > solution. > > On the memset, yes the 'and' that you added is fine - but I started > having a play and have > some performance results (on -t 128) that I don't really understand: > > > 1) and r1,#0xff > orr r1,r1,r1,lsl#8 > orr r1,r1,r1,lsl#16 > > That's your solution - and fastest at somewhere around 2270MB/s for > me - by the TRM I reckon > that should be 3 cycles. > > 2) lsls r1,#24 > orr r1,r1,r1,lsr#8 > orr r1,r1,r1,lsr#16 > > lsl isn't explicitly listed in the TRM, so I assumed that was the > same as a move with a constant > shift, which my reading is that it's a single cycle; and the lsls is 2 > bytes - so you would think > that should be as fast as yours but 2 bytes smaller - except it's > reliably down at 2228MB/s - so > it is slower. > > 3) Thinking it was an alignment issue I tried adding a mov r5,r1 to > the front of that, and got 2248MB/s - > so being faster with an extra instruction it probably was an alignment issue? > > 4) I also tried a pair of bfi's: > bfi r1,r1, #8, #8 > bfi r1,r1, #16, #16 > > That came out at 2228MB/s - and is 4 cycles by the book. Unfortunately you can't tell the performance from the latency. Attached is a micro benchmark that has the three different versions (and, ubx, lsl). After compensating for the loop time, I got: * lsl: 1.006 s * ubx: 0.876 s * and: 0.918 s even though ubx has a latency of two cycles. I then took the AND version and shifted it to the start of the file. This small change in alignment pushed it up to 1.048 s which is 14 % slower. -- Michael

14 years, 2 months

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Agenda - performance call - 2011-09-06

by Ramana Radhakrishnan

Hi, I've put a draft agenda for tomorrow's call at https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-09-06 Is there something else folks would like to add to this ? Follow-up on the cortex-strings discussion from today's call ? cheers Ramana

14 years, 2 months

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[ACTIVITY] 29th - August - 3rd September

by Andrew Stubbs

* Linaro GCC Fixed up, committed and posted two bug fixes to my thumb2 constants patches, found by other people running FSF trunk. Analysed bug lp:836401 / pr50193, developed a fix, and posted it both upstream and to launchpad for testing. The launchpad tests have come back clean, and the patch is approved, but upstream have not approved it yet. Posted a query to linaro-dev mailing list asking for ARM CPU ID register numbers, and got lots back. Entered these into the patch, and begun some test builds. I will post the new verion upstream, if all's well, next week. Started looking at an optimization I discussed with Richard Earnshaw in Cambourne, in which GCC attempts to synthesize constants more efficiently by reusing constant values already in registers. I've made a start, but not much more to say just yet. * Other - Public holiday Monday. - Half day leave on Wednesday. - Internal train session

14 years, 2 months

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[ACTIVITY] Weekly status

by Revital Eres

Continue looking at Richard's micro benchmarks w.r.t SMS. Examining Ayal's comments to the patch to support instructions with REG_INC_NOTE in SMS. (http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01216.html) Took one day off yestarday (4/9)

14 years, 2 months

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Csmith

by Andrew Stubbs

Do we know anything about "Csmith"? Maybe we should try it? Andrew -------- Original Message -------- Subject: Re: [PATCH][ARM] pr50193: ICE on a | (b << negative-constant) Date: Thu, 1 Sep 2011 13:21:38 +0000 (UTC) From: Joseph S. Myers <joseph(a)codesourcery.com> To: Andrew Stubbs <ams(a)codesourcery.com> CC: gcc-patches(a)gcc.gnu.org, patches(a)linaro.org Newsgroups: gmane.comp.gcc.patches References: <4E5F6B5F.2020207(a)codesourcery.com> On Thu, 1 Sep 2011, Andrew Stubbs wrote: > This patch fixes the problem by merely checking that the constant is positive. > I've confirmed that values larger than the mode-size are not a problem because > the compiler optimizes those away earlier, even at -O0. Do you mean that you have observed for some testcases that they get optimized away - or do you have reasons (if so, please state them) to believe that any possible path through the compiler that would result in a larger constant here (possibly as a result of constant propagation and other optimizations) will always result in it being optimized away as well? If it's just observation it would be better to put the complete check in here. Quite of few of the Csmith-generated bug reports from John Regehr have involved constants appearing in unexpected places as a result of transformations in the compiler. It would probably be a good idea for someone to try using Csmith to find ARM compiler bugs (both ICEs and wrong-code); pretty much all the bugs reported have been testing on x86 and x86_64, so it's likely there are quite a few bugs in the ARM back end that could be found that way. -- Joseph S. Myers joseph(a)codesourcery.com

14 years, 2 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, libunwind: * improvements in case the user doesn't use ARM unwind tables but DWARF info * code used to pick ARM unwind from the crt files which says "cantunwind" android: * upgraded working base to 11.08 * continue to port libunwind to android * noticed a header file clash that causes errors * finished an android app that uses a native part to crash the process * as a vehicle to test the modified debuggerd Regards Ken

14 years, 2 months

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[ACTIVITY] Sep 1 - Sep 2

by Ulrich Weigand

== GDB == * Russell King now wants to revert my kernel patch that fixed #615974; discussed alternative options. == GCC == * Patch review week. * Analyzed root cause of ICE when building Linux kernel with mainline GCC (reported by Arnd). Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 2 months

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[ACTIVITY] 2011-09-02

by David Gilbert

== QEmu == * Sent 64bit atomic helper fix upstream * Basic boot time and simple benchmarks v Panda board * Tested prebuilt images and Peter's latest post-merge QEmu tree - The full Ubuntu desktop on an emulated Overo is a bit slow - it's rather short on RAM - The full Ubuntu desktop on an emulated VExpress isn't bad; it's got the full 1G; (with particularly grim line of awk to mount vexpress images based on Peter's suggestion of the use of 'file') == String routines == * Pushed memcpy and memset up to cortex-strings bzr * Working through memset issue with Michael - Made my code a little less sensitive to initial alignment == Hard float == * Testing libffi 3.0.11rc1 - still hasn't got variadic patch in, but hopeing it will land later in the cycle. == Other == * Excavating inbox after week off. * Build LMbench and kicked run off on Panda. (Got stuck in some heuristics under emulation) Dave

14 years, 2 months

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[ACTIVITY] report week 34

by Peter Maydell

(short week; bank holiday on Monday) RAG: Red: Amber: OMAP3 patch upstreaming is (still) slower progress than hoped Green: Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || == upstream-omap3-patches == * omap_gpmc patches were committed upstream * cleaned up and sent usb related patches upstream (accepted) * converted omap interrupt controller to qdev and MemoryRegions, submitted to upstream * went through the patchstack trying to classify the patches in it as a first step in reestimating/replanning this epic blueprint == other == * submitted patches doing some minor cleanup of versatile platform following MemoryRegion conversion * submitted a ppc-host compilation fix patch (accepted) * submitted minor cleanup patch removing an unused makefile target Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: Oct 30-Nov 04: Linaro Connect Q4.11

14 years, 2 months

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Looked at the get_arm_condition_code ICE. Seems to be a popular bug: was reported as #589887 #823708 and #809761 in Lauchpad and as PR49030 in bugzilla. Sent a patch upstream. * Submitted SMS register-dependency patch upstream. * Reviewed Bernd's new shrink-wrap patch. * Tried to clean up my microbenchmarks. Found that preloading the caches at the start of the benchmark fixed the variations I was seeing on a Beagleboard. (As Dave says, it seems that there's no allocation on write.) Added code to check the results of each loop. Packaged it up and pushed into bzr. * An IBM colleague kindly tried my -fsched-pressure patch/hack on s390. Although it performed the best of the three runs (trunk, -fsched-pressure, patch+-fsched-pressure), there were some disappointing outliers. -fsched-pressure still introduces a 7% regression in one test (down from a 14% regression without the patch). Another test benefited from -fsched-pressure without my patch but regressed with it. == Next week == * Look more at SMS. * Look more at the sched-pressure thing (if I get time). Richard

14 years, 2 months

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[ACTIVITY] w35

by Asa Sandahl

* SPEC2K week. Experimented with building and running and finally did a full run on the Panda board. * Running SPEC2K on the Snowball board as well. It is troublesome to work with the board because of the ethernet problem that makes the board freeze after some time. I have to use the SD-card for file transfer. It seems to be a known issue on the Snowball V3. Tested a V5 board which was much more stable. Have asked for a V5 board from ST-E Linaro internal project manager. (Do not know when I will get it.) * Preliminary travel booking done for Linaro Connect in Orlando. Best Regards Åsa

14 years, 2 months

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libav-based microbenchmarks in bzr

by Richard Sandiford

I've tried to clean up the libav microbenchmarks that I did for the strided load/store stuff. They're on Launchpad at: lp:~rsandifo/+junk/loop-microbenchmarks The main changes are that the benchmarks now preload the caches (for CPUs that don't allocate on write) and that they now check the optimised loop against an unoptimised one. The usual big caveat applies: these loops were chosen because they were affected by strided load/stores. They aren't necessarily interesting for any other reason, and some were even explicitly marked as cold. I'm going to add some of the video decode routines from Michael's benchmark soon. These microbenchmarks aren't supposed to be libav-specific though, so if you have other interesting ones, please do add them. Richard

14 years, 2 months

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Trip report: KVM Forum/LinuxCon NA 2011

by Peter Maydell

Trip report: KVM Forum/LinuxCon NA 2011 KVM Forum is an annual conference; this year it was colocated with LinuxCon NA in Vancouver. There were about 150 attendees; many of them are simply users of KVM and so many of the talks are aimed at KVM users. However it's also an opportunity for the KVM and QEMU developer community to get together, with a number of informal BoF sessions and an all-day hackathon later in the week. The talk schedule is here, together with the slides for all talks: http://www.linux-kvm.org/page/KVM_Forum_2011 Some brief highlights: * Keynotes ARM/Linaro got positive mentions in both keynotes; Avi Kivity said of the ARM/A15 KVM work that he had "every reason to expect it to be very successful". Anthony Liguori's keynote summarising the year in QEMU development included some statistics about commits: Linaro came third in the list of "companies with most commits", behind only Red Hat and IBM; I came top of the "individual authors with most commits" list, being apparently responsible for 7% of all QEMU patches this year :-) * KVM on POWER/PPC There were several talks about KVM on PPC architectures; interestingly this is seeing use not just on the server end but also in the embedded/realtime space (including a talk from Freescale where they said they are working on KVM on embedded PPC because of customer demand for KVM). It was also reassuring to see that another architecture has preceded us in shaking out x86-isms from KVM. * KVM Tool This has got headlines recently as a potential replacement for the userspace launcher/device model role which QEMU currently plays when starting guest OSes under KVM. It's intended to be minimal and lightweight and only to run Linux guests (with paravirtualised devices for most purposes). The general reaction seemed to be that although the implementation is currently minimal it will become larger and bloatier as they add features off their wishlist. There's also some ill-feeling about the effective namespace grab of calling the userspace binary "kvm". From an ARM-centric point of view we can just wait and see whether it gets much traction. Possibly it may turn into a testbed for technology which is easier to develop on than the 'mature' QEMU which has to deal with backwards compatibility and supporting users. * QEMU Object Model and Device Model issues and redesign For me one of the most important strands of conversation at the conference was replacing QEMU's device model abstraction with something better. QEMU's current device model abstraction is "qdev"; this is the (vaguely object-oriented) framework which lets you create devices, configure them and connect them together. It models the world as a tree: a root device exposes a bus, to which child devices can connect; those child devices may expose further buses, and so on. This works quite well in the PC world where mostly you're interested in plugging in USB devices, PCI cards, etc; it is rather less well matched to the embedded board models where things are much less hierarchical. qdev's major flaws include: + insists on bus hierarchy, but not everything is a bus, and in any case there are often several trees (memory transactions, clock, interrupts) which don't necessarily coincide + no support for composition ("device foo is actually devices bar and baz glued into one box") + just barely supports having devices expose signal (gpio/irq) lines and memory regions (typically registers), but doesn't let you give them useful names, so you have to access them by index number We spent just about all of Thursday's hacking session going through this. I felt we got good agreement on the problems, and perhaps 80-90% agreement on Anthony Liguori's proposed new QEMU Object Model as a solution to them; some loose ends still need to be worked through. * LinuxCon NA KVM Forum was colocated with LinuxCon NA this year. My opinion (which seemed to be shared with the other Linaro attendees I talked to about it) was that LinuxCon NA suffered from being not very technical and not very focused -- it wasn't clear to me who they thought their target audience was. A few points of interest: + Linus Torvalds' keynote was reported in some places as more complaints about ARM hardware but I actually thought it was pretty positive about the progress we're making in sorting out the issues + Matthew Garrett's talk about x86 platform drivers (those things that deal with LEDs, funny keys, batteries and other odd laptop hardware) revealed that actually PC hardware manufacturers do just as much random non-standard undocumented silliness, it's just that accident of history has limited them to only doing so in the minor bits at the edges... -- PMM

14 years, 2 months

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request for gdb testing

by Nicolas Pitre

Hello Ulrich (or anyone else acquainted with gdb), Could the gdb test suite be run on a kernel with the below patch applied please? A confirmation that this patch doesn't regress gdb is required before this can move ahead. Quick feedback would be greatly appreciated. Thanks. ---------- Forwarded message ---------- Date: Thu, 25 Aug 2011 15:55:58 +0100 From: Russell King - ARM Linux <linux(a)arm.linux.org.uk> To: Tejun Heo <tj(a)kernel.org>, Arnd Bergmann <arnd(a)arndb.de>, Mark Brown <broonie(a)opensource.wolfsonmicro.com> Cc: Rafael J. Wysocki <rjw(a)sisk.pl>, linux-kernel(a)vger.kernel.org, linux-arm-kernel(a)lists.infradead.org Subject: Re: try_to_freeze() called with IRQs disabled on ARM On Thu, Aug 25, 2011 at 03:09:07PM +0200, Tejun Heo wrote: > Hey, Russell. > > If you can fix it properly without going through temporary step, > that's awesome. Let's put the arguments behind, okay? Here's the patch. As the kernel I've run this against doesn't have the change to try_to_freeze(), I added a might_sleep() in do_signal() during my testing to verify that it fixes Mark's problem (which it does.) I've tested functions returning -ERESTARTSYS, -ERESTARTNOHAND and -ERESTART_RESTARTBLOCK, all of which seem to behave as expected with signals such as SIGCONT (without handler) and SIGALRM (with handler). I haven't tested -ERESTARTNOINTR. I don't have a test case for the race condition I mentioned (which is admittedly pretty difficult to construct, requiring an explicit signal, schedule, signal sequence) but this should plug that too. How do we achieve this? Effectively the steps in this patch are: 1. Undo Arnd's fixups to the syscall restart processing (but don't worry, we restore it in step 3). 2. Introduce TIF_SYS_RESTART, which is set when we enter signal handling and the syscall has returned one of the restart codes. This is used as a flag to indicate that we have some syscall restart processing to do at some point. 3. Clear TIF_SYS_RESTART whenever ptrace is used to set the GP registers (thereby restoring Arnd's fixup for his gdb testsuite problem - it would be good if Arnd could reconfirm that.) 4. When we setup a user handler to run, check TIF_SYS_RESTART and clear it. If it was set, we need to set things up to return -EINTR or restart the syscall as appropriate. As we've cleared it, no further restart processing will occur. 5. Once we've run all work (signal delivery, and rescheduling events), and we're about to return to userspace, make a final check for TIF_SYS_RESTART. If it's still set, then we're returning to userspace having not setup any user handlers, and we need to restart the syscall. This is mostly trivial, except for OABI restartblock which requires the user stack to be written. We have to re-enable IRQs for this write, which means we have to manually re-check for rescheduling events, abort the restart, and try again later. One of the side effects of reverting Arnd's patch is that we restore the strace behaviour which we've had for years on ARM, and can still be seen on x86: strace can see the -ERESTART return codes from the kernel syscalls, rather than what seems to be the signal number: Before: rt_sigsuspend([] <unfinished ...> --- SIGIO (I/O possible) --- <... rt_sigsuspend resumed> ) = 29 sigreturn() = ? (mask now []) vs: rt_sigsuspend([]) = ? ERESTARTNOHAND (To be restarted) --- SIGIO (I/O possible) @ 0 (0) --- sigreturn() = ? (mask now []) x86: rt_sigsuspend([]) = ? ERESTARTNOHAND (To be restarted) --- {si_signo=SIGIO, si_code=SI_USER} (I/O possible) --- sigreturn() = ? (mask now []) So, this patch should fix: 1. The race which I identified in the signal handling code (I think x86 and other architectures can suffer from it too.) 2. The warning from try_to_freeze. 3. The unanticipated change to strace output. Arnd, can you test this to make sure your gdb test case still works, and Mark, can you test this to make sure it fixes your problem please? Thanks. arch/arm/include/asm/thread_info.h | 3 + arch/arm/kernel/entry-common.S | 11 ++ arch/arm/kernel/ptrace.c | 2 + arch/arm/kernel/signal.c | 209 ++++++++++++++++++++++++------------ 4 files changed, 155 insertions(+), 70 deletions(-) diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 7b5cc8d..40df533 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -129,6 +129,7 @@ extern void vfp_flush_hwstate(struct thread_info *); /* * thread information flags: * TIF_SYSCALL_TRACE - syscall trace active + * TIF_SYS_RESTART - syscall restart processing * TIF_SIGPENDING - signal pending * TIF_NEED_RESCHED - rescheduling necessary * TIF_NOTIFY_RESUME - callback before returning to user @@ -139,6 +140,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_NEED_RESCHED 1 #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ #define TIF_SYSCALL_TRACE 8 +#define TIF_SYS_RESTART 9 #define TIF_POLLING_NRFLAG 16 #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ @@ -147,6 +149,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_SECCOMP 21 #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) +#define _TIF_SYS_RESTART (1 << TIF_SYS_RESTART) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index b2a27b6..e922b85 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -45,6 +45,7 @@ ret_fast_syscall: fast_work_pending: str r0, [sp, #S_R0+S_OFF]! @ returned r0 work_pending: + enable_irq tst r1, #_TIF_NEED_RESCHED bne work_resched tst r1, #_TIF_SIGPENDING|_TIF_NOTIFY_RESUME @@ -56,6 +57,13 @@ work_pending: bl do_notify_resume b ret_slow_syscall @ Check work again +work_syscall_restart: + mov r0, sp @ 'regs' + bl syscall_restart @ process system call restart + teq r0, #0 @ if ret=0 -> success, so + beq ret_restart @ return to userspace directly + b ret_slow_syscall @ otherwise, we have a segfault + work_resched: bl schedule /* @@ -69,6 +77,9 @@ ENTRY(ret_to_user_from_irq) tst r1, #_TIF_WORK_MASK bne work_pending no_work_pending: + tst r1, #_TIF_SYS_RESTART + bne work_syscall_restart +ret_restart: #if defined(CONFIG_IRQSOFF_TRACER) asm_trace_hardirqs_on #endif diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 2491f3b..ac8c34e 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -177,6 +177,7 @@ put_user_reg(struct task_struct *task, int offset, long data) if (valid_user_regs(&newregs)) { regs->uregs[offset] = data; + clear_ti_thread_flag(task_thread_info(task), TIF_SYS_RESTART); ret = 0; } @@ -604,6 +605,7 @@ static int gpr_set(struct task_struct *target, return -EINVAL; *task_pt_regs(target) = newregs; + clear_ti_thread_flag(task_thread_info(target), TIF_SYS_RESTART); return 0; } diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 0340224..42a1521 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -649,6 +649,135 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, } /* + * Syscall restarting codes + * + * -ERESTARTSYS: restart system call if no handler, or if there is a + * handler but it's marked SA_RESTART. Otherwise return -EINTR. + * -ERESTARTNOINTR: always restart system call + * -ERESTARTNOHAND: restart system call only if no handler, otherwise + * return -EINTR if invoking a user signal handler. + * -ERESTART_RESTARTBLOCK: call restart syscall if no handler, otherwise + * return -EINTR if invoking a user signal handler. + */ +static void setup_syscall_restart(struct pt_regs *regs) +{ + regs->ARM_r0 = regs->ARM_ORIG_r0; + regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; +} + +/* + * Depending on the signal settings we may need to revert the decision + * to restart the system call. But skip this if a debugger has chosen + * to restart at a different PC. + */ +static void syscall_restart_handler(struct pt_regs *regs, struct k_sigaction *ka) +{ + if (test_and_clear_thread_flag(TIF_SYS_RESTART)) { + long r0 = regs->ARM_r0; + + /* + * By default, return -EINTR to the user process for any + * syscall which would otherwise be restarted. + */ + regs->ARM_r0 = -EINTR; + + if (r0 == -ERESTARTNOINTR || + (r0 == -ERESTARTSYS && !(ka->sa.sa_flags & SA_RESTART))) + setup_syscall_restart(regs); + } +} + +/* + * Handle syscall restarting when there is no user handler in place for + * a delivered signal. Rather than doing this as part of the normal + * signal processing, we do this on the final return to userspace, after + * we've finished handling signals and checking for schedule events. + * + * This avoids bad behaviour such as: + * - syscall returns -ERESTARTNOHAND + * - signal with no handler (so we set things up to restart the syscall) + * - schedule + * - signal with handler (eg, SIGALRM) + * - we call the handler and then restart the syscall + * + * In order to avoid races with TIF_NEED_RESCHED, IRQs must be disabled + * when this function is called and remain disabled until we exit to + * userspace. + */ +asmlinkage int syscall_restart(struct pt_regs *regs) +{ + struct thread_info *thread = current_thread_info(); + + clear_ti_thread_flag(thread, TIF_SYS_RESTART); + + /* + * Restart the system call. We haven't setup a signal handler + * to invoke, and the regset hasn't been usurped by ptrace. + */ + if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) { + if (thumb_mode(regs)) { + regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE; + regs->ARM_pc -= 2; + } else { +#if defined(CONFIG_AEABI) && !defined(CONFIG_OABI_COMPAT) + regs->ARM_r7 = __NR_restart_syscall; + regs->ARM_pc -= 4; +#else + u32 sp = regs->ARM_sp - 4; + u32 __user *usp = (u32 __user *)sp; + int ret; + + /* + * For OABI, we need to play some extra games, because + * we need to write to the users stack, which we can't + * do reliably from IRQs-disabled context. Temporarily + * re-enable IRQs, perform the store, and then plug + * the resulting race afterwards. + */ + local_irq_enable(); + ret = put_user(regs->ARM_pc, usp); + local_irq_disable(); + + /* + * Plug the reschedule race - if we need to reschedule, + * abort the syscall restarting. We haven't modified + * anything other than the attempted write to the stack + * so we can merely retry later. + */ + if (need_resched()) { + set_ti_thread_flag(thread, TIF_SYS_RESTART); + return -EINTR; + } + + /* + * We failed (for some reason) to write to the stack. + * Terminate the task. + */ + if (ret) { + force_sigsegv(0, current); + return -EFAULT; + } + + /* + * Success, update the stack pointer and point the + * PC at the restarting code. + */ + regs->ARM_sp = sp; + regs->ARM_pc = KERN_RESTART_CODE; +#endif + } + } else { + /* + * Simple restart - just back up and re-execute the last + * instruction. + */ + setup_syscall_restart(regs); + } + + return 0; +} + +/* * Note that 'init' is a special process: it doesn't get signals it doesn't * want to handle. Thus you cannot kill init even with a SIGKILL even by * mistake. @@ -659,7 +788,6 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ static void do_signal(struct pt_regs *regs, int syscall) { - unsigned int retval = 0, continue_addr = 0, restart_addr = 0; struct k_sigaction ka; siginfo_t info; int signr; @@ -674,32 +802,16 @@ static void do_signal(struct pt_regs *regs, int syscall) return; /* - * If we were from a system call, check for system call restarting... + * Set the SYS_RESTART flag to indicate that we have some + * cleanup of the restart state to perform when returning to + * userspace. */ - if (syscall) { - continue_addr = regs->ARM_pc; - restart_addr = continue_addr - (thumb_mode(regs) ? 2 : 4); - retval = regs->ARM_r0; - - /* - * Prepare for system call restart. We do this here so that a - * debugger will see the already changed PSW. - */ - switch (retval) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->ARM_r0 = regs->ARM_ORIG_r0; - regs->ARM_pc = restart_addr; - break; - case -ERESTART_RESTARTBLOCK: - regs->ARM_r0 = -EINTR; - break; - } - } - - if (try_to_freeze()) - goto no_signal; + if (syscall && + (regs->ARM_r0 == -ERESTARTSYS || + regs->ARM_r0 == -ERESTARTNOINTR || + regs->ARM_r0 == -ERESTARTNOHAND || + regs->ARM_r0 == -ERESTART_RESTARTBLOCK)) + set_thread_flag(TIF_SYS_RESTART); /* * Get the signal to deliver. When running under ptrace, at this @@ -709,19 +821,7 @@ static void do_signal(struct pt_regs *regs, int syscall) if (signr > 0) { sigset_t *oldset; - /* - * Depending on the signal settings we may need to revert the - * decision to restart the system call. But skip this if a - * debugger has chosen to restart at a different PC. - */ - if (regs->ARM_pc == restart_addr) { - if (retval == -ERESTARTNOHAND - || (retval == -ERESTARTSYS - && !(ka.sa.sa_flags & SA_RESTART))) { - regs->ARM_r0 = -EINTR; - regs->ARM_pc = continue_addr; - } - } + syscall_restart_handler(regs, &ka); if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = &current->saved_sigmask; @@ -740,38 +840,7 @@ static void do_signal(struct pt_regs *regs, int syscall) return; } - no_signal: if (syscall) { - /* - * Handle restarting a different system call. As above, - * if a debugger has chosen to restart at a different PC, - * ignore the restart. - */ - if (retval == -ERESTART_RESTARTBLOCK - && regs->ARM_pc == continue_addr) { - if (thumb_mode(regs)) { - regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE; - regs->ARM_pc -= 2; - } else { -#if defined(CONFIG_AEABI) && !defined(CONFIG_OABI_COMPAT) - regs->ARM_r7 = __NR_restart_syscall; - regs->ARM_pc -= 4; -#else - u32 __user *usp; - - regs->ARM_sp -= 4; - usp = (u32 __user *)regs->ARM_sp; - - if (put_user(regs->ARM_pc, usp) == 0) { - regs->ARM_pc = KERN_RESTART_CODE; - } else { - regs->ARM_sp += 4; - force_sigsegv(0, current); - } -#endif - } - } - /* If there's no signal to deliver, we just put the saved sigmask * back. */ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/

14 years, 2 months

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[ACTIVITY] Aug 31 - Sep 1

by Ira Rosen

Hi, - catching up with the mail - fixed GCC PR50178 - prepared a patch to fix vectorizer dumps Ira

14 years, 2 months

1
0
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how to properly enable multilib builds?

by Matthias Klose

Hi, the current gcc-4.6 packages build for both softfp and hard, so that the armel and (not yet existing) armhf packages can be installed together in the system. To enable multilib, I currently use the rather complicated arm-multilib.diff, which works, but doesn't seem to be correct. With the much simpler arm-ml2.diff, the directory for the default multilib is not resolved to . (as done for e.g. amd64). [amd64] $ gcc -print-multi-directory . [armel] $ gcc -print-multi-directory sf If I understand the code correctly, this comes from the hard setting of MULTILIB_DEFAULTS in the arm target. If you look at mips, you see #ifndef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } #endif which records the proper selected defaults. Should something similiar be done for arm? Matthias

14 years, 2 months

3
3
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request for testing: qemu-linaro git tree

by Peter Maydell

Hi; I've just completed a tricky rebase of qemu-linaro on upstream; there were several invasive upstream changes which have landed recently and which meant that I had to tweak a lot of the qemu-linaro patches as I did the rebase. I've tested the results but it's possible that some breakage may have slipped through... So if you're a regular user of qemu-linaro's system mode and feel like checking the sources out of git: git://git.linaro.org/qemu/qemu-linaro.git building them and testing that the things you regularly do with it haven't regressed, then I'd appreciate it, and you can help us avoid any nasty surprises in the next (2011.09) release. Thanks! -- Peter Maydell

14 years, 2 months

2
2
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GCC trunk fails to build

by Michael Hope

See: http://builds.linaro.org/toolchain/gcc-4.7~svn178154 The problem is -Werror triggering on: ../../../gcc-4.7~/gcc/config/arm/arm.c: In function 'int optimal_immediate_sequence_1(rtx_code, long long unsigned int, four_ints*, int)': ../../../gcc-4.7~/gcc/config/arm/arm.c:2690:46: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2690:60: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2691:20: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2691:34: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2701:16: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2702:18: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] ../../../gcc-4.7~/gcc/config/arm/arm.c:2703:18: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] -- Michael

14 years, 2 months

2
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[ACTIVITY] 22nd - 27th August

by Andrew Stubbs

Booked hotel and travel for Linaro Connect in Orlando. Fixed a couple of bugs in my thumb2 constants patch and retested. The test results came back clean, so I've committed it upstream. Bernd claimed he has found some test failures that might be caused by my patch, but I couldn't reproduce them at first. I've now got the failure, but I've not yet investigated the cause. Next week ... Committed my widening multiplies patches to Linaro GCC, after first convincing Richard Sandiford that it wasn't totally bonkers. Started work on ARM GCC tuning options: * Submitted a patch for -m{arch,cpu,tune}=native http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg14225.html * Submitted a patch for -m{arch,cpu,tune}=generic-armv7-a http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg14231.html Joseph found an issue with those patches, but that was easily resolved and I've reposted both.

14 years, 2 months

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[ACTIVITY] Weekly status

by Revital Eres

Continue looking at Richard's micro benchmarks w.r.t SMS. Wrote a new version to the patch to support instructions with REG_INC_NOTE in SMS. (http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01216.html)

14 years, 2 months

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[ACTIVITY] report week 34

by Peter Maydell

RAG: Red: Amber: OMAP3 patch upstreaming is (still) slower progress than hoped Green: Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 || ||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 || == upstream-omap3-patches == * finished the fairly nasty rebase of qemu-linaro onto upstream master (several invasive changes went into master that meant a number of our local patches needed updating) * omap_gpmc changes cleaned up, updated to use MemoryRegions, and submitted to upstream (17 patch patchset) == gsoc-support == * final meeting/evaluation writeup now the GSoC project has ended * we now have a first pass at what some upstream-acceptable versions of the Android goldfish platform devices might look like, and a much better idea of the degree of difference between the android and upstream qemu trees, and where the pitfalls/issues lie == other == * fixed some breakage upstream in n810 and integratorcp models caused by landing of MemoryRegion changes * trying to write up what my preferred model of device connections would look like in concrete C implementation terms * interesting discussion on boot-architecture list about how boot loaders should start hypervisor-aware software (xen, kvm kernel): http://www.mail-archive.com/boot-architecture@lists.linaro.org/msg00053.html Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: Oct 30-Nov 04: Linaro Connect Q4.11

14 years, 2 months

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Wrote some patches to make SMS schedule register moves. They made a significant difference to some libav loops. I'm running a regression test on pwoerpc-ibm-aix5.3.0 and will submit upstream next week if all goes OK. * Looked at why mjpegenc was so much worse with SMS. Turned out to be a register spilling problem. Found that -fira-algorithm=priority avoids the regression and makes several other tests better too. (I just tested that to see whether there was a feasible register allocation for these cases; -fira-algorithm=priority isn't the way to go.) * Saw that the register allocator seemed to be tripping over the XImode "structure" values, and that we still had one vector move per structure element by the time we get to the scheduling passes. Eliminated those with a combination of one fix and one hack. It seemed to avoid the allocation problems. * Patch review (Linaro and upstream). * Backported libgcc visibility fix to 4.6 and 4.5. == Next week == * Submit register-scheduling patch. * Submit memory cost patch (from auto-inc-dec changes) * Possibly submit the auto-inc-dec changes themselves, depending on how the rtx cost discussion goes. Richard

14 years, 2 months

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[Activity] Week ending 2011-08-26

by Ramana Radhakrishnan

==GCC== ===Progress=== * Looked at the vectorize_with_neon_quad failure again and decided that I had to handle another case but not convinced that the extra stall we'd get in this case was worth it. In any case it would have been a workaround but Richard Sandiford fixed this by getting df to do the right thing which would have been the right fix. * Backported tbh patch. * Backported conditional execution improvements patch from Jiangning to Linaro 4.6 branch. * Committed the LTO + Neon / Android intrinsics patch. * Panda seems more reliable this week but I suspect that's the room cooling more . * Broke up a few blueprints and marked some as done. * BRANCH_COST results show not a huge variation in SPEC and there are some results that are inconsistent.. Need to run a few benchmarks again Sigh :( . * Finished the A9 scheduler patch for smull and friends and committed upstream and into Linaro 4.6. * Reviewed the shrink-wrapping patch and the widening multiplies patch for a short duration. * Looked at the failures in the "popular embedded benchmark" for sometime with Asa. * Tried one of the ICE patches and that seemed to work just fine with bootstrap on FSF trunk. Need to figure out why this was breaking in the Linaro 4.6 tree. https://bugs.launchpad.net/gcc-linaro/+bug/689887 === Plans === Next Week - Holiday :) Feet not up but walking in what looks like typical bank holiday weather ... Might check email later in the week. Meetings: * 1-1s * TCWG calls * Thumb2 performance call. Absences. * 29th Aug - Sept. 2 - Holiday booked and approved. * 31st Oct - 4th Nov - Linaro Summit Orlando - Travel booked - hotel to be booked.

14 years, 2 months

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[ACTIVITY] 21th - 26th August

by Asa Sandahl

* Investigated the errors in the automotive test and concluded that they are CRC-errors, but not depending on the test case result (non intrusive crc check). We decided these errors need to be cleared out once and for all. Michael and Ramana helping out with continued investigation. * EEMBC run on both Panda and Snowball with gcc4.5.2. Results look reasonable, but Michael will also have a look. I will spend a little more time comparing the results from the two boards. * Started to run SPEC2K on the Panda board. Best Regards Åsa

14 years, 2 months

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Effect of SMS register move scheduling

by Richard Sandiford

Following on from yesterday's call about what it would take to enable SMS by default: one of the problems I was seeing with the SMS+IV patch was that we ended up with excessive moves. E.g. a loop such as: void foo (int *__restrict a, int n) { int i; for (i = 0; i < n; i += 2) a[i] = a[i] * a[i + 1]; } would end up being scheduled with an ii of 3, which means that in the ideal case, each loop iteration would take 3 cycles. However, we then added ~8 register moves to the loop in order to satisfy dependencies. Obviously those 8 moves add considerably to the iteration time. I played around with a heuristic to see whether there were enough free slots in the original schedule to accomodate the moves. That avoided the problem, but it was a hack: the moves weren't actually scheduled in those slots. (In current trunk, the moves generated for an instruction are inserted immediately before that instruction.) I mentioned this to Revital, who told me that Mustafa Hagog had tried a more complete approach that really did schedule the moves. That patch was quite old, so I ended up reimplementing the same kind of idea in a slightly different way. (The main functional changes from Mustafa's version were to schedule from the end of the window rather than the start, and to use a cyclic window. E.g. moves for an instruction in row 0 column 0 should be scheduled starting at row ii-1 downwards.) The effect on my flawed libav microbenchmarks was much greater than I imagined. I used the options: -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -mvectorize-with-neon-quad -fmodulo-sched -fmodulo-sched-allow-regmoves -fno-auto-inc-dec The "before" code was from trunk, the "after" code was trunk + the register scheduling patch alone (not the IV patch). Only the tests that have different "before" and "after" code are run. The results were: a3dec before: 500000 runs take 4.68384s after: 500000 runs take 4.61395s speedup: x1.02 aes before: 500000 runs take 20.0523s after: 500000 runs take 16.9722s speedup: x1.18 avs before: 1000000 runs take 15.4698s after: 1000000 runs take 2.23676s speedup: x6.92 dxa before: 2000000 runs take 18.5848s after: 2000000 runs take 4.40607s speedup: x4.22 mjpegenc before: 500000 runs take 28.6987s after: 500000 runs take 7.31342s speedup: x3.92 resample before: 1000000 runs take 10.418s after: 1000000 runs take 1.91016s speedup: x5.45 rgb2rgb-rgb24tobgr16 before: 1000000 runs take 1.60513s after: 1000000 runs take 1.15643s speedup: x1.39 rgb2rgb-yv12touyvy before: 1500000 runs take 3.50122s after: 1500000 runs take 3.49887s speedup: x1 twinvq before: 500000 runs take 0.452423s after: 500000 runs take 0.452454s speedup: x1 Taking resample as an example: before the patch we had an ii of 27, stage count of 6, and 12 vector moves. Vector moves can't be dual issued, and there was only one free slot, so even in theory, this loop takes 27 + 12 - 1 = 38 cycles. Unfortunately, there were so many new registers that we spilled quite a few. After the patch we have an ii of 28, a stage count of 3, and no moves, so in theory, one iteration should take 28 cycles. We also don't spill. So I think the difference really is genuine. (The large difference in moves between ii=27 and ii=28 is because in the ii=27 schedule, a lot of A--(T,N,0)-->B (intra-cycle true) dependencies were scheduled with time(B) == time(A) + ii + 1.) I also saw benefits in one test in a "real" benchmark, which I can't post here. Richard

14 years, 2 months

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Turn on SMS by default on ARM

by Revital Eres

Hello, Following today performance call (https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-08-23) here are some points raised regarding the steps towards enabling SMS by default: * Benchmarks testing: -- Running benchmarks as EEMBC and SPEC2006 with SMS enabled is crucial to expose loops where SMS degrades the performance. those loops need to be analysed to construct a cost model. -- SMS increases code size by introducing prologue and epilogue to the loop kernel. This should also be measured. -- Measure increase in compile time: on native or cross build? Currently SMS fails to bootstrap trunk on ARM machine. this should also be taken into account when considering enabling it by default. Should it be turned on with -O2 or -O3? SMS flags to use for testing: -O3 -fmodulo-sched-allow-regmoves -fmodulo-sched -funsafe-loop-optimizations -fno-auto-inc-dec Thanks, Revital

14 years, 2 months

3
3
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Generic Linux cross toolchain for tests

by Marcin Juszkiewicz

Hi Some time ago we agreed that not everyone here uses Ubuntu distribution and decided to provide so called 'generic linux' cross toolchain. Recently I managed to get it done and now need brave testers to tell is it working or not. Get it here: http://people.linaro.org/~hrw/generic-linux/ (64bit only) Needed files are toolchain-11.07.tar.xz and init.sh script. Unpack tarball from / so /opt/linaro/11.07/ will be populated and put init.sh anywhere you want (it will be integrated into tarball later). How to use: $ source init.sh this will add cross toolchain into PATH and also set LD_LIBRARY_PATH to two directories: - one with binutils libraries - second with all extra libraries which may be needed Feel free to experiment with second dir by removing files from there and checking are system provided libs are fine too. So far I checked this toolchain under few distributions: - Ubuntu 10.04 'lucid' LTS - Ubuntu 11.04 'natty' - Fedora 14 - OpenSUSE 11.4 - CentOS 5.6 It failed only under CentOS (which was expected due to it's age). How did I checked? So far compilation of 'gpm' and 'zlib' were tested.

14 years, 2 months

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