- linaro-toolchain - lists.linaro.org

Activity 13th - 16th June 2016

by Peter Smith

== Progress == TCWG-611 Initial Thumbv7a support for LLD committed upstream. Interworking is supported via BLX only. This is enough to run hello world on a modern arm-linux-gnueabihf target. TCWG-653 Interworking veneer support for LLD The existing support for veneers (thunks in LLD terminology) is Mips specific for non-pi to pi calls. Unless there is something I'm missing it looks broken in the general case as well. I have an implementation of minimal veneers that I'm not particular happy with, but can experiment with to see what the implementation options are. I am likely to need to go via and RFC first. Holiday on Friday. == Next Week == Continue working on TCWG-653.

10 years, 3 months

1
0
0 0

[ANNOUNCE] Linaro GCC 5 and 6 2016.06 snapshots

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.06 snapshot of both Linaro GCC 5 and Linaro GCC 6 source packages. Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn237469 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.1+svn237469 * Backport of [Bugfix] [AArch32] PR target/69857 Remove bogus early return false; in gen_operands_ldrd_strd * Backport of [AArch32] Add mode to probe_stack set operands * Backport of [AArch32] arm/ieee754-df.S: Fix typos in comments * Backport of [AArch32] Do not set ARM_ARCH_ISA_THUMB for armv5 * Backport of [AArch32] Error out for incompatible ARM multilibs * Backport of [AArch32] Fix costing of sign-extending load in rtx costs * Backport of [AArch32] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC * Backport of [AArch32] Use proper output modifier for DImode register in store exclusive patterns * Backport of [AArch64] 1/4 Add the missing support of vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64 * Backport of [AArch64] 2/4 Extend vector mutiply by element to all supported modes * Backport of [AArch64] 3/4 Reimplement multiply by element to get rid of inline assembly * Backport of [AArch64] 4/4 Reimplement vmvn* intrinscis, remove inline assembly * Backport of [AArch64] Adjust SIMD integer preference * Backport of [AArch64] Delete ASM_OUTPUT_DEF and fallback to default .set directive * Backport of [AArch64] Don't define a macro when a variable will do * Backport of [AArch64] Fix shift attributes * Backport of [AArch64] Improve aarch64_case_values_threshold setting * Backport of [AArch64] print_operand should not fallthrough from register operand into generic operand * Backport of [AArch64] Remove aarch64_simd_attr_length_move * Backport of [AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true * Backport of [AArch64] Simplify ashl<mode>3 expander for SHORT modes * Backport of [AArch64] Simplify reduc_plus_scal_v2[sd]f sequence * Backport of [AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled * Backport of [AArch64] Update documentation of AArch64 options for GCC6 * Backport of [AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets * Backport of [Testsuite] [AArch32] 01/11 Fix typo in vreinterpret.c test comment * Backport of [Testsuite] [AArch32] 02/11 Remove useless #ifdefs from these tests: vmul, vshl and vtst * Backport of [Testsuite] [AArch32] 03/11 AdvSIMD tests: be more verbose * Backport of [Testsuite] [AArch32] 04/11 Add forgotten vsliq_n_u64 vsliq_n_s64 tests * Backport of [Testsuite] [AArch32] 05/11 Add missing vreinterpretq_p{8,16} tests * Backport of [Testsuite] [AArch32] 06/11 Add missing vtst_p16 and vtstq_p16, and vtst_p{8,16} and vtstq_p{8,16} tests * Backport of [Testsuite] [AArch32] 07/11 Add vget_lane fp16 tests * Backport of [Testsuite] [AArch32] 08/11 Add missing vstX_lane fp16 tests * Backport of [Testsuite] [AArch32] 09/11 Add missing vrnd{,a,m,n,p,x} tests * Backport of [Testsuite] [AArch32] 10/11 Add missing tests for intrinsics operating on poly64 and poly128 types * Backport of [Testsuite] [AArch32] 11/11 Add missing tests for vreinterpret, operating of fp16 type * Backport of [Testsuite] [AArch64] Fix vmul_elem_1.c on big-endian * Backport of [Testsuite] [AArch64] Guard float64_t with __aarch64__ * Backport of [Testsuite] [AArch64] Skip cpu-diagnostics tests when overriding -mcpu * Backport of [Testsuite] gcc-dg: handle all return values when shouldfail is set * Backport of [Testsuite] PR70227, skip g++.dg/lto/pr69589_0.C on targets without -rdynamic support * Backport of [Testsuite] PR tree-optimization/57206 * Backport of [Testsuite] Skip tail call tests on Thumb-1 targets * Backport of [Misc] Increase default value of lto-min-partition to 10000 * Backport of [Misc] introduce --param max-lto-partition for having an upper bound on partition size * Backport of [Cleanup] [AArch32] Fix typos in *thumb1_mulsi3 comment * Backport of [Cleanup] [AArch32] Remove unused TARGET_ARM_V*M macros * Backport of [Cleanup] [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes * Backport of [Cleanup] [AArch64] Remove an unused reload hook * Backport of [Cleanup] Convert conditional compilation on WORD_REGISTER_OPERATIONS * Backport of [Cleanup] Remove spurious debug code * Backport of [Cleanup] Move wrong ChangeLog entry from toplevel to gcc ChangeLog * Backport of [Doc] Fix minor doc bugs, signalling typo, major version changes rare Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn237113 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.08 maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06/ Interesting changes in this GCC source package snapshot include: Updates to GCC 5.6+svn237113 * Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/69245: Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is the default node to recalculate optab availability * Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/70002: Make aarch64_set_current_function play nice with pragma resetting Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

10 years, 3 months

1
0
0 0

Error: non-constant expression in ".if" statement

by Jérôme Forissier

Hi, I've stumbled across an assembler error message that I don't understand. bl1/aarch64/bl1_exceptions.S: Assembler messages: bl1/aarch64/bl1_exceptions.S:53: Error: non-constant expression in ".if" statement It occurs when building ARM Trusted Firmware with aarch64-linux-gnu-gcc that ships with Ubuntu 16.04. It does _not_ occur with an older Linaro toolchain. More details in [1]. The .align directives in the vector_base and vector_entry macros _do_ make a difference. Are they the cause of the problem? Would you recommend writing the code differently? Or is it a compiler bug? [1] https://github.com/ARM-software/tf-issues/issues/401 Thanks, -- Jerome

10 years, 3 months

3
5
0 0

[TCWG] Split-stack for aarch64

by Adhemerval Zanella

Hi all, First sorry for the long message, but I am kinda stuck on an issue with my split-stack work for aarch64, so any new eyes to check if I am doing things properly would be really helpful. I pushed my current work on a local gcc git [1] and glibc [2] branches. The current code show not issue with the placed C tests, but there is one elusive GO tests that fails for some reason. The glibc patch is pretty simple: it adds a tcbhead_t field (__private_ss) which will be used to hold the split stack thread value. Different from stack protector, split-stack requires a pointer per thread and it is used frequently on *every* function prologue. So faster access is through TCB direct access (one instruction less than TLS initial-exec). I plan to digress a little more about why I decided to use TCB access, but in a short the advantages are: 1. It is faster than TLS initial-exec 2. Does not require any static or dynamic relocation The rest of patch is just to add a versioned symbol so either static or dynamic linking fails for an older glibc (to prevent split-stack binaries to run on non-supported glibcs). The GCC patch is more complex, but it follows the already implemented split-stack support on other architectures (x86, powerpc64, s390). Basically you add hooks to generate the required prologue and other bits (C varargs requires some work) and add some runtime support on libgcc (morestack.S). Split-stack idea is basically as this: let say you have a function that requires a very large stack allocation that might fail at runtime (due ulimit -s limit). Split-stack add some instrumentation that check if the stack allocation will fail based on initial value and allocates stack segments as required. So basically a function would be instrumented as: function foo ss := TCB::__private_ss if SP + stack_allocation_size > ss call __morestack // function code What __morestack basically does is create a new stack segment with some slack (using a platform neutral code), change the stack pointer and continue run the function. So a stack frame for a function that called __morestack is as: foo \_ __morestack \_ // function code And when the function code finished its execution (including all possible function calls), it returns to __morestack so it restore the old stack pointer and arguments. Now, this is the most straightforward usage of __morestack. However GO language allows a construct [3] that allows a function to register a callback that is called at end of its scope that allows to 'recover' from some runtime execution failure. And this is the remaining GO tests that fails [4]. What it basically does is run a set of tests that allocate some different structure and try to access it in different invalid way to check if accessing a know null pointer is caught by the runtime (GO adds null pointer checks for some constructs). 9 func main() { 10 ok := true 11 for _, tt := range tests { 12 func() { 13 defer func() { 14 if err := recover(); err == nil { 15 println(tt.name, "did not panic") 16 ok = false 17 } 18 }() 19 tt.fn() 20 }() 21 } 22 if !ok { 23 println("BUG") 24 } 25 } 41 var tests = []struct{ 42 name string 43 fn func() 44 }{ 76 {"*bigstructp", func() { use(*bigstructp) }}, 108 type BigStruct struct { 109 i int 110 j float64 111 k string 112 x [128<<20]byte 113 l []byte 114 } So basically here it tries to allocate a very big structure (BigStruct with about 128 MBs) on stack and since it does not have stack allocation it will need to call __morestack. Now, if have patient to read until now, the way GCCGO does that is by throwing an exception to unwind the stack and to add some CFI directives in both generated code and morestack to correct handling the unwinding. So if GCC generates the unwind information for the objects and if __morestack have the correct unwind information it should, so I presume my patch is failing in either define the correct exception handler directives in morestack.S or I am failing in generate the correct __morestack call. The __morestack call is done at 'aarch64_expand_split_stack_prologue' in my patch as: -- + /* Call __morestack with a non-standard call procedure: x10 will hold + the requested stack pointer and x11 the required stack size to be + copied. */ + args_size = crtl->args.size >= 0 ? crtl->args.size : 0; + reg11 = gen_rtx_REG (DImode, R11_REGNUM); + emit_move_insn (reg11, GEN_INT (args_size)); + use_reg (&call_fusage, reg11); + + /* Set up a minimum frame pointer to call __morestack. The SP is not + save on x29 prior so in __morestack x29 points to the called SP. */ + aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, 16); + + insn = emit_call_insn (gen_call (gen_rtx_MEM (DImode, morestack_ref), + const0_rtx, const0_rtx)); + add_function_usage_to (insn, call_fusage); + + reg29 = gen_rtx_REG (Pmode, R29_REGNUM); + cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg29, cfi_ops); + reg30 = gen_rtx_REG (Pmode, R30_REGNUM); + cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg30, cfi_ops); + insn = emit_insn (aarch64_gen_loadwb_pair (DImode, stack_pointer_rtx, + reg29, reg30, 16)); + + /* Reset the CFA to be SP + FRAME_SIZE. */ + new_cfa = stack_pointer_rtx; + cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops); + REG_NOTES (insn) = cfi_ops; + RTX_FRAME_RELATED_P (insn) = 1; + + emit_use (gen_rtx_REG (DImode, LR_REGNUM)); + + emit_insn (gen_split_stack_return ()); -- I do not add any stack frame allocation for the call, so it might a source of issues. Another issue might in morestack.S unwinding directives that is not following the ABI correctly. I am revising it using GCC generated exceptions examples. [1] https://git.linaro.org/toolchain/gcc.git/shortlog/refs/heads/linaro-local/a… [2] https://git.linaro.org/toolchain/glibc.git/shortlog/refs/heads/azanella/spl… [3] https://blog.golang.org/defer-panic-and-recover [4] gcc/testsuite/go.test/test/nilptr2.go

10 years, 3 months

1
0
0 0

[ACTIVITY] 06 - 10 June 2016

by Omair Javaid

=== This Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [3/10] -- Implementation successful without the need for instruction emulation. -- Watchpoint hit detection fixed with ptrace reporting hit address correctly. -- Used up watchpoint HitAddress function to return back the real address to host. Investigation of Nexus devices kernel issues.[TCWG-622] [2/10] -- Figured out steps to build custom kernel for Neuxs7. -- Kernel fails to boot though. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] [2/10] -- Submitted a patch to report back correct reason for watchpoint creation failure. Miscellaneous [3/10] -- Meetings, emails, discussions etc. -- A look into LLDB xfail decorators to fail on the basis of arm ABI. -- Out of office on Thursday 9th June for visa interview. === Next Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Finish up work, test and submit for review upstream. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] -- Patch review and further progress. Miscellaneous -- Testsuite Makefile.rulez update still pending, hopefully will be done this week. -- Xfail decorator updates to xfail based on ARM ABI.

10 years, 3 months

1
0
0 0

[ACTIVITY] 30 May - 03 June 2016

by Omair Javaid

=== This Week === Investigation of Nexus devices kernel issues.[TCWG-622] [6/10] -- Figured out source trees for various android devices and checked out kernel code. -- Comparison between watchpoint implementation of different kerenel sources supported by Nexus devices. -- Figured a way to burn a custom rom with updated kernel on Nexus 7. -- Figured Kconfig issue that was causing watchpoints not to be detected on Nexus 7. -- Watchpoint installation still doesnt work on Nexus 7. LLDB buildbot updates and maintenance [TCWG-241] [2/10] -- Upgraded cmake version after migration to new version. -- Migrating local buildbot setup (builders and testers) to ubuntu xenial 16.04 -- Buildbot restart after power outage. Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Out of office on Tuesday 31st 2016 for visa documents preparation. === Next Week === Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Continue work on hardware watchpoint support. Investigation of Nexus devices kernel issues.[TCWG-622] -- Figured out steps to build custom kernel for Neuxs7. LLDB hardware watchpoint capability test and skip watchpoint testing [TCWG-622] -- Investigate possible ways to solve this issue. Miscellaneous -- Out of office on Thursday 9th June for visa interview.

10 years, 3 months

1
0
0 0

[ACTIVITY] 6 - 10 June 2016

by Yao Qi

* One day off on Thu [2/10] # Progress # * TCWG-639, non-8-byte-aligned watchpoint is missed on aarch64. [4/10]. It is caused by limited kernel BAS support. RedHat reports this problem and posts a patch. Good to see they start to contribute to aarch64 GDB, but I don't like the patch. Spend much time writing a prototype to prove their patch is not perfect. We agree to fix this problem by extend RSP fortunately. * TCWG-333, [3/10] I follow the way how mips does, and fix some bugs. * TCWG-547, TCWG-518, blocked in upstream review. * Misc, meetings. [1/10] # Plan # * TCWG-333, TCWG-556. * Ping TCWG-547, TCWG-518. -- Yao

10 years, 3 months

1
0
0 0

[ACTIVITY] Week 23

by Yvan Roux

== Progress == o Extended Validation (4/10) - Investigate and reported Glibc/libsanitizer issue https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71445 - Looked at benchmark job issues - Discuss benchmark/lava notification mechanism o Linaro GCC (1/10) - Merged FSF GCC 5.4 branch o Upstream GCC (3/10) - ARMv8.1 libatomic investigation: seems to work fine when enabling multilib on AArch64 need to investigate completeness of the support. o Misc (2/10) * Various meetings and discussions. * Backlfip patch reviews == Plan == o Backport reviews and June snapshots o Continue libatomic o Benchmarking job fixes.

10 years, 3 months

1
0
0 0

[ACTIVITY] 6 - 10 June 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) a) committed r237207 to fix unresolved test-cases added in r236503 (1/10) b) move increase_alignment pass to regular pass (3/10) - Patch iterations based on suggestions from Honza and Richard - Understanding lto streaming and decl merging code c) TCWG-548 (1/10) - WIP patch * TCWG-319 (1/10) - updated patch submitted upstream: - changing vect_hw_misalign causes regression for vect-align-1.c * Benchmarking (1/10) - Benchmark successfully ran for linaro-gcc-5 submitted by Yvan - Benchmark for fsf-gcc-6 failed both with prebuilt route and letting job build the benchmark * Misc (3/10) - Meetings - Travel to Mumbai for Schengen Visa appointment == Next Week == - Try to get patch committed for increase_alignment - TCWG-319: Look at vect-align-1.c regression - TCWG-548: Complete implementation and validate patch. - ipa-vrp: Experiment with Kugan's patch.

10 years, 3 months

1
0
0 0

[ACTIVITY] 6-10 June 2016

by Christophe Lyon

== Progress == * Validation - disk full on one builder caused problem during the validation of the long series of backports. We'll have to refine the cleanup policy. - switch to docker on-hold until the builders are upgraded * ABE - looked a bit at the gdb/gdbserver issue * Backports - used a script to process the spreadsheet and submitted all the backports that backflip was able to complete in batch mode (a lot!) - fsf-5-branch merge review * GCC - regression reports on trunk, chasing problems that occur in corner case configurations - One of the Neon intrinsics tests I committed recently wrongly executed v8 Neon code on v7 HW: I didn't catch this earlier because of a bug in qemu, promptly fixed by Peter Maydell - neon-testgen.ml removal delayed because other cleanup is desirable before (fixing neon* effective-target tests on-going) - started looking at PR 67591 (ARM v8 Thumb IT blocks deprecated) * Support - started looking at bug 2315 * Misc (conf-calls, meetings, emails, ...) == Next == * Validation: - patch reviews - look at disk management/cleanup * Backports - check validation results * GCC - monitor trunk regressions - fix "check_vect" guard in gcc.dg/vect tests - fix neon* effective-target - hopefully test-neongen.ml removal - pr 67591 - advsimd tests

10 years, 3 months

1
0
0 0

[ACTIVITY] 6-10 June 2016

by Peter Smith

== Progress == TCWG-607 Initial ARM port for LLD committed upstream. Hello World on an ARM with an ARM only gcc libc is possible, but not much else. TCWG-611 Initial Thumb support sent for upstream review. Interworking is possible at the BLX level but full interworking support (veneers/thunks) isn't there yet. With this patch it will be possible to do Hello World with a recent Linaro gcc release. TCWG-634 llvm-mc putting out R_ARM_THM_PC24 for B<cond>.W instead of R_ARM_THM_PC19. Simple fix now committed upstream. == Plans == Interworking thunks for lld. The existing thunk design is very simple and only supports one type of thunk per target. For interworking we need at least two (ARM to Thumb) and (Thumb to ARM). I think it might be possible to fit a basic implementation just good enough for ARMv7a to be correct into the existing mechanism, however just one more thunk type will need a more sophisticated design. Current thought is to try and implement the basic design to learn a bit more about the mechanism as it will hopefully not take too long.

10 years, 3 months

1
0
0 0

Linaro GCC vs Valgrind

by William Mills

Hello, We have been using Linaro GCC 5.x[1] and valgrind. When the optimizer is turned on valgrind complains about writes beyond the current stack pointer. With the optimizer off, the problem report goes away. I have my own conclusion about what is going on but I won't bias you with it. Here are the facts: All files and logs attached as 10K tar.gz if it survives this maillist. test.c: #include <stdio.h> int main(int argc,char** argv) { int i; for (i = 1; i < argc; i++) { printf("argument is %s\n", argv[i]); } return 0; } $ arm-linux-gnueabihf-gcc -march=armv7ve -marm -mfpu=neon \ -mfloat-abi=hard -mcpu=cortex-a15 -O2 -g \ -o test-fail test.c $ valgrind --leak-resolution=high --track-origins=yes \ --trace-children=yes --leak-check=full --error-limit=no \ ./test-fail arg1 arg2 arg3 ==20011== Memcheck, a memory error detector ==20011== Copyright (C) 2002-2015, and GNU GPL'd, by Julian Seward et al. ==20011== Using Valgrind-3.11.0 and LibVEX; rerun with -h for copyright info ==20011== Command: ./test-fail arg1 arg2 arg3 ==20011== ==20011== Invalid write of size 4 ==20011== at 0x10300: main (test.c:4) ==20011== Address 0xbdbfcb58 is on thread 1's stack ==20011== 24 bytes below stack pointer ==20011== 000102f8 <main>: 102f8: e3500001 cmp r0, #1 102fc: da000014 ble 10354 <main+0x5c> 10300: e16d41f8 strd r4, [sp, #-24]! ; 0xffffffe8 ^^^^^^^^ Complaint is here 10304: e1a05001 mov r5, r1 10308: e3a04001 mov r4, #1 1030c: e1cd60f8 strd r6, [sp, #8] 10310: e300748c movw r7, #1164 ; 0x48c 10314: e1a06000 mov r6, r0 10318: e3407001 movt r7, #1 1031c: e58d8010 str r8, [sp, #16] 10320: e58de014 str lr, [sp, #20] 10324: e2844001 add r4, r4, #1 10328: e5b51004 ldr r1, [r5, #4]! 1032c: e1a00007 mov r0, r7 10330: ebffffe4 bl 102c8 <printf@plt> 10334: e1560004 cmp r6, r4 10338: 1afffff9 bne 10324 <main+0x2c> 1033c: e1cd40d0 ldrd r4, [sp] 10340: e3a00000 mov r0, #0 10344: e1cd60d8 ldrd r6, [sp, #8] 10348: e59d8010 ldr r8, [sp, #16] 1034c: e28dd014 add sp, sp, #20 10350: e49df004 pop {pc} ; (ldr pc, [sp], #4) 10354: e3a00000 mov r0, #0 10358: e12fff1e bx lr Without the optimizer, the code looks different and valgrind does not issue any errors. 000103d8 <main>: 103d8: e52db008 str fp, [sp, #-8]! ^^^^^^^ Valgrind does not complain about this 103dc: e58de004 str lr, [sp, #4] 103e0: e28db004 add fp, sp, #4 103e4: e24dd010 sub sp, sp, #16 103e8: e50b0010 str r0, [fp, #-16] 103ec: e50b1014 str r1, [fp, #-20] ; 0xffffffec 103f0: e3a03001 mov r3, #1 103f4: e50b3008 str r3, [fp, #-8] 103f8: ea00000b b 1042c <main+0x54> 103fc: e51b3008 ldr r3, [fp, #-8] 10400: e1a03103 lsl r3, r3, #2 10404: e51b2014 ldr r2, [fp, #-20] ; 0xffffffec 10408: e0823003 add r3, r2, r3 1040c: e5933000 ldr r3, [r3] 10410: e1a01003 mov r1, r3 10414: e30004a4 movw r0, #1188 ; 0x4a4 10418: e3400001 movt r0, #1 1041c: ebffffa9 bl 102c8 <printf@plt> 10420: e51b3008 ldr r3, [fp, #-8] 10424: e2833001 add r3, r3, #1 10428: e50b3008 str r3, [fp, #-8] 1042c: e51b2008 ldr r2, [fp, #-8] 10430: e51b3010 ldr r3, [fp, #-16] 10434: e1520003 cmp r2, r3 10438: baffffef blt 103fc <main+0x24> 1043c: e3a03000 mov r3, #0 10440: e1a00003 mov r0, r3 10444: e24bd004 sub sp, fp, #4 10448: e59db000 ldr fp, [sp] 1044c: e28dd004 add sp, sp, #4 10450: e49df004 pop {pc} ; (ldr pc, [sp], #4) [1] 5.3-2016.02 for Yocto-project and cross-compile 5.2 on the ARM target "since Linaro hasn’t yet fixed building 5.3 from recipes yet." Both versions give the same results for this test program. ---------------- William A. Mills Chief Technologist, Open Solutions, SDO Texas Instruments, Inc. 20450 Century Blvd Germantown MD 20878 240-643-0836

10 years, 3 months

3
3
0 0

[ACTIVITY] 6-10 June 2016

by Diana Picus

== Progress == * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing the MIR tests (PR27770) - committed upstream - Submitted a patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Submitted a patch fixing the ARM test (PR27765) - in upstream review * Use git worktree in llvm helper scripts [TCWG-587] [1/10] - Minor fixes during the review, hopefully we can wrap it up soon * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [3/10] - Investigated uses of isCortexA*, isSwift etc in the ARM backend - Started extracting subtarget features for the easy ones * LLVM ARM 3.8.1 [TCWG-642] [1/10] - Ran the ARM tests for the LLVM 3.8.1 release * Investigate clang-cmake-thumbv7-a15-full-sh failure [TCWG-635] [1/10] - Found patch that was causing problems, started discussion about it on the mailing list == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Address any code review comments - After committing the 2 remaining patches, we should be able to remove the flag and wrap this up * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] - Extract more subtarget features * OOO on Monday

10 years, 3 months

1
0
0 0

[ACTIVITY] 30 May - 3 June 2016

by Prathamesh Kulkarni

== This Week == * LTO (6/10) a) increase_alignment (2/10) - posted patch upstream to convert it to regular pass b) TCWG-548 (3/10) - Lava job #3424 failed with timeout (same as #3370) - Experimenting with partition sizes with and without the patch for different benchmarks, results consistently show a significant difference in last partition size. - Trying a new approach. c) TCWG-535 (1/10) - posted partial patch upstream: https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00143.html * TCWG-72 (2/10) - Further patch iterations - Approved by Richard * Misc (2/10) - Looked at function versioning. - Wrote patch to address missing diagnostic in C/C++ FE, fails on bootstrap. - Meetings == Next Week == - TCWG-548: Implement new approach and experiment with it. - ipa-vrp: Apply Kugan's prototype patch, and test it, sync on early vrp. - TCWG-72, TCWG-319, TCWG-535, increase_alignment: ping for reviews. - Travel to Mumbai on Monday for Schengen Visa appointment

10 years, 4 months

1
0
0 0

[ACTIVITY] Week 22

by Yvan Roux

== Progress == o Upstream GCC (4/10) - Continuing ARMv8.1 libatomic investigation (some infra issues now fixed) o Misc (6/10) * Various meetings and discussions. * patch reviews * Benchmarking notification investigation * Booked Hotel and flights for tcwg sprint == Plan == o Continue libatomic o GCC 5.4 branch merge o Benchmarking notification

10 years, 4 months

1
0
0 0

[ACTIVITY] 30 May - 3 June 2016

by kugan

== Progress == Fixed Bugs and posted patches for review - PR71281 and PR71408 PR66726 - Convert expr - Found way to handle this well and posted a patch. IPA VRP - Started with a simple implementation for intra-procedural early VRP by refactoring tree-vrp. - Still need to handle range dominance - Ran into a latent issue in tree-vrp. Looking into it. == Plan == - Follow upon remaining upstream patches - IPA VRP

10 years, 4 months

1
0
0 0

Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 3 June 2016 at 17:10, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote: > Do keep in mind you are comparing a 11 year old project and a 11 month > old one. There is a lot more churn on the 11 month old one. LLD is at least 5 years old. Every time you re-write it doesn't reset history. > Again, I am truly sorry we were unable to come up with a perfect > design the first time. For the record, I don't think it is perfect > yet. There will likely be more big changes to lld. That is the cost of > trying to build as good a linker as we can. This is not about what you do. It's about *how* you do it. We have developers trying to create a linker. They are working on LLD because Chris wanted a true LLVM linker. But it seems that you want a project that you can do whatever you want, whenever you want. This is *NOT* open source. Right now, LLD is *nothing more* than Rui's and Rafael's pet project. I cannot recommend Linaro to collaborate on those terms, and I sincerely recommend anyone that is listening to this thread to not do so either. > Being open source doesn't mean I get to implement what someone else > wants. You are more than welcome to send patches, but they have avoid > harming the rest of the linker. In particular, at this early stage > they cannot harm its development. Once we have a mature project we can > actually evaluate tradeoff. We're clearly not welcome to send patches. We did, and you re-wrote it and committed without asking the original author. So, the plan is to wait for you to finish the initial implementation alone? Again? What do we do in the interim? How many times are we going to go through this? I have waited 2 years before LLD was barely useful, then Adhemerval implemented the AArch64 back-end. Then you destroyed and now we have waited another year, but we're still unable to collaborate. If anything, now it's even harder than it was last year. Why can't we help with the design, too? We know about ARM and AArch64, that's what we do, and we can provide you with the expertise without having to go on your own doing everything. That is the whole point of collaborative development, and it seems that you're missing this point. > And just like we did, you are more than welcome to try to write > something better. Please let us know how it goes. Is this the position of every LLD developer? Rui, Nick, Chris? I'm seriously looking for others to chime in and let me know if that is the final stance on LLD, so that I can finally write it off and go work on another linker. If the official position is that LLD is a project that only Rui and Rafael can design and implement for another 2~3 years, I *cannot* recommend Linaro and its members to participate. cheers, --renato

10 years, 4 months

2
5
0 0

[ACTIVITY] 1st June - 3rd June 2016

by Peter Smith

== Progress == - Holiday Monday/Tuesday - Finished writing initial support for ARM in lld. Posted upstream as RFC, no comments so far. - Implemented, but not tested the static Thumb relocations present in the arm-linux-gnueabihf-gcc -- I'd forgotten how much I hated the Thumb 2 instruction encodings. == Plan == - Add tests for Thumb relocations - Start thinking about how interworking can be implemented in lld

10 years, 4 months

1
0
0 0

[ACTIVITY] 30 May-3 June 2016

by Yao Qi

* Monday off [2/10] # Progress # * TCWG-518, arm linux range stepping. [4/10] Finished V2, and send them out for review. More bugs in existing GDBserver are found, fixed them as well. 8 patches become 12 patches. * Upgrade linux kernel on chromebook to verify Russell King's ptrace fix. http://lists.infradead.org/pipermail/linux-arm-kernel/2016-May/431972.html [3/10] This may be the cause of unstable result of GDB floating point tests, and they are tracked by GNUTOOLS-4858. 4.6.1 is running on chromebook now, but haven't try the patch yet. * TCWG-547, "align software single step in other targets with arm's implementation". Patches are pending for review. Pinged Pedro to give a review. * Misc, [1/10] ** Commit fix to PR 19998, and review the follow-up patch. ** meeting and training, # Plan # * TCWG-518, TCWG-547, TCWG-333 -- Yao

10 years, 4 months

1
0
0 0

[ACTIVITY] 30 May-3 June 2016

by Diana Picus

== Progress == * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing the MIR tests (PR27770) - still in upstream review - Submitted another patch fixing two other BPF tests (PR27768/9) - committed upstream - Submitted a patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Investigating the ARM test (PR27765) * Use git worktree in llvm helper scripts [TCWG-587] [4/10] - In review, hopefully we can wrap it up soon * Misc [2/10] - More LLVM backend education (MI level), ARM ARM etc == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Fix the ARM test * Use git worktree in llvm helper scripts [TCWG-587] - Fix a regression in the error-handling - Address review comments

10 years, 4 months

1
0
0 0

[ACTIVITY] 30 May-3 June 2016

by Christophe Lyon

== Progress == * Validation - trying to improve cleanup job such that they skip offline nodes - reviews * Backports - successful backport for our gcc-6 branch * GCC - regressions reports on trunk - preparing removal of neon-testgen.ml * Misc (conf-calls, meetings, emails, ....) == Next == * Validation - prepare switch to docker for buildfarm job - cleanup * Backports * GCC - trunk monitoring - more on AdvSIMD intrinsics

10 years, 4 months

1
0
0 0

Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 2 June 2016 at 23:22, Rafael Espíndola <rafael.espindola(a)gmail.com> wrote: > Because the patch includes way too much and doesn't explain what it is doing. So let me get this straight: someone publishes a patch, you don't like it, you do some private investigations and commit whatever you want without even notifying the original authors? I don't know how you work at your company, but this is not how open source development works. This is not the first time either that you step over people's toes with your "design decisions" that you don't share with anyone. Last year, Adhemerval has worked for three months to get the LLD AArch64 back-end working and out of the blue, no warning, the whole back-end was yanked. It doesn't matter if it was the right decision or not in the long term, we don't just yank things, especially not before some deliberation on the list. See how long is taking for the new pass manager to be enabled, or FastIsel or the new Selection, or the new register allocators, etc. That's not how open source works and I assumed you knew that. > That is a general problem with aarch64, the documentation is missing > and comments have to make due. I had a lot of work to rewrite the > original aarch64 patches to be in line with the rest of lld and I > didn't want to have to do the same for tls. You shouldn't be rewriting *any* patch, but asking the original authors to do that themselves. There is a pattern that I'm seeing and that's that *you* refuse or dismiss more patches than most other people. There are many of your comments on reviews that are just personal, and then you step over people's toes and commits yourself. This does not scale. But more importantly, it puts into doubt the validity of the tool you're so hardly defending. You see, 3 years ago, I was asked to choose between MCLinker and LLD. MCLinker was a linker for all purposes, but Chris Lattner convinced me that LLD is the LLVM linker, and we should be focusing all efforts there. It goes against the commercial interests of Linaro members to choose such a premature technology, and it did put them back years of development, because MCLinker was very close to ready, and MediaTek, despite what people said, was very willing to accept our help. But in the interest of the community, and the open source nature of my work, I have decided to pursue LLD and managed to convince Linaro to put two people working on it. But now, I'm re-evaluating all my strategy, and sincerely, I do not trust the LLD community anymore. > The delay was because of the above mentioned issues. I wanted to make > sure there was a solid foundation. Some patches are quick to review, others take 6 months. If you work in open source you have *got* to understand that. If you're not willing to take that cost, than please, refrain from working open source. > Sorry, no. I understand your position, but you have to understand mine. I therefore call into question your ability to care about such an important project of the LLVM community. I sincerely believe that your actions are harming the project, and the people trying to help. I appreciate the value of your contribution, I really do, but if you don't change your way to handle open source contributions, LLD will, whether you like it or not, become irrelevant and be replaced. Such is the nature of open source. cheers, --renato

10 years, 4 months

2
2
0 0

Re: [lld] r271569 - Start adding tlsdesc support for aarch64.

by Renato Golin

On 2 June 2016 at 20:49, Rafael Espindola via llvm-commits <llvm-commits(a)lists.llvm.org> wrote: > Author: rafael > Date: Thu Jun 2 14:49:53 2016 > New Revision: 271569 > > URL: http://llvm.org/viewvc/llvm-project?rev=271569&view=rev > Log: > Start adding tlsdesc support for aarch64. > > This is mostly extracted from http://reviews.llvm.org/D18960. Rafael, Why commit part of Adhemerval's patch without reviewing his request? This is a really serious breach of community trust. Not only we're waiting for reviews on the TLS set of patches and having to rebase every two weeks, but now you implemented in a way that wasn't discussed on the review, didn't mention authorship, nor asked Adhemerval for any input. If you had technical input on his patch, you should have done on the review. If you wanted him to split in smaller patches, you should have asked on the review and let *him* do it. Even if you were the code owner (which you're not), it would still be a *serious* breach of trust and respect. I hereby respectfully request that you revert your patch and let Adhemerval finish the work that he started in the way that we normally do in the LLVM community. regards, --renato

10 years, 4 months

1
0
0 0

[ACTIVITY] 23 - 27 May 2016

by Yao Qi

* Off on Friday [2/10] # Progress # * TCWG-518, V1 got reviewed, and working on V2. Two existing bugs in GDBserver are found, and fixed. Testing them... [4/10] * Upstream patches review, all of them are about GDB python. [2/10] * Respond to Jim Wilson's question on AIX GDB build failure caused by his binutils patch for AArch64. Confirm that GDB build fail after his patch. [1/10] * Misc, [1/10] # Plan # * Bank holiday on Monday, * TCWG-518, get V2 ready for review, * Ping TCWG-561 and TCWG-547, -- Yao

10 years, 4 months

1
0
0 0

[ACTIVITY] 23 - 27 May 2016

by Omair Javaid

=== This Week === Resolved TCWG-231 (LLDB bring up and bug fixing on HiKey 96Board) [TCWG-231] [1/10] -- Ran tests on AArch64 LLDB tests on HiKey and compared with Nexus 9 test results. -- Less than 1% difference in test results and good pass rate found. LLDB ARM: Bug fixes, integration and testing on various ARM platforms [TCWG-228] [2/10] -- Progressed towards resolution. -- Prepared close out setting up RaspberryPi2, RaspberryPi3, Hikey and Chromebook as testers. -- Compiled armhf test results. LLDB Chromebook Test Stability [TCWG-563] [2/10] -- Some further investigation on llvm-chrome-06 test failures. -- Marked and committed some xfails and reported relevant bugs if not already logged. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] [1/10] -- Debugging of watchpoint handling code and tried out instruction decding. LLDB buildbot updates and maintenance [TCWG-241] [2/10] -- Improved tester script to initiate lldb-server inside a chroot. -- Monitored buildslave stability and Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Migrated laptop to Ubuntu 16.04 === Next Week === LLDB Chromebook Test Stability [TCWG-563] -- Final words on watchpoint issue on llvm-chrome-06 -- Submit updated makefile.rulez for LLDB tests. -- Report remaining bugs and commit xfails upstream. Support for watchpoint un-alligned watchpoint addresses on LLDB AArch64 [TCWG-367] -- Implement instruction decoding for watchpoint hit detection. A look into kernel code used by Nexus android devices failing watchpoint support [TCWG-622] Miscellaneous -- Out of office on Tuesday 31st 2016 for visa documents preparation.

10 years, 4 months

1
0
0 0

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain