# Progress #
* TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [1/10]
Patches are committed.
* TCWG-335, HW breakpoint on 2-byte aligned address, [3/10]
patch is tested against most recent kernel. Everything works.
Patch is committed.
* TCWG-166, Review ARM software breakpoint in GDBserver patches. [1/10]
Almost done.
* Review various upstream patches. [2/10].
* Misc, [3/10]
** Meeting,
** Write up some slides about recent GDB development, and present them
in ARM.
# Plan #
* TCWG-387, Move GDB using libopcodes to decode instructions.
* More upstream patches review.
* Two days off on Tue and Thu. Maybe off on Friday too.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.10 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn228499
* Backport of [Bugfix] [AArch32] Fix PR target/29693
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check
* Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane
bounds in expand
* Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target
* Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404
* Backport of [Bugfix] [AArch32] PR target/52144 attribute target
(thumb,arm) [2.2/6]
* Backport of [Bugfix] [AArch32] PR target/52144 target attributes
Clean up arm_option_params_internals macro settings for
attribute/pragma targets
* Backport of [Bugfix] [AArch32] PR target/65768
* Backport of [Bugfix] [AArch64] PR63870 Neon error messages for
vldN_lane/vstN_lane
* Backport of [Bugfix] Fix PR66168
* Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765
* Backport of [Bugfix] PR c/49551
* Backport of [Bugfix] PR middle-end/64130
* Backport of [Bugfix] PR middle-end/66726
* Backport of [Bugfix] PR target/65768 Check cost of constants before
propagating
* Backport of [Bugfix] PR tree-optimization/67043
* Backport of [AArch32] 1-ARM/Thumb target attributes
* Backport of [AArch32] 2-ARM/Thumb target attributes
* Backport of [AArch32] 3-ARM/Thumb target attributes
* Backport of [AArch32] Add ARM/thumb attribute target
* Backport of [AArch32] Add ARM/thumb pragma target
* Backport of [AArch32] Add TARGET_OPTION_PRINT
* Backport of [AArch32] attribute target (thumb,arm) [2.1/6]
* Backport of [AArch32] Correct spelling of references to ARMv6KZ
* Backport of [AArch32] Fix ChangeLog
* Backport of [AArch32] fix date
* Backport of [AArch32] Fix static interworking call
* Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM
* Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT
* Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when
-mrestrict-it is in place
* Backport of [AArch32] Use dmb ish instead of dmb sy for ARM
* Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap
instructions when available
* Backport of [AArch64] [1/4] Define candidates for instruction fusion
in a .def file
* Backport of [AArch64] 1/5 Use atomic instructions for swap and
fetch-update operations
* Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [2/4] Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch64] 2/5 Make BIC, other logical instructions, available
* Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [3/4] De-const-ify struct tune_params
* Backport of [AArch64] 3/5 Add atomic load-operate instructions
* Backport of [AArch64] [4/4] Add -moverride tuning command, and wire
it up for control of fusion and fma-steering
* Backport of [AArch64] 4/5 Use atomic load-operate instructions for
fetch-update patterns
* Backport of [AArch64] 5/5 Use atomic load-operate instructions for
update-fetch patterns
* Backport of [AArch64] Add ACLE predefined marcos:
__ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR
* Backport of [AArch64] Add support for ARMv8.1 command line options
* Backport of [AArch64] Always register fma_steering pass but gate it
on the target option instead
* Backport of [AArch64] [armv8.1] Expand +rdma documentation, small
changes to march and mcpu text
* Backport of [AArch64] --with-arch in config.gcc support "."
* Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter
* Backport of [AArch64] Fix another ICE with -mgeneral-regs-only
* Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp
* Backport of [AArch64] fix regrename pass to ensure renamings produce
valid insns
* Backport of [AArch64] Fix type of
*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern
* Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch64] Improve spill code - swap order in shl pattern
* Backport of [AArch64] Improve spill code - swap order in shr patterns
* Backport of [AArch64] movi type attribute confusion
* Backport of [AArch64] Removed unused SLOWMUL target flags
* Backport of [AArch64] typo fix in attribute for vst2_lane
* Backport of [AArch64] Use conditional negate for abs
* Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests
* Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when
Thumb mode is not supported
* Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c
* Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should
not add -mfloat-abi=soft
* Backport of [Testsuite] [AArch32] target attribute cleanup directives
* Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn
* Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case
* Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove
useless expected values
* Backport of [Testsuite] Don't specify "dg-do run" explicitly for
vect test cases
* Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove
movw and movt
* Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the
testsuite is explicitly passing -mfloat-abi=hard
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] Skip tests for inappropriate multilibs
* Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Set REG_EQUAL
* Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Fix ChangeLog
* Backport of [Misc] fix segfault in verify_flow_info() with -dx option
* Backport of [Misc] fix typo
* Backport of [Misc] Fix typo: Rename insn_reservation
cortex_53_advsimd to cortex_a53_advsimd
* Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [Misc] [ifcvt Fix typo in comment
* Backport of [Misc] [match-and-simplify] fix incorrect code-gen in
'for' pattern
* Backport of [Misc] [match-and-simplify] reject expanding
operator-list to implicit 'for'
* Backport of [Misc] [match-and-simplify] report error for invalid
operator-lists
* Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) ->
(!y ? -x : x)
* Backport of [Misc] The comparison in a compare exchange should not
take place in VOIDmode
* Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn
* Backport of [Misc] warn for empty struct -Wc++-compat
* Backport of [Misc] [Driver] Wrong C++ paths when configuring with
"--with-sysroot=/"
* Backport of [Misc] [combine][1/2] Try to simplify before substituting
* Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto}
* Backport of [Doc] [AArch64] Fix position of -moverride documentation
* Backport of [Doc] move (Variable Attributes, Type Attributes) up
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
== Progress ==
o Linaro GCC (9/10)
* Backports and Reviews
- FSF branch merge
- AArch64 armv8-1 support backported
- Attribute target almost done
* Long discussion on infra and stability
o Misc (1/10)
* Various meetings
== Plan ==
o Complete backports
o 2015.10 Snapshot
LAVA uinstance for benchmarking - TCWG-396 [3/10]
* Long meeting with Renato + LAVA/lab people
* Much thinking about the security side
* Wrote up rough draft of what I understand the design to be
Investigate effectiveness of noise control measures - TCWG-358 [3/10]
* Set up new host node
* Dealt with one host node crash, one target crash
** Noticed that target was writing logs to tmpfs, changed that so I
can investigate next crash
* Both sides stayed up through the weekend, hurrah
* Some work on data-massaging scripts
Misc [4/10]
Heavier than usual week mail-wise, plus performance review prep
=Plan=
Clean up uinstance design, circulate to make sure we're all on same page
Look at data from experiments so far
Investigate B&B's Debian-building tools
== Progress ==
- 1 day off public holiday (2/10)
- Upstream patch follow-ups (2/10)
* https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html
Trying to reproduce 1.cc failure found with Christophe's testing
* https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html
Committed it and verified this will not happen with linaro-5 branch
- Widening pass (TCWG-547) - 4/10
* iterated based on review comments
- Misc (2/10)
* gcc/bug list
* setup vpn to lab
== Plan ==
* perf with spec2000
* continue with widening pass based on feedback
== Progress ==
* Maintenance (1/10)
- Removed redundant DefaultCPU in ARMTargetInfo
* Buildbots (4/10)
- Looong discussions upstream about stability of buildbots
- Trial with IFC6410 marginally successfull, still not good enough, aborting
- Moved benchmark buildbot to silent (avoid unnecessary spam)
- Writing up some docs on current infra and plan
* Infrastructure (3/10)
- Long internal discussions about stability of TCWG validation
- Agreeing on a LAVA micro-instance in TCWG for benchmarks
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
- Checking status of OpenMP on AArch64 (~10 failures out of ~240 tests)
== Plan ==
More stuff...
# Progress #
* TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [4/10]
After testing, patches are posted upstream.
* In order to review one c++ debugging patch, learn some C++ abi,
vtable and VTT, etc. Understand gcc dump by -fdump-class-hierarchy.
[3/10]
* Fix GDB cxx build breakage caused by my patch. [1/10]
* Ask the effect of -fstack-check=specific to AArch64 prologue. GDB
needs update. [1/10]
* Misc, email, meeting. [1/10].
# Plan #
* TCWG-162, commit patches if no objections.
* TCWG-387, use libopcodes to decode instructions in GDB.
--
Yao
FYI. This is a parity feature with both PowerPC64 and x86_64. Needed to support GCCgo. Note full gold support is needed too.
---------- Forwarded message ----------
From: pinskia at gcc dot gnu.org <gcc-bugzilla(a)gcc.gnu.org>
Date: Tue, Oct 6, 2015 at 3:30 PM
Subject: [Bug target/67877] New: Split stack needs to be support for AARCH64
To: gcc-bugs(a)gcc.gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67877
Bug ID: 67877
Summary: Split stack needs to be support for AARCH64
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pinskia at gcc dot gnu.org
Target Milestone: ---
Target: aarch64-linux-gnu*
To support gccgo better split stack should be implemented.
Connect recovery - [2/10]
Investigate effectiveness of noise-control measures - TCWG-358 [3/10]
* Host node crashed, tried to recover it, failed, started building a new one
Jenkins automation - TCWG-348 [3/10]
* Everything in place up to first interaction with LAVA kvm
* Considered LAVA team's micro-instance proposal
Misc [2/10]
=Plan=
Discuss micro-instance proposal
Work on whatever comes out of discussion
Finish building new host node, get experiments running again
Investigate effectiveness of noise-control measures - TCWG-358 [6/10]
* Finished setup, started running experiments
* Initial data pretty noisy, more runs needed
* Kicked off more runs for week of Connect
Ensure that all critical data is logged - TCWG-349 [1/10]
* Logged a few more variables, tested, merged
* Put down until we have a controlled image build
Misc - [3/10]
* 2 post-connect days off (4/10)
== Progress ==
o Linaro GCC (3/10)
* Backporting armv8-1 support
* Dealing with conflicts
o Misc (3/10)
* Various meetings
* Internal report on Connect
== Plan ==
o Backports
o Releases process tasks
== This week ==
* TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (4/10)
- Patch sent upstream for review
- Fixed some failing tree-ssa testcases by modifying
'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate
Aarch32 supports vector widening add
- Fixed length attributes on patterns in neon.md
- Added test cases to ChangeLog
- Debugging failures on -flto and arm big endian
* TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (3/10)
- Fixed some failing tree-ssa testcases by modifying
'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate
Aarch64 supports vector widening add
- Debugging tree-ssa test suite failures
* Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Patch checked in upstream on trunk
* TCWG-77 - Transform end of loop conditions to min_expr (2/10)
- Submitted upstream waiting for final approval
- Merged multiple patterns into one pattern in match.md
- Rewrote test case to work on all targets
* Misc (1/10)
- Conference calls
== Next week ==
- Holiday/vacation
== Progress ==
- 1 day off recovering from travel and 1 public holiday (4/10)
- https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html (1/10)
* Approved patch
* re-based and retesting before committing
- https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html (1/10)
* Found a latent issue while testing patches
* posted a patch for review
- Widening pass (TCWG-547) - 4/10
* Working on review comments
== Plan ==
* Monday public holiday
* Post the revised patch for widening pass
* commit approved patches
== Progress ==
* Monday off (2/10)
* Buildbot (6/10)
- Investigating sanitizer crash in Thumb2+NEON
- Testing IFC6410 with Linaro 15.09
- CPUs good, 1.7GHz on all cores, stable, cool
- Not enough space on local (fast) flash
- USB stick stable, but slow (3h vs 2h on Chrome 2)
- USB disk unstable and slow (power management, etc)
- SATA broken, and slow
* Infrastructure (1/10)
- Discussing LAVA instance in TCWG lab, benchmarks
- Playing with D02: corrupted system, but the machine is *fast*
* Background (1/10)
- Code review, meetings, discussions, general support, etc.
== Plan ==
* More infrastructure meetings
* More buildbot work
* Whatever...
# Progress #
* TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10]
Patches V1 are ready for upstream submission, but find opcodes has
already interfaces to decode instructions, so decide to use opcodes
for aarch64 GDB first.
* TCWG-387, one patch exposing one opcode interface is pushed in. [4/10]
Switch software single step code for aarch64 to using opcodes
interface. Patch is pushed in.
Rewriting prologue analyser to use opcode interface too.
* TCWG-159, Kernel awareness in GDB. [1/10]
Resume the work as Peter Griffin has cycles to do so. We are happy
with the plan so far.
* Review arm software breakpoint in GDBserver patches. [1/10]
* Misc, [2/10]
# Plan #
* TCWG-387, TCWG-373
--
Yao
== Progress ==
2 days off (4/10)
* Infrastructure/validation: (3/10)
further checking of cross-testing results stability on aarch64-linux
- found a workaround for a timestamp problem (_Pragma3 testcase)
- looked at c11-atomic-exec-5 whose execution time ranges between 1s
and 1h :-)
- forcing make check to -j8 seems to work well, will work on a nicer
improvement
* reported and briefly looked at failure in a new libstdc++ test
(directory_iterator) on armv5t
* Misc (conf calls, meetings, emails, ....) (2/10)
* Internal (1/10)
- GNU linker patch review
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain Release-Candidate GCC 5.1-2015.08-rc2
Archives.
http://snapshots.linaro.org/components/toolchain/binaries/5.1-2015.08-rc2/
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will
shortly spin the Linaro GCC 5.1-2015.08 release if this release-candidate
passes stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at http://
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* 2015.08-rc2
* The Linaro 2015.08-rc2 release-candidate binary toolchain is based on
the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only
changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in
how the binary toolchains were built. The compiler itself was not changed.
* x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are
now correctly configured. This was broken in 2015.08-rc1. The
cross-compiler targetting armv8l-linux-gnueabihf is now correctly
configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8
--with-float=hard --disable-multilib --enable-multiarch.
* Glibc’s slibdir and libdir were once again modified to address Linaro
Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to
/libc/usr/lib/ which breaks things. The following are now the correct
locations:
libdir=lib/ (linker-scripts and static archives)
slibdir=usr/lib/ (shared objects)
rtlddir=lib/ (dynamic linker)
* 2015.08-rc1
* x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now
provided.
Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A)
cross binary toolchain product release and CARD-1637 – Enable Aarch32
(32-bit ARMv8-A) cross binary toolchain product releases ,
armv8l-linux-gnueabihf targetted toolchains are now available as part of
this release-candidate.
* Python support in GDB for both Linux and Mingw32 (32-bit windows).
Delivered as requested in the linaro-toolchain mailing list post
title – windows binary builds with gdb-python enabled?.
* Added missing expat support to GDB.
This addresses the following linaro-toolchain mailing list post –
"Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal
targets."
* A fix for multilib enablement in baremetal toolchains (as described
in ABE Review 6862).
* Library Paths are now congruent with older Linaro Toolchain path
layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved
system libs from /libc/lib/ to /libc/usr/lib/ which breaks things.
libdir=lib/ (shared objects)
slibdir=usr/lib/ (static libraries)
rtlddir=lib/ (dynamic linker)
# Progress #
* TCWG-189, Aarch64 fast tracepoint. [2/10]
Done. Patches are committed.
* TCWG-373, Support displaced stepping on aarch64-linux. [4/10]
GDB works basically, still need to refactor and polish the code.
* TCWG-374, Test displaced stepping on aarch64-linux. [1/10]
Add new tests.
* TCWG-166, gdbserver support for tracepoints on ARM. [3/10].
Review patches, play with patches, and investigate on some issues.
Ongoing.
# Plan #
* TCWG-373, TCWG-374, and TCWG-166.
--
Yao
# Progress #
* TCWG-188, aarch64 GDB multi-arch support. [2/10]
All patches went upstream except that one is blocked by kernel patch.
The work is done!
* TCWG-189, aarch64 fast tracepoint support. [2/10]
Update them and post V2 out. Pending for review.
* TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10]
Think about it, and break it into pieces. Refactor fast tracepoint
code so that some can be reused for displaced stepping.
* TCWG-375, Don't skip gdb.asm/asm-source.exp on aarch64. [1/10]
Patch is pushed in.
* TCWG-166, Review arm tracepoint patches from Ericsson upstream. [1/10]
May have something wrong for permanent breakpoint on thumb code.
Need to figure out a case to trigger that.
* Misc, meeting and training. [2/10]
# Plan #
* TCWG-189, TCWG-373, TCWG-166.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.09 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn227732 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn227732
* Backport of [Bugfix] [AArch32] PR target/26702
* Backport of [Bugfix] [AArch32] PR target/26702
* Backport of [Bugfix] [AArch32] PR rtl-optimization/34503
* Backport of [Bugfix] [AArch32] PR target/64208 iwmmxt pattern
* Backport of [Bugfix] [AArch32] PR target/65924
* Backport of [Bugfix] [AArch64] PR 65770 vstN_lane on bigendian
* Backport of [Bugfix] [AArch64] PR 65375 Fix RTX cost for vector SET
* Backport of [Bugfix] [AArch64] PR target/65491: Classify V1TF
vectors as AAPCS64 short vectors rather than composite types
* Backport of [Bugfix] [AArch64] PR target/66049
* Backport of [Bugfix] [AArch64] PR 63949
* Backport of [Bugfix] PR rtl-optimization/64616 Move insns without
introducing new temporaries in loop2_invariant
* Backport of [Bugfix] PR rtl-optimization/66076
* Backport of [Bugfix] PR tree-optimization/65447
* Backport of [AArch32] Add cpu_defines.h for ARM
* Backport of [AArch32] Additional bics patterns
* Backport of [AArch32] Add support for CFI directives in fp emulation
routines for ARM
* Backport of [AArch32] Add support for crtfastmath
* Backport of [AArch32] Apply arm.h change for previous commit
* Backport of [AArch32] (*arm_subsi3_insn): Fixed redundant alternatives
* Backport of [AArch32] Fix up bootstrap and fix typo in related changelog entry
* Backport of [AArch32] Handle UNSPEC_VOLATILE in rtx costs and don't
recurse inside the unspec
* Backport of [AArch32] insns attributes and alternative cleanups
* Backport of [AArch32] Make tune params tables more self-documenting
* Backport of [AArch32] Remove vec_shr and vec_shr optabs
* Backport of [AArch32] Use uppercase for code iterator names
* Backport of [AArch64] Add alternative 'extr' pattern, calculate rtx
cost properly
* Backport of [AArch64] Add branch-cost to cpu tuning information
* Backport of [AArch64] Add __extension__ and __always_inline__ to
crypto intrinsics
* Backport of [AArch64] Add vcond(u?)didi pattern
* Backport of [AArch64] Fix aarch64_rtx_costs of PLUS/MINUS
* Backport of [AArch64] Fix Cortex-A53 shift costs
* Backport of [AArch64] Fix geniterators.sh to use standard BRE syntax in sed
* Backport of [AArch64] Fix up new line in previous commit
* Backport of [AArch64] Handle FLOAT and UNSIGNED_FLOAT in rtx costs
* Backport of [AArch64] Idiomatic 64x1 comparisons in arm_neon.h
* Backport of [AArch64] Implement -m{cpu,tune,arch}=native using only
/proc/cpuinfo
* Backport of [AArch64] In aarch64_class_max_nregs use UNITS_PER_VREG
and UNITS_PER_WORD
* Backport of [AArch64] Make aarch64_min_divisions_for_recip_mul configurable
* Backport of [AArch64] Properly cost FABD pattern
* Backport of [AArch64] Properly cost MNEG/[SU]MNEGL patterns
* Backport of [AArch64] Properly handle mvn-register and add EON+shift
pattern and cost appropriately
* Backport of [AArch64] Properly handle SHIFT ops and EXTEND in
aarch64_rtx_mult_cost
* Backport of [AArch64] Remember to cost operand 0 in FP compare-with-0.0 case
* Backport of [AArch64] Use extend_arith rtx cost appropriately
* Backport of [AArch64] Use mov for add with large immediate
* Backport of [AArch64] Fix a couple of bugs regarding loop invariant
motion discovered by spec2k6 on aarch64
* Backport of [Musl libc] Add musl support to GCC
* Backport of [Musl libc] libitm fixes for musl support
* Backport of [Musl libc] musl libc config
* Backport of [Musl libc] mips musl support
* Backport of [Musl libc] unwind fix for musl
* Backport of [Musl libc] libstdc++, libgfortran gthr workaround for musl
* Backport of [Musl libc] fixincludes update for musl support
* Backport of [Musl libc] [AArch32] [4/13] arm musl support
* Backport of [Musl libc] [AArch64] [3/13] aarch64 musl support
* Backport of [Testsuite] [AArch32] advsimd-intrinsics.exp:
dg-do-what=compile if HW does not have Neon
* Backport of [Testsuite] [AArch32] Fix test for pr64616
* Backport of [Testsuite] [AArch32] Require Thumb2 effective target
* Backport of [Testsuite] [AArch32] Fix r222371 (PR target/26702)
* Backport of [Testsuite] Cleanup advsimd-intrinsics.exp, removing
unnecessary loop
* Backport of [Testsuite] don't clobber dg-do-what-default in
advsimd-intrinsics.exp
* Backport of [Testsuite] don't try to execute simd.exp tests on
targets without NEON
* Backport of [Testsuite] move check-gcc parallelize value into C front end
* Backport of [Testsuite] new vqmovn test
* Backport of [Testsuite] new vqmovun test
* Backport of [Testsuite] new vqrdmulh_lane test
* Backport of [Testsuite] new vqrdmulh_n test
* Backport of [Testsuite] new vqrdmulh test
* Backport of [Testsuite] new vqrshl test
* Backport of [Testsuite] new vqrshn_n test
* Backport of [Testsuite] new vqrshun_n test
* Backport of [Testsuite] new vqshl_n test
* Backport of [Testsuite] new vqshl test
* Backport of [Testsuite] new vqshlu_n test
* Backport of [Testsuite] new vqshrn_n test
* Backport of [Testsuite] new vqshrun_n test
* Backport of [Testsuite] Reinstate torture-init and torture-finalize
in advsimd-intrinsics.exp
* Backport of [Misc] Try REG_EQUAL for nonzero_bits
* Backport of [Misc] Don't reset ssa_name infor in struct iv
* Backport of [Misc] make clean' fix
* Backport of [Misc] Make vector_compare_rtx cope with VOID mode constants
* Backport of [Misc] set_nonzero_bits_and_sign_copies/combine.c
* Backport of [Misc] Expand pow (x, CONST) using square roots when possible
* Backport of [Doc] [AArch32] (ARM Options, mtune): add missing entries
* Backport of [Doc] Add missing jit and lto info.....
* Backport of [Doc] Declaring Attributes of Functions/split by target
* Backport of [Doc] reorganize (Type Attributes) and (Variable Attributes)
* Backport of [Doc] Update __atomic builtins documentation
* Backport of [Doc] Update definition location of attribute_spec in
documentation
Feedback and Support
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[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Ensure all critical (benchmarking) data is logged - TCWG-349 [1/10]
* Added logging of several factors
* Documented what we do and don't log
Noise control experiments on Juno - TCWG-349 [4/10]
* Rediscovered that my Juno is an r0, not an r1
* Rebuilt target image in a carefully scripted way
* Fiddled about with differences between local and LAVA targets
* Ran a couple of trials to test infrastructure
Connect preparation - [2/10]
* General sorting out of tickets et al
* Final pass through benchmarking presentation
Misc - [3/10]
=Plan=
Merge 'logging' branch
Final pass through logging documentation
Run some noise experiments on Juno
If time, work on Jenkins benchmarking jobs