The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.01 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.02
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn232321
* Fixes Linaro Bugzillas: #1982, #1980
* Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split
* Backport of [BugFix] [AArch32] PR target/68214: Delete
IP-reg-clobbering call-through-mem patterns
* Backport of [BugFix] [AArch32] PR target/68390
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add
compare-of-zero_extract pattern
* Backport of [BugFix] [AArch64] PR target/68696 FAIL:
gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1
* Backport of [BugFix] PR rtl-optimization/68381
* Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1
instructions
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane
and vqrdmlsh_lane
* Backport of [ARMv8.1] [AArch32] Add patterns for new instructions
* Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1
* Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1.
* Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests
* Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time
* Backport of [AArch32] Add attribute for compatibility with ARM pipeline models
* Backport of [AArch32] Fix vector TYPE_MODE in streaming-out
* Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions
* Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1
Adv.SIMD instructions
* Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD
* Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh
* Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane
* Backport of [AArch64] Documentation fix for -fpic
* Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] Fix a few failures with LSE enabled
* Backport of [AArch64] Improve add immediate expansion
* Backport of [AArch64] Improve comparison with complex immediates
followed by branch/cset
* Backport of [AArch64] Rework ARMv8.1 command line options
* Backport of [AArch64] Update patterns to support FP zero
* Backport of [AArch64] Use aarch64_sync_memory_operand in
atomic_store<mode> pattern
* Backport of [AArch64] Use vector wide add for mixed-mode adds
* Backport of [Misc] Only restrict pure simplification in mult-extend
subst case, allow other substitutions
* Backport of [Testsuite] [AArch64] Skip big-endian as well for
gcc.target/aarch64/got_mem_hoist_1.c
* Backport of [Testsuite] Make stackalign test LTO proof
* Backport of [Testsuite] Testcase for PR rtl-optimization/68381
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
o Teaching activity (6/10)
== Progress ==
o Linaro GCC (4/10)
* Restart validation blocked by the last infrastructure issues
* Discussed and reviewed Jenkins jobs fixes.
* Tested potential upstream fixes for linaro BZ 1980 and 1982,
but reverting the offending backports is a better solution.
== Plan ==
o Complete backports and deliver 2016.01 GCC snapshot.
Centralized benchmark source - TCWG-354 [1/10]
* Fixed some bugs in Coremark reporting
* Experimented some more with clang builds, set this aside for now
Port to microinstance - TCWG-432 [3/10]
* Fixed some false assumptions exposed by change to uinstance
* Worked on LAVA side of coremark reporting
Backport benchmarking - TCWG-352 [4/10]
* Fixed some bugs that appeared over the holiday
* Got job dispatching benchmark run to microinstance, with pointer to
backport-containing toolchain
* But resulting job fails
Benchmarking infra documentation - TCWG-496 [1/10]
* Started documenting LAVA wrapper
Misc [1/10]
=Plan=
LAVA side of coremark reporting
Fix backport-dispatched benchmark job
Much more documentation
== Progress ==
LLDB development
-- Fixed thumb mode issues if user triggers changes to PC register
[TCWG-228] [3/10]
-- Triage of testsuite failures on armel chromebook [TCWG-228] [2/10]
-- Update xfail decorators for arm-linux targets. Marked traiged as
xfail. [TCWG-494] [3/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
Half Day Leave [1/10]
-- Tooth extraction surgery.
== Plan ==
LLDB development
-- Triage more failures on armel chromebook [TCWG-228]
-- Submit an updated xfail decorator for arm-linux. [TCWG-494]
Miscellaneous
-- Connect visa follow up.
== This Week ==
* tcwg-72 (2/10)
- Following Jim's suggestions using XEXP (remainder, 0) worked to
resolve segfault
for DImode case
- Resolved ICE's due to (silly) mistakes.
* PR69133 (4/10)
- Reduced test-case following Markus's suggestions.
- I think it happens because node->lto_file_data is set to NULL in
lto_free_function_in_decl_state_for_node ().
Commenting out the following calls from get_untransformed_body():
lto_free_section_data (file_data, LTO_section_function_body, name,
data, len, decl_state->compressed);
lto_free_function_in_decl_state_for_node (this);
prevents the ICE. I suppose symbols with same name in same partition
share state (?), so setting lto_file_data = NULL
affects state of 2nd occurence of symbol and we hit the assert.
If this is true, gating on lto_file_data doesn't seem unreasonable IMO
to avoid ICE (the code anyway has undefined behavior due to violation of ODR).
I am still not sure why this "works" for partitioning enabled (one,
balanced, 1to1).
* 447.deallII bug (1/10)
- Bug not reproducible (verified with Kugan).
* TCWG-319 benchmarking (1/10)
- first job submission failed due to kernel panic
- a53: base fp run completed, with-patch in progress
* Misc (2/10)
- Meetings
- ipa
== Progress ==
* Validation
- a couple of fixes in the validation jobs
- improvements to the comparison scripts
* GCC
- investigated bugs #1980 and #1982.
Reverted the backports that introduced the problem.
- TCWG-485/PR68620: resumed
- TCWG-484: target attributes problems in the testsuite.
Sent an updated patch, but Christian has also submitted
a patch which modifies the compiler behavior. I'll have
to update mine when his patch is accepted.
* Misc (conf calls, meetings, emails, ....)
== Next ==
* Validation: more cleanup. Hopefully start extending validation scope
* GCC:
- bug fixing
- check trunk regressions reported during the holidays
== Progress ==
* Support (2/10)
- Having a go at PR25722, too hacky for a feature that can
be easily worked around.
- Reviewing some kernel issues with Arnd
* Planning (6/10)
- Drafting 2 year plans for LLVM
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
- Catching up from long holidays
# Progress #
* Handle input interrupt in GDB. TCWG-424. Done. [3/10]
Need to update GDB manual to clarify the expected behaviour of GDB.
* Estimate the effort of GDB kernel-awareness work. Done. [1/10]
* TCWG-491. Ongoing. [2/10]. Understand symbol handling
in GDB.
* Various patch review upstream. [2/10].
* Clean up code on arm software single step after some changes from
Ericsson. Ongoing. [2/10].
# Plan #
* TCWG-491.
* Follow up of TCWG-424 to update GDB manual.
* Clean up code on arm software single step.
* Assess the ARM and AArch64 GDB test result, as 7.11 release is
coming soon.
--
Yao
Is it in the 2015.11-1 release ?
- rob -
-------- Original message --------
From: Jim Wilson <jim.wilson(a)linaro.org>
Date: 01/05/2016 19:45 (GMT-07:00)
To: Xiaofeng Ren <xiaofeng.ren(a)nxp.com>
Cc: linaro-toolchain(a)lists.linaro.org, Zhenhua Luo <zhenhua.luo(a)nxp.com>
Subject: Re: gcc-linaro-5.1 vs gcc-linaro-4.8
On Tue, Jan 5, 2016 at 4:19 PM, Xiaofeng Ren <xiaofeng.ren(a)nxp.com> wrote:
> Hello Jim,
> Appreciate for your comments.
> I will try to manually apply that patch on my side and try it.
> BTW, may I know which released Linaro gcc version include that patch? Maybe I can download it and try it quickly.
> https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00025.html
It was backported to our gcc-5 branch on Nov 24 by Yvan. This is
after the latest release 2015-11 was made. The patch is in the
December snapshot, but I think that is a source only release.
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/
You would have to build your own toolchain from that, perhaps by using abe.
Jim
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Linaro TCWG,
In newer toolchains that are built with ABE, libc.a contains a lot of debugging information, including the paths to the source files on the build machine. I think that's because ABE builds the libraries with -g and never strips out the debug information. I verified this with both the 4.9-2015.05 and 5.2-2015.11 binary releases with the command:
arm-linux-gnueabih-objdump -g libc.a | grep '\.c'
In older toolchains that were built with crosstool-ng, libc.a did not contain the paths to the source files. I guess crosstool-ng either didn't build the libraries with -g, or it stripped out the debug information later. I verified this with the 4.9-2014.09 binary release.
I'm not sure whether this change was intentional, or just an oversight during the switchover to ABE. Regardless, it makes the libraries a lot bigger, and it potentially affects the end user during debugging.
The source files of libc, etc. are not typically included with the binary releases. So, when a user of an ABE-built binary release chooses to step into an extern function of libc, gdb will search for the source file. It likely won't be able to access the source file along the same path that worked for the build machine, so it will search its list of source directories. Ultimately, unless the user has downloaded the source files, gdb will likely display a message like "printf.c: No such file or directory".
In contrast, when a user of a crosstool-ng-built toolchain tries to step into an extern function of libc, gdb will be unaware of the name of the source file. As a result, the user will not get a message about a missing file.
So, should the toolchains' libraries really contain debug information? I think it could be useful for a theoretical multilib folder that covers a -g option. On the other hand, for the usual release builds, isn't the debug information a waste of space and a source of confusion?
Thanks,
Fred Peterson
Engineer - Developer Tools
NXP Semiconductors
Hello All,
I found one difference between gcc-linaro-5.1 vs gcc-linaro-4.8 while I'm doing lmbench benchmark test for our LS1043 (cortex-A53).
While using gcc-linaro-4.8, gcc will generate advanced SIMD instructions (like as ld1, etc), however, gcc-linaro-5.1 will not generate advance SIMD instructions. This will cause big performance gap between gcc-4.8 and gcc-5.1 for lmbench memory bandwidth "fcp" test (bw_mem program).
My compiler flags is "-O3 -mcpu=cortex-a53". I also tried several different compiler flags ("-O3 -mcpu=cortex-a53+fp+simd", "-O2 -ftree-vectorize -mcpu=cortex-a53", "-O3 -ftree-vectorize -mcpu=cortex-a53"), all of them doesn't work.
Gcc-5.1 toolchain was downloaded from following link:
https://snapshots.linaro.org/openembedded/sources/gcc-linaro-5.1-snapshot-2…
Can I have your comments on this?
Thanks
Ron
Hello toolchain gurus,
In the course of Linaro's kernel tinification project, the ability to
compile the Linux kernel using LTO is a frequent requirement. However
the kernel makes heavy usage of 'ld -r' with .o files resulting from LTO
build of .c files as well as .o files resulting from pure assembly code.
This mix of LTO and non-LTO object files is not supported by upstream
binutils unless a patch from H.J. Lu is applied. That patch has been
available since 2013 and was last refreshed in his 2.25.51.0.4 branch
last September. It is accessible here:
https://git.linaro.org/toolchain/binutils-gdb.git/commit/6da5456971
I've attached a very simple test case demonstrating the problem. With
the binutils-lto-mixed.patch applied, this test case compiles to a
working executable. Otherwise compilation fails at the 'ld -r' step.
One question and one request:
- What, if anything, has prevented this patch from being merged in the
master branch upstream?
- In the mean time, could we include this patch in the Linaro binutils
package and releases?
Having this available in our toolchain releases would greatly simplify
the LTO related work on the kernel. It was included in all binutils
releases from H.J. Lu since 2013 and therefore has obtained significant
exposure already.
Thanks.
Nicolas
== This Week ==
* TCWG-72 (2/10)
- Trying to address segfault with DImode
* LTO ICE with 483.xalancbmk (6/10)
- fighting with benchmark scripts
- segfaults with ICE on -flto-partitions=none
on symbol _ZThn8_N10xalanc_1_819XercesParserLiaison11resetErrorsEv
demangler.com says the symbol is non-virtual thunk to:
non-virtual thunk to xalanc_1_8::XercesParserLiaison::resetErrors()
./-lm.res (resolution map file) says PREVAILING_DEF_IRONLY
- Trace: http://pastebin.com/vxzmQFHg
- Possible fix: http://pastebin.com/rwq8z1N1
Patch passes test and bootstrap, not sure if that's correct approach however.
* Target hook conversion (2/10)
- Unconditionalizing ASM_OUTPUT_DEF on SET_ASM_OP and converting
both to hooks.
NB Last _6_ working days.
Centralised benchmark source - TCWG-354 [6/10]
* Abe integration
* Wrote up some notes on collaborate
* Enabled clang build, which flushed out some bugs, now fixed
* LAVA reporting script
Port to microinstance - TCWG-432 [1/10]
* Investigating issues with Juno boot
** One turns out to be user error
** The other is a failed heath check, passed to the admins
Backport benchmarking - TCWG-352 [2/10]
* Difficulties with passing information from matrix children to parent
** Came up with an ugly workaround, may have thought of a better one
Misc [3/10]
=Plan=
Holidays until 4th January
# Progress #
* TCWG-156, GDB Test-Suite Parity Between Aarch64 and x86_64. Done. [4/10]
After two patches are committed, except some tests written for x86_64
unnecessarily, the test results between aarch64 and x86_64 looks no
difference.
* TCWG-424, timeout when interrupt the inferior in remote debugging. [3/10]
The fail is caused by different two problems. Two patches are ready,
and being regression tested.
* TCWG-171, Enable gdb core file tests when testing remotely. [1/10]
Write down my conclusion as it can't be fixed.
* Upstream review, [2/10]
** Review patch about handling ada aarch64 HVA array in GDB.
** Discuss target description of GDB for cortex-m device with openocd.
# Plan #
* Post patches upstream for TCWG-424,
* Patches review.
* On holiday since Wed.
--
Yao
Hi All,
I am interested in understanding Linaro LLVM activity.
I have already gone through
https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM.
Could you please guide me on below questions.
1. On which LLVM & clang version, linaro is actively working now ?
2. Where can I find the latest "linaro-llvm" source code & binary? I could
not find any official git repo for "linaro-llvm" at https://git.linaro.org/.
3. Could you please explain Linaro LLVM working model? How
similar/different it is when compared with Linaro-GCC engagement.
4. Certain links (e.g Roadmap) at
https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM ask for login
credentials. Any comment on how to obtain the permission?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
* 1 day off (Friday) (2/10)
== Progress ==
* Validation: (2/10)
- improvements to the comparison scripts
- updated ABE stable and staging branches
* GCC: (3/10)
- TCWG-484: sent a new version of the patch to address problems with
the testsuite and target attributes.
- TCWG-485/PR68620: WIP, trying to understand the regressions
introduced by my patch
* Misc (conf calls, meetings, emails, ...) (3/10)
== Next ==
Holidays until next year
Hi All,
As per release notes, linaro_binutils-2_25-2015_01-2_release should be
present at http://git.linaro.org/toolchain/binutils-gdb.git.
But I am not able to see any "linaro_binutils" tags on
https://git.linaro.org/toolchain/binutils-gdb.git/tags.
Am I doing any mistake? or on git it is renamed to something else (same as
FSF binutils tags?).
Apology for asking such a trivial question.
Thanks for your time.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.12 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn231642 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn231642
* Backport of [Bugfix] [AArch32] 1/4 PR63870 Add qualifiers for NEON builtins
* Backport of [Bugfix] [AArch32] 2/4 PR63870 Mark lane indices of
vldN/vstN with appropriate qualifier
* Backport of [Bugfix] [AArch32] 3/4 PR63870 Remove error for invalid
lane numbers
* Backport of [Bugfix] [AArch32] 4/4 PR63870 Remove xfails for ARM targets
* Backport of [Bugfix] [AArch32] PR67305, tighten
neon_vector_mem_operand on eliminable registers
* Backport of [Bugfix] [AArch32] remove unused variable
* Backport of [Bugfix] [AArch64] PR 63304 Fix issue with global state
* Backport of [Bugfix] [AArch64] PR63304 Handle literal pools for
functions > 1 MiB in size
* Backport of [Bugfix] [AArch64] PR 68088: Fix RTL checking ICE due to
subregs inside accumulator forwarding check
* Backport of [Bugfix] [AArch64] PR rtl-optimization/67218
* Backport of [Bugfix] PR 56036 fix typo in doc
* Backport of [Bugfix] PR rtl-optimization/68236: Exit early from
autoprefetcher lookahead if not in haifa sched
* Backport of [Bugfix] PR tree-optimization/68234 Improve range info
for loop Phi node
* Backport of [AArch32] 1/4 Change GET_MODE_INNER to always return a
non-void mode
* Backport of [AArch32] 2/3 Make if_neg_move and if_move_neg into insn_and_split
* Backport of [AArch32] 2/4 Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch32] 3/3 Expand mod by power of 2
* Backport of [AArch32] 3/4 Replace the pattern GET_MODE_BITSIZE
(GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m)
* Backport of [AArch32] 4/4 Fix - Introduce new inline functions for
GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION
* Backport of [AArch32] 4/4 Introduce new inline functions for
GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION
* Backport of [AArch32/AArch64] 2/2 Add a new Cortex-A53 scheduling model
* Backport of [AArch32] Add missing v8a cpus to the t-aprofile file
* Backport of [AArch32] Fix checking RTL error in cortex_a9_sched_adjust_cost
* Backport of [AArch32] Fix for testcase after r228661
* Backport of [AArch32] Initialise cost to COSTS_N_INSNS (1) and
increment in arm rtx costs
* Backport of [AArch32] libgcc: include crtfastmath
* Backport of [AArch32] Unified assembler in ARM state
* Backport of [AArch64] 1/2 Give AArch64 ROR (Immediate) a new type attribute
* Backport of [AArch64] 1/2 Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G
* Backport of [AArch64] 1/2 Rename test source file for reuse
* Backport of [AArch64] 1/3 Add the option -mtls-size
* Backport of [AArch64] 1/3 Expand signed mod by power of 2 using CSNEG
* Backport of [AArch64] 2/2 Implement -fpic for -mcmodel=small
* Backport of [AArch64] 2/2 Implement TLS IE for tiny model
* Backport of [AArch64] 2/3 Rename SYMBOL_TLSLE to SYMBOL_TLSLE24
* Backport of [AArch64] 3/3 Implement local executable mode for all memory model
* Backport of [AArch64] Add initial qualcomm support
* Backport of [AArch64] Add missing entries in iterator vwcore
* Backport of [AArch64] Cleanup whitespace in aarch64.c
* Backport of [AArch64] Cortex-A57 Choose some new branch costs
* Backport of [AArch64] Define TARGET_UNSPEC_MAY_TRAP_P
* Backport of [AArch64] Distinct costs for sign and zero extension
* Backport of [AArch64] Do not ICE after apologising for -mcmodel=large -fPIC
* Backport of [AArch64] Don't allow -mgeneral-regs-only to change the
.arch assembler directives
* Backport of [AArch64] Don't transform sign and zero extends inside mults
* Backport of [AArch64] Fall back to -fPIC if no support of -fpic in binutils
* Backport of [AArch64] Fix for branch offsets over 1 MiB
* Backport of [AArch64] Fix ICE on (const_double:HF 0.0)
* Backport of [AArch64] Fix insn types
* Backport of [AArch64] Fix output assembly bug under TLSIE ILP32
* Backport of [AArch64] Handle vector float modes properly in
aarch64_output_simd_mov_immediate
* Backport of [AArch64] Mark GOT related MEM rtx as const to help RTL loop IV
* Backport of [AArch64] Properly handle simple arith+extend ops in rtx costs
* Backport of [AArch64] Rename SYMBOL_SMALL_GOTTPREL to SYMBOL_SMALL_TLSIE
* Backport of [AArch64] Restrict pic-small.c by new test directive
* Backport of [AArch64] Tighten direct call pattern for sibcall to
repair -fno-plt
* Backport of [AArch64] Tighten direct call pattern to repair -fno-plt
* Backport of [Testsuite] [AArch32] Fix thumb2-slow-flash-data.c failures
* Backport of [Testsuite] [AArch32] Switch ARM to unified asm
* Backport of [Testsuite] [AArch64] Add more TLS local executable testcases
* Backport of [Testsuite] [AArch64] Check branch types for noplt testcases
* Backport of [Testsuite] [AArch64] Fix gcc.target/aarch64/vclz.c
* Backport of [Testsuite] [AArch64] Fix some target attribute inlining
tests for -fPIC
* Backport of [Testsuite] [AArch64] Restrict got_mem_hoist_1.c with
small memory model
* Backport of [Testsuite] [AArch64] Skip tiny and large code model on
gcc.target/aarch64/pic-small.c
* Backport of [Testsuite] Add --param
sra-max-scalarization-size-Ospeed to sra-12.c
* Backport of [Testsuite] Fix target selector in
gcc.target/i386/noplt-[1234].c testcases
* Backport of [Misc] Allow sibcalls in no-PLT PIC
* Backport of [Misc] Eliminate PLT stubs for specified external
functions via -fno-plt
* Backport of [Misc] Fix for ICE with -g on testcase with incomplete types
* Backport of [Misc] Fix memory leak and wrong invariant dependence
computation in IVOPT
* Backport of [Misc] Improve rtl loop inv cost by checking if the inv
can be propagated to address uses
* Backport of [Cleanup] [AArch32/AArch64] fix ChangeLog
* Backport of [cleanup] [AArch32] Remove uses of CONST_DOUBLE_HIGH/LOW
* Backport of [Cleanup] [AArch64] Delete aarch64_symbol_context which
is not used
* Backport of [cleanup] [AArch64] Move iterators from atomics.md to iterators.md
* Backport of [cleanup] [AArch64] Remove uses of CONST_DOUBLE_HIGH,
CONST_DOUBLE_LOW
* Backport of [Doc] [AArch64] Document several AArch64-specific test directives
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Centralised benchmark source - TCWG-354 [6/10]
* Understood CoremarkPro run rules/behaviour better
* Experimented with shortening runs while still giving meaningful results
* Cleaned up build/run scaffolding
Port to microinstance - TCWG-432 [1/10]
* Got access to microinstance, learned a bit about SSL in the process
Backport benchmarking - TCWG-352 [2/10]
* Fixed 'build with sysroot' code for current deliverable shape
* Fixed a problem with multiple manifests
=Plan=
Review, test, debug build-triggers-benchmark job
Finish off Coremark Pro integration
Review security with shared uinstance/main instance code
Expose more data, benchmarks to bundles
Debug/test Jenkins job in microinstance
Create bootable image for at least 1 target, or know what the problems are
Write up noise control report (if time)
More support for SPEC-on-Android?
=Absence=
Holiday 22nd December - 1st January
== This Week ==
* TCWG-72 (2/10)
- Another iteration.
* LTO (4/10)
- Building spec with different combinations of -flto -flto-partition
-flto-compression-level
- Builds cleanly on AArch64, ICE's on ARM for 447.dealII with -flto
- Looked at segfault with 483.xalanpack
* TCWG-319 benchmarking (1/10)
- fp benchmark results on:
r1-a12: -0.04 %
cortex-a53: -0.09 %
cortex-a57: -0.14%
- int benchmarks completed running for reference revision on cortex-a15
- int benchmarks with-patch runnning on cortex-a15
* TCWG-310 benchmarking (1/10)
- r1-a12: 0.11%
- Benchmark jobs failed on a53, a57.
* Misc (2/10)
- Submitted patch to fix building 450.soplex
- Looked at how to write ipa pass, ipa-pure-const and ipa-cp.
- Meetings
== Next Week ==
- tcwg-319, tcwg-310 benchmarking
- tcwg-72
- LTO
