- linaro-toolchain - lists.linaro.org

by Bernie Ogden

Benchmark infrastructure - TCWG-360 [6/10] * Fixed remaining known critical issues in multinode ** Testing stymied by LAVA oversubscription ** Attempted to implement some workarounds for oversubscription * Some discussion/investigation on generating filesystems for benchmarking * Started brain-dumping state of infrastructure into cards.linaro.org Bringing up Juno for noise control experiments [1/10] * Some struggles with firmware/bootloader configuration Misc [3/10] Featuring some ARM management duties = Plan = * Get benchmarking tests through, if LAVA permits * Fix any critical issues discovered * Finish brain-dump into cards.l.o * Bring up Juno for noise control experiments * Some more ARM management

10 years, 12 months

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[ACTIVITY] 10-14 August 2015

by Christophe Lyon

== Progress == * GCC (4/10) - AdvSIMD failures on aarch64_be: WIP patch makes the intrinsics tests pass, but shows regressions in the vectorizer tests * Releases/snapshots/validation (2/10) - validation monitoring, fixed a couple of minor bugs * Misc (4/10) - meetings, conf-calls, emails == Next == * GCC aarch64_be AdvSIMD * Validation

10 years, 12 months

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[Weekly] 10-14 AUGUST 2015

by Michael Collison

== This week == * TCWG-140 - Transform end of loop conditions to min_expr (4/10) - Wrote initial test case as requested by maintainers - Need to determine how to not run test case on targets with no MIN_EXPR/MAX_EXPR * TCWG-833 - Exploit Wide Add operations when appropriate (4/10) - Fixed internal error by using unspec for vector sign/zero-extend - Fixed multiple issues with test cases - Investigating why gcc.dg/vect/slp-reduc-3.c with lto is regressing for aarch32 and aarc64 - Investigating two additional regression failures on aarch64 * TCWG-834 - Use non-unit stride loads by preference when applicable (1/10) - Spoke with Richard Biener at GNU cauldron. - He indicated this was a problem with a interaction problem with vectorizer not attempting multiple strategies - He indicated that he planned to fix this for GCC 6 and not to attempt a fix - My plan is to write a test case that fails until the issue is addressed in GCC 6 * Misc (1/10) - Conference calls == Next week == - Resolve testsuite regressions for TCWG-833 - Create bugzilla reports for TCWG-833 and TCWG-834 - Write testcase for TCWG-834 and submit upstream - Investigate TCWG-832 as time permits

10 years, 12 months

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[activity] 10 - 14 August 2015

by Prathamesh Kulkarni

== This Week == * TCWG-777 (4/10) - Working on RTL pass, prototype patch works for the test-case. - updating the trunk to r226907 , it appears combine can fold arm_andsi3_insn/arm_cmpsi_insn into zeroextractsi_compare0_scratch at -O2 while not at -O1. .* TCWG-835 (2/10) - Testing patch with Spec 2006 - Found ICE unrelated to my patch * Misc (4/10) - Travel to home from GNU Tools Cauldron 2015, Prague. == Next Week == - Continue working on TCWG-777 - Continue testing TCWG-835 patch with SPEC 2006

10 years, 12 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (CARD-1823 6/10) - Setting up new APMs - Running around for a decent UEFI, Kernel, Distro - Testing different builds, configurations - Managed to get one APM doing the test-suite *only*! sigh... - http://buildmaster.tcwglab.linaro.org/builders/clang-cmake-aarch64-lnt * Background (4/10) - Code review, meetings, discussions, etc. - Doing more reviews than usual due to buildbot work being erradic - Laptop is playing stupid again == Plan == * Moar bots * Moar code review * Maybe some vodka, to wash it all up

11 years

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[ACTIVITY] 3 - 7 August 2015

by Omair Javaid

== Progress == LLDB development -- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [9/10] -- Debugging of watchpoint test failures and problems with multiple watchpoints. -- Clean-up of AArch64 watchpoint code and fixing watchpoint cache bugs. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Submit and get review on bug fixes for lldb on hikey AArch64 code changes. -- Investigate further lldb test failues on hikey AArch64. Miscellaneous -- Friday 14th August, Independence day public holiday in Pakistan.

11 years

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[ACTIVITY] Week 32

by Yvan Roux

== Progress == o Linaro GCC validation (4/10) * Look at the various validation issues we have * Dug into the logs, restarted jobs, asked to restart builders/testers. etc ... o Upstream GCC (5/10) * Investigate OOM issue on armeb-linux-gnu target * Found the issue and raised an upstream bugzilla: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67127 * Submitted a fix for it o Misc (1/10) * Various meetings == Plan == o Continue validation babysitting

11 years

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[ACTIVITY] 3-7 August 2015

by Christophe Lyon

== Progress == * GCC (4/10) - investigating AdvSIMD Failures on aarch64_be. * Releases/snapshots (1/10) - re-spin 4.9-2015.06-1 snapshot - updated list of candidate backports * Misc (4/10) - meetings, conf-calls, emails * Internal (1/10) - ST internal support == Next == * GCC aarch64_be AdvSIMD

11 years

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[ACTIVITY]

by Renato Golin

== Progress == * Performance (CARD-1832 3/10) - Profiling SPEC2k mesa, found some issues - Investigating r232513, unlikely the culprit, but interesting case * Releases (CARD-1431 1/10) - Spinning 3.7.0 RC2 * Buildbots (CARD-1823 4/10) - Setting up new APMs - Dealing with ASAN/TSAN bot breakage - Other buildbot breakages * Background (2/10) - Code review, meetings, discussions, etc. - Writing a bisect script for LLVM

11 years

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[ACTIVITY] 27 - 31 July 2015

by Omair Javaid

== Progress == LLDB development -- Setup lldb test debug environment for testing failing tests on chromebook. [1/10] -- Debug various lldb hang scnarios on chromebook for armhf support [TCWG-855] [4/10] -- Figure out alternate fix for http://reviews.llvm.org/D11129. [TCWG-855] [3/10] Miscellaneous [2/10] -- Fix chromebook malfunction due to battery issues -- Meetings, emails, discussions etc. == Plan == LLDB development -- Debug lldb test cases on armhf to figure out problems in individual test-cases -- Create an updated lldb development project plan on JIRA. -- Update collaborate with steps on LLDB development process.

11 years

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[ACTIVITY] 27th - 31th July

by Kugan

== Progress == * Widening pass (TCWG-547) - 8/10 - Handled review comments. - Improved CONVERT_EXPR handling. - Re based and retested - found some failures. - This was due to VRP reusing the range info computed in VRP1 after type promotion is applied. Invalidating the range info when type is promoted. - ARM with type promotion now improves (-O2) about ~2.8% with one tiny benchmark (where it used to regress). - Still some test cases failures (not execution failures but scanning certain patterns in the dump/asm). * Misc - 2/10 - Connect slides. - gcc-patches, gcc-bgs list - Meetings == Plan == - Widening pass

11 years

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[Weekly] 27-31 JULY 2015

by Michael Collison

== This week == * TCWG-146 - Detect smin/umin idiom (1/10) - Incorporated final feedback and submitted code in SVN * TCWG-140 - Transform end of loop conditions to min_expr (1/10) - Misc. discussion upstream about concerning where optimization should be performed - Upstream maintainers asked me to create gimple ir test case * TCWG-833 - Exploit Wide Add operations when appropriate (1/10) - Unable to validate yet * TCWG-834 - Use non-unit stride loads by preference when applicable (5/10) - Further Aarch32 investigation to determine where decision to forgo vld3 decision is being made * Linaro connect preparation (1/10) * Misc (1/10) - Conference calls == Next week == - Validate patches for TCWG-833 and submit upstream - Further TCWG-834 investigation - GNU Cauldron conference and travel

11 years

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[activity] 27 - 31 July

by Prathamesh Kulkarni

== This Week == * TCWG-835 (4/10) - Validated and submitted patch upstream for review. - Made changes to patches according to upstream reviews. - Microbenchmarks: http://pastebin.com/tDnHZuG5 * TCWG-777 (5/10) - Investigating different ICE's caused by my gimple remove-temps pass - Looked at expansion of GIMPLE_COND - Trying to write rtl version of remove-temps pass * Misc (1/10) - Conference calls == Next Week == - Continue with TCWG-777 - GNU Tools Cauldron 2015

11 years

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[ACTIVITY]

by Renato Golin

== Progress == * Performance (CARD-1832 1/10) - Checking differences of PostRAListSched on OOO ARM cores - Not many changes, ignoring for now * Maintenance (CARD-1833 4/10) - Building libc++/abi/unwind in LLVM/Clang tree - Getting -Wa,-mfpu patches in, last important Clang driver ARM bug - Some patches to get libunwind and libc++ to compile in-tree on ARM - Fixed native sub-features detection (http://llvm.org/PR12794) * Background (5/10) - Code review, meetings, discussions, etc. - Long discussions about TargetTuple/TargetParser/Triple - Lots of patch reviews this week (I mean, *A LOT*) - Moving some machines around, checking for Chromebook batteries - Setting up cross-builder using multiarch / QEMU - Some future planning == Plan == * Look for some more performance issues in 3.7 * Try to hook up the cross-builder * Investigate libc++ check-all failures

11 years

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[ACTIVITY] 27-31 July

by Charles Baylis

Holiday [2/10] Illness [2/10] TCWG-835 - Vector division [1/10] . patch review TCWG-867 - AArch64 post-idx addressing [4/10] . prototype patch works . vectorizer needs more work to exploit this Misc [1/10]

11 years

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[ACTIVITY] 20-24 July

by Charles Baylis

Benchmarking [1/10] TCWG-775 NEON error messages [1/10] . AArch64 patch set approved . rebased/retested and applied TCWG-830/833/835 Vectorization project [5/10] . emails, calls, patch review TCWG-867 - AArch64 post-idx addressing [2/10] . debugging prototype patch Misc [1/10]

11 years

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[ACTIVITY] 13-17 July

by Charles Baylis

Holiday [4/10] Benchmarking [3/10] TCWG-867 - AArch64 post-idx addressing [2/10] . prototype patch Misc [1/10]

11 years

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[ACTIVITY] 27th - 31st July

by Bernie Ogden

Benchmark infrastructure - TCWG-360 [8/10] * Testing found many problems in multinode * Iterating to solutions Misc [2/10] =Plan= Holiday next week. Then back to fixing multinode, incorporating into jenkins, noise control experiments

11 years

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[ACTIVITY] 27th - 31th July

by Yao Qi

# Progress # * TCWG-806, aarch64 remote debugging multi-arch support. [4/10] Patches are posted upstream. * TCWG-860, aarch64 fast tracepoint. [1/10] Patch review and some discussions. * TCWG-757, upstream patch review. [2/10]. ** Review NIOS II R2 patches. ** Fix PR record/18691. * Misc, meeting. [3/10] # Plan # * TCWG-857, Investigate multi-arch HW watchpoint support in GDB and linux kernel. Clean up aarch64 HW watchpoint code. * GNU Tools Cauldron. -- Yao

11 years

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ABE - bug in copy_gcc_libs_to_sysroot() while building native toolchain for aarch64

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I am building a native toolchain for aarch64 with below configurations: --build=x86_64-unknown-linux-gnu --host=aarch64-linux-gnu --target=aarch64-linux-gnu. In copy_gcc_libs_to_sysroot() - which copy libgcc.a to sysroot, current implementation try to find the absolute path of libgcc.a as below : libgcc="`${local_builds}/destdir/${host}/bin/${target}-gcc -print-file-name=${libgcc}` But above line will not execute (i.e. gcc -print-file-name) on x86_64 as the toolchain is native toolchain for aarch64-linux-gnu. Thus a infinite loop will be created in copy command i.e. copying directory x in x. however, when I hard coded the libgcc.a path in my machine (as below), everything went fine. libgcc="/home/vpathak/arm/toolchain/build_abe_new/builds/destdir/aarch64-linux-gnu/lib/gcc/aarch64-linux-gnu/5.1.1/libgcc.a" I think this is a bug in ABE build infrastructure. Thanks. -- with regards, Virendra Kumar Pathak

11 years

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RE: [ACTIVITY] 20th - 24th July

by duane＠duaneellis.com

* TCWG-806, aarch64 remote debugging multi-arch support. [4/10] Patches are done. Need to test them and polish them. Fix various multi-arch issues when --wrapper is used in GDBserver. Patches are pushed in to mainline. Could you describe this activity in more detail? Is the goal here to support mixed aarch32/aarch64 in the same GDB binary and detect the change at runtime? Thanks. -Duane

11 years

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[ACTIVITY] 20th - 24th July

by Kugan

== Progress == * Factor conversion out of COND_EXPR - TCWG-849 (5/10) - Iterated through the review and more testing * Looked at widening pass and the test-case from Wilco (1/10) * Misc (2/10) - Connect slides. - gcc-patches, gcc-bugs list - Meetings * Sick (2/10) == Plan == - GCC Bugs - Widening pass - Linaro bug 1318

11 years

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[Weekly] 20-24 JULY 2015

by Michael Collison

== This week == * TCWG-146 - Detect smin/umin idiom (1/10) - Made change recommended upstream and resubmitted * TCWG-140 - Transform end of loop conditions to min_expr (1/10) - Validated and submitted upstream * TCWG-833 - Exploit Wide Add operations when appropriate (5/10) - Added early clobber and forced operand 0 and operand 2 to match - Finished Aarch32 by using mode iterators - Developed patch for Aarch64 - Wide add instructions are now emitted for both Aarch32 and Aarch64 * TCWG-834 - Use non-unit stride loads by preference when applicable (2/10) - Further Aarch32 investigation * Misc (1/10) - Conference calls == Next week == - Validate patches for TCWG-833 and submit upstream - Further TCWG-834 investigation - Linaro connect presentation preparation

11 years

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[activity] 20 - 24 July 2015

by Prathamesh Kulkarni

* TCWG-835 (6/10) - Looked at newton raphson method - Need to write new md pattern that matches sdiv_optab for modes == v2sf, v4sf - First attempt for patch: http://pastebin.com/NKy8WdWC * TCWG-830 (2/10) - Ran Charles's benchmarks on ARM and AArch64. - Investigating testsuite fallout for ARM patch. - Still blocked by permissions to do benchmarking * Misc (2/10) - Conference Calls - US visa collection == Next Week == - Continue with TCWG-830, TCWG-835, TCWG-777

11 years

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binutils - question on decoding decision tree for aarch64

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I am trying to learn the 'decoding decision tree' for aarch64 in binutils by trying to add a new assembly instruction 'addvp'. For example: addvp x0, x0, 9 For this, I added a entry in struct aarch64_opcode aarch64_opcode_table[] (file opcodes/aarch64-tbl.h) as below: {"addvp", 0x01000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF}, ARM manual say, bit 27 & bit 28 are unallocated. Thus for addvp, I am giving opcode 01000000 (with bit 27 & 28 as 0). With this, generating object file from assembly file is successful (test.s --> test.o); but while disassembling using objdump, it say undefined instruction. >From objdump log: 81002400 .inst 0x81002400 ; undefined (but instruction was generated correct i.e. 81002400 !!!). I know since addvp is a hack instruction, it won't execute on cpu. But still disassembly should succeed. 1. Please help me in knowing what I am doing wrong here ? What else I should do to add a new instruction in binutils ? 2. I also saw some printf in opcodes/aarch64-gen.c which I guess create decoding tree (initialize_decoder_tree()). How to print them ? I made debug =1 but still print is not coming. 3. There are some auto-generated files like aarch64-asm-2.c, aarch64-dis-2.c. How to re-generate them ? Thanks. -- with regards, Virendra Kumar Pathak

11 years

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