The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.03
engineering release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2015.03 is the twelfth Linaro GCC source package
release in the 4.9 series. It is based on FSF GCC 4.9.3-pre+svn221341
and includes performance improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include
* Linaro bugzilla PR fixed : #1149, #1291, #1314
* Updates to GCC 4.9.3-pre+svn221341
* Backport of PR tree-optimization/61607
* Backport of PR tree-optimization/64878
* Backport of PR bootstrap/63204
* Backport of PR ipa/63196
* Backport of PR tree-optimization/64083
* Backport of PR tree-optimization/64284
* Backport of PR middle-end/64246
* Backport of Abstract away marking loops for removal
* Backport of Sanity check removed loops
* Backport of [AArch64] Tighten predicates on SIMD shift intrinsics
* Backport of [AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32
* Backport of [AArch32/AArch64] Improve modeled latency between FP operations
and FP->GP register moves
* Backport of [AArch64] Adjust generic move costs
* Backport of [AArch64] Add range-check for Symbol + offset addressing
* Backport of [AArch64] Add vector pattern for __builtin_ctz
* Backport of [AArch64] Bics instruction generation for aarch64
* Backport of [AArch64] additional bics patterns
* Backport of [AArch64] Fix wrong-code bug in right-shift SISD patterns
* Backport of [Haifa Scheduler] Fix latent bug in macro-fusion/instruction
grouping
* Backport of [testsuite] Fix vaddl and vaddw tests
* Backport of [testsuite] revert changes on check_effective_target_arm_*_ok
* Backport of [testsuite] new set of Neon intrinsics tests
* Backport of [testsuite] fix vbic/vorn Neon tests
* Backport of [testsuite] Add explicit dependency on Neon Cumulative Saturation
flag
* Backport of [testsuite] Be more verbose, and actually confirm that a test was
checked.
* Backport of [testsuite] Add vld1_lane tests
* Backport of [testsuite] Add vldX_dup test.
* Backport of [testsuite] Add vmla and vmls tests.
* Backport of [testsuite] Add vmla_lane and vmls_lane tests.
* Backport of [testsuite] Add vtrn tests. Refactor vzup and vzip tests.
* Backport of [testsuite] Add vmlal and vmlsl tests.
* Backport of [testsuite] Add vmlal_lane and vmlsl_lane tests.
* Backport of [testsuite] Add vmlal_n and vmlsl_n tests.
* Backport of [testsuite] Add vqdmlal and vqdmlsl tests.
* Backport of [testsuite] Add vqdmlal_lane and vqdmlsl_lane tests
* Backport of [testsuite] Add vqdmlal_n and vqdmlsl_n tests.
* Backport of [testsuite] Add vsli_n and vsri_n tests.
* Backport of [testsuite] Add vsubl tests, put most of the code in common with
vaddl in vXXXl.inc.
* Backport of [testsuite] Add vsubw tests, putting most of the code in common
with vaddw
* Backport of [testsuite] Add vmovn tests.
* Backport of [testsuite] Add vmul_lane tests.
* Backport of [testsuite] Add vmul_n tests.
* Backport of [testsuite] Add vmull tests.
* Backport of [testsuite] Add vmull_lane tests.
* Backport of [testsuite] Add vmull_n tests.
* Backport of [testsuite] Add vqdmulh tests.
* Backport of [testsuite] Add vqdmulh_lane tests.
* Backport of [testsuite] Add vqdmulh_n tests.
* Backport of [testsuite] Add vqdmull tests.
* Backport of [testsuite] Add vqdmull_lane tests.
* Backport of [testsuite] Add vqdmull_n tests.
* Backport of [testsuite] Add vsubhn, vraddhn and vrsubhn tests.
* Backport of [testsuite] Add vmla_n and vmls_n tests.
* Backport of [testsuite] Add vpadd, vpmax and vpmin tests.
* Backport of [testsuite] Add vmovl tests.
* Backport of [testsuite] Add vmnv tests.
* Backport of [testsuite] Add vpadal tests.
* Backport of [testsuite] Add vpaddl tests.
* Backport of [testsuite] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
The release tarball will be available on: http://releases.linaro.org/
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Hi,
Linaro GCC 4.9 2015.01 source package has been respun and deployed on:
http://releases.linaro.org/15.01/components/toolchain/gcc-linaro/4.9
This package release contains two fixes for Linaro bugzilla's PR:
* #1291 - ICE (segmentation fault) on arm-linux-gnueabihf
* #1314 - ICE (in in expand_expr_addr_expr_1, at expr.c:7634) on
arm-linux-gnueabihf
You can find the original 2015.01 announcement below
Regards,
Yvan
---------------------------------------------------------------------------------------------------------------------
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.01
engineering release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2015.01 is the tenth Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.3-pre+svn219502 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include
* Linaro bugzilla PR fixed : #902
* Updates to GCC 4.9.3-pre+svn219502
* Backport of [AArch64] Support SISD variants of SCVTF,UCVTF
* Backport of [AArch64] Fix ICE in aarch64_float_const_representable_p
* Backport of [AArch64] Switch to sched-pressure by default.
* Backport of [AArch64] Add scheduler for ThunderX
* Backport of [AArch64] Remove crypto extension from default for cortex-a53,
cortex-a57
* Backport of [AArch64] doloop pattern for -fmodulo-sched
* Backport of [AArch32] Add execution tests of ARM REV intrinsics.
* Backport of [AArch32] Post-indexed addressing for NEON memory access
* Backport of [AArch32] Improve 64 bit division performance (serie)
* Backport of [AArch32] Revert 215321 backport.
* Backport of [AArch32/AArch64] Add ACLE 2.0 predefined macros
* Backport of PR tree-optimization/54742 - extend jump thread for finite state
automata
* Backport of PR target/61997 - cc1plus ICE with aarch64 target using PCH and
builtin functions
* Backport of PR target/63724 - Fix up BSL expander for floating point types
* Backport of [LRA] Relax one gcc_assert in lra-eliminate for fixed register
* Backport of Add clobber_reg function
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the
full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* Linaro bugs (6/10)
#1291 #1293, #1314
* Home PC crashed and required hardware upgrade and software
re-installation (2/10)
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- preparations for benchmarking of proposed changes
* Misc (1/10)
- gcc-patchs and gcc-bugs list
== Plan ==
* TCWG-620 and TCWG-547
* ASAN/TSAN run on 42 bit VA Aarch64 with 64 bit allocator (TCWG-634) (5/10)
* Bug 869 (2/10)
* Bug 1266(1/10)
* Emails, meetings. (2/10)
* Linaro 1-1 with christophe. status call.
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
== Plan ==
* TSAN/ASAN support look why 64 allocator on juno is failing .
* Look at ASAN failures if 64 allocator is enabled on amd-01.
* AMD internal meeting on Tuesday and Wednesday
== Progress ==
* Automation Framework (CARD-1378 5/10)
- Setting up new servers
* Background (5/10)
- Code review, meetings, discussions, etc.
- Updating some LLVM dev scripts
- Adding tools checks to LNT
- EuroLLVM Paper selection
- LLDB/ARM meetings
- Bisecting lots of failures in all bots
== Plan ==
Go back developing LLVM for a change...
Juno cache effects - LDTS-1238 [6/10]
* Ran more experiments
* Cobbled together some gdb/python script to run perf stat within an
address range
* Becoming more confident in my hypotheses
catomics - TCWG-436 [1/10]
* Found and fixed some more sysroot benchmark bugs
* Kicked off a bunch of spec runs, waiting for the results to come back
Benchmark automation - TCWG-360 [1/10]
* A couple of post-lab-maintenance fixups
* Took a first look at result consistency with a broken run intended
for catomics
Misc - [2/10]
* Featuring the start of fixing juno-01
=Plan=
Finish fixing juno-01
Carry on looking at LDTS-1238, hopeful of confirming hypotheses
Analyse catomics results (assuming that they land)
Carry on with Jenkins, if time
== Issue ==
* none
== Progress ==
* Linaro Bugzilla: (5/10)
- #1149: 4.9-2015.01 miscompiles GCC trunk on aarch64-linux-gnu
* Backported upstream bug fix in 2015.01 re-spin branch and our 4.9 one.
- #1291: [4.9 Regression] ICE (segmentation fault) on arm-linux-gnueabihf
* Identified a set of upstream revision that fixe the issue
* Backported them in 2015.01 re-spin branch and our 4.9 one.
- #1314: [4.9 Regression] ICE (in in expand_expr_addr_expr_1, at expr.c:7634)
on arm-linux-gnueabihf
* Identified that it's a duplicate of an upstream bug on 4.9
branch (PR 61207)
which is itself a duplicate of an already fixed bug on trunk (PR 64896)
* Tested backport of the fix on on 4.9 branch.
* Release and Backports (4/10)
- Re-spin 2015.01 source release with fixes for Linaro bugs: #1149 and #1291
- Various supports of backporting activity
- Reviewed some backports
- Discussed our new release/maintenance policy
- Worked on Backflip improvements
* Misc (1/10)
- Various meetings
== Plan ==
* Backport PR 64896 fix into FSF 4.9 branch
* Backport/FSF Merge/Release duty
== Progress ==
Benchmarking 2015.02 [2/10]
. it turns out to be difficult to build previous releases with abe.sh
(bz#776, bz#1307)
. submitted patch to gerrit to improve abe.sh error handling
. benchmarks started on Jenkins
Backports [4/10]
. investigating incorrect merge discovered in review
. resolved... then found more conflicts with other backports
. need to redo backports
bug #1254 [1/10]
. reduced
. started investigating
misc [1/10]
. mailing lists
. meetings
== Plan ==
redo backports of 217440, 217885
start backports of 218021, 218534
bug#1254
vectorization investigation
look at benchmarking results from Jenkins
# Progress #
* aarch64 gdb , TCWG-652, [6/10]
** TCWG-662: Fixed and committed (by Pedro).
** TCWG-660: Rebuild toolchain with ABE.
** TCWG-663: Root cause of fails are known, that test case sets HW
breakpoint on arbitrary address while aarch64 HW breakpoint requires
4-byte align. ARM has the similar HW breakpoint feature, need to
to check on arm target too.
* fsf gdb patch review [2/10]
** Review and approve one patch from IBM which fixes TCWG-669 too.
** Discuss on re-org for syscall catchpoint for different target/arch.
* misc [2/10]
** Meeting.
** Move to the new house.
# Issues #
* Need an ARM board with HW breakpoint support in kernel. I tried
32-bit system on my juno board via schroot, but
PTRACE_SETHBPREGS doesn't work properly.
# Plan #
* TCWG-660: Teach ABE to import systemtap and build glibc with
--enable-systemtap.
* TCWG-663: See how the tests behave on ARM if ARM board is available.
* Other cards under TCWG-652.
--
Yao
== Progress ==
* Validation: (2/10)
- reached a state where Jenkins "green" actually means no regression found
- submitted patches for review
- confirmed that ABE master branch produces results similar to merge branch
- stopped checking the accuracy of report.sh since a few bugzilla
had been submitted, using ST script instead
* Backports (3/10)
- reviews are getting difficult, with lots of conflicts as the 4.9
branch has diverged from trunk quite a lot
* Sanitizers (1/10)
- trying to build LLVM+run the ASAN tests on AArch32
- tried to reconfigure my Hikey 96board with a 42 VA bits enabled
kernel, but it didn't boot: I still don't have access to such a
platform
* GCC FSF trunk/4.9 monitoring
- stopped tracking random "Interrupted system call"
- builds and validations now run faster, but with more frequent such errors
* Misc (4/10)
- meetings, conf-calls, emails, ...
- Release/maintenance branches policy, respin criteria, validation matrix
== Next ==
* Backports: reviews, and improve review-tool
* Sanitizers
Hi,
I have being trying to persuade gcc to generate the ldp instruction without success. I have tried many combinations, below is an example.
--- cut here ---
#define LDP(x,y,p) { \
struct vec { long x, y; } data; \
data = *(struct vec *)p; p += 2; \
x = data.x; y = data.y; \
}
long testp(long *p) {
long x, y;
LDP(x, y, p);
return x+y;
}
--- cut here ---
$ gcc --version
gcc (GCC) 4.9.1
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ gcc -S -O3 ldp.c
$ cat ldp.s
.cpu generic+fp+simd
.file "ldp.c"
.text
.align 2
.global testp
.type testp, %function
testp:
ldr x1, [x0,8] ;; why not ldp?????
ldr x0, [x0]
add x0, x1, x0
ret
.size testp, .-testp
.ident "GCC: (GNU) 4.9.1"
What can I do do make it generate ldp?
Ed.
== Progress ==
Bug triage [2/10]
Bug 1199 analysis [4/10]
reproduced, studied IRA dumps for a while, will have to report this upstream
Backports + BackFLiP enhancement [3/10]
Misc [1/10]
meetings, git training presentation, mailing lists
== Plans ==
benchmark 2015.02 release
more bugs
== Progress ==
LLDB development
-- Some code sniffing and created JIRA cards with some task estimation [2/10]
-- Trying AArch64 cross build and update howto [1/10]
-- Trying Arm cross build and update howto [2/10]
GDB patch updates and test cases for ARM record-replay instruction
recording [4/10]
Miscellaneous [1/10]
-- 96board with custom kernel no success with getting ethernet
working on it yet
== Plan ==
Wind up all pending gdb patches
== Issue ==
* none
== Progress ==
* Release and Backports (6/10)
- Supported backporting activity
- Added new feature to Backflip
- Discussed redefinition of release/maintenance policy
* Misc (4/10)
- Various meetings
- Catch up with mails
- Updated GCC release process in collaborate
- HiKey
== Plan ==
* Release and backport support
== This week ==
Short week - 3 days. Took Sat, Sun off due to health issues, severe
ear infection -:(
* Modularization project
a) TCWG-637: Applied TLC to parser in include-remove tool
b) TCWG-621: Began refactoring rtl.h
c) TCWG-628.
* TCWG-619:
- Started going through LTO documentation.
* Bugs
1178: Found a possible fix, prevents the ICE for the test-case.
== Next week ==
* TCWG-619
* Submit fix to 1178 upstream
* TCWG-628
== This week ==
* GCC Modularization project
- TCWG-621: Refactoring rtl.h almost completed.
- TCWG-639: Working on rewriting the tool in python.
- TCWG-637: Working on basing the tool on rtags instead of ctags.
- TCWG-629: Continue target-hook conversion.
* Backports:
- Submitted following backports for review:
r215612, r215722, r219656, r219657, r219659, r219661
== Issues ==
- Building chromium dependencies.
- Cannot log in to NX session on tcwg-env-05.
== Next Week ==
- Chromium LTO build (TCWG-619)
- Validate and commit backports.
== Progress ==
* compiler-pass to widen computation (TCWG-547) - (7/10)
- ran into -std=gnu90 issue in compiling spec2k/2006 with the trunk
using the new infrastructure
- ran benchmarking but the results are not much different
- tried with -save-temps but the intermediates are gone. Not sure if
infrastructure cleans it
- setting up spec2k in nx aarch64 chroot for easy comparison of
intermediate values (asm and tree dumps)
- also plan to try benchmarking with widening pass enabled only for
unsigned type where BIT_AND_EXPR (zero_extend) is optimized well as
compared to new middle-end ZEXT_EXPR (which is not handled well yet) to
see if the difference is there.
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- Looked at the relevant patches and code
* https://bugs.linaro.org/show_bug.cgi?id=1291 (1/10)
* Misc (1/10)
== Plan ==
* TCWG-620 and TCWG-547
* https://bugs.linaro.org/show_bug.cgi?id=1291
* TSAN support for Aarch64 (5/10)
TCWG-642
Discussed on making -pie for -fsanitize=thread as default in GCC.
Learnt that LLVM sanitizers now support both -pie and non -pie mode.
Discussed the same issue with sanitizer's group. They asked me to
do -pie for aarch64 as first version. Pushed GCC changes to
linaro git.
TCWG-654
Discussed with Renato, moved to LLVM tree and woking on that.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946.
TCWG-634
Ran ASAN tests which 32 bit allocator code now as default on amd-01.
/home/venkataramanan.kumar/LLVM/TSAN_port/Source/projects/compiler-
rt/lib/sanitizer_common/sanitizer_allocator.h:841
((res)) < ((kNumPossibleRegions)) (4193146, 524288)
I got similar error in TSAN and it went off when I switched to 64
bit allocator.
* Bug 869 - Wrote a pattern in match.pd to remove type promotion in
ABS_EXPR . Richard Beiner suggested to add ABSU_EXPR to take care of
signed overflows (3/10)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946
* Emails, meetings. (2/10)
* Linaro 1-1 with christophe, maxim and Ryan.
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
== Plan ==
* TSAN/ASAN support look if 64 allocator is needed or not .
* LLVM build with local patches.
* Bug869.
* Misc and Meetings (AMD, LInaro)
== Progress ==
* Releases (CARD-1431 2/10)
- Spinning RC4, final, all green
* Buildbots (CARD-1823 1/10)
- Adding new quick Thumb2 non-NEON bot
- Adding new full self-hosting Thumb2 bot
* Libraries (CARD-1831 1/10)
- Trying to build a soft-float compiler-rt test-suite
* Sanitizers for AArch32/64 (CARD-1753 4/10)
- Investigating/fixing broken sanitizer bots (4 failures)
- Investigating other sanitizer failures on Junos
- More planning on TSAN, ASAN
* Background (2/10)
- Code review, meetings, discussions, etc.
- Reviewing the remaining EuroLLVM papers
- More LLDB planning
== Plan ==
* LLDB meeting with Google
* EuroLLVM final paper review meeting
* Continue building test-suite with Compiler-RT, libc++
* Continue help on ASAN/TSAN
* Try our first sprint planning...
# Progress #
* aarch64 gdb, TCWG-652, [5/10]
** TCWG-653: triage fails in aarch64-linux gdb testing, both native and
remote. Nearly done.
** TCWG-670: Clean up GDB testsuite for syscall catchpoint first.
Ongoing.
** TCWG-672: GDB can't unwind from glibc with the expected function name
if glibc is stripped. Nearly done.
** Committed two patches upstream fixing two fails on aarch64-linux
target.
** Clean up arm and aarch64 bug reports on sourceware.org bugzilla.
* fsf gdb patch review [4/10]
** Reviewed Omair's two process record GDB patches.
** Reviewed one patch may cause fails on remote testing.
* misc [1/10]
** 1x1 with Ryan.
** With Bernard's help, set up ssh access to linaro servers.
# Plan #
* All cards under TCWG-652.
* Move out of temporary apartment to a rented one on Friday.
--
Yao
Go away where ? ABE just uses whatever triplet you give it. I commonly use just arm-linux-gnueabi for example. If you don't specify 'none', it shouldn't appear anywhere. If it does, let me know and I'll fix it.
- rob -
-------- Original message --------
From: Christopher Covington <cov(a)codeaurora.org>
Date: 02/26/2015 2:52 AM (GMT+07:00)
To: linaro-toolchain(a)lists.linaro.org
Subject: Debian Multiarch Tuple Style Naming With ABE
Hi,
I recently built with ABE for the first time. It's pretty slick.
Is there a way to make the vendor string (the "none" in
"arm-none-linux-gnueabihf-*") go away? It breaks my scripts without appearing
to add value.
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Holiday Friday [2/10]
catomics - TCWG-436 [2/10]
* Fixed broken benchmark-against-sysroot code in scripts
* Built a lot of sysroots
Juno cache effects - LDTS-1238 [4/10]
* Quite a bit of reading and learning some more perf and other tools
* Formed a few hypothesis, started testing
* Looking promising, but I find these things often go wrong, so we'll see
Misc [2/10]
* Featuring first successful Jenkins run of all of SPEC2006
=Plan=
Make sure I've really fixed the last sysroot bug, actually run
benchmarks on catomics
Attempt to close out the cache effects issue
Carry on with Jenkins
