== Progress ==
* Automation Framework (CARD-1378 1/10)
- Setting up Junos with ARM
* Toolchain (CARD-862 1/10)
- Some progress on fpu parser issue
- Produced a lot more work for the near future
* Buildbots (TCWG-76 4/10)
- Setting up a libc++ buildbot, working on reducing failures
- Some bots broken, bisecting
* Background (4/10)
- Code review, meetings, discussions, etc.
- Annual review
- More lab move planning
- EuroLLVM meetings and planning
== Plan ==
* US LLVM whole next week
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.10
release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.10 is the seventh Linaro GCC source package release. It is
based on FSF GCC 4.9.2-pre+svn216130 and includes performance improvements and
bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly enginering[2] releases.
Interesting changes in this GCC source package release include
* Updates to GCC 4.9.2-pre+svn216130
* Backport of [AArch64] Define TARGET_FLAGS_REGNUM
* Backport of PR target/61565
* Backport of [AArch64] libitm: Improve _ITM_beginTransaction
* Backport of [AArch64] Fix *extr_insv_lower_reg<mode> pattern
* Backport of [AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
* Backport of [AArch32] Implement and vectorize lceil, lfloor, lround optabs
with new ARMv8-A instructions
* Backport of [AArch64] Improve epilogue unwind info rth
* Backport of [AArch64] Add a mode to operand 1 of sibcall_value_insn
* Backport of [AArch64] Add a builtin for rbit(q?)_p8; add intrinsics and tests
* Backport of [AArch32/AArch64] Schedule alu_ext for Cortex-A53
* Backport of [AArch64] Remove varargs from aarch64_simd_expand_args
* Backport of [AArch64] Tidy: remove unused qualifier_const_pointer
* Backport of [AArch32/AArch64] Add scheduling info for ARMv8-A FPU new
instructions in Cortex-A53
* Backport of [AArch32] Convert FP mnemonics to UAL.
* Backport of [AArch32] Enable auto-vectorization for copysignf
* Backport of [AArch32][tests] Make input and output arrays 128-bit aligned in
vectorisation tests
* Backport of [AArch64] Add crtfastmath
* Backport of PR target/56846 libstdc++
* Backport of PR target/63209
* Backport of [Ree] Ensure inserted copy don't change the number of hard
registers
* Backport of [AArch64] Fix force_simd macro in vdup_lane_2
* Backport of [AArch32] Disallow -mfpu=neon for unsuitable architectures
* Backport of [AArch32] movmisalign<mode>_neon_load
* Backport of [AArch64] Add constraint letter for stack_protect_test pattern
* Backport of [AArch64] Auto-generate the "BUILTIN_" macros
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Hi,
I start to use Linary AArch64 toolchain recently and just joined this maillist. I went through some of the archived threads but didn't read all of them. So bear me if I'm asking dumb question or old question which had been answered before.
For our use case, we are running the gdb client at early state of boot. So the ARMv8 target might be running into any EL and into either AArch64 or AArch32 state. My questions are:
1) Is the aarch64-none-elf-gdb.exe good for both AArch64 and AArch32 or I have to run the arm-none-eabi-gdb.exe if the target running in AArch32 state?
2) If the target is in AArch64 state, can I use the aarch64-none-elf-gdb.exe to load binary built for AArch32 to the target?
I'm really appreciated if anybody can help me on these two questions.
Thanks in advance,
StrongQ
cbuild2 benchmarking - TCWG-360 [3/10]
* A few small enhancements and bug-fixes
* Tried to run spec2006 on Juno, looks tricky
libm profiling - CARD-1693 [3/10]
* Pulled together lapack + blas
* Looked a bit at how it exercises libm on x86
* Tried to look at how it exercises libm on Juno, looks tricky
Meetings/mail/etc [4/10]
* Featuring some fun with backups and ARM performance review season
=Plan=
* cbuild2 benchmarking - keep chipping away at spec/juno
* libm profiling - attempt to assemble an AArch64 setup that works for me
* further performance review/corporate admin will take up extra time
this week, but should then fall back to normal levels
=Issues=
State of the setup on our Junos
== Progress ==
* Part way through integrating Cbuild2/Jenkins with Gerrit. (#1692,
8/10)
- Implemented functions to use the REST API to Gerrit via SSH.
- Integrated into build and test processes.
* Meetings and Misc (2/10)
- Ordered 10 Snapdragon boards
== Plan ==
* Finish Gerrit integration with Cbuild2 and Jenkins. (#1692)
- Find a way the buildslave user can use the SSH connection to Gerrit.
* Start merging the linaro branch in DejaGnu to master to get
ready for the next release.
* Start getting ready for the lab move, do what I can ahead of time.
== Issues ==
* Gerrit comments via REST strip out all newlines, so I need to
limit the message size after a test run.
= Progress ==
* Core mark benchmark and report for PGO and PGO + LTO (TCWG-544) (6/10)
Going by CPU cycles adding LTO gains in x86 and degrades in Aarch64 .
Looked at hot functions and examining assembly the code generation seems to
be same. X86_64 does alignment of code. Also branch misses decreased in
X86_64 compared to Aarch64 with -flto + -O3.
Also profiled for instruction counts on Aarch64 with linaro compiler. These
profiles say that we are executing less instructions with LTO and PGO for
Aarch64.
* PR 63173- Reproduced the issue and changed the test case to work with
trunk. Now Looks like someone else has a patch for it. (1/10). so will
work on other bugs.
* Misc [3/10]
Internal work, emails, AMD meetings and 1-1 with inline manger.
1-1 with Maxim, christophe and 1-1 with ryan
== Plan ==
* Coremark benchmark and profiling.
Investigate trunk degradation for O3+ PGO + LTO and report.
== leaves ==
Diwali holiday (22-24)
== Issues ==
* Still no network at home and will not be fixed before at least one week :(
== Progress ==
* GCC 4.9 2014.10 (8/10)
- Merged FSF 4.9 branch
- Released Linaro 4.9 2014.10
* Misc: (2/10)
- Various meetings.
== Plan ==
* Analyse some failures that occur only in --enable-release.
== Progress ==
Catch up with work after return from Eid ul Adha and Annual Holidays [7/10]
* Hong Kong visa application
* UPS repairs and office cleanup
* Catching up with work, gdb roadmap and open/running cards.
* Emails/Patch scrolling/Meetings etc
* Sick day off on Monday
GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480] [3/10]
* Getting re-synced with code where I left.
== Plan ==
Further progress on GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480]
Investigate possibility of AArch64 trace-point work without
availability of hardware.
Check for GDB status on ARM and AArch64 vs x86.
== Progress ==
* Zero/sign extension elimination with widening types (TCWG-546 - 9/10)
- Fixed ICEs and now can build the cross compiler and do the regression
testing with qemu
- some test-cases are failing due to condition that rely on overflow;
this need fixing.
- Bootstrapping on AArch64 still fails (but much later than previously).
- Verified CRC is optimized
* Improve block memory operations by GCC (TCWG-142 - 1/10)
- Looked at the changes since the card was drafted
== Plan ==
* Continue with Zero/sign extension pass.
== Progress ==
* GCC trunk/4.9 validation (CARD-647) (3/10)
- committed testsuite patch to test if -shared is supported
- forcing -mword-relocations flags when compiling testglue works on
my Ubuntu machines, but does not in the Compute Farm RHEL5 servers.
- investigating why, all the more as it made me incorrectly report
failures in the 4.9 branch
* Validation (2/10)
- compared cbuild2 schroot-test branch and master
the results of this manual run does not seem to match Jenkins results
* Neon intrinsics tests (1/10)
- fixed .exp harness to support parallelization
- looking at how to pre-support fp16, will probably skip it for now,
and add dedicated tests later
* AArch64 sanitizer (1/10)
- GCC trunk seems to need to cherry pick a sanitizer patch when
building using recent kernel headers
- tried to use Jenkins to build trunk and trunk+cherry-pick, but the
results are not consistent
needs more investigation
* Misc (3/10)
- calls, meetings, irc
== Next ==
* GCC trunk/4.9 cross-validation
- fix -mword-relocations support
- investigate abi_check test
* AArch64 sanitizer
* Neon intrisics tests update
* cbuild2:
- analyze previous results (mostly check the logs....)
- look at backport-test script + logs
Short next week: off Wednesday/Thursday
== Progress ==
* Respin of malloc single-thread optimizations (4/10, TCWG-436)
- Create a generic header, include AArch64 in series
* Further work on malloc app benchmark framework (4/10, TCWG-441)
- Cleaned up, improved reliability, added comments
- Committed to cortex-malloc.git
* Email, meetings, etc. (1/10)
* Upstream work (1/10, CARD-341)
- glibc patch review and pings
- Look into some bug reports and testsuite failures
== Issues ==
* Electricians and gas engineers turning off power/heating at various points
== Plan ==
* Hopefully get some resolution of single thread atomic stuff for glibc
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Linux Plumbers (6/10)
- Attended conference, Android/Tools/LLVM tracks
- Presented 2 talks (GCC+LLVM and LLVM+ARM)
* Buildbots (TCWG-76 2/10)
- Made the Compiler-RT bot green! Now on to the libc++ one
* Background (2/10)
- Code review, meetings, discussions, etc.
- Internet upgrade, re-wiring the house, building works
== Plan ==
* Add libc++abi buildbot
* Follow up on the fpu issues on Clang/asm
FYI.
The whole thread is available here:
http://article.gmane.org/gmane.linux.ports.arm.omap/119412
---------- Forwarded message ----------
Date: Thu, 16 Oct 2014 01:18:01 +0100
From: Russell King - ARM Linux <linux(a)arm.linux.org.uk>
To: Peter Hurley <peter(a)hurleysoftware.com>
Cc: Nathan Lynch <Nathan_Lynch(a)mentor.com>,
David Laight <David.Laight(a)ACULAB.COM>,
Otavio Salvador <otavio(a)ossystems.com.br>,
Linus Torvalds <torvalds(a)linux-foundation.org>,
Nicolas Pitre <nico(a)fluxnic.net>,
Linux OMAP Mailing List <linux-omap(a)vger.kernel.org>,
linux-arm-kernel(a)lists.infradead.org
Message-ID: <20141016001801.GQ12379(a)n2100.arm.linux.org.uk>
Subject: Re: [PATCH] ARM: Blacklist GCC 4.8.0 to GCC 4.8.2 - PR58854
On Wed, Oct 15, 2014 at 06:18:30PM -0400, Peter Hurley wrote:
> On 10/15/2014 05:56 PM, Russell King wrote:
> > I was in two minds whether to include 4.8.3 as Linaro released a buggy
> > toolchain which identifies itself as 4.8.3, but I decided that's also
> > a distro problem. IMHO Linaro should really think about taking that
> > compiler down given the seriousness of this bug and it being
> > indistinguishable from the fixed stock version.
>
> Maybe it's unfair to blame them; Linaro just took a snapshot and
> released what was there.
>
> If gcc is going to retain the "change release number then add all the
> new features" model, some kind of prerelease indicator would help
> eliminate this kind of problem. And that indicator should be both
> a preprocessor define and parseable from the command line :)
My comment is not to attribute blame to them, my comment is entirely
on a technical level.
My reasoning is that the bug is just as prevalent in userspace, though
it will occur less often. Any program which uses signal handlers is
a candidate for exactly the same kind of corruption, since you can
receive that signal between the point that the stack pointer is
modified and the function loads the parent context.
Of course, there are ways around that: don't use signal handlers, or
if you do, use alternate signal stacks. Neither of those can be
guaranteed for any program though.
So, let me put this another way: a compiler with this bug is _completely_
unsuitable for use for compiling programs for use under the Linux
kernel _as well_ as the Linux kernel itself.
The difference is that the Linaro compilers come with an expectation
that they are usable on ARM... whereas stock versions cover a lot more
and so the ARM arch is probably very small number of their users.
Hence why I recommend that Linaro takes down their buggy compiler.
Their 4.8.3 version should not be used *anywhere*, just the same as
the stock 4.8 to 4.8.2 inclusive should also not be used anywhere on
ARM either.
== Progress ==
Neon vld/vst [4/10]
. submitted v2 of vldN_lane patch (respin of patches 1&2 only)
. continued ML discussion about patches 3&4.
Tried out jenkins/cbuild infrastructure [1/10]
. hardest part was getting git.linaro.org/people to hold my test tree
. https://wiki.linaro.org/Platform/Systems/GitServer#Creating_new_repositories
. if it doesn't work, ask ITS to check you are in the git-users group
. still need to find where the results go.
bug 403/418 wrong line number on neon error messages [2/10]
. experimented with a couple of ways to solve this
bug 715 [2/10]
. investigated and closed as only affects deprecated old ABI
Misc [1/10]
== Plan ==
Benchmark 2014.10 release
Continue bug 403/418 work
== Progress ==
* Further work on malloc single-thread optimizations (2/10, TCWG-436)
- Still pending some resolution on direction from upstream
* Upstream work (1/10, CARD-341)
- Patch review
- Applied binutils patch for missing AArch64 relocs
* Further work on malloc app benchmark framework (2/10, TCWG-441)
- Found a possible way to get memory statistics without hacks, should improve
speed and reliability of the benchmark framework
* Email, meetings, etc. (1/10)
* Thursday and Friday annual leave (4/10)
== Issues ==
* None
== Plan ==
* Get malloc app benchmark framework into shape and committed
* Figure out direction for malloc single thread optimization work
--
Will Newton
Toolchain Working Group, Linaro
cbuild2 benchmarking - TCWG-360 [7/10]
* Fixed/worked around some especially resilient bugs
** Mostly relate to running benchmarks through LAVA, which may be less
important in the near future
* Wrote a doc
* Upstreamed some code that works about as I want it to
Meetings/mail/etc [3/10]
=Plan=
cbuild2 benchmarking
* Work through TODO list from connect
* Tidy up behaviour on shutdown
* Storage issues
* (Maybe) persuade a LAVA Juno to work for benchmarking or configure spec
Hopefully pick up something else
= Progress ==
* Core mark benchmark and report for PGO and PGO + LTO (4/10)
More profiling and collected numbers and reported. JIRA card TCWG-181 updated.
Adding LTO gains in x86 and degrades in Aarch64 .
* Addressed machine bring up issues, debugged and installed necessary
packages for both x86 and Aarch64 (1/10)
* PR 62308 - Analyzed RTL dumps. Looks to be similar issue solved in
trunk. Git bisected and found the passing revision in trunk. posted my
comments. waiting for feedback. (2/10)
* Misc [3/10]
Internal work, emails, AMD meetings and 1-1 with inline manger.
1-1 with Maxim, christophe and 1-1 with ryan
Linaro status call
== Plan ==
* Coremark benchmark and profiling for PGO and PGO + LTO. Investigate
LTO degradation causes and report.
* Investigate PR 63173
* Setup Cbuildv2 build in internal machine.
== Issues ==
Experiencing Hardware connection issues and kernel instability issues
with my local machines.
== Holiday ==
* Public Holiday (2/10)
* Leave (4/10)
== Progress ==
* Zero/sign extension elimination with widening types (4/10)
- Started experimented with a pass for widening type.
- Verified for one simple test-case.
- Bootstrapping is failing and looking into it.
== Plan ==
* Continue with Zero/sign extension pass.
== Progress ==
* Automation Framework (CARD-1378 1/10)
- Planning LAVA server for new TCWG gateway
* Buildbots (TCWG-76 7/10)
- Fixing Compiler-RT buildbot (from 69 to 4 failures)
* Background (2/10)
- Code review, meetings, discussions, etc.
- Re-testing a change in inst combine that broke bots before
- Reviewing CMake builder for Windows builds
- Discussing clang-reformat on lld's codebase
== Plan ==
* Continue fixing the Compiler-RT buildbot
* Present 2 talks at Linux Plumbers
== Progress ==
* GCC trunk/4.9 cross-validation (CARD-647) (2/10)
- trunk build for aarch64 reported to fail because libsanitizer
requires an update. Pinged libsanitizers maintainers but got no answer
so far.
- posted testsuite patch to test if -shared is supported
- managed to find how to force target-dependent -mword-relocations
flags to compile testglue, without needing a testuite patch :-)
* Validation (3/10)
- compared cbuild2 schroot-test branch using (default) shared libs
and forcing static libs
Using static libs causes many unresolved and unsupported tests
- compared using unix.exp and arm-linux.exp: the latter causes
creates instability in the results
* Neon intrinsics tests (2/10)
- rebased on trunk, applied requested changes
- the make-check parallelization support has changed mid-September,
took some time to discover that my .exp harness was now incompatible.
* Misc (3/10)
- calls/meetings
== Next ==
* GCC trunk/4.9 cross-validation
- continue investigation of abi_check test
* Neon intrinsic tests update, trying to take float16 types into account
* cbuild2:
- compare results + validation time of stable and schroot-test branches
- look at backport-test script + logs