Hi,
I'm having some very odd problems building the 2014.08 toolchain respin --
in the cbuild1 i686-lucid env, building glibc fails with
[ERROR] ../sysdeps/unix/sysv/linux/bits/sched.h:127:14: error:
variably modified '__bits' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sched.h:127:14: error:
variably modified '__bits' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sigset.h:29:23: error:
variably modified '__val' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sigset.h:29:23: error:
variably modified '__val' at file scope
[ERROR] ../misc/sys/select.h:69:15: error: variably modified
'fds_bits' at file scope
[ERROR] ../misc/sys/select.h:69:15: error: variably modified
'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/linux/posix_types.h:25:16:
error: variably modified 'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:33:2:
error: requested alignment is not a positive power of 2
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:53:2:
error: unknown type name '__uint128_t'
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/linux/posix_types.h:25:16:
error: variably modified 'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:33:2:
error: requested alignment is not a positive power of 2
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:53:2:
error: unknown type name '__uint128_t'
[ERROR] ../ports/sysdeps/unix/sysv/linux/aarch64/sys/user.h:32:3:
error: unknown type name '__uint128_t'
[ERROR] ../ports/sysdeps/unix/sysv/linux/aarch64/sys/user.h:32:3:
error: unknown type name '__uint128_t'
(Yes, the fix is to get rid of cbuild1 and more importantly the requirement
for 32-bit builds in a prehistoric environment - it builds just fine on
64-bit present-day boxes... But I don't think we want to make that change
in a respin).
The "variably modified" errors remain even after hardcoding
typedef struct {
__cpu_mask __bits[16];
} cpu_set_t;
instead of relying on __CPU_SETSIZE and __NCPUBITS, and the line where it
complains about alignment not being a positive power of 2 actually
hardcodes an alignment of 16.
Have you run into those before?
ttyl
bero
== Progress ==
Debug KGDB with gdb for testing [4/10]
LCU14 slides preparation and study for presentation. [2/10]
Miscellaneous [4/10]
* Configure to use hackbox to test aarch64 gdb remote configs
* Retrieve gdb test results in different configurations.
* Emails/Patch scrolling/Meetings etc
== Plan ==
patch updates and re submission.
Figure ARM and AArch64 gdb missing features.
Prepare and travel LCU14
=Progress=
cbuild2 benchmarking - TCWG-360 [8/10]
* Got an end-to-end run in my test environment
* Patched tests to run more selectively (in review)
Meetings/mail/etc - [2/10]
=Plan=
cbuild2 benchmarking:
* Clean up some lose ends
* Sort out source/results storage
glibc:
* Finish comments in lowlevellock.h (if time)
4 days week.
== Issues ==
* Unfortunate cbuild schroot-branch merge, silently brake the validation, and we
had to revert a commit in our FSF repo.
* aarch64 bare valdiation was broken all week, now workaround but it
still have to
be fixed.
== Progress ==
* GCC 4.9 2014.09 (6/10)
- Completed new backports.
- Started FSF 4.9 branch merge for 2014.09
- Investigated validation breakages.
* Misc:
- Various meetings (2/10)
== Next ==
- 4.9 2014.09 release.
- Prepare LCU hacking session
- Travel to CA
== This week ==
* USA Holiday, Monday September 1st
* TCWG-534 - Neon intrinsic testing part 8 (2/10)
- Tested final eighteen neon intrinsics on ARM with no regressions
identified
- Unable to test on aarch64 due to test harness issues
* Linaro Bugzilla 331 - [4.9 Regression] ICE in final_scan_insn, at
final.c:2952 (aarch64-linux-gnu) (2/10)
- Bug fix investigation
* Launchpad 1312931- gcc 4.8 internal compiler error: in add_stores, at
var-tracking.c (2/10)
- validation test results review and code review submission
* Misc. (2/10)
- Linaro Connect presentation finalization and conference call
- 1:1 with Christophe
== Next week ==
- Complete Neon intrinsic testing on Aarch64
- Identify bug fix for Linaro Bugzilla 331
- Investigate failures identified in Neon intrinsic testing
== Progress ==
* TCWG-181 - Bench marking core mark with LTO (2/10)
Measured -O3 -flto vs -O3 on Aarch64 machine with Linaro GCC and
Trunk FSF GCC on Aarch64 and X86_64. Performance in both cases seems
to be same level. Planning to remeasure in trunk now.
* TCWG-531 Fix invalid use of vector register (3/10).
Completed fixing. patch tested on Aarch64 machine and up streamed the
patch to FSF trunk.
* TCWG-532 Fix abinit fails to build on AArch64 (2/10)
Bug does not appear in trunk. Case of missing back port.
Did git bisect experiments in trunk and found that r213078 solves the problem.
Case of code generation for loading labels at -O0 getting fixed after
changes to IRA register class.
* Cbuildv2 preparation for hack session in LCU14.(1/10)
* Others (2/10)
* Meetings Christophe, Ryan, Maxim and GCC status meeting
* Misc and internal meeting.
* Cbuildv2 preparation for hack session in LCU14.
== Plan ==
* Continue testing fix for TCWG-532
* Continue backport fix for TCWG-531.
* Continue Benchmark Core mark with LTO (TCWG-181).
* TCWG-533 Creating scripting to run git bisect with cbuild2.
* Cbuildv2 preparation for hack session in LCU14.
== Progress ==
* Regression on alphaev68-linux-gnu due to uxt/sxt commit (6/10)
- posted patch for promoted type based VRP after fixing issues found in
bootstrapping and regression testing. But had to drop this as this might
have performance implications.
https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00288.html
- Proposed setting a flag to indicating overflow/wrap so that we can
remove uxt/sxt safely.
* Preparation for connect hacking session (2/10)
- Started with materials for the discussions.
* misc (2/10)
- Visa
- Meetings
== Issues ==
- Value range data generated by VRP is not reliable for uxt/sxt removal
as wrapping/overflow is not propagated.
- Patch for Calculating range in promoted type is rejected
- Proposed propagating additional flag (with some tweaking to preserve
size) so that this information is available at the time we deicide on
uxt/sxt redundancy
- If this cannot be agreed, this patch has to be reverted
== Plan ==
* finalize overflow/wrap propagation
* prepare for connect
== Progress ==
* Email, meetings, etc. (1/10)
* Upstream work (1/10, CARD-341)
- Patch review
* LCU14 slides and review (4/10)
* More work on malloc app benchmark framework (4/10, TCWG-441)
- Ironed out a few bugs and sources of noise
- Still need to find a broader range of workloads
== Issues ==
* None
== Plan ==
* Look into malloc single thread optimization patches situation
* Find more workloads to add to malloc benchmarks
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Automation Framework (CARD-1378 2/10)
- Configuring D01s into a three-schroot box
- Turned out unstable, reverting to 4-core setup
* Toolchain (CARD-862 0/10)
- Re-committed vectorizer patch with MSVC2012-friendly code
* LLVM 3.5 Release (TCWG-476 1/10)
- Final release out, all done
* Buildbots (TCWG-76 4/10)
- Adding support for CMake on buildbot Zorg's interface
- Making the CMake builds test without NEON
- Created a compiler-rt bot, found some bugs, investigating
- Submitting changes upstream, will be up soon
* Background (3/10)
- Code review, meetings, discussions, etc.
- Presentations (Connect, LPC)
== Plan ==
* Migrate stack unwinding to VFP for ARMv7+ in compiler-rt
* Start implementing fpu stuff in assembler (parser/attributes)
* Finish LPC presentations
== Progress ==
* GCC trunk/4.9 cross-validation (1/10)
- monitoring results
- noticed failures on newly introduced tests when running on armeb.
Kyrill will fix his tests.
* bug #306 (bootstrap failure on i686) (1/10)
- unable to reproduce it
* AArch64 libsanitizer (3/10)
- asan and most of ubsan tests now pass
- submitted a gcc patch to enable it
- thread sanitizer does not work yet
* Neon intrinsic tests (1/10)
- ran the whole testsuite on aarch64* and arm* targets on gcc trunk
- reported an ICE on aarch64*; was a duplicated, fixed today by Carrot
- there are still several tests failing at runtime, need time to
reduce the testcases
* Misc (conf calls, meetings, ...) (4/10)
- usual 1:1 and team calls
- bugzilla management
== Next ==
* GCC trunk/4.9 cross-validation monitoring
* AArch64 thread sanitizer
* Neon intrinsic tests
* Connect preparation (hacking sessions)
Folks,
Clang+LLVM 3.5.0 was released yesterday (3rd Sep) and Linaro, as
usual, have tested both ARM and AArch64 native builds. This is a major
milestone for LLVM on ARM/AArch64, please read the release notes to
find out more.
http://llvm.org/releases/3.5.0/docs/ReleaseNotes.html
You can download the native ARM binaries (and sources) at:
http://llvm.org/releases/download.html#3.5.0
Since LLVM is natively a cross-compiler, you can download the binary
to your host platform and compile to ARM or AArch64, but you'll need
extra tools (linker, libc, etc).
The main changes are:
* EHABI is now enabled by default and it's compatible with both gcc_eh
and libc++abi unwinding libraries.
* The integrated assembler has got a complete makeover and is now
enabled by default on ARM and AArch64. It supports most of what GCC
produces and a good part of the hand-coded assembly we've seen in the
wild. Please report bugs!
* The current AArch64 back-end is the resulting of a merge between the
existing back-end with Apple's own private back-end (that they open
sourced). It's faster and as stable as the previous and has been
further improved since the merge.
* Compiler-RT has been integrated to the ARM/AArch64 CMake build,
including the sanitizers, though the resulting quality is still beta.
Please report bugs!
This is the first time that Linaro has produced binaries for both ARM
and AArch64 and we'll continue to do so for all major and minor
releases from now on. If there is any patch on trunk for ARM/AArch64
that you need back-ported to 3.5.1 (and beyond), please let us know.
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in LLVM's bugzilla:
http://www.llvm.org/bugs/
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? Inquire at "Linaro support":mailto:
support(a)linaro.org
Regards,
--renato
On 09/02/2014 01:36 PM, Renato Golin wrote:
> Plus, the American culture that I like the most is steak. And bacon. I
> think I'll pass.
I won't be making it either. Around here, American culture is called
the Rodeo. :-)
- rob -
== Progress ==
Arm gdb record-replay pending patches up-streaming [3/10]
* Update, test and resubmit patches
AArch64 gdb record-replay patches up-streaming [3/10]
* Update, test and resubmit patches
Miscellaneous [4/10]
* Configure git for replying to previous patch submission using send email.
* PERF try out on chromebook
* Update record-replay slides and debug using cdt integration.
* Emails/Patch scrolling/Meetings etc
== Plan ==
Up-streaming of all pending patches after updates.
GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480]
LCU14 slides preparation and study for presentation.
== This week ==
* TCWG-515 - Neon intrinsic testing part 1 (1/10)
- Completed testing on ARM targets
- Identified failure on vclz intrinsic at all optimization levels
* TCWG-524 - Neon intrinsic testing part 4 (1/10)
- Completed ARM testing with no regressions found
* TCWG-525 - Neon intrinsic testing part 5 (1/10)
- Completed ARM testing with no regressions found
* TCWG-528 - Neon intrinsic testing part 6 (1/10)
- Completed ARM testing with no regressions found
* TCWG-529 - Neon intrinsic testing part 7 (1/10)
- Completed ARM testing with no regressions found
* Launchpad 1312931- gcc 4.8 internal compiler error: in add_stores, at
var-tracking.c (2/10)
- Resolved and tested on linaro 4.9 branch
* Linaro Connect Presentation (2/10)
- Completed "Optimization Levels" portion of presentatio
* Misc. (2/10)
- Launchpad to bugzilla transition
- Conference calls with Ryan and Christophe
* Issues
- Delay in validating Launcpad 1312931 due to SchrootFarm instability
- Unable to issue code review on Gerrit after server upgrade
== Next week ==
- USA Holiday, Monday, september 1s
- Continue Neon intrinsic testing
- Finalize Linaro Connect presentation
- Bug fixing
== Progress ==
* TCWG-181 - Bench marking core mark with LTO (2/10)
Measuring -O3 -flto vs -O3 on Aarch64 machine with Linaro GCC and
Trunk FSF GCC.
* TCWG-520 ICE in linaro compiler for ARMv7 target (4/10).
Completed fixing. patch tested on schroot. Backported revision from
trunk using gerrit and jenkins. upstreamed the patch.
* Others (2/10)
* Meetings Christophe, Ryan, Maxim and GCC status meeting
* Misc and internal meeting.
* Discussed with Yvan on using gerrit and backflip script.
4 day week, Friday 29/8 was holiday.
== Plan ==
* Another Bug fixing task .
* Continue Benchmark Core mark with LTO (TCWG-181).
* Upstream patch review.
* Cbuildv2 preparation for hack session in LCU14.
== Progress ==
* Regression on alphaev68-linux-gnu due to uxt/sxt commit (7/10)
- built cross alphaev68-linux-gnu and reproduces it with qemu.
- Issue is due to PROMOTE_MODE definition and VRP truncating values.
- discussed upstream and after a failed patch, it was suggested that
the value ranges have to be calculated in promoted_mode precision.
- Patch to do VRP in promoted_mode is in testing. There are few
failures to fix.
- An easier fix probably is to check the promoted mode against
word_mode and disable uxt/sxt elimination.
* TCWG-521 - Analysed Coremark and Spec2k for uxt/sxt optimizations
TCWG-521(2/10)
- Continue with Coremark and have additional patches in development for
missing cases.
* bswap pr43550 (No card yet) (1/10)
- Finished regression testing. Will post the patch after resolving
regression with alpha.
== Paln ==
* Continue with VRP in promoted mode, TCWG-521 and bswap pr43550.
== Issues ==
* Multiple validation infrastructure issues (gerrit/jenkins/git.linaro.org)
now fixed.
* aarch64-none-elf is now really long to complete (~11hrs) whereas it
was less than 1hr last week.
== Progress ==
* GCC 4.9 2014.09 (3/10)
- Committed last week backports
- More backports under validation
- vca* intrinsics test are faiures analysis ongoing.
* Misc
- Linaro GCC git repo migration: (2/10)
+ Discussed and test the migration with Milo,
we'll be ready to move the coming week.
- Upstream bugzilla: (2/10)
+ Fixed PR 62248 : Configure error with --with-fpu=fp-armv8
- Linaro bugzilla: (1/10)
+ Fixed #562 : New tests failed on linaro 4_9 branch
- Various meetings: (1/10)
- Helped Venkat with backports (1/10)
- launchpad bug migration duty.
== Next ==
* Off on Monday
* Complete backports.
* Back on AArch64 libunwind
* Prepare Connect Hacking session
== Progress ==
* Monday bank holiday (2/10)
* Email, meetings, etc. (1/10)
* Upstream work (1/10, CARD-341)
- Patch review
* Built releases of newlib, binutils and gdb for 2014.09 (2/10)
* LCU14 research and slides (4/10)
== Issues ==
* None
== Plan ==
* Finish LCU slides
* malloc benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* GCC trunk/4.9 cross-validation (1/10)
- checking results
* bug #306 (bootstrap failure on i686) (3/10)
- fixed an incorrect backport than made GCC build to fail in stage1
- now trying to reproduce the original bug reported
* AArch64 libsanitizer (2/10)
- resumed work, debugged sysroot / chroot problems with cbuild2
thanks to Maxim
* Misc (conf calls, meetings, ...) (4/10)
- usual 1:1 and team calls
- wrote some doc for Wang
== Next ==
* GCC trunk/4.9 cross-validation monitoring
* bug #306 (bootstrap failure on i686)
* AArch64 libsanitizer
* Neon intrinsic tests
== Progress ==
GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480] [4/10]
* FAST tracepoints try out on arm chromebook with trampoline code
borrowed from kernel.
AArch64 gdb record-replay bug fix [TCWG-503][TCWG-498] [2/10]
* Debugging of issues
Miscellaneous [4/10]
* Reading on PreLink for LCU14 Presentation
* Reading on PERF tools for LCU14 Presentation
* LCU14 slides preparation.
* Emails/Patch scrolling/Meetings etc
== Plan ==
GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480]
Some progress on AArch64 gdb record-replay bug fix [TCWG-503] [TCWG-498]
LCU14 slides preparation and study for presentation.
= Progress ==
* Upstream work (2/10, CARD-341)
- Bug investigations
- Applied a couple of patches
* Booting upstream kernel on Chromebook (2/10)
- Kernel booting and running
- No builtin wifi but dongle works ok
- Breakpoint issue fixed but the test still fails for some other
reason, created upstream issue
* Malloc application benchmarking (3/10, TCWG-441)
- Various improvements of the scripts
- Investigate benchmark variability in the presence of frequency scaling
- Is it possible to get repeatable numbers on Intel i{7,5,3}?
* Start looking at LCU session requirements (1/10)
* Annual leave on Friday (2/10)
== Issues ==
* None
== Plan ==
* LCU session slides
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* TCWG-180 Debugging - LTO bootstrap failure in Aarch64 with GCC 4.9. (4/10)
Completed. Patch that sets same tune parameters solves the bootstrap
compare errors in Branch. Closed the JIRA cards. There are still LTO
IR streaming issues in trunk which needs to tracked down and fixed at
tree level. and no plans of doing that now.
* TCWG-520 ICE in linaro compiler for ARMv7 target. Bisected the
revision in trunk which fixes that. Backported and tested and fixes
tha bug. (4/10)
* Others (2/10)
* Bug migration from launchpad
* Meetings Christophe, Ryan, Maxim and GCC status meeting
* Misc and internal meeting.
* setup LLVM.
== Plan ==
* Continue Bug fix (TCWG 520).
* Benchmark Core mark with LTO (TCWG-181).
* Upstream patch review.
== MISC ==
* Local Holiday on 29th August
== Progress ==
* TCWG-413 - Release benchmarking (2/10)
- Analysed all the patches gone into the release for performance impact
* TCWG-521 - Analysed Coremark and Spec2k for uxt/sxt optimizations
TCWG-521(3/10)
- Studied Coremark and have additional patches in development for
missing cases.
* bswap pr43550 (No card yet) (3/10)
- Looked at the pr and it is not fixable with VRP
- An alternate approach based patch is in testing to fix this.
* 1 day off Sick (2/10)
== Paln ==
* Continue with TCWG-521 and bswap pr43550
