== Issues ==
* None
== Progress ==
* Create prebuilt sysroot based on Linaro eglibc 2014.04 release
(https://launchpad.net/linaro-toolchain-binaries/support/01/+download/linaro…)
(1/10).
* Enable shrink-wrap for apcs. Patch was out for community review. (1/10)
* Reinvestigate shrink-wrap enhancement (4/10, TCWG-133)
- There was improvement in ira to split_live_ranges_for_shrink_wrap
(http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10474). But it still can
not handle the case in 453.povray.
- Investigate to do a simple copy-forward when prepare_shrink_wrap.
* Investigate lp:1296942 (pr60663). Patch is sent out for community
review. (4/10)
* Backporting the fix for pr60264 to Linaro 4..8.
== Plans ==
* Continue on shrink-wrap enhancement.
== Planned leaves ==
* April 7: Qingming holiday.
== Progress ==
- TCWG-413 Spec2006 (7/10)
- Investigated compiler error for 481.wrf with FSF 4.8.2. Issue is
due to aarch64_cm<cmp><mode> pattern (fcmle and fcmlt supports only #0
as third val). This is already fixed in trunk and Linaro 4.8.
- Ran profiling to analyse 4.9 regressions. Started looking into
P7Vitterbui which is one of the functions that performs badly.
- TCWG-291 CRC (3/10)
Came up with a patch for improving vrp for test-case. Some c++ test
cases are failing in regression testing with this patch. Looking into it.
- TCWG-394 / PR60034
Patch committed and card closed.
http://gcc.gnu.org/viewcvs?rev=208949&root=gcc&view=rev
== Plan ==
Continue with Spec2006 and crc
== Progress ==
* Android (no card, 10 minutes. ;)
- Implemented __builtin___clear_cache in Clang
* Kernel (TCWG-417) 6/10
- VLAIS in crypto (last place in kernel)
- __builtin__stack_pointer (new builtin)
- Discussion in GCC list, named registers might be a better option
- Discussion in LLVM list about implementing named registers
- Implementing named register variables...
- Planning on LAVA testing LLVM kernels with LLVMLinux
- __aeabi_memset/cpy/move (both Android and Kernel) will have to be fixed
* Libraries (TCWG-125) 2/10
- libc++abi's unwind routines assume (ARM == SjLj)
- libc++ doesn't work without them
- We'll need to teach it about EHABI (later)
* Background 2/10
- Installed ArchLinux on my laptop, took some time to setup
- Re-org of LLVM Jira Cards (TCWG-417)
- Reviewing some GSoC proposals
== Plan ==
* implement named register variables in LLVM, then Clang
* Continue helping LLVMLinux and Milosz to test the LLVM kernel
* Time allowing, check CBuild2 for an LLVM build
* Two long weeks of holidays...
== Progress ==
* Bugfix aarch64 setcontext patch (2/10, TCWG-410)
* malloc requirements wiki page (2/10, TCWG-414)
* Lots of creating and updating and updating JIRA cards (1/10)
* glibc patch review (1/10)
* Assorted small patches - ld relasz, gnulib obstack, glibc strtod
benchmark (2/10)
* Investigate a couple of issues raised by member services and on lists (2/10)
== Issues ==
* None
== Plan ==
* Resurrect glibc malloc benchtest
* More glibc benchmark infrastructure work
* Check status of glibc ARM port build warnings
--
Will Newton
Toolchain Working Group, Linaro
== Week of March 17th ==
- STREAM regression (TCWG-388, 4/10)
-- Investigated how to prioritize memory references instructions in GCC scheduler to take full advantage of L2 autopretch hardware in certain ARM cores.
-- Fixed -fdbg-cnt=sched_insn debug counter along the way. It appear to have been broken since GCC 4.7.
- Discussed reg_pressure instruction scheduling with Charlie. (TCWG-135, 1/10)
- Various discussions about instruction scheduling in GCC. (1/10)
- Together with Michael prepared patch list for GCC contingency plan. (3/10)
- Made first-in-series video about tips-and-trick of GCC development. Your critiques are welcome!
-- Using GCC debug counters (7m34s): https://www.youtube.com/watch?v=IWRYCOkgL04
== Week of March 24th ==
- STREAM regression (TCWG-388)
-- Get a prototype patch.
- Other expected and unexpected tasks that come up.
--
Maxim Kuvyrkov
www.linaro.org
Last week
* one day off [2/10]
* NEON scheduling investigation - TCWG-135 [3/10]
. investigated scheduler register pressure heuristics
. call with Maxim about scheduling algorithm
. still more investigation required
* NEON intrinsics vs assembler libvpx performance difference
investigation [5/10]
. GCC seems to generate poor code for address generation in NEON loads/stores
. maybe some improvements to the intrinsics code would also be possible
Plan:
. write down some conclusions about libvpx performance
. investigate PR60609
. more on TCWG-135
. investigate LP1296676 & LP1296601 ICEs when building the kernel
== Progress ==
Machine descriptions for stack smashing in Aarch64 - TCWG-23 (5/10)
* Completed building QEMU for Aarch64 on Ubuntu 13.10. Ran
regression tests on it.
* Submitted patches for libssp as per Marcus suggestions and got it approved.
PGO support for Aarch64 -TCWG- 179 (2/10)
* Installed "CPU2006" tools in foundation model running open embedded image
and started running benchmarks. Plan is to build it with -PGO next.
Bug fix (2/10)
* Working on reproducing and fixing PR60617.
Misc (1/10)
* AMD Internal meeting and work.
== Plan ==
* Bug fix PR60617.
* Build CPU006 benchmarks with -PGO flag
* Restart PGO bootstrap failure investigations
Hi,
I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out.
The following are obsoleted in ARMv8:
A32 SWP and SWPB instructions.
Jazelle (only trivial implementations are supported).
VFP short vectors and asynchronous bounces.
Fast Context Switch Extension (FCSE).
Thanks: Magnus
Magnus Karlsson
Software Development Engineering Manager
LSI Corporation
Box 1024, Knarrarnäsgatan 15
SE-164 21 Kista, Sweden
TEL +46 8 594 607 09
FAX +46 8 594 607 10
CELL +46 73 80 444 88
magnus.karlsson(a)lsi.com
== Issues ==
* none
== Progress ==
* LRA on AArch32:
o TCWG-343 : Make LRA the default for the ARM backend (0/10)
- Stop progress on this card, will close it when FSF 4.9 will be released.
o TCWG-345 : Analyse performance of LRA for ARM. (4/10)
- Spec2K figures on Cortex-a15 Analysis.
- re-run benchs in console mode chrubuntu without ASLR + perf tool
* Backports review: (2/10)
o Start to prepare cortex-a53 backports review
* Misc:
o Various meetings and slideware (4/10).
- Linaro and internal ones.
== Next ==
- continue cortex-a53 review
- some backports to do.
- continue on TCWG-345
== Progress ==
* Worked on getting eglibc git mirror back up and running
* Released eglibc 2.19 2014.04
* Respin of glibc aarch64 setcontext patches
* Respin of ld aarch64 RELASZ patch
* Tidied up, rebased and committed ARM ld pointer equality patch
* Work on resurrecting glibc benchmark result graphing script
* Holiday on Friday
== Issues ==
* Couple of hours power outage on Monday
== Plan ==
* Get outstanding glibc and binutils patches committed
* Reorganise JIRA cards for malloc work
* glibc benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Add support for fork/vfork/exec events/catchpoints in remote
gdbserver [TCWG-263] [4/10]
-- Debugged catchpoint code and reviewed gdbserver implementation for events.
-- Still require a lot of code understanding before actual
implementation can start.
* Wrote a script that takes two gdb build trees and configuration
arguments to test them in native, remote-native and remote-target
configurations [TCWG-96] [3/10]
* Laptop OS re-install [1/10]
* GDB open cards issues review [1/10]
* Sick half day off on Friday [1/10]
== Plan ==
* Complete work on TCWG-96.
-- Write a script that tests gdb in remote-native configuration using ssh.
-- Integrate all testing scripts and test them.
-- Update wiki page with updated scripts and how to use them.
* Monday Day Off: Pakistan Day 23rd March public holiday roll over.
== Progress ==
CARD-1210 - optimizing prologue/epilogue With -fomit-frame-pointer (4/10)
- regression tested the patch and fixed issues
- Dropping the patch and closing the card as it has been worked on at arm.
TCWG-15 - zero/sign extension elimination for crc (3/10)
- Looked at crc and looked at the other optimizations listed in card 440.
- Improved the local patch to remove the missing optimization
TCWG-413 - Running spec2006 with aarch64 (3/10)
- Built and set-up spec2006.
- Ran into to some compile time and run time errors
== Plan ==
Continue with zero/sign extension elimination
Start looking at literal pool merging
== This week ==
Merged all backports related to a53 support and successfully built arm
and aarch64 cross compilers:
202333 - [AArch64, ARM] Introduce "mrs" type attribute.
202334 - [AArch64] Use neon_<ldm,stm>_2 where appropriate as "type".
202448 - [AArch64] Prevent generic pipeline description from dominating
other pipeline descriptions.
202560 - set "type" attribute properly in arm_cmpsi_insn, cleanup
203241 - Cortex-a53 use Cortex tuning
203611 – 203621 – Neon types Parts 1 to 10
204575 - [ARM, AArch64] Make aarch-common.c files more robust.
205050 - [ARM] Add missing type attribute to zero_extend on arm
204782 - [AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default.
204784 - [AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2"
tuning options.
204852 - [AArch64] Remove simd_type
205014 - [AArch64] Remove v8type attribute.
205105 - [AArch64] Remove "mode", "mode2" attributes
204783 - [AArch64] [-mtune cleanup 3/5] [Temporary] When asked to tune
for Cortex-A57, tune for Cortex-A15
== Next week ==
Test a53 support
Backport vectorization bug
== Future ==
== Issues ==
* None
== Progress ==
* Identify a missing instruction pattern which blocks fcsel
optimization. A patch was sent out for community review. [2/10,
TCWG-309]
* Identify a ICE when handling dwarf-info in ARM backend when testing
shrink-wrap. A fix was committed to trunk. [2/10]
* Rebase and test the shrink-wrap codes for APCS_FRAME. [5/10]
* Prepare Linaro toolchain 2014.03 binaries release [1/10].
* Investigate CRC improvement chances.
== Plans ==
* Create a prebuilt sysroot based on Linaro eglibc-2014.04.
* Continue on shrink-wrap.
== Progress ==
* AArch64 (TCWG-387)
- Implemented simple C sin/cos functions for sphereflake
- AArch64 builds, passes check-all and test-suite
- Closed Jira task
* IAS (TCWG-377)
- Updated release notes
- IAS build, passes check-all, test-suite and compiles other large codebases
- Closed Jira task
* EHABI (TCWG-124)
- Updated release notes
- EHABI builds, passes check-all, test-suite
- Waiting for last patch to go to close the Jira task
* Compiler-RT (TCWG-125)
- Re-testing with current trunk+RT, all pass
- Next step, libunwind (not ready yet)
* Background
- Patch review, etc
- Studying TableGen, writing some docs (http://llvm.org/docs/TableGen/)
- Proposing changes to debug/EH unwind function attributes in IR
- Changing Zorg to not submit LNT reports by default (avoids bot breakage)
- Planning LLVM+Linux involvement as next big task
* Time
- CARD-862 8/10
- Others 2/10
== Plan ==
* Continue pushing __builtin___clear_cache and -fno-unwind-tables upstream
* Implement the Clang part of __builtin___clear_cache and update the docs
* Try to add LLVM/Clang to cbuildv2
* Start merging libunwind from libc++ to Compiler-RT and test it on ARM
* Get the kernel task started with the LLVMLinux guys
Hello,
the attached program changes the output from "true" to "false" when the
-Bsymbolic / -Bsymbolic-functions options are passed to GCC. This
happens on ARM -- on x86-64 output is always "true".
The program involves a comparison, within a shared library, of a PMF
defined inside the shared library itself with the same PMF passed by the
application.
At this stage I still don't know if it's a GCC problem, a ld.so problem,
ABI constraints, undefined behaviour, or whatnot; but any help is
appreciated.
Compile with:
> g++ -fPIC -shared -Wall -o libshared.so -Wl,-Bsymbolic shared.cpp
> g++ -fPIE -Wall -o main main.cpp -L. -lshared
(The long story is that Qt 5 is taking PMFs in its public API, and the
comparison failing inside of Qt shared libraries is breaking code on
ARM, as -Bsymbolic is set by default there.)
Thanks,
--
Giuseppe D'Angelo | giuseppe.dangelo(a)kdab.com | Software Engineer
KDAB (UK) Ltd., a KDAB Group company
Tel. UK +44-1738-450410, Sweden (HQ) +46-563-540090
KDAB - Qt Experts - Platform-independent software solutions
== Progress ==
* Off Monday after travelling back from Connect
* Catching up on email and post-Connect admin
* Released Linaro binutils 2.24.0 2014.03
* Submitted aarch64 setcontext patches upstream
* Submitted a patch for ld RELASZ issue
* Looked into eglibc svn mirroring
== Issues ==
* None
== Plan ==
* Resolve eglibc mirror situation
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Get started with Aarch64 GDB testing and development process using
foundation model. [6/10] [CARD-1115]
-- Figured out steps for running gdb in remote mode using foundation model.
-- Wrote a wiki page with steps on development process, still in progress.
-- Completed a gdb testsuite run and made a comparison with arm gdb.
-- All new testsuite results will be available on gdb wiki page.
-- Setup aarch64 gdb remote debugging.
* Updates to GDB pages on wiki.linaro.org [TCWG-96] [2/10]
-- Added pages containing test scripts and gdb testing tips
-- Added page containing current gdb testsuite results in various
configurations
* Add support for fork/vfork/exec events/catchpoints in remote
gdbserver [TCWG-263] [1/10]
-- GDB code review for task break down, still in progress.
* Fix network and internet problems [1/10]
== Plan ==
* Arm v8 reverse debugging support.[CARD-1115]
-- Provide card update and deliverable list.
-- Implement reverse debugging infrastructure for aarch64 gdb.
* Add support for fork/vfork/exec events/catchpoints in remote
gdbserver [TCWG-263]
-- GDB code review for task break down, still in progress.
* Update and cleanup gdb wiki pages on wiki.linaro.org
* All open gdb card review and update.
== Progress ==
* Went through few Linaro Connect - LCA14 slides and videos .
* Restarted upstream discussions on writing machine descriptions for
stack smashing. Working on submitting patches again as per Marcus
suggestions.
* Installed "CPU2006" in foundation model running open embedded image
and tried running 403.gcc benchmark.
* Tried buiding QEMU for aarch64 on ubuntu 12.04,2. I am getting
segment fault on using -L <library path >. Need to debug further.
* PGO runs: GCC boot strap failed when libjava building at stage3.
Need to have re-look further. Issue may be missing package in
opembedded image on foundation model.
Misc
------
Attended some Internal meetings.
== Plan ==
* Continue machine descriptions for stack smashing work.
* Work on using QEMU for running gcc test suites
* Restart PGO bootstrap failure investigations
== Issues ==
* None
== Progress ==
* Validate R/M toolchain 4.8 q1 update release.
* Try Cross-Native build based on Linaro crosstool-ng.
* Handle conditional compare in ifcvt.c to make ccmp and csel work together.
* Read document about FCMP/FCCMP and investigate on how to generate
FCCMP instructions:
- The tree representation of UNORDERED compare (UNLT, etc) can not
fit into current framework to handle CCMP.
- For LT, LE, GT and GE, the compiler will generate FCMPE
instruction, which can not be the first compare of CCMP.
- For NE, EQ, it is easy to handle them based on previous patches.
== Plan ==
* Continue on ccmp performance tuning.
== This week ==
Completed the following backports related to a53 support:
201375 - Insn classification refactoring 7/n Factor out "type" attribute
201376 - Insn classification refactoring 7/n Factor out common
scheduling dependency routines (done)
201399 - Insn classification unification 1/n Define "type" attrib for
all patterns (done)
201400 - Share the a53 pipeline description between arm and aarch64 backends
201436 - Insn classification unification 4/N load/store types
202272 - [AArch64, AArch32][Insn classification refactoring 6/N] Remove
"neon_type" attribute
202291 - [AARCH64][Insn classification unification 3/N] ALU/shift types
202292 - [AArch64] Fix categorisation of the frecp* insns.
202323 - [Patch ARM] Add "type" attribute to Everything!
202328 - [ARM,AARCH64] Insn type reclassification. Split f_cvt type.
202329 - [Patch ARM AARCH64] Split "type" attributes: fdiv
202330 - [Patch AArch64] Fix types for some multiply instructions.
202331 - [AArch64, ARM] Rename the FCPYS type to FMOV
202332 - [AArch64, ARM] Use "multiple" for type, where more than one
instruction is used for a move
== Next week ==
Complete remaining backports for a53 support and complete builds for arm and aarch64.
== Future ==
--
Michael Collison
Linaro Toolchain Working Group
michael.collison(a)linaro.org
The Linaro Toolchain Working Group is pleased to announce the 2014.03
engineering release of Linaro GCC 4.8.
As announced at Linaro Connect USA 2013 Linaro GCC is moving to a
pattern of quarterly stable releases, with engineering releases in the
intervening months. This is the second engineering release. The next stable
release will be the 2014.04 release.
Linaro GCC 4.8 2014.03 is the twelfth release in the 4.8 series. Based
off the latest GCC 4.8.3+svn208264 release, it includes performance
improvements and bug fixes.
Interesting changes include:
* Updates to GCC 4.8.3+svn208264
The source tarball is available from:
http://releases.linaro.org/14.03/components/toolchain/gcc-linaro/4.8
Downloads are available from the Linaro Releases website:
http://www.linaro.org/downloads/
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.8/4.8-2014.03
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
~