- linaro-toolchain - lists.linaro.org

regression of x86 gcc bootstrap with Linaro sourcebase

by Robert Schiele

Hi Ulrich, Before I build the cross compiler for ARM target I do a bootstrap process of an i686 compiler on the same code base to use that one building the cross compiler to reduce the chance of seeing subtle problems late in the game. This process unveiled a x86 bootstrap regression with some of your changes on the Linaro 4.7 branch. It all boils down to the following set of changes you did: commit c904094f2421bbd5d2cab6d7fbccecf055509629 Author: Ulrich Weigand <uweigand(a)de.ibm.com> Date: Mon Jul 16 16:31:58 2012 +0200 Update to exactly reflect upstream version. commit bf378903a1b749b904ae64635182e7fc9b43e0e4 Author: Ulrich Weigand <uweigand(a)de.ibm.com> Date: Tue Jul 10 15:46:51 2012 +0200 Fix backport. commit e0c3b0a21916ffafc058cd88d82423d87ce77b50 Author: Ulrich Weigand <uweigand(a)de.ibm.com> Date: Mon Jul 9 22:52:10 2012 +0200 Fix LP 1020601. This is the introduction of optimize_unreachable in gcc/tree-ssa-ccp.c. When configuring with ../gcc/configure --host=i686-build_pc-linux-gnu --build=i686-build_pc-linux-gnu --target=i686-build_pc-linux-gnu --prefix=/ --libexecdir=//lib --program-prefix=i686-build_pc-linux-gnu- --with-sysroot=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot --with-local-prefix=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot --with-gmp=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr --with-mpfr=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr --with-mpc=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr --with-cloog=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr --with-ppl=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr '--with-host-libstdcxx=/user/rschiele/l/builddir/i686-build_pc-linux-gnu/tools/lib/libstdc++.a -lm' --disable-multilib --disable-checking --enable-__cxa_atexit --enable-libmudflap --enable-libgomp --enable-libssp --enable-languages=c,c++ --enable-threads=posix --disable-libstdcxx-pch --enable-c99 --enable-long-long --disable-shared It fails in the bootstrap at /user/rschiele/l/src/gccbuild/./prev-gcc/g++ -B/user/rschiele/l/src/gccbuild/./prev-gcc/ -B//i686-build_pc-linux-gnu/bin/ -nostdinc++ -B/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/src/.libs -B/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/libsupc++/.libs -I/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/include/i686-build_pc-linux-gnu -I/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/include -I/user/rschiele/l/src/gcc/libstdc++-v3/libsupc++ -L/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/src/.libs -L/user/rschiele/l/src/gccbuild/prev-i686-build_pc-linux-gnu/libstdc++-v3/libsupc++/.libs -c -g -O2 -gtoggle -DIN_GCC -fno-exceptions -fno-rtti -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -DHAVE_CONFIG_H -I. -I. -I../../gcc/gcc -I../../gcc/gcc/. -I../../gcc/gcc/../include -I../../gcc/gcc/../libcpp/include -I/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr/include -I/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr/include -I/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr/include -I../../gcc/gcc/../libdecnumber -I../../gcc/gcc/../libdecnumber/bid -I../libdecnumber -I/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr/include -I/user/rschiele/l/builddir/i686-build_pc-linux-gnu/sysroot/usr/include ../../gcc/gcc/sel-sched.c -o sel-sched.o ../../gcc/gcc/sel-sched.c: In function 'void sel_sched_region_2(int)': ../../gcc/gcc/sel-sched.c:7472:1: error: mismatching comparison operand types struct rtx_def * bool if (insn_1716 == 0) ../../gcc/gcc/sel-sched.c:7472:1: internal compiler error: verify_gimple failed Please submit a full bug report, with preprocessed source if appropriate. See <http://gcc.gnu.org/bugs.html> for instructions. Note, that the --disable-checking is essential to reproduce. As soon as you do --enable-checking the bootstrap completes successfully. I would assume that you then still have the bug in the compiler but it is just subtle enough not to be triggered then. Reverting your mentioned changes fixes this problem. If you need further information about my environment to reproduce the problem feel free to contact me. Greetings, Robert

12 years, 8 months

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[MINUTES] Toolchain Performace Call 2012-12-11

by Yvan Roux

The minutes of the performance call held on 11 December 2012 can be found at: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-12-11 In summary the actions from the meeting are: * ACTION: Matt update meeting template attendees - to include Yvan * ACTION: mgrettondann split LRA blueprint * ACTION: Christophe to update Hot/Cold partitioning bugzilla * ACTION: mgrettondann: benchmark on Hold/Cold partitioning * ACTION: Christophe to look at the loop peeling cost Thanks, Yvan

12 years, 8 months

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[PATCH 3/5] cortex strings preparation for aarch64

by Marcus Shawcroft

This patch provides support to detect the host architecture in configure.in use the detected architecture to conditionalize parts of the Makefile.am. The intention is that we retain a single top level Makefile which contains rules relevant to all supported architectures, each gated by the AM_CONDITIONAL infrastructure. /Marcus

12 years, 8 months

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[PATCH 0/5] cortex strings preparation for aarch64

by Marcus Shawcroft

Folks, In preparation for adding aarch64 string functions into cortex-strings, I'd like feed back on the following series of patches. 1/5 Trivial whitespace cleanups. 2/5 Autotools foo for cross building support. 3/5 Autotools foo for architecture detection. 4/5 Missing LDADD and CFLAGS setting. 5/5 Use --std=gnu99 I'm particularly interested in views on 3/5. This patch sets direction for autoconf detection of the host architecture. The intention is that we retain the single toplevel Makefile.am which gains AM_CONDITIONAL support for the detected host triple. The aarch64 specific code will follow in a different patch set. Cheers /Marcus

12 years, 8 months

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4.6 merge: ARMv5 sync_synchronize failures

by Yvan Roux

Hi, the issue seems indeed to be introduced by r193959 and fixed in r194161, as it is reported in: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55571 Unfortunately, my merge attempt was at r190461 :( I redo the merge... Yvan

12 years, 8 months

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[ACTIVITY] 3-7 December 2012

by Yvan Roux

== Progress == * 4.6 and 4.7 merges - Many merge attempts - 4.7 merged - 4.6 under approval * Boehm GC AArch64 support: - Resume the libatomic work - started the garbage collector configuration * Internal support. == Next == * Do GCC-linaro releases * Boehm GC

12 years, 8 months

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[ACTIVITY] week 49

by Mans Rullgard

* https://blueprints.launchpad.net/linaro-toolchain-misc/+spec/webp-upsamplin… - working 'fancy' upsampling, actual yuv-rgb conversion still major time hog - next: do yuv-rgb conversion in neon * reported valgrind bug https://bugs.kde.org/show_bug.cgi?id=311318 * implemented runtime cpu feature (neon, vfp, etc) detection in Libav * ongoing: tracking gcc trunk on Libav test systems, no ARM regressions this week * user support on irc -- Mans Rullgard / mru

12 years, 8 months

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[Activity] Week 49

by Zhenqiang Chen

Summary: * Validate RM toolchain, Linaro QENU 2012.12 and Linaro aarch64 2012.11. * Collect performance data for different branch cost. Details: * Validate RM toolchain release. * Set up test environment with the help of Michael and validate Linaro QEMU 2012.12 release. * Validate aarch64 toolchain 2012.11. From 2012.12, it will be released regularly like arm-linux-gnueabihf toolchain. * Collect denbench and spec2000int performance data for branch cost tuning. * Investigate how to do copy propagation for shrink-wrap to optimize 453.povray benchmark. Will reuse current codes in pass_cprop_hardreg. Plans: * Performance reports for branch cost tuning. * Fix README issue (lp:1068402) in Linaro crosstool-ng. Best regards! -Zhenqiang

12 years, 8 months

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What tools can be used to protect the KVM and qemu quality？

by chenq

Hi all， I am a rookie, and now I'm focusing on ARM virtualization. As we know,KVM (for Kernel-based Virtual Machine) is a full virtualization solution. KVM-Autotest is a set of virtualization tests for X86 platform, but it may not be suitable for ARM.I want to know, in the linaro , what tools can protect the KVM and qemu quality ? Thanks and Regards,Qun Chen

12 years, 8 months

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[ACTIVITY] report week 49

by Peter Maydell

* usual set of meetings etc * rebased qemu-linaro on upstream 1.3, rolled tarball for 2012.12; Zhenqiang has tested it and it should be ready to go next week * qemu arm patch catchup; pinging or resending some patches of mine from before upstream freeze * applied a set of boot-wrapper patches from tixy * virtio patch code review: design definitely coming together now KVM blueprint progress tracker (note new url): http://cbuild.validation.linaro.org/helpers/backlog?group_by=topic&colour_b… -- PMM

12 years, 8 months

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[ACTIVITY] 3-7 December 2012

by Christophe Lyon

== Progress == * Turn off 64-bits bitos in Neon: Ping-ed patch proposal. * Disable peeling: benchmarks show good results; sent a proposal upstream to discuss preliminary implementation & needed testsuite modifications. * builtin_bswap16 backport to linaro-4.7: need to investigation an unexpected regression reported for i686 target. * Updated gdb linaro sources to 7.5.1, exercising the release process. * Trying to bootstrap gcc-linaro/4.7 on board: need to retry with a different rootfs distribution. == Next == * handle 64-bits bitops in Neon and disable-peeling feedback from upstream if any. * finish builtin_bswap16 backport

12 years, 8 months

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[ACTIVITY] 3-7 December 2012

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 14 Dec 2012 aarch64-baremetal-testing 31 Oct 2012 14 Dec 2012 fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Took over from Michael * Preparation for taking over from Michael * re-PINGed triplet backport patches upstream * Patch review * Initial thoughts about cards == Next Week == * initial-aarch64-backport and aarch64-baremetal-testing * Complete documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

12 years, 8 months

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selected processor does not support Thumb mode `smc 0'

by Shivamurthy Shastri

Hi, I am trying to compile UEFI code with linaro toolchain version: # arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.1-5ubuntu1~ppa1) 4.7.1 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. I got the erros as follows: "/usr/bin/arm-linux-gnueabi-gcc" -mthumb -march=armv7-a -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform -g -Os -fshort-wchar -fno-strict-aliasing -Wall -Werror -Wno-missing-braces -Wno-array-bounds -c -include AutoGen.h -mword-relocations -mlittle-endian -mabi=aapcs -mapcs -fno-short-enums -save-temps -fsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -O0 -o /home/shiva/workspace/arndale/edk2/Build/Arndale-Exynos/DEBUG_ARMLINUXGCC/ARM/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec/OUTPUT/./Smc.obj -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec -I/home/shiva/workspace/arndale/edk2/Build/Arndale-Exynos/DEBUG_ARMLINUXGCC/ARM/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec/DEBUG -I/home/shiva/workspace/arndale/edk2/MdePkg -I/home/shiva/workspace/arndale/edk2/MdePkg/Include -I/home/shiva/workspace/arndale/edk2/MdePkg/Include/Arm -I/home/shiva/workspace/arndale/edk2/MdeModulePkg -I/home/shiva/workspace/arndale/edk2/MdeModulePkg/Include -I/home/shiva/workspace/arndale/edk2/ArmPkg -I/home/shiva/workspace/arndale/edk2/ArmPkg/Include -I/home/shiva/workspace/arndale/edk2/ArmPlatformPkg -I/home/shiva/workspace/arndale/edk2/ArmPlatformPkg/Include -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250 -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include /home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Smc.c Smc.s: Assembler messages: Smc.s:51: Error: selected processor does not support Thumb mode `smc 0' Is there any issue with the toolchain or any flags I am using? -- Thanks and Regards, Shiva.

12 years, 8 months

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Scheduler tweaks

by Michael Hope

I've done a couple of tweaks to the scheduler. You now see pending jobs by the class of machine they'll run on. Clicking a job takes you to the detail, which includes a link to drop/cancel the job. -- Michael

12 years, 8 months

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Toolchain Working Group Meeting Times

by Matthew Gretton-Dann

All, As I mentioned on Monday, due to new members of the team coming on board I am going to rejig the meeting times from 18th December. My proposal is as follows (all times UK Local - UTC+0h winter, UTC+1h summer): 0. These changes will come into effect the week commencing 18th December. 1. The weekly call will happen on a Monday, at 0930 and 1600. You only need to make it to one instance of the call. For those who are physically near each other arranging it so that both calls get attended would be good and notes shared would be good. 2. The Stand-up call will happen on a Thursday, alternating between 0930 and 1600. This is 'best effort' - but please try to attend at least every other week. 3. The performance call will go weekly, and will happen on a Thursday, alternating between 0930 and 1600. If you are on the invite list to this call again please try to attend at least every other week, but if you can manage every week that would be great. If you have any comments on these please can you raise them by the end of the week as I would like to confirm what we are going to do at the call on Monday (at the normal time of 0915UTC). Thanks, Matt -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

12 years, 8 months

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[MINUTES] Toolchain Performace Call 2012-12-03

by Michael Hope

The minutes of the performance call held on 3 December 2012 can be found at: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-12-03 In summary the actions from the meeting are: * ACTION: Yvan will do the trunk merge this week * ACTION: Yvan to do the GCC release next week * ACTION: Christophe to do the GDB release branch merge * ACTION: Matt volunteered Zhenqiang as the QEMU manual tester this month * ACTION: Matt: want shrinkwrap to go upstream * ACTION: Matt - Can blueprint improvements in shrink wrap past that * ACTION: Matt to create a blueprint on aarch32 ARMv8 instructions in QEMU * ACTION: Matt to decide if aarch32 ARMv8 instructions in QEMU needs a card * ACTION: Christophe to send Michael cross build failures to investigate Thanks, -- Michael

12 years, 8 months

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[ACTIVITY] 26-30 November

by Christophe Lyon

== Progress == * Turn off 64-bits bitops in Neon: patch proposed upstream after positive benchmarking. Re-submitted after request to add testcases and documentation for the new option. * Disable peeling: running benchmarks with peeling completely disabled to see the impact. * PGO/hot-cold partitioning: tested new patch from google, which solves some of the ICEs, but makes new ones appear. * builtin_bswap16 backport to Linaro-4.7: checking if there would be a possibility to keep the testcase which fails in one of our configurations, after rebasing my branch. * Trying to bootstrap gcc-linaro/4.7 on board * Internal support == Next == * Follow-up on 64-bits bitops in Neon * Look at benchmarks results with peeling disabled * finish builtin_bswap16 backport

12 years, 8 months

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random corruption while doing popen pclose

by Ajeet Yadav

Linux version 3.0.33 (Cortex A15) Below program crashes with 2.14.1 glibc but runs fine with 2.11.1 glibc. #include <pthread.h> #include <stdio.h> #include <stdlib.h> #include <signal.h> #include <string.h> #include <errno.h> #define MAX_LINE_SIZE 80 #define MAX_THREAD 20 #define MAX_POPEN 10 #define MALLOC_SIZE 16 void* pipe_thread(void *arg) { int i; char *p = NULL; FILE *fp[MAX_POPEN]; char shellCommand[MAX_LINE_SIZE]; memset(shellCommand, 0x00, MAX_LINE_SIZE); sprintf(shellCommand, "mount"); signal(SIGPIPE, SIG_IGN); while (1) { for (i = 0; i < MAX_POPEN; ++i) { fp[i] = popen(shellCommand, "r"); } if (p) { free(p); } for (i = 0; i < MAX_POPEN; ++i) { if (fp[i]) pclose(fp[i]); } p = malloc(MALLOC_SIZE); if (p) memset(p, 0, MALLOC_SIZE); } return NULL; } int main(int argc, char *argv[]) { int i; pthread_t tid; for (i = 0; i < MAX_THREAD; ++i) { pthread_create(&tid, NULL, &pipe_thread, (void*)NULL); } sleep(60); } gdb logs: (gdb) bt #0 0x4014f998 in _IO_new_fclose (fp=0x1) at iofclose.c:74 #1 0x4015b59c in fwide (fp=0xb8, mode=<optimized out>) at fwide.c:47 #2 0x00008a6c in ?? () Cannot access memory at address 0x8 #3 0x00008a6c in ?? () Cannot access memory at address 0x8 Backtrace stopped: previous frame identical to this frame (corrupt stack?)

12 years, 8 months

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[Activity] Week 48

by Zhenqiang Chen

Summary: * Verify shrink-wrap related bugs. * Validate and release Linaro toolchain binary 2012.11 release. * Collect performance data for different branch costs. Details: * Validate and release Linaro toolchain binary 2012.11. * Test aarch64 toolchain. All the basic tests PASS except gdbserver. * Collect performance data for branch cost combination. For eembcv1, some combinations have more than 2% performance improvement on PandaBoard THUMB mode. More test results will come later. * Verify shrink-wrap related bugs (http://goo.gl/6fGg5). All pass with the new patch. Native tests are ongoing. Identify the root cause why the copy, which blocks the shrink-wrap optimization for 453.povray benchmark, is not optimized. Plans: * Finalize the aarch64 toolchain binary release plan. * Collect performance data for branch cost tuning. * Enhance shrink-wrap to optimize the copy. Best regards! -Zhenqiang

12 years, 8 months

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[ACTIVITY] 26-30 November

by Yvan Roux

== Progress == * Boehm GC AArch64 support: - Read wikis and papers on the memory model - Reported an issue with the current ARMv7 atomic builtins - Submitted the fix, which was approved - Improving libatomic-ops AArch64 support with load-acquire/ store-release usage. == Next == * Continue on the Boehm GC AArch64 support.

12 years, 8 months

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corruption while doing open close

by Ajeet Yadav

Linux version 3.0.33 (Cortex A15) Below program crashes with 2.14.1 glibc but runs fine with 2.11.1 glibc. #include <pthread.h> #include <stdio.h> #include <stdlib.h> #include <signal.h> #include <string.h> #include <errno.h> #define MAX_LINE_SIZE 80 #define MAX_THREAD 20 #define MAX_POPEN 10 #define MALLOC_SIZE 16 void* pipe_thread(void *arg) { int i; char *p = NULL; FILE *fp[MAX_POPEN]; char shellCommand[MAX_LINE_SIZE]; memset(shellCommand, 0x00, MAX_LINE_SIZE); sprintf(shellCommand, "mount"); signal(SIGPIPE, SIG_IGN); while (1) { for (i = 0; i < MAX_POPEN; ++i) { fp[i] = popen(shellCommand, "r"); } if (p) { free(p); } for (i = 0; i < MAX_POPEN; ++i) { if (fp[i]) pclose(fp[i]); } p = malloc(MALLOC_SIZE); if (p) memset(p, 0, MALLOC_SIZE); } return NULL; } int main(int argc, char *argv[]) { int i; pthread_t tid; for (i = 0; i < MAX_THREAD; ++i) { pthread_create(&tid, NULL, &pipe_thread, (void*)NULL); } sleep(60); } gdb logs: (gdb) bt #0 0x4014f998 in _IO_new_fclose (fp=0x1) at iofclose.c:74 #1 0x4015b59c in fwide (fp=0xb8, mode=<optimized out>) at fwide.c:47 #2 0x00008a6c in ?? () Cannot access memory at address 0x8 #3 0x00008a6c in ?? () Cannot access memory at address 0x8 Backtrace stopped: previous frame identical to this frame (corrupt stack?)

12 years, 8 months

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[ACTIVITY] report week 48

by Peter Maydell

[Short week: 3 days] * looked at (but failed to reproduce) a hang in QEMU reported by Christoffer when shutting down a KVM ARM guest using TUN/TAP networking * investigated LP:1084148 (segfault in qemu usermode) sufficiently to diagnose it as probably another of qemu's "can't handle multithreaded guest programs" bugs * fixed some problems with QEMU's secondary CPU boot code which were masked by errors in QEMU's GIC model but revealed by real hardware (ie KVM); fixed the GIC model bugs as well * investigated LP:955379 (cmake hangs under qemu-arm-static). Tracked down to a race condition involving signal delivery, the fix to which would require the significant redesign I sketched out here a year or so ago: http://lists.gnu.org/archive/html/qemu-devel/2011-12/msg00384.html KVM blueprint progress tracker: http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr… -- PMM

12 years, 9 months

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[ACTIVITY] 26-30 November

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 7 Dec 2012* aarch64-baremetal-testing 31 Oct 2012 7 Dec 2012* fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Preparation for taking over from Michael * Investigate patches for literal pool layout bug * Applied * PINGed triplet backport patches upstream * Other bug issues * Including an issue running SPEC2K on x86 with recent trunk * And a 4.6 gcc-linaro only issue == Next Week == * Start leading Toolchain team * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * initial-aarch64-backport & aarch64-baremetal-testing * Finish documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. == Planned Leave == * Monday 24 December - Monday 31 December -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

12 years, 9 months

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Atomic builtins questions

by Yvan Roux

Hi, I think I have identified some issues with the atomic builtins, but I want your advises. For instance : A: __atomic_store_n (addr, val, __ATOMIC_SEQ_CST); gives the armv7 code: DMB sy STR r1, [r0] DMB sy but if I have well understood, the DMBs instructions only provide the property that the code is sequentially consistent, but not the atomicity for which we have to use the LDREX/STREX instructions. Thus I think that the code should be : DMB sy 1: LDREX r2, [r0] STREX r1, r2, [r0] TEQ r1, #0 BNE 1b B: __atomic_load_n (addr, __ATOMIC_ACQUIRE); gives the armv7 code: DMB sy LDR r0, [r0] but the load-acquire semantique specifies that all loads and stores appearing in program order after the load-acquire will be observed after the load-acquire, thus the DMB should be after the LDR, no ? -- Yvan

12 years, 9 months

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ARMv8 load acquire / store release question

by Yvan Roux

Hi, I'm working on the libatomic-ops (part of the Boehm gc) AArch64 support, I mainly use GCC's __atomic builtins to do this, but in our 4.7 version they don't use the load acquire / store release instructions now available in the ARMv8 ISA. These instructions are used in the mainline GCC (in atomic.md) but not in their exclusive form, I understand that it should be due to the performance penalty, but I want your feeling on that point as I don't find the ARMv8 ISA really clear. If we want to implement an atomic load acquire, is LDAR x1, [x0] sufficient, or do we have to write it like that : L: LDAXR x0, [x3] STEX x1, x0, [x3] CBZ x0, L1 Thanks Yvan

12 years, 9 months

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