- linaro-toolchain - lists.linaro.org

by Peter Maydell

Activity: * usual set of calls and meetings (and there is another KVM related weekly meeting in the pipeline...) * reviewed virtio patches * rebased qemu-linaro on upstream * rebased KVM patches; couldn't get updated kernel to run on RTSM (probably a device tree or config issue; need to attack problem again this week) NB: I'm currently working a reduced set of hours due to RSI, though I am trying to remain responsive to email etc. -- PMM

13 years, 3 months

1
0
0 0

[ACTIVITY] 14-18 January 2013

by Yvan Roux

== Progress == * Prepared Venkat on-boarding. * Aarch64 porting meeting: - libunwind is in the pipe * Boehm GC AArch64 support: - basic port done, test on-going == Next == * Boehm GC AArch64 support: - test and ask for up stream review.

13 years, 3 months

1
0
0 0

[Activity] Week 03

by Zhenqiang Chen

Summary: * Investigate automotive benchmark. * Linaro gcc 4.6 release Details: 1. Automotive benchmark performance analysis for different branch cost for Cortex-A9. * Debug function WriteOut, which is called 12 times on average, leads common performance issue since the IF-THEN in the function is converted to IT block, which TRUE probability is less than 4%. * Identify the root cause of performance regression with IT block for bitmnp01, rspeed01, pntrch01 and ttsprk01. Overall, - The performance of a taken bpl is better than an ITTT. If this is a common sense, for IF-THEN, we'd set branch-cost to 1. - For IF-THEN-ELSE, we'd take branch probability into account when converting it to IT block. - ifcvt might generate useless IT block. 2. Try to do Linaro GCC release. But meet several issues: * Can not branch a clean lp:gcc-linaro/4.7. As a workaround, I had downloaded a clean bzr tree from other site. For next release, I can use the local tree to create the release tarball. * All a9hf-builder ubutests fail due to test environment issue. Plan: * Investigate more benchmarks for different branch costs. Planed leaves: * Feb. 9 - 15: Chinese Spring Festival. Best Regards! -Zhenqiang

13 years, 3 months

1
0
0 0

[ACTIVITY] 14-18 January 2013

by Christophe Lyon

== Progress == * 64-bits ops in Neon: pinged patch proposal. * vectorizer cost model: received results from spec2k. Prepared initial tuning to submit to benchmarking again. * smin-umin: tests OK, benchmarks ran, but did not generate the diff over a valid ancestor. I didn't make the manual comparison yet. * updated board for local benchmarking * tcpanda heat problems: built a new kernel with the thermal driver; need to reboot the board with it == Next == * handle 64-bits bitops in Neon feedback from upstream if any * analyze results of benchmarking with vectorizer cost model * analyze results of benchmarking with smin-umin idiom patch * continue board setup/update; I will probably try to cross-build the benchmarks to avoid having the build GCC itself on the board and save time. * followup on tcpanda heat problems

13 years, 3 months

1
0
0 0

[ACTIVITY] 14-18 Jan

by Renato Golin Linaro

== Progress == * Buildbots - Added a Panda ES buildbot on clang-native-arm-cortex-a9 group - Reporting and helping fix bot bugs on ARM - ARM buildbots are green again! - Each ARM buildbot takes 4h15min to complete, versus 15min on Intel - We're still testing up to 12-15 patches on each build, on peak times (PST) * LAVA - Created a test run for llvm check-all, infrastructure is there - Need to make it actually do some work * Vectorization - Refactored cost model's temp tables - http://llvm.org/viewvc/llvm-project?view=rev&revision=172658 - Studying NEON costs, changing ARM target lowering * test-suite A15 - Building LLVM on Chromebook, check-all (1h, 181 failures) - Self-hosting LLVM on Chromebook, check-all (50min, many more) - Found some floating point type errors, only on Chromebook (libs?) * AArch64 back-end - Reviewed patches, look ok, some comments - Should be all in by next week * LLVM cross-compilation woes - Had to define include path for c, c++ and arm locations - It calls the wrong assembler, even defining the right gnu toolchain - Someone needs to fix these cross-compilation bugs!! :) == Plan == * Finish basic NEON costs for vectorization * Finish LAVA bot compiling clang + check-all * Install Panda buildbot on rack * Continue investigating Chromebook failures * Continue thinking about the long term plan for LLVM

13 years, 3 months

1
0
0 0

[ANNOUNCE] Linaro GCC 4.7 and 4.6 2013.01 released

by Zhenqiang Chen

The Linaro Toolchain Working Group is pleased to announce the 2013.01 release of both Linaro GCC 4.7 and Linaro GCC 4.6. Linaro GCC 4.7 2013.01 is the tenth release in the 4.7 series. Based off the latest GCC 4.7.2+svn194772 release, it includes ARM-focused performance improvements and bug fixes. Interesting changes include: * Updates to GCC 4.7.2+svn194772 * Includes arm/aarch64-4.7-branch up to svn revision 194808 * Support for the rev16 and revsh instructions * A15 Neon pipeline backported from trunk * FMA intrinsic backported from trunk * Better extending core to NEON transfers * Fused multiply-add support Fixes: * LP #1088898 regression of x86 gcc bootstrap with Linaro sourcebase * LP #1067766 Backport support for arm-linux-gnueabihf to GCC Linaro * LP #1084010 __atomic_load doesn't match ACQUIRE memory model Linaro GCC 4.6 2013.01 is the 23st release in the 4.6 series. Based off the latest GCC 4.6.3+svn194771 release, this is the tenth release after entering maintenance. Interesting changes include: * Updates to 4.6.3+svn194771 The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.7-2013.01 https://launchpad.net/gcc-linaro/+milestone/4.6-2013.01 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release pages: https://launchpad.net/gcc-linaro/4.7/4.7-2013.01 https://launchpad.net/gcc-linaro/4.6/4.6-2013.01 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org

13 years, 3 months

1
0
0 0

Thursday 17th January 2013 1600 UTC Performance Call cancelled

by Matthew Gretton-Dann

All, Due to items in the performance call being covered in other meetings, travel and other issues I have decided to cancel today's 1600 UTC call. Thanks, Matt -- Matthew Gretton-Dann Toolchain Working Group, Linaro

13 years, 3 months

1
0
0 0

[PATCH] Cortex Strings AArch64 strnlen.S fix

by Marcus Shawcroft

This patch fixes an issue in the AArch64 strncmp implementation which occurs if ULONG_MAX-15 <= n <= ULONG_MAX. Matt, this is the last of my outstanding patches for cortex-strings. /Marcus

13 years, 4 months

2
1
0 0

[PATCH] Cortex Strings AArch64 fix for strncmp.S

by Marcus Shawcroft

This patch fixes an issue in the AArch64 strncmp implementation which occurs if ULONG_MAX-15 <= n <= ULONG_MAX. /Marcus

13 years, 4 months

2
1
0 0

AArch64 NEON polynomial types

by Renato Golin Linaro

Hi folks, On the LLVM list, Tim (ARM) is trying to push a patch to update the polynomial types on NEON to unsigned, on both 32-bits and 64-bits, since AArch32 says nothing and AArch64 specifies unsigned (char and short). Is there any such movement on the GCC end? The LLVM folks would rather this be a common move (or GCC first), than going solo and risk losing ABI compatibility. Any comments? cheers, --renato

13 years, 4 months

1
0
0 0

Linking error - VFP register arguments

by Anup Kini

Hi All, I am trying to build OpenNI drivers and stuck with the following linker error. /usr/bin/ld: error: ../../Bin/Arm-Release/libOpenNI.so uses VFP register arguments, ./Arm-Release/XnBaseNode.o does not /usr/bin/ld: failed to merge target specific data of file ./Arm-Release/XnBaseNode.o /usr/bin/ld: error: ../../Bin/Arm-Release/libOpenNI.so uses VFP register arguments, ./Arm-Release/XnDump.o does not /usr/bin/ld: failed to merge target specific data of file ./Arm-Release/XnDump.o and many more of similar errors with VFP. System : ZYNC ZC702 board with ARM Cortex A9 dual core. OS: Linaro 12.04 LTS GCC - 4.6.3 Is there some flag i have to set in the Makefile to correct the Hard/Soft float type ? How do i figure out the correct one ? -- *Anup Kini *Systems Engineer**** * ------------------------------ * *Synapticon** * | Cyber-Physical System Solutions **** Direct:**** +49 7335 / 186 999 17**** Fax:**** +49 7335 / 186 999 1 **** **** synapticon.com <http://www.synapticon.com/> | @synapticon_co<https://twitter.com/#!/synapticon_co> **** Synapticon GmbH | Hohlbachweg 2 | 73344 Gruibingen, DE Secretary +49 7335 / 186 999 0 | General Manager: Nikolai Ensslen Registry Court Ulm HRB 725114 | USt-ID DE271647127**** This message and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. Please notify the sender immediately if you have received this e-mail by mistake and delete it from your system.

13 years, 4 months

1
0
0 0

Possible toolchain bug with handling return value of read()

by Riku Voipio

Hi, The testcase at https://launchpadlibrarian.net/128616769/compare-test.c With aarch64: aarch64-oe-linux-gcc -o a-test ./compare-test.c ./a-test: fail ret: -1: Bad address With X86_64: gcc -o test ./compare-test.c ./test correct. ret: -1: Bad address setting -D_FILE_OFFSET_BITS=64 doesn't make a difference. This is with: gcc version 4.7.3 20121205 (prerelease) (Linaro GCC 4.7-2012.12) This was found while debugging: https://bugs.launchpad.net/linaro-aarch64/+bug/1099896 Riku

13 years, 4 months

1
0
0 0

[MINUTES] Toolchain Working Group Weekly Meeting 14/Jan/2013

by Matthew Gretton-Dann

All, The minutes for today's calls are here: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2013-01-14 Action items are: TODO: Matt to investigate EEMBC Office gs8 failures ONGOING: Matt to talk to Dave Pigott about HF builders TODO: Matt blueprint backport of binutils 2.23.1 - backport just needs merging TODO: Matt to blueprint options for reducing QEMU based cross test noise TODO: Matt to unreserve Michael Hope's reservations TODO: Matt to look at why Cortex-A9 softfloat bootstraps fail in Stage2. TODO: Zhenqiang to do GCC Release: https://wiki.linaro.org/WorkingGroups/ToolChain/GCC/ReleaseProcess TODO: Matt to do Cortex Strings release. TODO: Matt chase up EEMBC Networking License TODO: Matt chase up with morvek who is leading KVM Virtual team. TODO: All to think of proposals for GNU Tools Caudron The agenda for next week's call is here: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2013-01-21 Please feel free to add your own agenda items before hand. Thanks, Matt -- Matthew Gretton-Dann Toolchain Working Group, Linaro

13 years, 4 months

1
0
0 0

[Activity] Week 02

by Zhenqiang Chen

Summary: * Rebase and test the shrink-wrap patches. * Learn how branch cost impact on code generation. Details: 1. Rebase and test the shrink-wrap patches. * For pretend arguments, it is hard to generate correct dwarf info for case: * Add dwarf info for ldrd_pop. Testing is ongoing. * Expose an interface from regcpprog and do copy propagation for the entry block. Benchmark logs show there are much more functions can be shrink-wrapped. 2. Read codes and enhance ifcvt.c. * For IF-THEN-ELSE, if the last insn of then_bb or else_bb is ANY_RETURN_P, we can save one JUMP. In this, we'd keep max MAX_CONDITIONAL_EXECUTE, not "max *= 2". A patch is sent out for review. * Take the branch probability into account. Test is ongoing. 3. R/M toolchain related work. Plan: * Follow up the shrink-wrap dwarf info issue. * Investigate benchmarks which is impacted by different branch cost. Planed leaves: * Feb. 9 - 15: Chinese Spring Festival. Best Regards! -Zhenqiang

13 years, 4 months

1
0
0 0

[ACTIVITY] 7-11 January 2013

by Yvan Roux

== Progress == * Short week again (leading compilation courses) * Merge request review - finished 4.6 and 4.7 requests. * Boehm GC AArch64 support - Back on this topic == Next == * Continue Boehm GC activity

13 years, 4 months

1
0
0 0

[ACTIVITY] 7-11 Jan 2013

by Renato Golin Linaro

== This Week == * Livermore Loops - Test was badly adapted, failures were due to undefined behaviour - Removed from test-suite until a propper adaptation can be done - LTO and Static Analysis issues raised - http://llvm.org/bugs/show_bug.cgi?id=14851 - http://llvm.org/bugs/show_bug.cgi?id=14852 * LLVM Builds - Builds fine on Chromebook, same check-all failures as other ARM targets - test-suite fails, haven't had time to properly investigate - Getting a pandaboard to act as a buildbot - Creating a LAVA job to run often and on-demand internally * AArch64 in LLVM - reviewing lots of patches from ARM (Tim Northover) - full back-end just sent, will review over the weekend * Loop Vectorize - Some discussions with Tao Wang about cost models - Got some ideas on what are the best changes for LLVM's cost model - Not much on this front * EuroLLVM 2013 - Trying to define the level of sponsorship Linaro can provide - CFP will go out next week, committee created, conference confirmed * Commits http://llvm.org/viewvc/llvm-project?view=rev&revision=171642 http://llvm.org/viewvc/llvm-project?view=rev&revision=171859 == Next Week == * Get the LAVA job running - need account at people.linaro.org, RT created * Get at least one buildbot in sync with LLVM's lab * Get some traction on the cost model * Cambridge LLVM Social, liaise with ARM == Future == * Try to draft an LLVM story for Linaro (and understand why I'm here in the first place) ;) * Have builds with vectorization turned on

13 years, 4 months

3
4
0 0

[ACTIVITY] 7-11 January 2013

by Brice Dobry

== Blueprints == gcc-investigate-lra-for-arm == Progress == * Built "lra" gcc branch of gcc for x86 * Collected and compared SPEC benchmark results with and without LRA enabled * Bootstrapped ARM toolchain with last reported working revision from lra branch * Tracked down and resolved ICE * Bootstrapped ARM toolchain with head revision from lra branch * Tracked down and resolved another ICE * Verified two patches (from above ICEs) have no regressions on trunk * Began investigation into target hooks for LRA for ARM to improve performance * Admin * Connect registration and trip preparations == Next week == * Collect benchmark results from SPEC for LRA on ARM * Complete target hooks and benchmark again * Review roster

13 years, 4 months

1
0
0 0

[ACTIVITY] 7-11 January 2013

by Christophe Lyon

== Progress == * 64-bits ops in Neon: pinged patch proposal. * disable peeling/vectorzer cost model: initial benchmarking done wth cost-model on (now default). Received some results with cost model off, waiting for spec2k. * started looking at smin-umin idiom patch from Ramana. Rebased and launched build to make some benchmarking. * restarted working on local board setup for benchmarking * discussed bug reports on ARM-Neon instrinsics testsuite == Next == * handle 64-bits bitops in Neon feedback from upstream if any * analyze results of benchmarking with vectorizer cost model * analyze results of benchmarking with smin-umin idiom patch * continue board setup/update

13 years, 4 months

1
0
0 0

[ACTIVITY] 7-11 January 2013

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual fix-gcc-multiarch-testing 31 Dec 2012 31 Jan 2013 == Progress == * Infrastructure * Investigations of why Cortex-A9 HF boards are failing * Admin * Booked tickets to Connect * 'Onboarding' prep for new starters and assignees * Cortex Strings * Applied patches == Next week == * Prepare Cortex Strings release * Ensure GCC backports are up to date. * Release week. * Catch up on outstanding cards. == Future == * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. -- Matthew Gretton-Dann Toolchain Working Group, Linaro

13 years, 4 months

1
0
0 0

Help on epilogue dwarf info

by Zhenqiang Chen

Hi, Would you please help on how to generate correct epilogue dwarf info? Without correct dwarf info, when shrink-wrap is enabled, it tends to ICE at dwarf2cfi.c: function maybe_record_trace_start. /* We ought to have the same state incoming to a given trace no matter how we arrive at the trace. Anything else means we've got some kind of optimization error. */ gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row)); Issues: 1) pretend_args The attached pretend_arg.c shows an example about pretend_args dwarf info push {r2, r3} .cfi_def_cfa_offset 8 .cfi_offset 2, -8 .cfi_offset 3, -4 use r3 push {r4, r5, lr} ... pop {r4, r5, lr} add sp, sp, #8 //No instruction here to restore r2 and r3 Can we RESTORE r2 and r3? * If we notes to RESTORE r2 and r3, it might lead to wrong info for GDB since no instruction restores them. * If we do not RESTORE them, the reg_save dwarf info will not be cleared. Then the dwarf check will fail when the function is shrink-wrapped. 2) frame_pointer_needed In prologue, we set fp like fp = sp + INT After this instruction, cfi_def_cfa_register is set to fp In epilogue. we have fp += INT sp = fp Can we reset cfi_def_cfa_register back to sp? * If we set it back to sp, how to handle it in arm_unwind_emit_set, which assumes sp can not be set from other register? /* A stack increment. */ if (GET_CODE (e1) != PLUS || !REG_P (XEXP (e1, 0)) || REGNO (XEXP (e1, 0)) != SP_REGNUM || !CONST_INT_P (XEXP (e1, 1))) abort (); * If we do not set it back, to get correct dwarf info for POP after "sp = fp", we have to add notes " sp = fp + INT" for dwarf-info while we have "sp = sp + INT" in the insn. Here is the workaround POP RTL example for the attached alloca,c: (insn/f 62 61 66 3 (parallel [ (set/f (reg/f:SI 13 sp) // sp = sp + 8 (plus:SI (reg/f:SI 13 sp) (const_int 8 [0x8]))) (set/f (reg:SI 3 r3) (mem/c:SI (reg/f:SI 13 sp) [3 S4 A32])) (set/f (reg/f:SI 7 r7) (mem/c:SI (plus:SI (reg/f:SI 13 sp) (const_int 4 [0x4])) [3 S4 A32])) ]) alloca.c:8 329 {*load_multiple_with_writeback} (expr_list:REG_UNUSED (reg:SI 3 r3) (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp) (plus:SI (reg/f:SI 7 r7) // sp = fp + 8 (const_int 8 [0x8]))) (expr_list:REG_CFA_RESTORE (reg/f:SI 7 r7) (expr_list:REG_CFA_RESTORE (reg:SI 3 r3) (nil)))))) (3) No idea for if (crtl->calls_eh_return) emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM))); Currently I have no shrink-wrapped test case which crtl->calls_eh_return is true. Thanks! -Zhenqiang

13 years, 4 months

1
0
0 0

Instruction costs for ARM/NEON

by Renato Golin

Hi all, I'm helping the loop vectorization in LLVM and for that we need first to build the instruction cost model so we can decide whether the vectorization is worth or not. I was looking at some papers, but most of them concern with energy consumption, which is not the issue (at least not for now). The "cost" model should take the point of view of latency, stalls and pipeline cost. I know there are sporadic comments on this on the ARM ARM, but would be good to have a definite resource where to get the data from (and hope it's a public document). Does anyone know of a good place to start looking for that? Even if the document is private, we can certainly hide the information enough to make it to the LLVM code base. cheers, --renato

13 years, 4 months

2
4
0 0

compiler crash while building c++ libs

by Anup Kini

Hi All, I am using linaro-precise-ubuntu-desktop-20120626 on my ZYNQ ZC702 board which has an ARM Cortex-A9 dual core processor. I am trying to compile Point Cloud Library and its dependent libraries like FLANN, VTK, EIGEN etc.. which are basically c++ libraries. The compiler crashes with the following error msg and i am unable to figure out where the problem is. linaro@linaro-ubuntu-desktop:~/flann/flann-1.8.3-src/build$ make install [ 33%] Building CXX object src/cpp/CMakeFiles/flann_s.dir/flann/flann.cpp.o In file included from /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/algorithms/kmeans_index.h:51:0, from /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/algorithms/all_indices.h:38, from /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/flann.hpp:45, from /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/flann.h:466, from /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/flann.cpp:31: /home/linaro/flann/flann-1.8.3-src/src/cpp/flann/util/logger.h:73:9: note: the mangling of ‘va_list’ has changed in GCC 4.4 c++: internal compiler error: Killed (program cc1plus) Please submit a full bug report, with preprocessed source if appropriate. See file:///usr/share/doc/gcc-4.6/README.Bugs for instructions. make[2]: *** [src/cpp/CMakeFiles/flann_s.dir/flann/flann.cpp.o] Error 4 make[1]: *** [src/cpp/CMakeFiles/flann_s.dir/all] Error 2 make: *** [all] Error 2 linaro@linaro-ubuntu-desktop:~/flann/flann-1.8.3-src/build$ Let me know if someone has faced similar issue or has any solution for this. -- *Anup Kini *Systems Engineer**** * ------------------------------ * *Synapticon** * | Cyber-Physical System Solutions **** Direct:**** +49 7335 / 186 999 17**** Fax:**** +49 7335 / 186 999 1 **** **** synapticon.com <http://www.synapticon.com/> | @synapticon_co<https://twitter.com/#!/synapticon_co> **** Synapticon GmbH | Hohlbachweg 2 | 73344 Gruibingen, DE Secretary +49 7335 / 186 999 0 | General Manager: Nikolai Ensslen Registry Court Ulm HRB 725114 | USt-ID DE271647127**** This message and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. Please notify the sender immediately if you have received this e-mail by mistake and delete it from your system.

13 years, 4 months

2
6
0 0

[PATCH] cortex strings adding aarch64 specific memcmp

by Marcus Shawcroft

/Marcus

13 years, 4 months

2
1
0 0

[PATCH] Adding test-strnlen to cortex strings.

by Marcus Shawcroft

This patch adds the strnlen test from glibc in preparation for an AArch64 specific strnlen implementation... /Marcus

13 years, 4 months

2
1
0 0

[PATCH] cortex strings adding aarch64 specific strnlen

by Marcus Shawcroft

/Marcus

13 years, 4 months

2
1
0 0

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain