- linaro-toolchain - lists.linaro.org

[ACTIVITY] 3-7 December 2012

by Christophe Lyon

== Progress == * Turn off 64-bits bitos in Neon: Ping-ed patch proposal. * Disable peeling: benchmarks show good results; sent a proposal upstream to discuss preliminary implementation & needed testsuite modifications. * builtin_bswap16 backport to linaro-4.7: need to investigation an unexpected regression reported for i686 target. * Updated gdb linaro sources to 7.5.1, exercising the release process. * Trying to bootstrap gcc-linaro/4.7 on board: need to retry with a different rootfs distribution. == Next == * handle 64-bits bitops in Neon and disable-peeling feedback from upstream if any. * finish builtin_bswap16 backport

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[ACTIVITY] 3-7 December 2012

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 14 Dec 2012 aarch64-baremetal-testing 31 Oct 2012 14 Dec 2012 fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Took over from Michael * Preparation for taking over from Michael * re-PINGed triplet backport patches upstream * Patch review * Initial thoughts about cards == Next Week == * initial-aarch64-backport and aarch64-baremetal-testing * Complete documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years

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selected processor does not support Thumb mode `smc 0'

by Shivamurthy Shastri

Hi, I am trying to compile UEFI code with linaro toolchain version: # arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.1-5ubuntu1~ppa1) 4.7.1 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. I got the erros as follows: "/usr/bin/arm-linux-gnueabi-gcc" -mthumb -march=armv7-a -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform -g -Os -fshort-wchar -fno-strict-aliasing -Wall -Werror -Wno-missing-braces -Wno-array-bounds -c -include AutoGen.h -mword-relocations -mlittle-endian -mabi=aapcs -mapcs -fno-short-enums -save-temps -fsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -O0 -o /home/shiva/workspace/arndale/edk2/Build/Arndale-Exynos/DEBUG_ARMLINUXGCC/ARM/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec/OUTPUT/./Smc.obj -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec -I/home/shiva/workspace/arndale/edk2/Build/Arndale-Exynos/DEBUG_ARMLINUXGCC/ARM/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec/DEBUG -I/home/shiva/workspace/arndale/edk2/MdePkg -I/home/shiva/workspace/arndale/edk2/MdePkg/Include -I/home/shiva/workspace/arndale/edk2/MdePkg/Include/Arm -I/home/shiva/workspace/arndale/edk2/MdeModulePkg -I/home/shiva/workspace/arndale/edk2/MdeModulePkg/Include -I/home/shiva/workspace/arndale/edk2/ArmPkg -I/home/shiva/workspace/arndale/edk2/ArmPkg/Include -I/home/shiva/workspace/arndale/edk2/ArmPlatformPkg -I/home/shiva/workspace/arndale/edk2/ArmPlatformPkg/Include -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250 -I/home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include /home/shiva/workspace/arndale/edk2/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Smc.c Smc.s: Assembler messages: Smc.s:51: Error: selected processor does not support Thumb mode `smc 0' Is there any issue with the toolchain or any flags I am using? -- Thanks and Regards, Shiva.

13 years

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Scheduler tweaks

by Michael Hope

I've done a couple of tweaks to the scheduler. You now see pending jobs by the class of machine they'll run on. Clicking a job takes you to the detail, which includes a link to drop/cancel the job. -- Michael

13 years

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Toolchain Working Group Meeting Times

by Matthew Gretton-Dann

All, As I mentioned on Monday, due to new members of the team coming on board I am going to rejig the meeting times from 18th December. My proposal is as follows (all times UK Local - UTC+0h winter, UTC+1h summer): 0. These changes will come into effect the week commencing 18th December. 1. The weekly call will happen on a Monday, at 0930 and 1600. You only need to make it to one instance of the call. For those who are physically near each other arranging it so that both calls get attended would be good and notes shared would be good. 2. The Stand-up call will happen on a Thursday, alternating between 0930 and 1600. This is 'best effort' - but please try to attend at least every other week. 3. The performance call will go weekly, and will happen on a Thursday, alternating between 0930 and 1600. If you are on the invite list to this call again please try to attend at least every other week, but if you can manage every week that would be great. If you have any comments on these please can you raise them by the end of the week as I would like to confirm what we are going to do at the call on Monday (at the normal time of 0915UTC). Thanks, Matt -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years

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[MINUTES] Toolchain Performace Call 2012-12-03

by Michael Hope

The minutes of the performance call held on 3 December 2012 can be found at: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-12-03 In summary the actions from the meeting are: * ACTION: Yvan will do the trunk merge this week * ACTION: Yvan to do the GCC release next week * ACTION: Christophe to do the GDB release branch merge * ACTION: Matt volunteered Zhenqiang as the QEMU manual tester this month * ACTION: Matt: want shrinkwrap to go upstream * ACTION: Matt - Can blueprint improvements in shrink wrap past that * ACTION: Matt to create a blueprint on aarch32 ARMv8 instructions in QEMU * ACTION: Matt to decide if aarch32 ARMv8 instructions in QEMU needs a card * ACTION: Christophe to send Michael cross build failures to investigate Thanks, -- Michael

13 years

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[ACTIVITY] 26-30 November

by Christophe Lyon

== Progress == * Turn off 64-bits bitops in Neon: patch proposed upstream after positive benchmarking. Re-submitted after request to add testcases and documentation for the new option. * Disable peeling: running benchmarks with peeling completely disabled to see the impact. * PGO/hot-cold partitioning: tested new patch from google, which solves some of the ICEs, but makes new ones appear. * builtin_bswap16 backport to Linaro-4.7: checking if there would be a possibility to keep the testcase which fails in one of our configurations, after rebasing my branch. * Trying to bootstrap gcc-linaro/4.7 on board * Internal support == Next == * Follow-up on 64-bits bitops in Neon * Look at benchmarks results with peeling disabled * finish builtin_bswap16 backport

13 years

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random corruption while doing popen pclose

by Ajeet Yadav

Linux version 3.0.33 (Cortex A15) Below program crashes with 2.14.1 glibc but runs fine with 2.11.1 glibc. #include <pthread.h> #include <stdio.h> #include <stdlib.h> #include <signal.h> #include <string.h> #include <errno.h> #define MAX_LINE_SIZE 80 #define MAX_THREAD 20 #define MAX_POPEN 10 #define MALLOC_SIZE 16 void* pipe_thread(void *arg) { int i; char *p = NULL; FILE *fp[MAX_POPEN]; char shellCommand[MAX_LINE_SIZE]; memset(shellCommand, 0x00, MAX_LINE_SIZE); sprintf(shellCommand, "mount"); signal(SIGPIPE, SIG_IGN); while (1) { for (i = 0; i < MAX_POPEN; ++i) { fp[i] = popen(shellCommand, "r"); } if (p) { free(p); } for (i = 0; i < MAX_POPEN; ++i) { if (fp[i]) pclose(fp[i]); } p = malloc(MALLOC_SIZE); if (p) memset(p, 0, MALLOC_SIZE); } return NULL; } int main(int argc, char *argv[]) { int i; pthread_t tid; for (i = 0; i < MAX_THREAD; ++i) { pthread_create(&tid, NULL, &pipe_thread, (void*)NULL); } sleep(60); } gdb logs: (gdb) bt #0 0x4014f998 in _IO_new_fclose (fp=0x1) at iofclose.c:74 #1 0x4015b59c in fwide (fp=0xb8, mode=<optimized out>) at fwide.c:47 #2 0x00008a6c in ?? () Cannot access memory at address 0x8 #3 0x00008a6c in ?? () Cannot access memory at address 0x8 Backtrace stopped: previous frame identical to this frame (corrupt stack?)

13 years

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[Activity] Week 48

by Zhenqiang Chen

Summary: * Verify shrink-wrap related bugs. * Validate and release Linaro toolchain binary 2012.11 release. * Collect performance data for different branch costs. Details: * Validate and release Linaro toolchain binary 2012.11. * Test aarch64 toolchain. All the basic tests PASS except gdbserver. * Collect performance data for branch cost combination. For eembcv1, some combinations have more than 2% performance improvement on PandaBoard THUMB mode. More test results will come later. * Verify shrink-wrap related bugs (http://goo.gl/6fGg5). All pass with the new patch. Native tests are ongoing. Identify the root cause why the copy, which blocks the shrink-wrap optimization for 453.povray benchmark, is not optimized. Plans: * Finalize the aarch64 toolchain binary release plan. * Collect performance data for branch cost tuning. * Enhance shrink-wrap to optimize the copy. Best regards! -Zhenqiang

13 years

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[ACTIVITY] 26-30 November

by Yvan Roux

== Progress == * Boehm GC AArch64 support: - Read wikis and papers on the memory model - Reported an issue with the current ARMv7 atomic builtins - Submitted the fix, which was approved - Improving libatomic-ops AArch64 support with load-acquire/ store-release usage. == Next == * Continue on the Boehm GC AArch64 support.

13 years

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corruption while doing open close

by Ajeet Yadav

Linux version 3.0.33 (Cortex A15) Below program crashes with 2.14.1 glibc but runs fine with 2.11.1 glibc. #include <pthread.h> #include <stdio.h> #include <stdlib.h> #include <signal.h> #include <string.h> #include <errno.h> #define MAX_LINE_SIZE 80 #define MAX_THREAD 20 #define MAX_POPEN 10 #define MALLOC_SIZE 16 void* pipe_thread(void *arg) { int i; char *p = NULL; FILE *fp[MAX_POPEN]; char shellCommand[MAX_LINE_SIZE]; memset(shellCommand, 0x00, MAX_LINE_SIZE); sprintf(shellCommand, "mount"); signal(SIGPIPE, SIG_IGN); while (1) { for (i = 0; i < MAX_POPEN; ++i) { fp[i] = popen(shellCommand, "r"); } if (p) { free(p); } for (i = 0; i < MAX_POPEN; ++i) { if (fp[i]) pclose(fp[i]); } p = malloc(MALLOC_SIZE); if (p) memset(p, 0, MALLOC_SIZE); } return NULL; } int main(int argc, char *argv[]) { int i; pthread_t tid; for (i = 0; i < MAX_THREAD; ++i) { pthread_create(&tid, NULL, &pipe_thread, (void*)NULL); } sleep(60); } gdb logs: (gdb) bt #0 0x4014f998 in _IO_new_fclose (fp=0x1) at iofclose.c:74 #1 0x4015b59c in fwide (fp=0xb8, mode=<optimized out>) at fwide.c:47 #2 0x00008a6c in ?? () Cannot access memory at address 0x8 #3 0x00008a6c in ?? () Cannot access memory at address 0x8 Backtrace stopped: previous frame identical to this frame (corrupt stack?)

13 years

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[ACTIVITY] report week 48

by Peter Maydell

[Short week: 3 days] * looked at (but failed to reproduce) a hang in QEMU reported by Christoffer when shutting down a KVM ARM guest using TUN/TAP networking * investigated LP:1084148 (segfault in qemu usermode) sufficiently to diagnose it as probably another of qemu's "can't handle multithreaded guest programs" bugs * fixed some problems with QEMU's secondary CPU boot code which were masked by errors in QEMU's GIC model but revealed by real hardware (ie KVM); fixed the GIC model bugs as well * investigated LP:955379 (cmake hangs under qemu-arm-static). Tracked down to a race condition involving signal delivery, the fix to which would require the significant redesign I sketched out here a year or so ago: http://lists.gnu.org/archive/html/qemu-devel/2011-12/msg00384.html KVM blueprint progress tracker: http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr… -- PMM

13 years

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[ACTIVITY] 26-30 November

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 7 Dec 2012* aarch64-baremetal-testing 31 Oct 2012 7 Dec 2012* fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Preparation for taking over from Michael * Investigate patches for literal pool layout bug * Applied * PINGed triplet backport patches upstream * Other bug issues * Including an issue running SPEC2K on x86 with recent trunk * And a 4.6 gcc-linaro only issue == Next Week == * Start leading Toolchain team * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * initial-aarch64-backport & aarch64-baremetal-testing * Finish documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. == Planned Leave == * Monday 24 December - Monday 31 December -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years

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Atomic builtins questions

by Yvan Roux

Hi, I think I have identified some issues with the atomic builtins, but I want your advises. For instance : A: __atomic_store_n (addr, val, __ATOMIC_SEQ_CST); gives the armv7 code: DMB sy STR r1, [r0] DMB sy but if I have well understood, the DMBs instructions only provide the property that the code is sequentially consistent, but not the atomicity for which we have to use the LDREX/STREX instructions. Thus I think that the code should be : DMB sy 1: LDREX r2, [r0] STREX r1, r2, [r0] TEQ r1, #0 BNE 1b B: __atomic_load_n (addr, __ATOMIC_ACQUIRE); gives the armv7 code: DMB sy LDR r0, [r0] but the load-acquire semantique specifies that all loads and stores appearing in program order after the load-acquire will be observed after the load-acquire, thus the DMB should be after the LDR, no ? -- Yvan

13 years

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ARMv8 load acquire / store release question

by Yvan Roux

Hi, I'm working on the libatomic-ops (part of the Boehm gc) AArch64 support, I mainly use GCC's __atomic builtins to do this, but in our 4.7 version they don't use the load acquire / store release instructions now available in the ARMv8 ISA. These instructions are used in the mainline GCC (in atomic.md) but not in their exclusive form, I understand that it should be due to the performance penalty, but I want your feeling on that point as I don't find the ARMv8 ISA really clear. If we want to implement an atomic load acquire, is LDAR x1, [x0] sufficient, or do we have to write it like that : L: LDAXR x0, [x3] STEX x1, x0, [x3] CBZ x0, L1 Thanks Yvan

13 years

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[MINUTES] Toolchain Performace Call 2012-11-27

by Matthew Gretton-Dann

All, [Editiorial: Michael & I discussed making what we do as a working group more visible at Connect. One thing we discussed was making our meeting minutes more visible by emailing actions out after each meeting. This will be part of the job of the 'minuter' - a job I plan to spread around as I am useless at it whilst also running a call - more info on the Wiki: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings] The minutes of the performance call held on 27 November 2012 can be found at: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-11-27 In summary the actions from the meting are: * mgrettondann split LRA blueprint * Christophe to update Hot/Cold partitioning bugzilla * mgrettondann: benchmark on Hold/Cold partitioning * Michael to log a ticket to improve reporting of benchmarks when the run complete. * Ramana to log EEMBC failure with Hot/Cold partitioning into bugzilla. * Christophe to backport bswap16 builtin, except for the testcase which fails in one of our configurations (Thumb1 + hard FP ABI) The next performance call will be on 11 December 2012 and the agenda can be found at: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-12-11 Thanks, Matt -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years

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[ANNOUNCE] Linaro Toolchain Binaries 2012.11 released

by Zhenqiang Chen

The Linaro Toolchain Working Group is pleased to announce the 2012.11 release of the Linaro Toolchain Binaries, a pre-built version of Linaro GCC and Linaro GDB that runs on generic Linux or Windows and targets the glibc Linaro Evaluation Build. Uses include: * Cross compiling ARM applications from your laptop * Remote debugging * Build the Linux kernel for your board What's included: * Linaro GCC 4.7 2012.11 * Linaro GDB 7.5 2012.09 * A statically linked gdbserver * A system root * Manuals under share/doc/ The system root contains the basic header files and libraries to link your programs against. The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian 6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation 5.7 and later, and should run on any Linux Standard Base 3.0 compatible distribution. Please see the README about running on x86_64 hosts. The Windows version is supported on Windows XP Pro SP3, Windows Vista Business SP2, and Windows 7 Pro SP1. The binaries and build scripts are available from: https://launchpad.net/linaro-toolchain-binaries/trunk/2012.11 Need help? Ask a question on https://ask.linaro.org/ Already on Launchpad? Submit a bug at https://bugs.launchpad.net/linaro-toolchain-binaries On IRC? See us on #linaro on Freenode. Other ways that you can contact us or get involved are listed at https://wiki.linaro.org/GettingInvolved.

13 years

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[Activity] Week 47

by Zhenqiang Chen

Summary: * Investigate shrink-wrap result. * Prepare for Linaro toolchain binary release, script merge and aarch64 test. Details: 1. Investigate shrink-wrap result of function Ray_In_Bound. By default, ARM/MIPS/PPC/X86 toolchain can not shrink-wrap the function. For ARM, there is copy "r6 = r1" which blocks the optimization. By hacking the assemble code, I got ~3% performance improvement for 453.povray benchmark. 2. Setup AARCH64 simulation environment by following http://www.linaro.org/engineering/armv8. 3. Write scripts to collect branch cost performance. It will take weeks to get all the benchmark results. 4. Smoke test Linaro toolchain binaries 2012.11 release. 5. Try export crosstool-ng trunk to a bzr project. bzr fast-import always fail on Ubuntu 10.04, but it works on 12.04. 6. RM toolchain related work. Plans: * Collect performance data for branch cost tuning. * Linaro binary toolchain 2012.11 release. * Verify shrink-wrap bugs. Best regards! -Zhenqiang

13 years

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[ACTIVITY] 19-23 November 2012

by Yvan Roux

== Progress == * Infrastructure: - Upgraded my laptop. * Boehm GC AArch64 support: - Added basic aarch64 support to libatomics (by use of GCC's atomics builtins). - Analysed testsuite results and the generated code. - Identified potential builtins' issues. * Some internal support. == Next == * Re-work libatomics support.

13 years

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[ACTIVITY] 19-23 November 2012

by Christophe Lyon

== Progress == * Turn off 64-bits bitops in Neon: initial implementation under benchmarking. Currently it modifies the handling of: add, sub, and, or, xor, shifts, not. In some case the generated code is quite larger, so it will careful benchmarking. * Started looking at "disable peeling" blue-print. Reading GCC source code to get more familiar with that area. * Internal support

13 years, 1 month

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[ACTIVITY] report week 46

by Peter Maydell

* meetings/discussions + upcoming architecture & h/w features + virtio patchset review/discussion + 1-2-1 Matt, Michael + arndale board secondary CPU boot + naming conventions for v8 qemu + v7 KVM blueprint status + posture assessment + KVM call * thinking through possible corner cases for KVM with stage2 faults that don't tell the hypervisor the offending IPA * rebased qemu-linaro on qemu 1.3 rc0 * fixed upstream regression in "-usb" command line KVM blueprint progress tracker: http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr… -- PMM

13 years, 1 month

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[ACTIVITY] 19-23 November 2012

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 30 Nov 2012 aarch64-baremetal-testing 31 Oct 2012 30 Nov 2012 fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Investigate patches for literal pool layout bug * Took longer than expected as the 'simple' fix is wrong due to GCC not knowing how large instructions actually are. * Patch posted upstream * Post triplet backport patches upstream * Other bug issues * Including an issue running SPEC2K on x86 with recent trunk == Next Week == * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * initial-aarch64-backport & aarch64-baremetal-testing * Finish documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years, 1 month

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Shrink-wrap on povray

by Zhenqiang Chen

Hi, I try ARM, MIPS, PowerPC and X86 on povray benchmark. No one can shrink-wrap function Ray_In_Bound. Here is: bool Ray_In_Bound (RAY *Ray, OBJECT *Bounding_Object) { ... for (Bound = Bounding_Object; Bound != NULL; Bound = Bound->Sibling) {...} return (true); } For ARM O2/O3, "Bound" is allocated to "r6" during ira. So there is copy r6 = r1 before testing Bound != NULL The copy (using r6) blocks the shrink-wrap optimization since r6 should be saved. Need enhance shrink-wrap to handle this case. Overall, for povray benchmark, 54 functions are shrink-wrapped for ARM; 59 functions are shrink-wrapped for X86; 25 functions are shrink-wrapped for MIPS; 26 functions are shrink-wrapped for PowerPC. Thanks! -Zhenqiang

13 years, 1 month

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Re: Re: Re: Re: unexpected reloc type 0x03 error with gcc-4.6.4 (2012.10 version)

by Michael Hope

On 15 November 2012 01:58, 남관우 <kw46.nam(a)samsung.com> wrote: > > Hi, > > > > As your guide, i tried to build again. > > > > without : -mapcs -fno-common -fstack-protector --param==ssp=buffer-size=4 > > > and -fPIC instead of -fpic > > > > But it is failed with same the message. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03) > > > > Thank you, > > Kwanwoo Nam. > > > > ------- Original Message ------- > > Sender : 남관우<kw46.nam(a)samsung.com> S4(선임)/선임/SLP개발그룹(무선)/삼성전자 > > Date : 2012-11-14 21:45 (GMT+09:00) > > Title : Re: Re: Re: unexpected reloc type 0x03 error with gcc-4.6.4 (2012.10 version) > > > > Hi, > > > > Here is our LDFLAGS. > > -Wl,--rpath=/usr/lib -Wl,--as-needed > > > > And i try to build with your guide. > > without : -mapcs -fno-common > and -fPIC instead of -fpic > > > > But it is failed with same the message. (/usr/lib/libnfc-common-lib.so.1: unexpected reloc type 0x03) Ta. I'm afraid we don't have enough information to solve this. Could you please send a full build log and we can go from there. gzipped on a public server is best. -- Michael

13 years, 1 month

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[ACTIVITY] 12-16 November

by Matthew Gretton-Dann

== Blueprints == Initial Current Actual initial-aarch64-backport 31 Oct 2012 30 Nov 2012 aarch64-baremetal-testing 31 Oct 2012 30 Nov 2012 fix-gcc-multiarch-testing 31 Dec 2012 31 Dec 2012 backport-fma-intrinsic 31 Dec 2012 31 Dec 2012 fused-multiply-add-support 31 Dec 2012 31 Dec 2012 gcc-investigate-lra-for-arm 31 Dec 2012 31 Dec 2012 == Progress == * Admin * Interviewing * Hand over prep with Michael * Release Week * Made 2012.11 releases of gcc-linaro 4.6 and 4.7. * LEG interations: * Investigated CILK+ and how much work to port to AArch64. * HOT/COLD partitioning * Ran benchmarks on ARM * LRA * Ran x86-64 benchmarks == Next Week == * Investigate patches for literal pool layout bug * Post triplet backport patches upstream * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * initial-aarch64-backport & aarch64-baremetal-testing * Finish documentation * gcc-investigate-lra-for-arm * Analyse benchmarks * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. == Future == * backport-fma-intrinsic & fused-multiply-add-support * Backport patches once fix-gcc-multiarch-testing has been done. -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

13 years, 1 month

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