== Progress ==
* builtin_bswap16:
* Backported missing patch from thunk to Linaro/4.7. One test still
failing in the hard-float + thumb configuration because it forces
armv6 and results in a unsupported configuration: vfp-1 + hard-float.
Resumed discussion about a fix I proposed 3 weeks ago.
* PGO/hot-cold partitioning/Spec2k:
* read doc about spec2k
* started looking at 254.gap causing an ICE.
* started studying qemu traces about 175.vpr crashing when compiled
using profiling info. Cold code returns from a function using a
clobbered lr value.
== Next ==
* builtin_bswap16:
* complete backport to linaro-gcc 4.7.
* PGO/hot-cold partitioning/Spec2k:
* investigate compiler crash and runtime failures.
== Progress ==
* Deputising for Michael
* 4.6 and 4.7 2012.10 releases
* Included extra AArch64 merge into gcc-lianro/4.7
* AArch64 support
* Did another merge
* Starting another one.
* HOT/COLD partitioning for PGO
* PINGed If/Then/Else block conversion patch
* Started reworking postreload-gcse.c patch
* Ran into issues with vanilla gcc-linaro/4.7 not being able to
build for 'arm-none-linux-gnueabihf' without some configury magic
* Admin
* Interviewing
== Next Week ==
* Do another AArch64 merge.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Hi Guys,
I just found an issue in kernel code and thought we must have a
compilation warning for such cases.
Submitted a bug here:
https://bugs.launchpad.net/gcc-linaro/+bug/1064218
Problem description:
-------------------------
When we have following declaration:
struct foo {
char array[5];
....
};
And have a definition like:
struct foo foo_abc = {
.array = "12345",
};
Problem here is: size of array is 5 bytes and so we can actually add a
string with four characters only to it, as '\0' will take
an additional space.
But with my definition of foo_abc.. i had 5 characters + '\0'... that
will make it 6 and that will overflow the array..
What will actually happen here?
- compiler will not add '\0' at all?
-or it will go outside of boundaries of array?
--
viresh
On 5 October 2012 12:10, Rob Herring <robherring2(a)gmail.com> wrote:
> I've been scratching my head with a "scheduling while atomic" bug I
> started seeing on 3.6. I can easily reproduce this problem when doing a
> wget on my system. It ultimately seems to be a combination of factors.
> The "scheduling while atomic" bug is triggered in do_alignment which
> gets triggered by this code in net/ipv4/af_inet.c, line 1356:
>
> id = ntohl(*(__be32 *)&iph->id);
> flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id ^ IP_DF));
> id >>= 16;
>
> This code compiles into this using "gcc version 4.6.3 (Ubuntu/Linaro
> 4.6.3-1ubuntu5)":
>
> c02ac020: e8920840 ldm r2, {r6, fp}
> c02ac024: e6bfbf3b rev fp, fp
> c02ac028: e6bf6f36 rev r6, r6
> c02ac02c: e22bc901 eor ip, fp, #16384 ; 0x4000
> c02ac030: e0266008 eor r6, r6, r8
> c02ac034: e18c6006 orr r6, ip, r6
>
> which generates alignment faults on the ldm. These are silent until this
> commit is applied:
Hi Rob. I assume that iph is something like:
struct foo {
u32 x;
char id[8];
};
struct foo *iph;
GCC merged the two adjacent loads of x and id into one ldm. This is
an ARM specific optimisation done in load_multiple_sequence() and
enabled with -fpeephole2.
I think the assembly is correct - GCC knows that iph is aligned and
knows the offsets of both x and id. Happy to be corrected if I'm
wrong, but I think the assembly is valid given the C code.
-- Michael
== Progress ==
* builtin_bswap16:
* backporting of builtin_bswap16 for ARM to Linaro/4.7: one of the
tests fails. Waiting for Ramana's return to see if he can help me
identify the patch needed from trunk.
* Useless zero extensions: despite Ulrich support I didn't succeed
to rewrite the bswap16 pattern in a way that would avoid
generating useless zero extension. Asking for help on gcc list
shows that it would actually need a complete new optimization
pass, which has already been discussed several times.
* PGO/hot-cold partitioning/Spec2k:
* looking at spec2k build & run system
* Branch reviews: approved Matt's october merges for Linaro-gcc 4.6 and 4.7.
Briefly looked at aarch64-4.7 merge request.
== Next ==
* builtin_bswap16:
* try to complete backport to linaro-gcc 4.7.
* PGO/hot-cold partitioning/Spec2k:
* investigate compiler crash and runtime failures.
* setup Snowball
== Progress ==
* Started Linaro ramp up process.
* Started to look at Crosstool-ng and CBuild
* Fighting against proxy and bazaar configuration
== Next Week ==
* Continue the started tasks.
== Progress ==
* 4.6 and 4.7 start of month merges
* Fixed missing binary files issues whilst doing this.
* 4.7 AArch64 merge into gcc-linaro/4.7
* Completed initial merge
* Admin
* Interviewing
== Next Week ==
* Deputise for Michael
* Do GCC-Linaro releases
* Fix up any issues with aarch64 merge.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Adding linaro-toolchain
On Tue, Oct 02, 2012, Khem Raj wrote:
> On Tue, Oct 2, 2012 at 4:59 PM, Tim Bird <tim.bird(a)am.sony.com> wrote:
> > When I try to build the Linux kernel version 3.6 with the gcc-4.7
> > nightly build Linaro toolchains,
>
> linaro binutils needs to back port
>
> http://sourceware.org/git/?p=binutils.git;a=commit;h=3fd1fadc205bc69410080a…
>
> >
> > $ arm-eabi-gcc --version
> > arm-eabi-gcc (Linaro GCC 4.7-2012.09-1~dev) 4.7.2 20120910 (prerelease)
> > $ arm-eabi-as --version
> > GNU assembler (Linux/GNU Binutils) 2.23.51.0.3.20120918
> >
> > I get a compiler error (actually, assembler error):
> >
> > AS arch/arm/lib/copy_from_user.o
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S: Assembler messages:
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r3,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:100: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:118: Error: selected processor does not support ARM mode `ldralt r3,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:119: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:120: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:121: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:122: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:123: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:124: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:173: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:243: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:245: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r4,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r5,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r6,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r7,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r8,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt r9,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt ip,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > /a/home/tbird/work/auto-reduce/lto-test/linux-3/arch/arm/lib/copy_template.S:247: Error: selected processor does not support ARM mode `ldralt lr,[r1],#4'
> > make[2]: *** [arch/arm/lib/copy_from_user.o] Error 1
> > make[1]: *** [arch/arm/lib] Error 2
> > make[1]: *** Waiting for unfinished jobs....
> >
> >
> > This appears to be related to the following bug report for binutils:
> > http://sourceware.org/ml/binutils/2012-09/msg00128.html
> >
> > I'm compiling the kernel for PandaBoard
> >
> > Any ideas for work-arounds or fixes for this? Note that the ldralt instruction
> > doesn't actually appear in copy_template.S (maybe it's coming from a macro?)
> > -- Tim
> >
> > =============================
> > Tim Bird
> > Architecture Group Chair, CE Workgroup of the Linux Foundation
> > Senior Staff Engineer, Sony Network Entertainment
> > =============================
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev(a)lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev
--
Loïc Minier
== GCC ==
* Implemented patch to prevent lower-subreg pass from splitting
pseudo register moves during first pass. Committed to mainline.
* Updated patch to perform 64-bit integer shifts in NEON registers
to avoid NEON single to NEON double register hazard. Re-started
testing via Launchpad branch neon-shifts-4.7-v3.
* Rebased patch to improve 32-to-64-bit extended from core into
NEON registers, added backport of lower-subreg mainline fix.
New Launchpad branch neon-extendsidi-4.7-v3.
* Tested reload patch to fix aarch64 find_reloads_subreg_address
bug on multiple platforms to prepare for mainline.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
== Progress ==
* builtin_bswap16:
* patch to catch (x<<8)|<x>>8) committed upstream after confirmation
it was OK by PowerPC guys.
* backporting of builtin_bswap16 for ARM to Linaro/4.7: one of the
tests fails. Trying to isolate the trunk change that would make is
pass.
* useful discussions with Ulrich to investigate if we could avoid
generating useless zero-extensions after rev16. I still need to
experiment.
* PGO/hot-cold partitioning:
* applied info from Matt, I have now a usable Spec2000 setup based
on qemu.
== Next ==
* builtin_bswap16:
* try to avoid useless zero-extensions.
* PGO/hot-cold partitioning:
* investigate runtime failures.
* run on a Snowball board.
== Progress ==
* 4.7 AArch64 merge into gcc-linaro/4.7
* Got Foundation model working
* Ran testsuite - results OK - some obvious infrastructure issues though
* Hot/Cold partitioning in PGO:
* Posted second patch upstream
* Had basic flaw with it pointed out (shame was the flaw fixed the issue)
* Admin
* Interviewing
== Next Week ==
* Start of month branch merges.
* HOT/COLD partitioning for PGO:
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* ARM/aarch64-4.7-branch merge into gcc-linaro/4.7.
* Investigate failure in testsuite run
* Check that I am merging the svn branches correctly.
* Participate in sprint
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
(two week rollup report since week 38 was a short week for me)
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== other ==
* looked briefly at the result of running the clang static analyzer
over QEMU
* wrote some fixes to totally broken code in the ds1338 model as
result
* reviewed some nice TCG optimisation patches from Aurelien which bump
up performance for ARM guests by 10-15%
* reviewed, bugfixed and committed some patches for the bootwrapper
from Dave Martin
* removed obsolete SMC API support from bootwrapper (lets us knock
the final item off a blueprint)
* implemented the new movcond TCG IR insn in the ARM backend
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
-- PMM
Summary:
* Validate and release Linaro binary toolchain 2012.09
* Identify the root cause of dwarf check fail in native build when
enabling shrink-wrap.
Details:
1. Validate and release Linaro binary toolchain 2012.09.
2. Analyze the dwarf check fail in native build when enabling shrink-wrap:
* Root cause: tail calls from simple-return path and normal return
path are optimized as one common tail call.
* To fix it, use simple-return to indicate the one from simple-return
path, which will block the optimization to mix them.
Plans:
* Test shrink-wrap performance.
Planed leaves:
* Sept. 30 - Oct. 7: Mid-Autumn Festival and National Day of China's holiday.
Best regards!
-Zhenqiang
Hi,
I am using Linaro Toolchain for compiling UEFI and I am getting alignment
fault as exception while running UEFI on Origen Board.
When I was using other cross compilers the issue was not there.
The crash report is as follows:
Data Abort Exception PC at 0x4F84DCDC CPSR 0x60000133 nZCveAifT_svc
/home/shiva/workspace/armserver/uefi_origen/edk2/Build/OrigenBoard-Exynos/DEBUG_ARMLINUXGCC/ARM/FatPkg/EnhancedFatDxe/Fat/DEBUG/Fat.dll
loaded at 0x4F84D000 (PE/COFF offset) 0xCDC (ELF or Mach-O offset) 0xA9C
0xF8BD6037 LDRH r6, [sp, #0x37]
R0 0x0000000B R1 0x0000000A R2 0x4FCEEAD8 R3 0x80000000
R4 0x4F836010 R5 0x4F863619 R6 0x00000000 R7 0x4F837F10
R8 0xFFFFFFFF R9 0x00000000 R10 0x00000001 R11 0x00000000
R12 0x00000000 SP 0x4FCEEA20 LR 0x4F84DCDD PC 0x4F84DCDC
DFSR 0x00000001 DFAR 0x4FCEEB17 IFSR 0x0000140B IFAR 0x00910883
Alignment fault: read from 0x4FCEEB17
Instruction Domain fault on Page at 0x00910883
ASSERT
/home/shiva/workspace/armserver/uefi_origen/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c(304):
((BOOLEAN)(0==1))
--
Thanks and Regards,
Shiva.
Interested in working with us on improving the performance of Linux on
ARM? We’re looking for motivated engineers to work in our toolchain
team on compiler technology, developer tools, and low level
performance libraries. You will use your specialised knowledge to work
in the open, work upstream, and make ARM flavoured improvements to a
range of tools that are fundamental to making the latest mobile and
server products.
We’re currently looking for:
* GCC developers
* Developer tools engineers, especially on the GNU tools like binutils and GDB
* ARM performance engineers, to work on a range of low level libraries
We’re a distributed team. Working from the home office is an option.
Please see the careers page on our website for more information and
how to contact us.
-- Michael
== GCC ==
* Committed patch to use vld1.64/vst1.64 instead of vldm/vstm
to GCC mainline and Linaro GCC 4.7
* Committed patch to use vld1/vst1 to implement vec_set/vec_extract
to GCC mainline and Linaro GCC 4.7
* Posted patch to perform 64-bit integer shifts in NEON registers
for mainline inclusion. Started to address review comments.
* Rebased patch to improve 32-to-64-bit extends from core
into NEON registers; ran into lower-subreg regression.
* Worked on implementing fix for lower-subreg regression.
* Handed over (Richard's) auto-inc-dec patches to Matt.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The Linaro Toolchain Working Group is pleased to announce the 2012.09
release of the Linaro Toolchain Binaries, a pre-built version of
Linaro GCC and Linaro GDB that runs on generic Linux or Windows and
targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.7 2012.09
* Linaro GDB 7.5 2012.09
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
Interesting changes include:
* gdbserver is stripped.
* gdbtui is replaced by "gdb --tui"
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on
x86_64 hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2012.09
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Summary
* Prepare Linaro binary toolchain 2012.09 release
* Fix lp:1036170/pr50970
Details:
1. Prepare Linaro binary toolchain 2012.09 release
* Update linaro gcc and gdb to 2012.09 release
* Workaround gdb lsb build issue.
* Strip gdbserver.
* Smoke tests.
2. Merge shrink-wrap patch to lp:gcc for cbuild test. But dwarf checks
fail when building fortan related codes at stage 2.
3. Identify the root cause of lp:1036170/pr50970 and work out a patch to fix it.
Plans:
* Linaro binary toolchain 2012.09 release.
* Fix shrink-wrap build fail issues.
Planed leaves:
* Sept. 30 - Oct. 7: Mid-Autumn Festival and National Day of China's holiday.
Best regards!
-Zhenqiang
== Progress ==
* Discussed big-endian patches for vext tests: careful review of the
specification is required and this patch might actually expose GCC
bugs in big-endian/Neon.
* builtin_bswap16:
* Posted 2 implementations of the generic patch for
(x<<8)|(x>>8). The 2nd one looks OK, but I was asked to make some
checks on powerPC, which are on-going.
* backporting it to Linaro/4.7. On-going: merged obvious patches but
one test does not produce the same code as on trunk.
* validations in cbuild in with GCC configured for thumb and hard FP
showed that some bswap16 tests fail because they force armv6,
which leads to unsupported thumb1 configuration. Proposed
testsuite modification to make this easier, under discussion with
Matt & Richard.
== Next ==
* builtin_bswap16:
* check powerPC results and have the patch accepted upstream.
* measure probable regression in libav when using the builtin
instead of an asm().
* complete backport in Linaro/4.7.
* PGO/hot-cold partitioning: start working on this blueprint.
== Progress ==
* Fixed
https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/1029454
* After investigating further found that this was actually an issue
already fixed in FSF upstream
* 4.7 AArch64 merge into gcc-linaro/4.7
* Did an initial merge of upstream ARM/aarch64-4.7-branch into gcc-linaro/4.7
* So far it hasn't broken other platforms
* Investigated getting FastModels working for me
* Hot/Cold partitioning in PGO:
* Tidied up current patches ready for reposting upstream
* Handed current status to Christophe
== Next Week ==
* HOT/COLD partitioning for PGO:
* Complete hand-over to Christophe
* Get two current patches accepted upstream
* Post question upstream about register allocation 'mistakes' I am seeing
* ARM/aarch64-4.7-branch merge into gcc-linaro/4.7.
* Get a test run of aarch64 targetted compiler complete
* Confirm no code generation changes for other back-ends
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
* Admin
* Several interviews
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
Current Milestones:
|| || Planned || Estimate || Actual ||
|| clean up kvm-qemu cp i/f || 2012-09-20 || 2012-09-20 || ||
|| fake-trustzone || 2012-10-15 || 2012-10-15 || ||
Also planned: general keeping up with kernel changes; upstream patch
review; qemu-linaro releases. May change dates to align with overall
KVM plan for the quarter when that is finalised.
Previous Milestones:
||cp15-rework || 2012-01-06 || 2012-06-23 || 2012-06-24 ||
||a15-lpae-support || 2012-07-13 || 2012-07-20 || 2012-07-20 ||
== track-kvm-abi-changes ==
* folded in Christoffer's interrupt ABI changes
* updated to new ONE_REG ABI for register accesses
* QEMU now in sync with the kernel patchset Christoffer has just sent to alkml
== other ==
* qemu-linaro 2012.09 released
* various meetings/status calls
KVM blueprint progress tracker:
http://ex.seabright.co.nz/helpers/backlog?group_by=topic&colour_by=state&pr…
Summary
* Workaround the unwind issue for shrink-wrap
* Verify Linaro tickets.
Details:
1. Debugging the failed cases for shrink-wrap. To workaround the
unwind issue, update arm_expand_epilogue to generate return not
simple_return when sp is changed.
2. Setup Linaro toolchain and verify 8 tickets:
*Linaro gcc:
lp:1036170: Function pointer dereferenced twice. It is ARM special bug
which is confirmed in 4.6, 4.7 and FSF trunk only on ARM.
lp:1048709: wrong assembler, out of range vldr instruction. Confirmed
in Linaro 4.6. Can not reproduce it in 4.7 or FSF 4.6.
lp:1014658: It is c++11 related issue in 4.6.
lp:944572: It is a gcc general issue.
lp:972503 and lp:1039401 can not be reproduced.
* Linaro binary toolchain:
lp:1046718: confirmed and fixed it.
lP:1049498: invalid
Plans:
* Prepare Linaro binary toolchain 2012.09 release.
* Performance test for shrink-wrap.
* Follow-up the tickets.
Best regards!
-Zhenqiang
== Progress ==
* Committed patch to fix 3 testcases in big-endian after upstream comments.
* Updated patch to make vext tests support big-endian after upstream comments.
* builtin_bswap16:
* Committed implementation for ARM.
* Investigating testsuite regressions caused by my patch to catch
(x<<8)|(x>>8)
== Next ==
* Continue with bswap16 support.
== Progress ==
* Started looking at
https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/1029454
* Confirmed the failure
* Unfortunately the git bisect I thought would find the fix didn't
* Hot/Cold partitioning in PGO:
* Some further investigations
* Talked to Uli about one failure - he gave me some further pointers
* Admin
* Some interviewing
== Next Week ==
* Continue looking at 1029454: cselim tree optimizer generates incorrect code
* Start looking at merging the ARM public 4.7 GCC branch into gcc-linaro/4.7
* Hot/Cold Partitioning:
* Investigate remaining silent code-gen faults and non-termination
issue in SPEC
* If failures are fixed start profiledbootstraps and tests on the
central boards.
* symbol_ref splitting
* Test code alignment hypothesis
* Test v2 patch.
== Future ==
* Look at Cards for Vectorization, PGO and LTO with Michael.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann(a)linaro.org
== GDB ==
* Created and published Linaro GDB 7.5 release.
== GCC ==
* Posted patch to use vld1.64/vst1.64 instead of vldm/vstm
for mainline inclusion.
* Posted patch to use vld1/vst1 to implement vec_set/vec_extract
with scalar operand residing in memory.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
