- linaro-toolchain - lists.linaro.org

by Christopher Covington

Hi, It seems to me that your current toolchain releases [1] don't default to a multiarch layout. Am I looking in the right place? Do you anticipate enabling multiarch in the future? Is doing this currently blocked by limitations in tools such as crosstool-ng? 1. http://releases.linaro.org/13.01/components/toolchain/binaries Thanks, Christopher -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation

13 years, 8 months

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AArch64 built by default in LLVM

by Renato Golin

As of revision 174322, AArch64 back-end is compiled by default on all architectures. This means it'll be built and tested on all platforms and it'll get heavy bombardment of the changes in the front- and middle-end without breaking for too long. Thanks Tim for the hard work! cheers, --renato

13 years, 8 months

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[ACTIVITY] 28 January - 1 February 2013

by Yvan Roux

== Progress == * Boehm GC AArch64 support: - Added information to the libatomic_ops patch, stiil under review - backported AArch64 support to the GCC boehm-gc, test on-going * Libunwind AArch64 support: - started. * Aarch64 porting meeting: - request to move to eglibc 2.17 (done by Zhenqiang) * LCA13: - hotel and plane booked == Next == * Validate boehm-gc GCC integration * Libunwind AArch64 support

13 years, 8 months

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[ACTIVITY] 28th Jan 2013 - 1st Feb 2013

by Omair Javaid

== This Week === * Joined Linaro, had welcome meeting with Matt * Set up my office at home * Laptop purchased and had it ready for development * Exchanged emails with various people for getting started and read a lot of administrative material on the wiki pages. * Registered for the connect, figured out visa process and sent request to Arwen for required documents. * Attended Weekly toolchain call, stand-up call and 1:1 with Matt. * Started work on GDB Testing in various configurations for analysis of current GDB status on ARM. * Build GDB on x86_64 machine and had test suite run in local and remote configuration. * Suffered from a bad run of cough n fever. == Next week == * Continue with Analysis of GDB status on ARM, hopefully get to access a pandaboard remotely and setup QEMU as well. * Apply for Hong Kong Visa for the connect. * Visit local market to resolve pending office setup and hardware requirements. * More Wiki reading and getting to know different processes at Linaro. * 5th February public holiday in Pakistan.

13 years, 8 months

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[Activity] Week 05

by Zhenqiang Chen

Summary: * Linaro toolchain binary 2013.01 release * Move to using EGLIBC 2.17 in aarch64 build Details: 1. Linaro toolchain binary. * Document on how to do release test. * Help Bero on 2013.01 release. * Investigate lp:1107659. Crosstool-ng upstream has a workaround fix. 2. Move to using EGLIBC 2.17 in aarch64 build. * Update Linux version to 3.7.0 since eglibc 2.17 configure "checking for kernel header at least 3.7.0". * Migrate local patches for eglibc 2.16 to 2.17 and update the config to 2.17 * Package build is OK. Test on simulation is ongoing. 3. Collect SPEC performance for different branch costs. * The total results wave less than 0.5%. * Three cases have 1-2% regression for smaller branch cost. Will analyze the detail impact for the three cases. Plan: * Investigate coremark performance impact for different branch costs. * Commit EGLIBC 2.17 changes Planed leaves: * Feb. 9 - 15: Chinese Spring Festival. Best Regards! -Zhenqiang

13 years, 8 months

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[ACTIVITY] 28 January - 1 February 2013

by Venkataramanan Kumar

== Progress == * Backport Tested and backported patch written to CSE optmize compares. http://gcc.gnu.org/ml/gcc-patches/2013-02/msg00015.html Ran GCC regression suite with ARMV8 foundation model for aarch64-none-elf * Implementing GC sections support in bintuils Had a quick look at changes need to be added. Reading about relocations that needed to considered for elf_backend_gc_sweep_hook * Tried using Cbuild for buildign and testing gcc4.7 aarch64 branch. ssh keys are not in sync. I am getting permission denied. Cheking with David and Andy in valdation team. Misc * Attend tool chain weekly meet, and stand up call * Attend usual AMD meetings * Performed one x86_64 AMD task * Booked tickets, hotel and got invite letter for Linaro connect. == Next week == * Complete Cbuild experiments to test gcc svn aarch64 4.7 branch. * Continue gc section support. Implement elf_backend_gc_sweep_hook

13 years, 8 months

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[ACTIVITY] 28 January - 1 February 2013

by Christophe Lyon

== Progress == * 64-bits ops in Neon: No news from upstream. * vectorizer cost model: added possibility to tune the problem by processor type. * smin-umin: regression actually caused by a previous patch brought when merging bswap16 support. Investigation on-going. * managed to run spec2k on local board. Need to upload tools compiled for hf platform. * tcpanda heat problems: GCC testsuite passed. * hot-cold partitioning: posted a follow-up to google patches on gcc-patches. * looked at some codecs needing improvements (Neon intrinsics usage) * feedback on lava/cbuild integration * hotel/plane booked for Connect. == Next == * handle 64-bits bitops in Neon feedback from upstream if any * smin-umin: check bench results with probable culprit patch reverted. Will need investigation on trunk too. * vectorizer cost model: check bench results * get more codecs sample codes.

13 years, 8 months

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[ACTIVITY] report week 5

by Peter Maydell

Activity: * calls and meetings * last bits and pieces of ARM QEMU patches sent prior to upstream 1.4 hardfreeze * continuing fixes for running a 3.8-rc4 vexpress kernel on QEMU: * refactored the way we handle SYS_CFG vexpress registers so it's possible to reasonably add support for more of them * put together a basic implementation of the various regs we're missing (oscillator, voltage, and some misc) * ideally this would be done via variable-length qdev array properties; started looking at how hard those would be to implement * investigated linux-user bug where an edge case in use of get_user_u32() had accidentally been broken; sent patch * all travel/hotels now booked for Connect -- PMM

13 years, 8 months

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[ACTIVITY] 31 Jan - 1 Feb

by Matthew Gretton-Dann

== Progress == * Welcomed Omair to the team working on GDB * Starting investigating cortex-a9 bootstrap failure * Blueprints updating * Preparing for two new starters next week == Next week == * Welcome two new members to the team. * Finish cortex-a9 bootstrapping investigations == Future == * Run HOT/COLD partitioning benchmarks * Analyse ARM results * On x86_64 to see what the actual benefit we could get * fix-gcc-multiarch-testing * Come up with strawman proposal for updating testsuite to handle testing with varying command-line options. -- Matthew Gretton-Dann Toolchain Working Group, Linaro

13 years, 8 months

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[ACTIVITY] 28-31 Jan

by Renato Golin

== Progress == * Maintenance - Fixing ARM buildbots, poking people to fix bugs, keeping them green - http://llvm.org/viewvc/llvm-project?view=rev&revision=173510 * Cost Model - Fixing some bugs on the generic code - http://llvm.org/viewvc/llvm-project?view=rev&revision=173691 - Adding some simple free cast (plus some infrastructure) - http://llvm.org/viewvc/llvm-project?view=rev&revision=173849 * LLVM - Investigating APFloat issue on Chromebook (bad libraries?) - Clang miscompiles and show same synthoms, will play with options next week - AArch64 back-end in, to be built by default * LAVA - Got three last errors due to include path ('bits/predefs.h' file not found) - libc6-dev + libstdc++-dev have no effect, problem doesn't show on buildbots - Testing heating problem with multiple images (only 12.02 is good) - Testing other boards, other images (with Dave) * Friday Holiday == Plan == * Try a bit more on the APFloat issue in Chromebook, but I think that's just bad distro (ChrUbuntu), since no one else has this problem. Has anyone put any Linaro image on a Chromebook? * Continue working on getting faster builds on LAVA (quad-core origen, Arndale, etc) with Dave Pigot. * Continue micro-benchmarking the vectorization and updating the cost-model. Start discussing the side-effects that are not modelled at all.

13 years, 8 months

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[ANNOUNCE] Linaro Toolchain Binaries 2013.01 released

by Bernhard Rosenkränzer

The Linaro Toolchain Working Group and Platform Team are pleased to announce the 2013.01 release of the Linaro Toolchain Binaries, a pre-built version of Linaro GCC and Linaro GDB that runs on generic Linux or Windows and targets the glibc Linaro Evaluation Build. Uses include: * Cross compiling ARM applications from your laptop * Remote debugging * Build the Linux kernel for your board What's included: * Linaro GCC 4.7 2013.01 * Linaro GDB 7.5 2012.12 * A statically linked gdbserver * A system root * Manuals under share/doc/ The system root contains the basic header files and libraries to link your programs against. The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian 6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation 5.7 and later, and should run on any Linux Standard Base 3.0 compatible distribution. Please see the README about running on x86_64 hosts. The Windows version is supported on Windows XP Pro SP3, Windows Vista Business SP2, and Windows 7 Pro SP1. The binaries and build scripts are available from: https://launchpad.net/linaro-toolchain-binaries/trunk/2013.01 Need help? Ask a question on https://ask.linaro.org/ Already on Launchpad? Submit a bug at https://bugs.launchpad.net/linaro-toolchain-binaries On IRC? See us on #linaro on Freenode. Other ways that you can contact us or get involved are listed at https://wiki.linaro.org/GettingInvolved.

13 years, 8 months

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Newbie question

by Kalai Narayanan-SSI

Hi, I have a few armv7 assembly tests. I'm trying to compile these using the linaro aarch64 toolchain and I'm getting errors. Is there any specific flag that I have to pass to enable backward compatibility to allow v7 assembly to be compiled for a v8 model? reset.s: Assembler messages: reset.s:32: Error: operand 1 should be an integer register -- `mov r0,#0' reset.s:33: Error: unknown mnemonic `mcr' -- `mcr p15,0,R0,C13,c0,1' reset.s:36: Error: unknown mnemonic `mrc' -- `mrc p15,0,r0,c1,c0,0' reset.s:40: Error: operand 1 should be a SIMD vector register -- `orr r0,r0,#0x00001000' .... Relevant assembly code: .... _reset: // init Context ID Register MOV r0, #0 MCR p15, 0, R0, C13, c0, 1 // Enable Instruction cache mrc p15, 0, r0, c1, c0, 0 /* set bits: 12 = I i-cache */ orr r0, r0, #0x00001000 mcr p15, 0, r0, c1, c0, 0 ..... This is my assembler command: aarch64-linux-gnu-as -march=armv8-a+fp --keep-locals -o "reset.o" "reset.s" Thanks, Kalai

13 years, 8 months

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[ACTIVITY] 21-25 January 2013

by Christophe Lyon

== Progress == * 64-bits ops in Neon: waiting for upstream. * vectorizer cost model: initial activation with unaligned load/store cost equal to aligned ones; benchmarking shows no significant difference. * smin-umin: a few benchmarks show a few unexpected regressions (10-15%). * setting up spec2k on local board * tcpanda heat problems: GCC built OK. Don't know how hot it became. == Next == * handle 64-bits bitops in Neon feedback from upstream if any. * analyze regressions in smin-umin * check if more tuning of the vectorizer cost model is desirable. * finish local board setup * tcpanda: run gcc testsuite to check heat

13 years, 8 months

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[ACTIVITY] 21-25 January 2013

by Yvan Roux

== Progress == * Boehm GC AArch64 support: - Tested on Foundation model - Patches sent to mailing list - Boehm GC has been accepted and merged into mainline - Libatomic_ops under review, some improvements are needed. == Next == * Boehm GC AArch64 support: - Fix libatomic_ops for mainline merge * Start gc sections support for AArch64 binutils * Review roster

13 years, 8 months

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[Activity] Week 04

by Zhenqiang Chen

Summary: * Investigate Automotive benchmark performance on different branch cost. Details: 1. Automotive benchmark performance analysis for different branch cost on Pardaboard ES. * Design small test cases to simulate bitmnp01 to compare the performance between ITTT and conditional branch. Test results show - If branch prediction does not work (put the codes in a function), ITTT is always better than conditional branch. - If branch prediction works (inline the codes t in the loop body), for most cases, conditional branch is better than ITTT. * Code alignment has big impact for tblook01. By default IT block has better performance. When adding __attribute__((aligned (16))) for function t_run_test, performance of conditional branch is better than IT block. 2. Prepare Linaro toolchain binary release. * Update Linaro crosstool-ng local patches due to the fix of lp:1067766 in source package. * Spawn all builds and smoke tests. Plan: * Investigate SPEC2k performance for different branch costs. * Work with Bero for 2013.01 toolchain binary release . Planed leaves: * Feb. 9 - 15: Chinese Spring Festival. Best Regards! -Zhenqiang

13 years, 8 months

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[ACTIVITY] 21-25 Jan

by Renato Golin

== Progress == * Buildbot - Taking buildbot to Linaro - Had wireless/GPU overheating, disabled kernel modules - Running smooth again (most of the time) - Debugging errors that only appear on ARM. * Building and Testing LLVM - Compiling on Intel with only the ARM backend helps a lot - Sent a call for Action to people clean up cross-compilation failures * LAVA - Progress on LAVA LLVM job - Got it checking out, configuring and building - Got PASS/FAIL/SKIP patterns working - https://validation.linaro.org/lava-server/scheduler/job/46027 - Need to get a patch from a specific place to apply * Cost Model - Re-wrote table lookup patch a few times, finally in for good - http://llvm.org/viewvc/llvm-project?rev=173382&view=rev - Studying costs of instructions, all seem good enough - Better approach now is to change the target description (less code, more gain) * EuroLLVM - 136 people so far == Plan == * Test distcc (or similar) on Pandas * Get a buildbot running with cross-compilation * Internal git repository for LAVA LLVM job * Confirm Linaro's sponsorship for EuroLLVM * Continue cost model changes in between == Background == * Monitor list for ARM changes * Monitor buildbot for failures

13 years, 8 months

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[ACTIVITY] report week 04

by Peter Maydell

Activity: * calls and meetings (about 20% of my working week this week ;-)) * finished rebasing and testing the KVM QEMU patches (thanks to Pawel for getting me an updated RTSM device tree), sent out updated version to go with -v17 kernel * minor qemu maintenance patches (including a minor cfi01 flash model bugfix) * trying to track down issues running a 3.8-rc4 vexpress kernel on QEMU. Among other things: * looks like we need to emulate some more of the oscillator and voltage config registers now (if only to make the kernel a bit quieter) * the kernel doesn't like the way qemu's boot loader puts the DTB blob after the initrd but beginning in the same page as the initrd ends [free_initrd_mem will trash memory outside the initrd proper but inside that last page] * a15 reports the wrong board model number -- PMM

13 years, 8 months

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AArch64 cross compile

by naveen yadav

Dear All, Is it possible to compile ARCH "AArch64 " for 32 mode, like if I have x86 64 bit machine and I install 32 bit OS on it, and machine is compatible with 32 bit binary. So is it possible to use AARCH64 (Cortex-V8) with installation of kernel 32 bit and use 32 bit tool chain. If answer is yes, can I build tool chain or is there option available in linaro cross-compile available from https://launchpad.net/linaro-toolchain-binaries/+milestone/2012.12 Thanks

13 years, 8 months

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[ACTIVITY] report week 03

by Peter Maydell

Activity: * usual set of calls and meetings (and there is another KVM related weekly meeting in the pipeline...) * reviewed virtio patches * rebased qemu-linaro on upstream * rebased KVM patches; couldn't get updated kernel to run on RTSM (probably a device tree or config issue; need to attack problem again this week) NB: I'm currently working a reduced set of hours due to RSI, though I am trying to remain responsive to email etc. -- PMM

13 years, 8 months

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[ACTIVITY] 14-18 January 2013

by Yvan Roux

== Progress == * Prepared Venkat on-boarding. * Aarch64 porting meeting: - libunwind is in the pipe * Boehm GC AArch64 support: - basic port done, test on-going == Next == * Boehm GC AArch64 support: - test and ask for up stream review.

13 years, 8 months

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[Activity] Week 03

by Zhenqiang Chen

Summary: * Investigate automotive benchmark. * Linaro gcc 4.6 release Details: 1. Automotive benchmark performance analysis for different branch cost for Cortex-A9. * Debug function WriteOut, which is called 12 times on average, leads common performance issue since the IF-THEN in the function is converted to IT block, which TRUE probability is less than 4%. * Identify the root cause of performance regression with IT block for bitmnp01, rspeed01, pntrch01 and ttsprk01. Overall, - The performance of a taken bpl is better than an ITTT. If this is a common sense, for IF-THEN, we'd set branch-cost to 1. - For IF-THEN-ELSE, we'd take branch probability into account when converting it to IT block. - ifcvt might generate useless IT block. 2. Try to do Linaro GCC release. But meet several issues: * Can not branch a clean lp:gcc-linaro/4.7. As a workaround, I had downloaded a clean bzr tree from other site. For next release, I can use the local tree to create the release tarball. * All a9hf-builder ubutests fail due to test environment issue. Plan: * Investigate more benchmarks for different branch costs. Planed leaves: * Feb. 9 - 15: Chinese Spring Festival. Best Regards! -Zhenqiang

13 years, 8 months

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[ACTIVITY] 14-18 January 2013

by Christophe Lyon

== Progress == * 64-bits ops in Neon: pinged patch proposal. * vectorizer cost model: received results from spec2k. Prepared initial tuning to submit to benchmarking again. * smin-umin: tests OK, benchmarks ran, but did not generate the diff over a valid ancestor. I didn't make the manual comparison yet. * updated board for local benchmarking * tcpanda heat problems: built a new kernel with the thermal driver; need to reboot the board with it == Next == * handle 64-bits bitops in Neon feedback from upstream if any * analyze results of benchmarking with vectorizer cost model * analyze results of benchmarking with smin-umin idiom patch * continue board setup/update; I will probably try to cross-build the benchmarks to avoid having the build GCC itself on the board and save time. * followup on tcpanda heat problems

13 years, 8 months

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[ACTIVITY] 14-18 Jan

by Renato Golin Linaro

== Progress == * Buildbots - Added a Panda ES buildbot on clang-native-arm-cortex-a9 group - Reporting and helping fix bot bugs on ARM - ARM buildbots are green again! - Each ARM buildbot takes 4h15min to complete, versus 15min on Intel - We're still testing up to 12-15 patches on each build, on peak times (PST) * LAVA - Created a test run for llvm check-all, infrastructure is there - Need to make it actually do some work * Vectorization - Refactored cost model's temp tables - http://llvm.org/viewvc/llvm-project?view=rev&revision=172658 - Studying NEON costs, changing ARM target lowering * test-suite A15 - Building LLVM on Chromebook, check-all (1h, 181 failures) - Self-hosting LLVM on Chromebook, check-all (50min, many more) - Found some floating point type errors, only on Chromebook (libs?) * AArch64 back-end - Reviewed patches, look ok, some comments - Should be all in by next week * LLVM cross-compilation woes - Had to define include path for c, c++ and arm locations - It calls the wrong assembler, even defining the right gnu toolchain - Someone needs to fix these cross-compilation bugs!! :) == Plan == * Finish basic NEON costs for vectorization * Finish LAVA bot compiling clang + check-all * Install Panda buildbot on rack * Continue investigating Chromebook failures * Continue thinking about the long term plan for LLVM

13 years, 8 months

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[ANNOUNCE] Linaro GCC 4.7 and 4.6 2013.01 released

by Zhenqiang Chen

The Linaro Toolchain Working Group is pleased to announce the 2013.01 release of both Linaro GCC 4.7 and Linaro GCC 4.6. Linaro GCC 4.7 2013.01 is the tenth release in the 4.7 series. Based off the latest GCC 4.7.2+svn194772 release, it includes ARM-focused performance improvements and bug fixes. Interesting changes include: * Updates to GCC 4.7.2+svn194772 * Includes arm/aarch64-4.7-branch up to svn revision 194808 * Support for the rev16 and revsh instructions * A15 Neon pipeline backported from trunk * FMA intrinsic backported from trunk * Better extending core to NEON transfers * Fused multiply-add support Fixes: * LP #1088898 regression of x86 gcc bootstrap with Linaro sourcebase * LP #1067766 Backport support for arm-linux-gnueabihf to GCC Linaro * LP #1084010 __atomic_load doesn't match ACQUIRE memory model Linaro GCC 4.6 2013.01 is the 23st release in the 4.6 series. Based off the latest GCC 4.6.3+svn194771 release, this is the tenth release after entering maintenance. Interesting changes include: * Updates to 4.6.3+svn194771 The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.7-2013.01 https://launchpad.net/gcc-linaro/+milestone/4.6-2013.01 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release pages: https://launchpad.net/gcc-linaro/4.7/4.7-2013.01 https://launchpad.net/gcc-linaro/4.6/4.6-2013.01 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org

13 years, 8 months

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Thursday 17th January 2013 1600 UTC Performance Call cancelled

by Matthew Gretton-Dann

All, Due to items in the performance call being covered in other meetings, travel and other issues I have decided to cancel today's 1600 UTC call. Thanks, Matt -- Matthew Gretton-Dann Toolchain Working Group, Linaro

13 years, 8 months

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