- linaro-toolchain - lists.linaro.org

by Zhenqiang Chen

Summary: * Code size benchmark analysis. * Linaro binary toolchain 2012.04 release. Details: 1. Tuning the heuristic to assign register for copies. * Take the CONFLICT_HARD_REGS and HARD_REG_COSTS of copies into account when conflict_costs is NULL in update_conflict_hard_regno_costs, which handles the following case: a = ... ... b = a // a can be assigned with r3 or r5 which have the same min_cost. ... // b is conflicted with r3 or the cost of r3 is very high = b In this case, if a is assigned with r3, b can not be assigned with r3, so the copy "b = a" can not be optimized. When taking the CONFLICT_HARD_REGS or HARD_REG_COSTS of b into account, we can assign a with r5. 2. Linaro binary toolchain 2012.04 release. * Update gdb/TOOLCHAIN_PKGVERSION/README to 2012.04. * Test workaround localization patch to fix lp:918926. * Local build and tests show the toolchain can find the corresponding .mo file. * But if the host system does not have the corresponding font packages, it will show some mess characters. * gdb does not have gdb.mo. 3. Investigate code size regressions in 4.7. * Loop invariant hoisting might increase register pressure, which leads to much more spilling. Plans: * Finalize Linaro binary toolchain 2012.04 release * Investigate other code size regressions in 4.7. Planed leaves: * Labor Day’s holiday: April 30 and May 1. Best regards! -Zhenqiang

13 years, 4 months

1
0
0 0

Issue with libgcc_s.so.1 location

by Felipe Contreras

Hi, I have been using CodeSourcery tool-chains since forever, and I decided to try Linaro's tool-chain. So far I haven't had any issues, except one: libgcc_s.so.1 is located in arm-linux-gnueabi/lib, which is not available from arm-linux-gnueabi/libc. The CodeSourcer tool-chain has all those files inside the 'libc' directory, which is useful for Scratchbox2, because you need to specify a "target root" which is basically the libc directory which acts in a similar fashion to /. I've managed to create a rule to workaround this issue, but I wonder why are those files in that location, why not in 'libc/lib'? Cheers. -- Felipe Contreras

13 years, 4 months

2
1
0 0

[Activity] Week 15 / 16

by Ramana Radhakrishnan

=== Progress === * Worked on the VFP addressing modes patch upstream. Handled most comments. Final version has finished testing and looks almost ready to commit. * Investigated an issue with min type transformations for loop terminating conditions. Wrote up a small patch which appears to do the right thing - passed a bootstrap on x86 but that probably means it never got triggered :( . The particular case of interest was not vectorizing : #define min(x,y) ((x) <= (y) ? (x) : (y)) int a[256] __attribute__((aligned (16))); int b[256] __attribute__((aligned (16))); int c[256] __attribute__((aligned (16))); void foo (int x, int y) { int i; for (i = 0; i < x && i < y; // i < min (x, y); i++) a[i] = b[i] * c[i]; } but vectorizing the commented region. I've tentatively worked out a fix in tree-loop-im.c which looks like a bit of a grotesque hack .... * Attended LLVM devcon in Week 15. Useful and interesting and conference. == Plans == * Pursue backporting gnu_unique_object upstream. * Look at some of the existing blueprints and start discussions around prioritizing this. * Investigate some of the SEGVs with h-c partitioning. * Finish off the VFP addressing modes patch. Absences. * 03 May 2012 - 08 May 2012. * Linaro Connect Q2.12 - May 28 - June 1 -

13 years, 4 months

1
0
0 0

[ACTIVITY] Apr 16 - Apr 20

by Ulrich Weigand

== GCC == * Checked in backport patch to fix LP #972648 into Linaro GCC 4.6. * Checked in fix for incorrect vld alignment hints to FSF mainline and 4.7 branch. * Investigated options to fix stack re-alignment. * Ongoing investigation of LP #959242: design problem in vectorizer pattern detection logic causes ICE in certain cases where an original sequence is recognized as part of *two* potential patterns simultaneously. * Ongoing work on improving end-of-loop value computation. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 4 months

1
0
0 0

[ACTIVITY] report week 16

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-04-10 || || Historical Milestones: ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * sent out v1 patchseries for cp15 cleanup to the mailing list, finally * handled review comments on drop-cpu-reset-model-id patchseries == kvm-boot-wrapper == * imported libfdt device tree library and Dave Martin's code from the big.LITTLE boot-wrapper, to add support to the KVM boot wrapper for handling device tree blobs. Patch series sent, will probably commit next week unless there are review issues * that will more or less wrap this blueprint up == other == * usual upstream patch review; QEMU 1.1 soft feature freeze was start of this week, hardfreeze will be beginning of May, people (including me :-)) are trying to squeeze things in under the wire... -- PMM

13 years, 4 months

1
0
0 0

[ACTIVITY] 16th - 19th April

by Andrew Stubbs

* Linaro GCC Investigated the latest test failure for the neon-extend patch. The test for GCC Bugzilla 43137 is failing again. It turns out to be because my switching sign_extend to use a DImode output, rather than two SImode subreg outputs has exposed a bug in the lower-subreg pass. I've spent most of the week trying to figure what can be done about this and discussing the problem with Richard Sandiford upstream. Richard Earnshaw approved my neon-negate patch. That patch depends on the neon-immediates patch which is not approved yet, so I'll have to wait to commit it. Continued looking at NEON-v-core register allocation. Not much progress this week though. * Other Created a patch to make the GCC RTL dumps easier to diff. Posted it upstream and discussed it on the list. Vacation on Friday. * Next week Vacation Monday and Tuesday

13 years, 4 months

1
0
0 0

Update on stack (re-)alignment issues

by Ulrich Weigand

Hello, I've been following up on the discussion we had on Monday regarding stack alignment, and noticed that I had mis-remembered the current state of affairs. Ramana asked me on Tuesday to provide a write-up of the actual status, so here we go ... To summarize the background of the problem: on ARM, the incoming stack pointer is only guaranteed to be aligned to an 8 byte boundary. This means that objects on the stack (local variables, spill slots, temporaries etc.) cannot easily be aligned to more than 8 bytes. This can potentially cause problems in two situations: 1) The object's default alignment (according to its type) is larger than 8 bytes 2) The object has a forced non-default alignment that is larger than 8 bytes The first situation should in theory never appear, since according to the ARM ABI all types have a default alignment of at most 8 bytes. However, due to the current mix-up in GCC, vector types actually are considered to have a 16-byte alignment requirement in GCC. The second situation can only appear with local variables that are declared using attribute ((aligned)). We had discussed on Monday that we need to fix the second situation, since this can always occur and is supported on other platforms. By doing so, we would then automatically fix the first situation as well. However, this reasoning turns out to be incorrect. There are currently in GCC *two* completely separate mechanisms that can be used to align objects on the stack to larger than the ABI guaranteed stack pointer alignment: A) Re-alignment of the full stack frame. This is what is used by the Intel back-end (and only the Intel back-end). At function entry, generated code will align the stack pointer itself to whatever is necessary to fulfil alignment requirements of all objects on the stack. This may necessitate follow-on changes: the frame pointer, if there is one, will likewise need to be aligned at runtime. Also, since incoming stack arguments are now no longer at a fixed offset relative to the stack pointer *or* frame pointer in some cases, we might need an extra register as argument pointer. This method allows extra alignment for *any* object on the stack, but needs significant back-end support in order to be enabled on any non-Intel architecture. B) Dynamic allocation of selected stack variables. This is implemented by common code with no involvement of the back-end. In effect, the code in cfgexpand.c:expand_stack_vars that decides on how to allocate local variables on the stack will remove all variables that require extra alignment and place them into an extra structure. Generated prologue code will then in effect dynamically allocate and align that structure on the stack, and just store a pointer to it as "variable" into the normal stack frame. All other areas of the frame are unaffected. Since this method just simulates code the programmer could have written themselves using alloca, it does not require *any* back-end support and is enabled by default everywhere. However, it only works for regular local variables, and not for any other objects on the stack. Objects on the stack *except* local variables always use default alignment. Since on most platforms, except Intel and *currently* ARM, the ABI stack pointer alignment is sufficient to implement default alignments, method B) as above is able to fulfil all stack alignments. Intel uses method A), so they're also OK. In effect, it's only ARM due to the vector type alignment problem that runs into the situation that neither method works. Under those circumstances, given that: - we want to fix vector type alignment in order to become ABI compliant - once we've fixed this, we're in the same situation as other platforms and method B) already fixes stack alignment problems - implementing method A) is therefore both quite involved *and* actually superfluous I'd now rather recommend that we *don't* try to implement method A) (full stack-frame re-alignment) on ARM. Comments? Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 4 months

2
1
0 0

[ACTIVITY] April 9 - April 13

by Thiago Jung Bauermann

Hi, GDB for Android: * Continued conversation about .note.ABI-tag. * Committed upsream the second of three patches for building gdbserver on Android. * Continued working on a crtbrand.c for bionic. 2012.04 release: * Tested the gdb-linaro/7.4 branch on armv5tel, x86 and x86_64, both natively and remotely. Compared results against the 2012.02 release. * Ran the release process, made the release. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 4 months

1
0
0 0

[ACTIVITY] April 2 - April 6

by Thiago Jung Bauermann

Hi, GDB for Android: * Investigated .note.ABI-tag generation in glibc and FreeBSD. Wrote crtbrand.c for bionic based on FreeBSD's crtbrand.c. Tried to integrate it with bionic's build system. * Contacted Google engineers about adding .note.ABI-tag to Android binaries. 2012.04 release: * Started working on the release. Applied the latest patches from the FSF 7.4 branch to gdb-linaro/7.4 and also my patches to compile gdbserver with the Android toolchain. -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 4 months

1
0
0 0

[ACTIVITY] 9th - 13th April

by Andrew Stubbs

* Linaro GCC Spun release tarballs for Linaro GCC 4.6 and 4.7. Pushed them to Michael's servers and launched the testing. Continued trying to get the 64-bit NEON stuff to work. The negdi2 patch needed some reworking following upstream review, and the extend patch has mysteriously reintroduced a performance regression when the operation is done in core-registers, which needs to be solved, but the other patches seem ok at the moment, although the shift stuff is blocked on benchmarking. I've begun looking at how my changes affect spec2000, and whether the register allocation could be done better. Unfortunately, given that the test systems are currently giving spec results with a low level of consistency (and therefore confidence), this has mostly been by visual inspection, so far. * Other Public Holiday on Monday.

13 years, 4 months

1
0
0 0

getting armv7 linker to emit armv4t thumb interworking

by Allen Martin

I have a cross toolchain I configured with "--with-arch=armv7-a --with-cpu=cortex-a9 --with-tune=cortex-a9" and I want the linker to emit armv4t compatible thumb interworking, but I can't seem to get it to. I noticed that if I create a armv4t toolchain with "--with-arch=armv4t --with-cpu=arm7tdmi --with-tune=arm7tdmi" and then I pass "--use-blx" to the linker it will emit armv7 thumb interworking. There doesn't seem to be any inverse "--no-use-blx" type switch though. Is this a bug/limitation of the linker or am I misunderstanding something? -Allen nvpublic

13 years, 4 months

5
7
0 0

[PATCH] ld: add switch to disable use of BLX instructions

by Allen Martin

Add --no-use-blx switch to force disabling of BLX instructions for thumb interworking. This allows ld to emit code that is armv4t safe even if configured for armv5 or later. --- bfd/bfd-in.h | 4 ++-- bfd/bfd-in2.h | 4 ++-- bfd/elf32-arm.c | 10 +++++++++- ld/emultempl/armelf.em | 11 +++++++++-- 4 files changed, 22 insertions(+), 7 deletions(-) diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h index a477b49..0a81327 100644 --- a/bfd/bfd-in.h +++ b/bfd/bfd-in.h @@ -872,8 +872,8 @@ extern bfd_boolean bfd_elf32_arm_process_before_allocation (bfd *, struct bfd_link_info *); void bfd_elf32_arm_set_target_relocs - (bfd *, struct bfd_link_info *, int, char *, int, int, bfd_arm_vfp11_fix, - int, int, int, int, int); + (bfd *, struct bfd_link_info *, int, char *, int, int, int, + bfd_arm_vfp11_fix, int, int, int, int, int); extern bfd_boolean bfd_elf32_arm_get_bfd_for_interworking (bfd *, struct bfd_link_info *); diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 22fcdf6..45c5376 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -879,8 +879,8 @@ extern bfd_boolean bfd_elf32_arm_process_before_allocation (bfd *, struct bfd_link_info *); void bfd_elf32_arm_set_target_relocs - (bfd *, struct bfd_link_info *, int, char *, int, int, bfd_arm_vfp11_fix, - int, int, int, int, int); + (bfd *, struct bfd_link_info *, int, char *, int, int, int, + bfd_arm_vfp11_fix, int, int, int, int, int); extern bfd_boolean bfd_elf32_arm_get_bfd_for_interworking (bfd *, struct bfd_link_info *); diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 1f6c1a0..7cbb5f8 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -2782,6 +2782,9 @@ struct elf32_arm_link_hash_table /* Nonzero if the ARM/Thumb BLX instructions are available for use. */ int use_blx; + /* Nonzero to prevent BLX instructions from being used. */ + int no_use_blx; + /* What sort of code sequences we should look for which may trigger the VFP11 denorm erratum. */ bfd_arm_vfp11_fix vfp11_fix; @@ -3332,6 +3335,7 @@ elf32_arm_link_hash_table_create (bfd *abfd) #endif ret->fix_v4bx = 0; ret->use_blx = 0; + ret->no_use_blx = 0; ret->vxworks_p = 0; ret->symbian_p = 0; ret->use_rel = 1; @@ -5939,7 +5943,9 @@ check_use_blx (struct elf32_arm_link_hash_table *globals) cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch); - if (globals->fix_arm1176) + if (globals->no_use_blx) + globals->use_blx = 0; + else if (globals->fix_arm1176) { if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K) globals->use_blx = 1; @@ -6800,6 +6806,7 @@ bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd, char * target2_type, int fix_v4bx, int use_blx, + int no_use_blx, bfd_arm_vfp11_fix vfp11_fix, int no_enum_warn, int no_wchar_warn, int pic_veneer, int fix_cortex_a8, @@ -6825,6 +6832,7 @@ bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd, } globals->fix_v4bx = fix_v4bx; globals->use_blx |= use_blx; + globals->no_use_blx = no_use_blx; globals->vfp11_fix = vfp11_fix; globals->pic_veneer = pic_veneer; globals->fix_cortex_a8 = fix_cortex_a8; diff --git a/ld/emultempl/armelf.em b/ld/emultempl/armelf.em index d29da59..14a0dcf 100644 --- a/ld/emultempl/armelf.em +++ b/ld/emultempl/armelf.em @@ -36,6 +36,7 @@ static int target1_is_rel = 0${TARGET1_IS_REL}; static char *target2_type = "${TARGET2_TYPE}"; static int fix_v4bx = 0; static int use_blx = 0; +static int no_use_blx = 0; static bfd_arm_vfp11_fix vfp11_denorm_fix = BFD_ARM_VFP11_FIX_DEFAULT; static int fix_cortex_a8 = -1; static int no_enum_size_warning = 0; @@ -462,7 +463,7 @@ arm_elf_create_output_section_statements (void) bfd_elf32_arm_set_target_relocs (link_info.output_bfd, &link_info, target1_is_rel, - target2_type, fix_v4bx, use_blx, + target2_type, fix_v4bx, use_blx, no_use_blx, vfp11_denorm_fix, no_enum_size_warning, no_wchar_size_warning, pic_veneer, fix_cortex_a8, @@ -533,6 +534,7 @@ PARSE_AND_LIST_PROLOGUE=' #define OPTION_NO_MERGE_EXIDX_ENTRIES 316 #define OPTION_FIX_ARM1176 317 #define OPTION_NO_FIX_ARM1176 318 +#define OPTION_NO_USE_BLX 319 ' PARSE_AND_LIST_SHORTOPTS=p @@ -547,6 +549,7 @@ PARSE_AND_LIST_LONGOPTS=' { "fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, { "fix-v4bx-interworking", no_argument, NULL, OPTION_FIX_V4BX_INTERWORKING}, { "use-blx", no_argument, NULL, OPTION_USE_BLX}, + { "no-use-blx", no_argument, NULL, OPTION_NO_USE_BLX}, { "vfp11-denorm-fix", required_argument, NULL, OPTION_VFP11_DENORM_FIX}, { "no-enum-size-warning", no_argument, NULL, OPTION_NO_ENUM_SIZE_WARNING}, { "pic-veneer", no_argument, NULL, OPTION_PIC_VENEER}, @@ -567,7 +570,7 @@ PARSE_AND_LIST_OPTIONS=' fprintf (file, _(" --target2=<type> Specify definition of R_ARM_TARGET2\n")); fprintf (file, _(" --fix-v4bx Rewrite BX rn as MOV pc, rn for ARMv4\n")); fprintf (file, _(" --fix-v4bx-interworking Rewrite BX rn branch to ARMv4 interworking veneer\n")); - fprintf (file, _(" --use-blx Enable use of BLX instructions\n")); + fprintf (file, _(" --[no-]use-blx Disable/enable use of BLX instructions\n")); fprintf (file, _(" --vfp11-denorm-fix Specify how to fix VFP11 denorm erratum\n")); fprintf (file, _(" --no-enum-size-warning Don'\''t warn about objects with incompatible\n" " enum sizes\n")); @@ -625,6 +628,10 @@ PARSE_AND_LIST_ARGS_CASES=' use_blx = 1; break; + case OPTION_NO_USE_BLX: + no_use_blx = 1; + break; + case OPTION_VFP11_DENORM_FIX: if (strcmp (optarg, "none") == 0) vfp11_denorm_fix = BFD_ARM_VFP11_FIX_NONE; -- 1.7.5.4

13 years, 4 months

2
1
0 0

[ACTIVITY] report week 15

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-04-10 || || Historical Milestones: ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == cp15-rework == * completed last of the register conversions, started on the final check-through and polish before it goes out to the mailing list * implemented changes following review of the clean-up-reset patchset == other == * qemu-linaro 2012.04 final testing (confirming an audio issue on the vexpress model LP:977610 wasn't a regresion) and release * patch review: pl330 dma controller model * patch review: samsung's sd card model overhaul * minor patch: fix compile failure on bsd * minor patch: fix failure to reset timer on a9 mptimer reset * minor patch: diagnose attempts to use python3 at configure time * sent arm-devs.next pullreq * put together a bug report in the form of a youtube video (!) as requested by the gmail folks -- PMM

13 years, 4 months

1
0
0 0

[ACTIVITY] Apr 11 - Apr 13

by Ulrich Weigand

== GCC == * Committed fix for LP #968766 (PR tree-optimization/52880) to FSF mainline and Linaro GCC 4.6 and 4.7. * Created merge reqest to fix LP #972648 for Linaro GCC 4.6 by backporting mainline patch; pending approval. * Updated patch to use vld1.64/vst1.64 instead of vldm/vstm for vector moves. Testing detected problems in GCC core memory alignment logic (GCC assumes vector types are naturally aligned, which contradicts ARM ABI and ARM back-end assumptions). Started discussion on possible fixes. * Updated and retested patch to use vld1/vst1 to implement vec_set/vec_extract for cases where the scalar operand resides in memory. * Ongoing work on fixing LP #959242. * Ongoing work on improving end-of-loop value computation. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 4 months

1
0
0 0

Linaro GDB 7.4 2012.04 released

by Thiago Jung Bauermann

The Linaro Toolchain Working Group is pleased to announce the release of Linaro GDB 7.4 2012.04. Linaro GDB 7.4 2012.04 is the second release in the 7.4 series. Based off the latest GDB 7.4, it includes a number of ARM-focused bug fixes and enhancements. Interesting changes include: * gdbserver can now be compiled with Android's toolchain. * Additional fixes from the GDB 7.4 branch, one of them being that it doesn't require makeinfo to build anymore. The source tarball is available at: https://launchpad.net/gdb-linaro/+milestone/7.4-2012.04 More information on Linaro GDB is available at: https://launchpad.net/gdb-linaro -- []'s Thiago Jung Bauermann Linaro Toolchain Working Group

13 years, 4 months

1
0
0 0

[ANNOUNCE] Linaro QEMU 2012.04 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2012.04. Linaro QEMU 2012.04 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. New in this month's release: - ppoll syscall now supported in ARM linux-user mode - the SETEND instruction in the Thumb encoding now UNDEFs to match behaviour for the ARM encoding - the OMAP36xx UART FIFO status registers are now implemented (thanks to Jan Vesely) Known issues: - Graphics do not work for OMAP3 based models (beagle, overo) with 11.10 Linaro images. - Audio may not work on Versatile Express models with the latest Linaro kernel/hardware packs (LP:977610). The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2012.03 More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

13 years, 4 months

1
1
0 0

[ANNOUNCE] Linaro GCC 4.7 and 4.6 2012.04 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the 2012.04 release of both Linaro GCC 4.7 and Linaro GCC 4.6. Linaro GCC 4.7 2012.04 is the first release in the 4.7 series. Based off the latest GCC 4.7.0+svn186061 release, it includes performance improvements especially around 64 bit operations. Interesting changes include: * Our first 4.7 based release * Updates to GCC 4.7.0+svn186061 * Better use of 16 bit Thumb-2 instructions for smaller code size * Implements 64 bit ones complement in NEON * Adds support for the ARMv6 saturation instructions * Backports the NEON lexer improvements for faster compilation * Backports the 64 bit multiply, divide, and mod improvements Fixes: * LP: #960283 slp pass assert when compiler configure with --enable-checking Linaro GCC 4.6 2012.04 is the fourteenth release in the 4.6 series. Based off the latest GCC 4.6.3+svn186060 release, this is the first release after entering maintenance. Interesting changes include: * Updates to 4.6.3+svn186060 Fixes: * LP: #960283 slp pass assert when compiler configure with --enable-checking The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.7-2012.04 https://launchpad.net/gcc-linaro/+milestone/4.6-2012.04 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.7/4.7-2012.04 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org -- Michael

13 years, 4 months

1
0
0 0

O2 optimization with vectorize

by Singh, Ravi Kumar (Ravi)

All, In the below code, I tried few compiler options and got following observations: 1) arm-linux-gnueabi-gcc -O2 -mcpu=cortex-a15 -mfpu=neon -ftree-vectorizer-verbose=6 -ftree-vectorize Compiler throws following info messages: foo.c:16: note: not vectorized: unsupported use in stmt. foo.c:16: note: not vectorized: unsupported use in stmt. foo.c:18: note: not vectorized: unsupported use in stmt. foo.c:18: note: not vectorized: unsupported use in stmt. 2) -O2 -mcpu=cortex-a15 -mfpu=neon None of the generated code contains the NEON instructions. Code generated with case 1 is taking 3000 cycles, and code generated by option 2 is taking 2500 cycles. Even if vectorization failed in case1, it should not generate more inefficient code than case 2. My belief was that the executables from both would take same cycles, any thing done for doing unsuccessful vectorization must be reverted if it did not succeed. ################################################################### #define SIZE1 20 #define SIZE2 26 unsigned int array[SIZE1][SIZE2]; void foo() { unsigned int i,j; unsigned int max = 0; for(i = 0; i < SIZE1; i++) { for(j = 0; j < SIZE2; j++) { if (array[i][j] > max) { max = array[i][j]; index = j; } } } printf("Max value: %u Index: %u\n", max, index); } Regards RKS

13 years, 4 months

2
3
0 0

2012.04 release prep

by Michael Hope

Hi there. The 2012.04 toolchain release is this week. Ulrich, I see your fix for LP: #968766 has been approved upstream. In theory it's too late but I'm happy to land it if you are. Could you decide and let Andrew know by the middle of Tuesday? Andrew, if you don't hear from Ulrich then spin away. Andrew, could you run the release process on Tuesday please? There's one extra step this month: once you've uploaded and spawned the job, go to the scheduler screen and click on 'Release' beside each of the ursas. I reserved them to make sure they'd be idle and ready to pick up the release build when ready. Thiago, let us know if Ulrich or I can lend a hand with the GDB release. -- Michael

13 years, 4 months

2
2
0 0

Changing the time of the fortnightly performance call

by Ramana Radhakrishnan

Hi there, At the last call Michael asked if we could push this call back by 30 minutes given the changes due to daylight savings. Does anyone have any objections to a new time of 10 a.m. BST - 11 a.m. Central European - 9 p.m. New Zealand. ? cheers Ramana

13 years, 4 months

3
3
0 0

[ACTIVITY] 2nd - 5th April

by Andrew Stubbs

* GCC Identified the latent bug that's upset my NEON-shifts testing. It turns out the define-insn-and-shift patterns in arm/sync.md have no length attributes set. Now that the NEON 64-bit shifts appear to be not broken, I've relaunched the 64-bit extend testing. Identified the problem with my NEON-64-bit-negate patch: I already knew it works better (produces more optimal code) with my NEON-immediates patch, but it turns out that at -O0 the other patch is a hard requirement or else bad things happen in output_move_vfp. Backported Ramana's patch for ARM-mode testing of my recent Thumb 64-bit test cases. I've applied it to Linaro GCC directly, without a merge proposal, as it's a very low-risk patch. Caught up with some launchpad blueprint fiddling. Completed the merges from 4.6 and 4.7 FSF. The 4.7 merge was tricky as it required working around a BZR bug; I've posted the workaround to the toolchain list. * Other On leave on Tuesday Public holiday on Friday. Attached a copy of the ARM Linux ABI document to KBentry 39 so we're hosting it somewhere, at least. Posted an internal Mentor/CS question about getting its old home restored, and getting a relicensed edition to allow others to use it as the basis for a hard-float equivalent.

13 years, 4 months

1
0
0 0

[Activity] Week 14

by Ramana Radhakrishnan

=== Progress === * Worked on VFP addressing patch and corrected the failures. * Got SPEC2k up and running with hot cold partitioning. Some SEGVs that need investigation. In general results appear to be better in quite a few cases. * Investigated an issue with a merge request for upstream 4.7 branch into our tree. There was a testsuite failure and I wasn't able to reproduce it with a local i386 rebuild of the toolchain. Therefore we'll have to let this go in. == Plans == * I will be away for 2 days this week attending the LLVM conference in London. * Pursue backporting gnu_unique_object upstream. * Finish off the VFP addressing modes patch upstream. * Look at some of the existing blueprints and start discussions around prioritizing this. * Investigate some of the SEGVs with h-c partitioning. Absences. * Apr 12-13 : Euro-LLVM London. * Linaro Connect Q2.12 - May 28 - June 1 -

13 years, 4 months

1
0
0 0

[Activity] Week 14

by Zhenqiang Chen

Summary: * Revise the patch for relocatable NLS support. * Code size benchmark analysis. Details: 1. Revise the patch for relocatable NLS support: lp:918926. * Read the gcc configure and makefile. * It seams hard to get the relative dir if the gcc is configured with --bindir=... --datadir/datarootdir. E.g. --bindir=/opt/bin --datarootdir=/tmp/data 2. Code size benchmark analysis with -Os * Investigate regression in small cases. 3. Try to build linaro gcc trunk with crosstool-ng. But it reports error when configuring libquadmath. * configure:9829: error: Link tests are not allowed after GCC_NO_EXECUTABLES. * Manual check or a simple case show libc.so can be linked. Plans: * Tuning optimization heuristics for -Os Planed leaves: * April 9 - 11: Vacations Best regards! -Zhenqiang

13 years, 4 months

1
0
0 0

[ACTIVITY] report week 14

by Peter Maydell

Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-04-10 || || Historical Milestones: ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 || == other == * LP:970252 got a beagle board booting so I could read the UART version register; reviewed and applied to qemu-linaro the set of patches provided by Jan Vesely (thanks!) * sent a patchset cleaning up the GIC model so it is a self-contained sysbus device; this should make it easier to just drop in a functionally equivalent device which is a shim for an in-kernel GIC model that uses the hardware VGIC features * upstream review: save/load support for sd.c [patchset from Samsung] SPI bus [patchset from Petalogix] * put together qemu-linaro prerelease tarball and did some testing * performance evaluation finished and submitted

13 years, 4 months

1
0
0 0

[ACTIVITY] 26th - 30th March

by Andrew Stubbs

Continued work on neon 64-bit correctness. This is really dragging out now. I had hoped to have had it fixed by now, but subtle bugs are subtle. The 16-bit opcodes patch is now committed both upstream and in Linaro GCC 4.7, however, so that's some progress at least. Posted benchmark results for the the 64-bit shifts in core registers. The results are inconclusive: the benchmark runs are too noisy.

13 years, 4 months

1
0
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain