Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-03-30 || ||
Historical Milestones:
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* converted crn=1; still TODO: crn=0, some loose ends; then reassess
the design in the light of experience doing register conversion
* I've estimated another two weeks here but this might be out, because
in practice much of my time is sucked up by 'other' issues
== other ==
* tracked down cause of LP:947888 gpg crash bug: newer glibc use
/proc/self/maps to decide whether a printf format string using '%n'
is in writable memory, and qemu's maps emulation wasn't good enough
* fixed a thumb decoder bug where we were treating 'setend' like 'cps'
* investigated whether we had any conveniently testable cores which take
advantage of the ARM ARM latitude for UNDEFfing even on failed condition
code checks (answer, not really but the KVM code to handle this case
should be small enough not to worry about its not-yet-tested nature)
* qemu-linaro 2012.03 release (lots of bug fixes, plus exynos4 and
highbank models thanks to Samsung and Calxeda)
* code review: imx31 board patches
* rebased qemu-linaro on upstream and applied some new patches from
Christoffer for ARM KVM support
* LP:956799: added ppoll to QEMU arm-linux-user (a one liner...)
* boot-wrapper: moved initrd load address up so we can handle large
kernels (like Android!)
* sent pullreqs for target-arm, arm-devs patchqueues
== GCC ==
* Checked first part of fwprop-subreg patch into mainline.
* Checked Ira's vectorizer patches into mainline.
* Ongoing work on improving end-of-loop value computation.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
The final version of the 'Building at -O3' writeup is at:
https://wiki.linaro.org/Internal/ToolChain/BuildingAtO3
This updates the SPEC 2000 results to show that there is a net win
which is held back by a bad (but understood) regression in one
benchmark.
Thank you all for your work on this,
-- Michael
The Linaro Toolchain Working Group is pleased to announce the release of
Linaro QEMU 2012.03.
Linaro QEMU 2012.03 is the latest monthly release of qemu-linaro. Based
off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes
and enhancements.
Highlights in this month's release:
- we now default to enabling 'reserve memory for guest' on 64 bit hosts
in linux-user-mode. This significantly reduces the chances of QEMU
being unable to satisfy a guest process mmap() request.
- Fix for a bug that was causing spurious failures of the glibc check
for "%n in a format string must be in a read-only area of memory"
when running in linux-user-mode.
- QEMU's built-in boot loader now supports passing a device tree blob
to the kernel: if you boot with -kernel mykernel (and optionally
-initrd myinitrd) you can now also use the new command line option
-dtb my.dtb to pass a device tree.
- This version includes an initial implementation of a model of the
Samsung Exynos4210 SoC, used by board models 'nuri' and 'smdkc210'
(thanks to Evgeny Voevodin, Maksim Kozlov, Igor Mitsyanko and
Dmitry Solodkiy from Samsung, who submitted this work to upstream
QEMU).
- This version includes an initial implementation of a model of the
Calxeda Highbank SoC, used by board model 'highbank' (thanks to Rob
Herring and Mark Langsdorf of Calxeda, who submitted this work to
upstream QEMU).
- various other minor bug fixes (detailed in the Changelog.LINARO).
Known issues:
- Graphics do not work for OMAP3 based models (beagle, overo)
with 11.10 Linaro images.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2012.03
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The GCC release tested up just fine. The branch is now open for commits.
The next release is Thursday the 12th of April. Note that this is the
week after Easter.
-- Michael
The Linaro Toolchain Working Group is pleased to announce the 2012.03
release of both Linaro GCC 4.6 and Linaro GCC 4.5.
Linaro GCC 4.6 2012.03 is the thirteenth release in the 4.6 series. Based
off the latest GCC 4.6.3 release, it contains a new scheduler pressure pass,
implements new instructions, and contains a number of bug fixes.
Interesting changes include:
* Updates to 4.6.3.
* Better performance by accounting for register pressure when
scheduling instructions.
* Support for the ARMv6 USAT/SSAT saturation instructions.
* Support for the VFP VCVT fixed to floating point conversion instruction.
Fixes:
* LP: #922474 Bug in __sync_lock_release with 64 bit primitives
* LP: #923397 Alignment attribute has no effect under certain conditions
* LP: #926855 [ARMhf] gcc produces assembler it can't compile
* LP: #936863 ICE in constprop.2 (ARM NEON related?)
* LP: #942307 'asm' operand requires impossible reload
* LP: #952565 Not compliant with the ABI for multi-register NEON intrinsics
Linaro GCC 4.5 2012.03 is the nineteenth release in the 4.5 series. Based
off the latest GCC 4.5.3+svn184976 release, this is a maintenance only
update.
Interesting changes include:
* Updates to 4.5.3+svn184976.
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.6-2012.03https://launchpad.net/gcc-linaro/+milestone/4.5-2012.03
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.6/4.6-2012.03
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? Inquire at support(a)linaro.org
-- Michael
EEMBC have announced AndEBench, a mixed native/Java benchmark for
Android. It's available on the Market.
I don't know much more. It seems to be CPU bound and the test names
sound a bit like CoreMark. The source is available for license and
might be worth the Android guys looking into.
The awesome thing is they used the 2012.01 Linaro Binary toolchain
release to build the native parts - see the compiler version string in
the log :)
-- Michael
Hi,
GDB for Android:
* Wrote first draft of the GDB for Android card.
* Found out that there actually is a libthread_db.so in /system/lib
and was able to compile (after a small hack) an FSF gdbserver 7.3
which uses the libthread_db.so from Android and correctly shows
all threads in the process. So the libthread_db.so from Android
actually works, still have to learn why they don't use it.
* Tried to compile a native GDB which uses libthread_db.so but no
luck so far. There are many differences in bionic's header files
which upset libiberty and gnulib which are not easy to work around.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
We now do a SPEC ref run when benchmarking. I've updated the
linaro-toolchain-benchmarks scripts to handle the changes and spawned
some historical builds to do comparisons. All earlier builds have
been archived to prevent confusion.
The human readable summary is now also included in the results. See:
http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.6-2012.02/logs/armv7l-nat…
for an example.
Half an hour to build, 26 hours to run. Not too bad.
-- Michael
Here's brief notes on running different benchmark variants across the
auto builders. Asa, could you pull these plus your notes into a wiki
page?
Spawn a job:
http://ex.seabright.co.nz/helpers/scheduler/spawn
Merge requests are automatically built. Otherwise, drop arbitrary
tarballs into cbuild@orion:~/snapshots and spawn <tarball name minus
extension>. For example, scp gcc-4.6.3.tar.gz
cbuild@orion:~/snapshots; spawn gcc-4.6.3 into a9-builder.
Jobs:
* gcc-version - build and test GCC
* benchmarks-gcc-version - run coremark, denbench, eembc against the
already built version
* benchmarks-spec2000-gcc-version - run spec2000
Queues:
* a9-builders: anything that can naive build a A9 compiler
* a9-ref: reference A9 boards
* a8-ref: reference A8 boards
Variables:
* BENCHMARKS = list, such as coremark spec2000 pybench - run these
benchmarks instead of the defaults
Variants:
* By default we build o3-neon
* See http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/trunk/view/head:/l…
for all names
* Spawn a job with VARIANT_SRC = all and VARIANT_LIST = glob-pattern
Examples:
* VARIANT_LIST = o3-neon o3-vfpv3 (compare NEON with VFPv3D32)
* VARIANT_LIST = o3-neon-cortexa8 o3-neon-cortexa9 (compare
-mtune=cortexa8 vs -mtune=cortexa9(
* VARIANT_LIST = o3-neon-novect o3-neon (compare with/without the vectoriser)
-- Michael
I'd like to announce a change in how the Linaro Toolchain group notify
about our monthly releases. In the past we've sent one email per
product to the linaro-announce list. From this week forward a summary
of all products will be included in the main, end of month
announcement instead.
We'll continue to send a per product emails to the linaro-toolchain
list when the mid-month release is available. If you'd like to get
things two weeks early, please subscribe[1]. You can filter on the
word '[ANNOUNCE]' to filter out the development chatter. A RSS feed
is also available[2].
-- Michael
[1] http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[2] http://feeds.launchpad.net/linaro-toolchain/announcements.atom
All,
I need to supply a Linaro toolchain "aligned" (same source code)
bare-metal compiler to a group doing benchmarking on A15.
First off my assumption is that we will write our own boot and semi
hosting code. (semi-hosting for TI emulators/simulators is different
than ARM RDI semi-hosting.)
I was planning on looking at the two toolchains here[1] and here [2]:
[1] https://launchpad.net/linaro-toolchain-binaries
[2] https://launchpad.net/gcc-arm-embedded
I was then going to build a hybrid that was newlib based but appropriate
for armv7-a (instead of cortext-m3) and maybe even -mtune'ed for A15.
However looking at the gcc-arm-embedded release more[3] I see that it
supports ARMv7-R. It supports both thumb and non-thumb modes, both
softfp and hardfp ABIs.
What would I really gain by building my own? For app code the user
should be able to add -mtune=cortex-a15 and still be compatible with the
pre-built R4/R5 libraries. The only performance difference should be in
the library code and that should be only pipeline tuning if I understand
the difference between armv7-a and armv7-r correctly.
Am I missing something? Should I build my hybrid anyway?
[1] https://launchpadlibrarian.net/88152755/readme.txt
[BTW: has the below project been obsoleted by the gcc-arm-embedded one?
Perhaps gcc-arm-embedded should be referenced in the description of
the page below.
https://launchpad.net/linaro-toolchain-unsupported ]
Thanks,
Bill
Committed the 4.6.3 merge to Linaro GCC 4.6.
Merged from FSF 4.5 to Linaro GCC 4.5.
Thought about how to do register-class allocation for NEON v. core
registers case. Discussed the problem at the GCC performance meeting.
Lots of interesting discussion was had. I have some interesting
experiments to do, but the first step needs to be to get my 64-bit
operator patch to work correctly.
Tried to track down the problems in my NEON-immediates patch. The
problem is that it's putting constants in different pools in stage 3 to
what it does in stage 2. Presumably this is something to do with the
pool-offset attributes in the instruction patterns? My patch has caused
it to switch from using 'fldd' to using 'vmov' in some cases (the
instructions are aliases, but it's indicative of a different machine
description pattern in the compiler), but I don't know why the change
would be different between the different bootstrap stages? I made some
alterations to switch it back to `fldd` when it wasn't supposed to
change, but bootstrap still fails. More investigation required...again.
Rewrote the NEON one's-complement patch and posted it upstream.
Tracked down the cause of the bootstrap failures in my NEON 64-bit
shifts patch: out-of-range shift amounts were not handled leading to
ICEs. Reworked the constant shift handling cases, and resumbitted the
patch for testing. It's failed again. A job for next week.
Summary:
* Multilib test for linaro toolchain.
* Code size test for embedded toolchain.
Details:
1. Multilib test for linaro toolchain.
* Workaround the marm/march=armv5t build by setting the
MULTILIB_DEFAULT to mthumb.
* Investigate how to make multiarch and multilib work together.
Based on current multiarch/multilib patches, it is hard to make them
work together. Trying to set the default multilib dir to the multiarch
dir to workaround it. Need more work to build libgcc.
2. Code size investigation for embedded toolchain.
* Try to test benchmarks.
* Run gcc regression test with –mthumb/-mcpu=cortex=m3/-Os and
analyze the new failed cases. After skipping the cases based on
scan-assembler, warning/error message, etc, there are 5 new failed
cases in three categories:
(1) gcc.target/arm/neon/vst1_lanes64.c: known issue
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51631
(2) Wrong optimization for gcc.dg/atomic-lockfree.c,
gcc.dg/atomic-noinline.c and gcc.dg/pr30951.c.
(3) g++.dg/eh/filter1.C abort in libsupc++.
Plans:
* Root cause the new failed cases.
* Continue to investigate the multilib/multiarch issue.
Best regards!
-Zhenqiang
Hi Michael,
Spec2000 is now running successfully: there are results at
http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.7%2bbzr114965/logs/armv7l…
However, they seem to have been run in 'train' mode, and none of the
runs are long enough for comparison.
I thought the a9-ref queue was supposed to run in full 'ref' mode?
Andrew
Hi,
OpenEmbedded:
* removed the recipe for building the linux-linaro-3.1 kernel
* add support for the default OE-core kernel
* allows to build the linux-yocto_3.2 kernel for the
qemuarmv7a MACHINE using a vexpress defconfig
* updated the wiki on how to build OE-core with meta-linaro
https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core
* worked OEMetaLinaroCard
* started to talk to CI folks about automating the oe-core+meta-linaro
* wrote a script that automates the process
* ran it on tcserver01 to build the qt4e and sato images against the
source gcc-linaro-4.6-2012.02
Regards,
Ken
Hi Ken. In follow up to our 1-on-1 yesterday, here's what I'd like done next.
The goal is to use OE Core as a release test suite. The releases are
tarballs so we can keep the current recipe format and punt bzr support
for later. The first step is to be able to reliably build a release
in the cloud or validation lab.
In all cases keep the other teams in mind. Much of this is related to
Validation. Platform will be involved later. Ping them early.
Kernel:
We're starting with GCC and need a kernel to supply headers and to
boot some type of ARMv7 image. I don't want a linux-linaro recipe as
people will use it and it's too early for that.
Find a kernel, preferably from OE Core, that is recent, ARMv7, >= 512
MB RAM, and works well with qemu-linaro. Prefer vexpress-a9, else
OMAP?
Talking:
Say Hi to Validation re: EC2 and plans
Say Hi to the ARM landing team re: vexpress upstream support
Say Hi to Beth Flanagan re: Yocto's existing auto builders and any hints
Cloud builds:
Find out who is already doing OE builds in the cloud and how
Run a build locally and time
Push ~/downloads into the cloud, build, and time[1]
Figure how much this build will cost in dollars
[1] c1.xlarge might be best. Builds are normally I/O bound and the
cloud is I/O poor. Put /tmp and other chunks in a tmpfs? EC2 rounds
up to the nearest hour as well.
If the cloud is too expensive then we'll get a machine installed.
S3 for storage:
(only proceed if affordable)
Use S3 for storing the input tarballs
Use S3 either as a pre-mirror by serving over HTTP, or use s3cmd to
sync down the tarballs before starting the build
Scripting:
Re-use existing scripts if feasible. Integrate with LAVA providing we
can run exactly the same scripts on a laptop for debugging.
Script the bitbake, OE meta layer, and Linaro meta layer setup.
Script the configuration including setting the release tarball URL and
GCC preferred version.
Script the build and result capture, especially the log, any ICEs, and
the final sizes
Future:
OE can grab a repository seed then update based on that. Check if the
bzr backend supports this. If so, play with seeding to do tip builds.
Let me know what you think then we'll spawn blueprints. Let's keep an
eye on this as it's sounding expensive.
-- Michael
Hi Ken, Thiago. Could you try your hand at writing cards for the
OpenEmbedded Core meta-layer and GDB and Android? Here are some past
cards:
https://linaro-public.papyrs.com/TCWG2011-GCC-O3https://linaro-public.papyrs.com/TCWG2011-OPENOCD-SUPPORThttps://linaro-public.papyrs.com/TCWG2011-WINDOWS-TOOLCHAIN
They cover:
* An introduction
* The why/advantages
* The what/features
* The how/steps
* Dependencies
* Acceptance criteria (which is a post-tense version of the body)
A card should cover three calendar months. Check the unknowns - we
need to investigate the acceptance criteria and make sure there is no
unexpected side work in there.
We use roadmap cards as the highest level of organising our work.
Cards are the interface between working groups and the TSC and sit at
the project brief / deep but concise level.
Draft them on the wiki (cf https://wiki.linaro.org/KenWerner/Sandbox)
and we'll go from there.
-- Michael
== Issues ==
It would be nice to have perf installed on the porter boxes in the
canonical data center as well if we are allowed to run benchmarks
there. Filed RT request.
==Progress===
* Understood STB_GNU_UNIQUE_NOTE - Helped fix a problem with compiz
crashing but then it was a very nice testcase to investigate the
toolchain issue with. Thanks Alexandros.
* Merged pending patches.
* ABI fix
* Fix for ICE - LP bug 942307
* Off sick on Monday.
* Did some work to improve code generation for addressing modes in VFP
registers.
* Did some work in setting up SPEC2k for running hc partitioning
patches. Still needs to be completed.
=== Plans ===
* Ping configure.ac changes.
* Complete pending benchmark run with hc partitioning and look at
results with hc partitioning and run things. Was unable to run the vfp
benchmarks today as ex.seabright.co.nz was down.
* Resurrect partial-partial PRE
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
Hi Ken. This month's release is next week. Let's be aggressive and
see if we can use your meta-linaro layer to check the source release.
I want to use tcserver01 in the validation lab instead of the cloud
until we know how much it costs. I've added you an account and done a
test build to check that the dependencies are there. There's a shared
directory in /home/shared that includes downloads and a sstate-cache.
The machine seems fast enough for the job.
The tarball should be ready around Tuesday next week. Once ready,
could you mix it in with the meta-linaro layer, do a build, boot the
rootfs in qemu, and document as you go? Anything past that is
welcome.
It's all manual but a nice proof of concept. Can we check the binary
build as well?
-- Michael
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-??-?? || ||
(new blueprints & reestimate for this one pending still; will try to
do this early next week)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* converted cp15 crn={6,7,9}, still TODO just crn={0,1}. These take
longer than I was expecting because to find some useful compromise
between QEMU's previous (usually broken) behaviour and reality I
have to cross reference half a dozen different TRMs and several
revisions of the ARM ARM.
== other ==
* getting qemu-linaro into shape for next week's release:
applying patches, writing changelog, etc
* patch review for more exynos4 devices
* tracked down a regression in the spitz (zaurus) model,
sent patch
* first pass comments on blueprints for this quarter
* investigating LP:947888 (gpg crashes under qemu)
-- PMM
Hi Alexandros,
Could you use the linaro-toolchain list for stuff like this please?
You're more likely to find somebody who knows the answer that way.
I'm pretty sure the problem is not the compiler because, as far as I can
see, both architectures' compilers emit ".weak" directives. If there is
a problem, I'd say it's in the linker.
Your test case gives two different addresses on Lucid x86, and on ARM
(so you say, I've not tested it), but the same address twice on Precise.
This is a surprising result. *I* would have expected that static values
in different dlopen'd libraries would not be unified, but apparently
they are ... somtimes.
I'm afraid I don't really have any insight here. :(
Anyway, regardless of whether one is correct, or not, I'd suggest *not*
relying on this behaviour - it's clearly not portable. I say leave it at
arm's length in production software for a few years.
Andrew
On 06/03/12 14:27, Alexandros Frantzis wrote:
> On Tue, Mar 06, 2012 at 09:51:01AM +0800, Sam Spilsbury wrote:
>> On Mon, Mar 5, 2012 at 11:50 PM, Alexandros Frantzis
>> <alexandros.frantzis(a)linaro.org> wrote:
>>> Hi all,
>>>
>>> this is an update on my progress with the updated compiz branches.
>>>
>>> I have been trying to run our update compiz branches
>>> (compiz-*/linaro-gles2-update) on ARM (precise armhf), but I have stumbled onto
>>> the same issue Marc reported some days ago. In particular, I get:
>>>
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeWindow_index_4" already stored in screen.
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeScreen_index_4" already stored in screen.
>>>
>>> and then a segfault when I try to run compiz.
>>>
>>> Note that I *don't* have this problem when running on x86_64 precise.
>>>
>>> The issue can be recreated with:
>>>
>>> $ compiz composite opengl
>>>
>>> I added some debugging messages to pluginclasshandler.h to get a better
>>> feeling of what is going on, and ran on both my desktop and on ARM.
>>> This is the output near the point when GLScreen get initialized:
>>>
>>> ...
>>>
>>> compiz (core) - Info: get(): mIndex.initiated for "8GLScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "8GLScreen_index_4"
>>> compiz (core) - Info: initializeIndex(): Private index value added for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Get instance for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Spawning new class for "8GLScreen_index_4"
>>> compiz (core) - Info: ctor(): mIndex.initiated for "8GLScreen_index_4" : 1
>>> compiz (core) - Info: ctor(): Increasing reference count for "8GLScreen_index_4": 1
>>>
>>> --- x86_64 ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 1
>>> --- armhf ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "15CompositeScreen_index_4"
>>> compiz (core) - Fatal: initializeIndex(): Private index value "15CompositeScreen_index_4" already stored in screen.
>>
>> After the composite plugin loads and mIndex.initiated is set to 1,
>> place a watchpoint on mIndex.initiated (it should be a separate
>> template instantiation for each different class) and check if it
>> changes, or check if we are reading mIndex.initiated from a different
>> address, and if so, check the addresses of this for each constructor
>> and destructor being called. (could be a compiler bug, I've hit these
>> on this part of the code before).
>>
>>> -------------
>>>
>>> In the armhf case, CompositeScreen is erroneously considered not
>>> initialized, and is initialiazed again, therefore messing up the plugin system.
>>>
>>> I am trying to figure out if this is a manifestation of some kind of memory
>>> corruption that doesn't affect us on x86_64 for whatever reason (alignment,
>>> integer size etc), or something completely different.
>>>
>>> Thoughts?
>>>
>>> Thanks,
>>> Alexandros
>>
>>
>>
>> --
>> Sam Spilsbury
>>
>
> Hi all,
>
> (I have also added Michael, Andrew and Ulrich from the Linaro toolchain group
> to the recipients. Hi!)
>
> Checking the addresses, as Sam suggested, I found that there are two different
> PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex and
> PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex objects.
>
> After a bit of investigation, objdump gave an explanation:
>
> objdump -t /usr/lib/compiz/libcomposite.so | c++filt | grep mIndex
>
> -- x86_64 --
> 0000000000277a80 u O .bss 0000000000000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 0000000000277a70 u O .bss 0000000000000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> -- armhf --
> 00065648 w O .bss 00000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 00065658 w O .bss 00000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> ------------
>
> And the same kind of output for libopengl.so
>
> On x86_64 the symbols are marked 'u': 'unique global', whereas on armhf
> they are marked 'w': 'weak'. This seems to be causing our troubles.
>
> I have produced a small test case for this:
>
> http://people.linaro.org/~afrantzis/cpp_unique_global.tar.gz
>
> Building and running 'LD_LIBRARY_PATH=. ./main' on x86_64 prints out f1 and f2
> with the same address, whereas on armhf the addresses are different (i.e. two
> different objects). On x86_64 the symbol A<int>::a is 'u', on armhf it is 'w'.
>
> For completeness, when running without templates (edit a.h to change) the two
> printed addresses are different on both x86_64 and armhf. Also A::a is 'g':
> 'normal global' for both.
>
> Michael, Andrew, Ulrich can you please give us some insight into the situation?
> Does this seem like a compiler or linker bug on ARM, or is the code depending
> on undefined behavior, or something different? I have pasted the used g++
> versions at the end of the email.
>
> Thanks,
> Alexandros
>
> --- g++ x86_64 --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.6/lto-wrapper
> Target: x86_64-linux-gnu
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++,go --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --disable-werror --with-arch-32=i686 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
> --- g++ armhf --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/4.6/lto-wrapper
> Target: arm-linux-gnueabihf
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --enable-multilib --disable-sjlj-exceptions --with-arch=armv7-a --with-float=hard --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabihf --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
Hi!
* Bug reports
Made an effort clean up among the remaining not-triaged bug. Michael will
help out with 941676, where the failure is on power-pc.
* Wiki
Created a wiki page for running benchmarks in cbuild:
https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/RunningBenchmark…
* V8
Build system has changed in V8 from SCones to GYP. With GYP I can pass the
normal flags like CXXFLAGS to control the build, so this looks like a good
change.
I have created a cbuild make file, patterned after the other benchmark make
files.
Working on x86 sofar, will go for arm next week. Will also add a parser for
the results.
Regards
Åsa
== GCC ==
* Checked patch to generate usat/ssat instructions into
Linaro GCC 4.6 and 4.7.
* Submitted (first part of) fwprop-subreg patch for mainline.
* Submitted Ira's vectorizer patches for mainline.
* Ongoing work on improving end-of-loop value computation.
* Patch review week.
== Misc ==
* On leave 3/9 - 3/14.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
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