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Error: selected processor does not support requested special purpose register

by mins.lin＠globalunichip.com

Hi, I used Linaro cross-toolchain version 4.5 (gcc-4.5-arm-linux-gnueabi) to compile linux-linaro-11.05 for beagle board, but got the following error messages: ---- AS arch/arm/boot/compressed/head.o arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr' arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr' arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2' make[2]: *** [arch/arm/boot/compressed/head.o] Error 1 make[1]: *** [arch/arm/boot/compressed/vmlinux] Error 2 make: *** [uImage] Error 2 ---- The .config file I used for kernel build is "config-2.6.38-1003-linaro-omap" which is from hwpack_linaro-omap3-x11-base_20110526-5_armel_supported.tar.gz My host development platform is 64-bit Ubuntu 10.04.2 LTS (Linux ubuntu 2.6.32-32-generic #62-Ubuntu SMP Wed Apr 20 21:52:38 UTC 2011 x86_64 GNU/Linux). Is this a known bug, or did I miss anything else ? Thanks. --------------------------------- Email Confidentiality Notice ------------------------------------------ If you are not the intended recipient for this CONFIDENTIAL E-mail, please delete it immediately without keeping or distributing any copy and notify the sender. ----------------------------------------------------------------------------------------------------------------------

13 years, 11 months

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[Activity] Week ending July 8th .

by Ramana Radhakrishnan

== GCC == === Progress === * Panda board up again with apparently no change with software on it. Not sure what caused the difference today ! Now chugging along with SPEC2k. * Back on to BRANCH_COST . SPEC2k now running fully whence panda board was restored. * Submitted cleaned up neon shift immediates patch for merging. * On merge request review in Linaro this week. * Backported arith_shiftsi patch to 4.6 branch upstream. (done) * Identified particular patterns that have issues with scheduler descriptions in A8 and A9 . Working on fixes. === Plans === * Submit one_cmpldi2 patch for neon upstream. * Finish the scheduler patches. * Investigate A8 vs A9 regressions. * Look at EPILOGUE_USES and coremark . not sure why it regresses in performance yet. Meetings: * 1-1s * TCWG calls Absences. * 1st Aug - 5th August - Linaro sprint. * 8th - 9th August - Internal training. * 29th Aug - Sept. 2 - Vacation.

13 years, 11 months

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[ACTIVITY] 4th - 8th July

by Andrew Stubbs

Completed the merge of FSF GCC 4.5 & 4.6 to Linaro GCC. There were a few extra test failure in the i686 testing for both toolchains, but x86_64 and arm were clean, so it seems likely to be an environmental issue (in particular, some of the failures were linker crashes). Posted an update to my widening multiplies patch 3. This one hopefully addressed the issues found by Richard Guenther. Also tested an posted updates to my other patches that had their context changed. Richard picked more holes in my patch, and also reviewed patches 4, 5 and 6. 4 & 5 only have minor issues so far, and 6 has actually been approved! :) Rewrote patch 3 yet again following review. Richard has now modified the VRP pass to make the widening pass's job simpler, so I don't need it to do as much. Also rebaslined the whole patch set; Bernd's recent patch has introduced some conflicts. Found (some of?) the bugs that broke my thumb2 constants patch. Pushed the updated patch to Launchpad for testing. Updated a lot of the patch tracker data. Half day Thursday. ---- Upstream patched requiring review: * NEON scheduling patch http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html * Widening Multiplies 1/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08721.html * Widening Multiplies 2/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08723.html * Widening Multiplies 3/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08724.html * Widening Multiplies 4/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08725.html * Widening Multiplies 5/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08726.html * Widening Multiplies 7/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08728.html

13 years, 11 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, * fixed a bug where libunwind could segfault when unwinding through a shared library using the ARM specific unwind tables * discussed the libuwind internals with Uli (thanks!) and concluded that the best way to implement remote unwinding for ARM is to integrate the support for the ARM.exidx* directly into the DWARF code * otherwise the user visible remote API needs to be extended for ARM only which seems to be a bad idea * requires to re-implement the existent ARM code (both local and remote) * will also benefit from libunwind's (dwarf) caching mechanism * started to re-implement the ARM code Regards Ken

13 years, 11 months

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[ACTIVITY] Weekly status

by Revital Eres

- Continue Spec2006 analysis: Looking into SMS opportunities in SPEC2006/462.libquantum. - Looking into recent bootstrap failure with SMS flags on ARM -- it seems to be related to do-loop optimization.

13 years, 11 months

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Generating ancilliary sections with gas (fwd)

by Nicolas Pitre

Hello Michael, We do have more and more instances of the following issues turning up in the kernel requiring toolchain assistance to solve the problem properly. Could you or someone from your team follow this up please? ---------- Forwarded message ---------- Date: Tue, 1 Feb 2011 12:16:48 +0000 From: Dave Martin <dave.martin(a)linaro.org> To: binutils(a)sourceware.org Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org> Subject: Generating ancilliary sections with gas Hi all, Every now and again I come across a situation where it would be really useful to be able to query the assembler state during assembly: for example, to query and do something based on the current section name. This makes it possible to write generic macros to do certain things which otherwise require manual maintenance, or complex and fragile external preprocessing. Below, I give a real-world example of the problem, and sketch out a possible solution. What do people think of this approach? Does anyone have any better ideas on how to solve this? Cheers ---Dave EXAMPLE An example is the generation of custom ancilliary sections. Suppose you want to write macros which record fixup information. Currently, there's no way to put each fixup in an appropriately named section automatically within gas. Tellingly, gas has had to grow the ability to do this internally at least for ARM, since the exception handling information in .ARM.ex{idx,tab}* must go in sections with names based on the associated section name. However, this ancillary section generation support is neither flexible nor exposed to the user. By putting fixups in sections whose names are based on the name of the section they refer to, selective link-time discard of the fixups (and hence the code referenced by the fixups) will work; otherwise it doesn't. This would help avoid a situation where we have to keep dead code in the kernel because custom fixups are applied to it: at run-time, the code gets fixed up, then is thrown away. The fixups can't be selectively discarded because they are all in the same section: we seem have to no good way to separate them out into separate sections appropriately. For context, see: http://www.spinics.net/lists/arm-kernel/msg112268.html PROPOSAL To solve the problem of generating custom ancillary sections during assembly, here's a simple proposal: introducing a new kind of macro argument can make aspects of the assembler state available to macros in a flexible way, with only minimal implementation required. Basically, the macro qualifier field could be used to identify arguments which are filled in by the assembler with information about the assembly state, rather than being filled in by the invoker of the macro: e.g.: .macro mymacro name:req, flags, secname:current_section /* ... */ .pushsection "\secname\name", "\flags" /* ... */ .popsection .endm /* ... */ mymacro .ancillary, "a" During expansion, \name and \flags are expanded as normal. But \secname is substituted instead with the current section name, so the macro expansion would look like this: /* ... */ .pushsection ".text.ancillary", "a" /* ... */ .popsection Without the special :current_section argument, it doesn't appear possible to implement a macro such as mymacro in a generic way. This surely isn't the only way to achieve the goal, and it's probably not the best way, but it does have some desirable features. Principally, while a new pseudo-op(s) could have been defined to append text to the current section name, etc., allowing the current section name to be appear as a macro parameter avoids prejudicing the way the text is used. So there should never be a need to introduce additional pseudo-ops to do things with the current section name: with this patch, the user can always implement their own macro to do the desired thing. This gets the desired behaviour and maximum flexibility, while keeping the implementation in gas very simple. Also, using the macro expansion system in this way allows the caller a free choice of macro parameter names, and so pretty much guarantees that existing code won't get broken by the change. Because my hack is currently simplistic, it has shortcomings: in particular, it's not desirable to parse an argument from the invocation line at all to fill a :current_section argument. Currently, an argument is read in if present, but its value is ignored and the current section name pasted in at macro expansion time instead. However, that should be straightforward to fix with a bit more code. Of course, there's no reason only to expose the current section name in this way. Any aspect of the the assembler state (current subsection, current section flags, current instruction set, current macro mode, etc.) could be made available in a similar way. USAGE EXAMPLE AND PATCH Note that the specific implementation described here is intended to be illustrative, rather than complete or final. binutils$ cat <<EOF >tst.s .macro push_ancillary_section name:req, flags, csec:current_section .pushsection "\name\csec", "\flags" .endm .macro register_fixup _register_fixup 100\@ .endm .macro _register_fixup label:req \label : push_ancillary_section .fixup, "a" .long \label\(b) .popsection .endm .long 1 register_fixup .long 2 .data .long 3 register_fixup .long 4 .long 5 register_fixup .long 6 EOF binutils$ gas/as-new -ahlms -o tst.o tst.s ARM GAS tst.s page 1 1 .macro push_ancillary_section name:req, flags, csec:current_section 2 .pushsection "\name\csec", "\flags" 3 .endm 4 5 .macro register_fixup 6 _register_fixup 100\@ 7 .endm 8 9 .macro _register_fixup label:req 10 \label : 11 push_ancillary_section .fixup, "a" 12 .long \label\(b) 13 .popsection 14 .endm 15 16 0000 01000000 .long 1 17 register_fixup 17 > _register_fixup 1000 17 >> 1000: 17 >> push_ancillary_section .fixup,"a" 17 >>> .pushsection ".fixup.text","a" 17 0000 04000000 >> .long 1000b 17 >> .popsection 18 0004 02000000 .long 2 19 20 .data 21 0000 03000000 .long 3 22 register_fixup 22 > _register_fixup 1003 22 >> 1003: 22 >> push_ancillary_section .fixup,"a" 22 >>> .pushsection ".fixup.data","a" 22 0000 04000000 >> .long 1003b 22 >> .popsection 23 0004 04000000 .long 4 24 0008 05000000 .long 5 25 register_fixup 25 > _register_fixup 1006 25 >> 1006: 25 >> push_ancillary_section .fixup,"a" 25 >>> .pushsection ".fixup.data","a" 25 0004 0C000000 >> .long 1006b 25 >> .popsection 26 000c 06000000 .long 6 ARM GAS tst.s page 2 NO DEFINED SYMBOLS NO UNDEFINED SYMBOLS binutils$ arm-linux-gnueabi-objdump -rs tst.o tst.o: file format elf32-littlearm RELOCATION RECORDS FOR [.fixup.text]: OFFSET TYPE VALUE 00000000 R_ARM_ABS32 .text RELOCATION RECORDS FOR [.fixup.data]: OFFSET TYPE VALUE 00000000 R_ARM_ABS32 .data 00000004 R_ARM_ABS32 .data Contents of section .text: 0000 01000000 02000000 ........ Contents of section .data: 0000 03000000 04000000 05000000 06000000 ................ Contents of section .fixup.text: 0000 04000000 .... Contents of section .fixup.data: 0000 04000000 0c000000 ........ Contents of section .ARM.attributes: 0000 41150000 00616561 62690001 0b000000 A....aeabi...... 0010 08010901 2c01 ....,. diff --git a/gas/macro.c b/gas/macro.c index e392883..95c4de1 100644 --- a/gas/macro.c +++ b/gas/macro.c @@ -516,6 +516,8 @@ do_formals (macro_entry *macro, int idx, sb *in) formal->type = FORMAL_REQUIRED; else if (strcmp (qual.ptr, "vararg") == 0) formal->type = FORMAL_VARARG; + else if (strcmp (qual.ptr, "current_section") == 0) + formal->type = FORMAL_CURRENT_SECTION; else as_bad_where (macro->file, macro->line, @@ -540,6 +542,15 @@ do_formals (macro_entry *macro, int idx, sb *in) name, macro->name); } + else if (formal->type == FORMAL_CURRENT_SECTION) + { + sb_reset (&formal->def); + as_warn_where (macro->file, + macro->line, + _("Pointless default value for current_section parameter `%s' in macro `%s'"), + name, + macro->name); + } } /* Add to macro's hash table. */ @@ -734,7 +745,11 @@ sub_actual (int start, sb *in, sb *t, struct hash_control *formal_hash, ptr = (formal_entry *) hash_find (formal_hash, sb_terminate (t)); if (ptr) { - if (ptr->actual.len) + if (ptr->type == FORMAL_CURRENT_SECTION) + { + sb_add_string (out, segment_name (now_seg)); + } + else if (ptr->actual.len) { sb_add_sb (out, &ptr->actual); } diff --git a/gas/macro.h b/gas/macro.h index edc1b6b..ea6cabb 100644 --- a/gas/macro.h +++ b/gas/macro.h @@ -38,7 +38,8 @@ enum formal_type { FORMAL_OPTIONAL, FORMAL_REQUIRED, - FORMAL_VARARG + FORMAL_VARARG, + FORMAL_CURRENT_SECTION, }; /* Describe the formal arguments to a macro. */ _______________________________________________ linaro-toolchain mailing list linaro-toolchain(a)lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain

13 years, 12 months

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[ACTIVITY] report week 27

by Peter Maydell

RAG: Red: Amber: OMAP3 patch upstreaming is slower progress than hoped Green: Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || == upstream-omap3-patches == * split and did most of the cleanup of 'overhaul onenand support' patch * updated the omap gpio qdev patchset in response to review comments, just about ready to send v2 * this is going more slowly than I had anticipated == other == * patch review, etc * confirmed attendance at KVM Forum and LinuxCon NA Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: 1-5 August: Linaro sprint 1111 15-19 August: KVM Forum and LinuxCon NA, Vancouver

13 years, 12 months

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Updated armel cross toolchains for lucid/maverick/natty releases

by Marcin Juszkiewicz

Hi Linaro backport PPA [1] got updated to latest versions of armel cross toolchains -- oneiric packages were used as a base. What got changed: - gcc 4.4 was updated to 4.4.6-3ubuntu1 - gcc 4.5 was updated to 4.5.3-1ubuntu2 - binutils was updated to 2.21.52.20110606-1ubuntu1 - eglibc was updated to 2.13-6ubuntu2 - gcc 4.6 was provided as 4.6.0-14ubuntu1 in Maverick, Natty - gcc-defaults-armel-cross was updated to 1.6 in Maverick, Natty (uses gcc-4.6 as default) There is no gcc-4.6 for Lucid currently as it requires newer versions of few libraries (mpfr, mpc) and one of rule of this PPA is "do not update packages which may affect other packages". Please test them and report any bugs found. 1. https://launchpad.net/~linaro-maintainers/+archive/toolchain/

13 years, 12 months

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[ACTIVITY] Jul 4 - Jul 8

by Ulrich Weigand

== GDB == * Posted patch to fix shared library remote test problems (#804387). * Started reviewing Yao's latest Thumb-2 displaced stepping patch. == GCC == * Reviewed and approved Richard's mainline reload patch to fix #803232 (ICE on code that uses vld4q_s16() NEON intrinsic). * Followed up on gcc-patches to address concerns about Julian's unaligned access patch. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 12 months

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Looked at why the fix for #721531 wasn't working on the Linaro branches. Wrote follow-up patches for both. Fix now committed to 4.5 and 4.6. * Looked at #736007. Submitted and committed patch upstream. * Looked at some "odd" ivopts behaviour. It turned out that this was working mostly as expected. I'm still wondering about a couple of tweaks. * Looked briefly at a miscompilation of vector code that turned out to occur during predictive commoning. I haven't yet checked whether the bug is there or not. For the time being, I'm using -fno-predictive-commoning so that I can get on with other stuff. * Looked at why the auto-inc-dec stuff wasn't as effective with current mainline. It turns out that the new misaligned load/store patterns are using overly weak predicates, so it appears to the RTL optimisers as though we support reg+offset addresses. * Reviewed the shrink-wrap patch. * More auto inc/dec. == Next week == * Backport the fix for #736007. * More loop stuff. Richard

13 years, 12 months

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[ACTIVITY] 4th - 8th July

by Asa Sandahl

Achieved: * HW in place. Borrowed another Panda board that I can use permanently. * linaro-media-create installed and working. Flashed sd-card with 11.05 for Panda board. * Played around with the Panda board. Networking is on the way. I can ssh to my computer from the Panda but not the other way around yet. Issues: * Serial log from Panda board not working yet. Mike suggested I try a straight-through cable instead in of a null-modem cable. (Have not done this yet.) * The ST-E firewall (proxy) is causing me some headache. But at least everyone here is facing the same issues, so there are people to talk to about the problems. Good to know: * I will be on vacation 18th July - 15 August Best Regards Åsa

13 years, 12 months

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[ACTIVITY] July 3-6

by Ira Rosen

Hi, - continued working on prevention of over-widening in vectorization - finalizing the patch - improvement of vectorizer peeling heuristic - merged to gcc-linaro-4.6 - vectorization of widen-mult with over-promoted operands - proposed for merge to gcc-linaro-4.6 - fixed PR 49610 - patch reviews I am on vacation tomorrow and on Sunday. Ira

13 years, 12 months

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LLVM on ARM testing.

by Karel Gardas

Hello, I'm interested in LLVM correct performance on ARM hardware and it looks like LLVM is kind of sensitive to what GCC version is used for its compilation. I tested LLVM 2.9 as a reference point and LLVM HEAD as of June 29 on ARMv7 (two boards with two different Ubuntu versions) compiled by GCC 4.3.4, 4.4.1, 4.4.5, 4.5.2, 4.6.1 Linaro 2011.05 and 4.6.1 Linaro 2011.06. Please see http://ghcarm.wordpress.com/2011/07/03/llvm-on-arm-testing/ It looks like LLVM HEAD does have about 28 regressions in comparison with LLVM 2.9. But also Linaro's GCC 4.6.1s do have some regressions in comparison with older GCC 4.3.4 and 4.4.1. Also what is really interesting with LLVM is how much tests fails when compiled with -O2 or default -O3 compilation option. I don't know if the culprit here is LLVM code or just GCC miscompilation/overoptimization? Is there any testing I may do to help you fix those regressions? Thanks, Karel

13 years, 12 months

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[ACTIVITY] 27th June - 1st July

by Andrew Stubbs

Worked on updates to the widening multiplies patches following upstream review. This was never going to be as easy as it first looked, so I've spent much of the week trying to figure out how make annoying type casts go away. Merged both FSF GCC 4.5 and 4.6 to Linaro GCC. Pushed the new tree to Launchpad for testing. ---- Upstream patched requiring review: * NEON scheduling patch http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html * Widening Multiplies 1/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08721.html * Widening Multiplies 2/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08723.html * Widening Multiplies 3/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08724.html * Widening Multiplies 4/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08725.html * Widening Multiplies 5/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08726.html * Widening Multiplies 6/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08727.html * Widening Multiplies 7/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08728.html

14 years

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[ACTIVITY] weekly status

by Ken Werner

Hi, * continued to look into how to add remote support for libunwind using ptrace * reworked the lookup of the ARM specific unwind tables for local unwinding * re-use the existent (dwarf related) infrastructure to find the ARM specific unwind tables rather than doing it on our own * removes some code and the limitation of only supporting a certain amount of unw tables * (hopefully) smooths the way for remote unwinding via ptrace * submitted a patch that fixes the syntax of inline assemblies for some GCC versions Regards Ken

14 years

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[Activity] June 23 - July 1

by Ramana Radhakrishnan

(This is a combined report having realized that I didn't manage to send this out on Monday because of some power issues). == GCC == == Progress == * Cleared out some backlog of backports from mainline. * Investigating some of the BRANCH_COST results. * Small patches to fix VFP constraints being tested and fixed on trunk upstream. * Upstream bugzilla triaging. * Upstream bugzilla triaging. * Looked at Neon 64 bit arithmetic and sent out report. * Reviewed the unaligned access patch and the EPILOGUE_USES regression with coremark. * Issues with my panda board means my benchmark runs aren't happening. Need to urgently find a way of running them. The panda board dies mysteriously once a while. Playing around with the kernel to get something going . Will look at it again next week. * Merged neon shift immediates patch into linaro-4.6 but needs some rework. * Merged the fix for LP744754 into linaro 4.5 and 4.6 == Plans == * Back on to BRANCH_COST . * Resubmit neon shift immediates patch for merging. * Look at some of the perf regressions between a8 and A9. * Get a working panda board again. ! * Backport arith_shiftsi patch to 4.6 branch upstream. Meetings: * 1-1s * TCWG calls.

14 years

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * More on the address-of-main() bug. The original patch caused regressions on x86_64, so I submitted a different approach, which has now been applied upstream. * Worked on the libnih bug. It turned out to be a problem in the libc start routine. * A bit of patch review. * More on auto inc/dec. == Next week == * General bug-fixing. * More auto inc/dec. Richard

14 years

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[ACTIVITY] 2011-07-01

by David Gilbert

== 64 bit atomics == * Submitted patches to gcc patch list - One comment back already asking if we should really change ARM to have a VDSO to make checks of the user helper version easier * Added thumb ldrexd/strexd to valgrind; patch added to bug in their bugtracker (KDE bug 266035) * Came to the conclusion eglibc doesn't actually need any changes - It's got a place holder for a 64bit routine, but it's unused and isn't exposed to the libc users - Note that neither eglibc or glibc built cleanly from the trunk on ARM. * Started digging into QEmu a bit more to find out how to solve the helper problem == String routines == * Added SPEC2k6 string routine results to my charts; while most stuff is in the noise it seems the bionic routine is a bit slower overall than everything else, and my absolutely trivially simple ~5 instruction loop is a tie for the fastest with my smarter 4 byte/loop using uadd. == Next week == * Sleep, Rest, Relaxation, getting older * (Will be polling email for any more follow ups on my gcc patches) Dave

14 years

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[ACTIVITY] Jun 27 - Jul 1

by Ulrich Weigand

== GDB == * Analyzed all failures and skipped tests in remote gdb testsuite. Opened bug reports to track problems and missing features: 804387 [remote testsuite] Shared library test problems 804392 [remote testsuite] Rebuilt executables not copied 804396 [remote testsuite] Spurious failures 804400 [remote testsuite] Unnecessarily disabled tests 804401 [remote testsuite] Thread support 804403 [remote testsuite] Support for "attach" tests 804405 [remote testsuite] Core file tests 804406 [remote feature] Generate core files 804407 [remote feature] fork/vfork/exec events 804408 [remote feature] Address space randomization 804409 [remote feature] Checkpoints 804411 [remote feature] "info proc" == GCC == * Reviewed several Linaro GCC merge requests. * Fixed mainline reload bug PR rtl-optimization/49114 Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years

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[ACTIVITY] report week 26

by Peter Maydell

RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || || Historical Milestones: (q1 milestones deleted) ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || == upstream-omap3-patches * analysed omap3 patchstack and identified some initial parts to pull out * extracted and submitted upstream a 3-patch set to qdevify omap gpio * disentangled a cluster of patches for fixing and qdevifying NAND, ONENAND and the OMAP GPMC model; started on the cleanup process * spotted and fixed a bug where n810 segfaults if a key is pressed (this was already fixed in qemu-linaro but not very cleanly) == other == * submitted patch for proper implementation of prlimit64 syscall for qemu usermode * sent a patch to fix the final gcc 4.6 write-only-variable warning * patch review, etc Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: 1-5 August: Linaro sprint 1111 (maybe) 15-16 August: QEMU/KVM strand at LinuxCon NA, Vancouver [LinuxCon proper follows on 17-19th]

14 years

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[ACTIVITY] 27th June - 1st July

by Asa Sandahl

* Got introduced to most of the team members - great! * My manager fixed a linaro laptop for med which I have installed with Natty. (This is very good since I cannot run as root on my STEricsson laptop. There are also other security restrictions that makes it very hard to work in Linaro.) * Started working a little bit with the Snowball board. I have managed to flash it using the "riff" tool. * Read through the material about SPEC2000. * I have borrowed a Panda board that I can use for the next two weeks. A question that popped up is how to get one from Linaro? * I will be on vacation 18th July - 15 August Best regards Åsa

14 years

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No usb on omap3: 4.6 toolchain issue?

by Paolo Pisati

It all started with this: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/791552 basically, switching toolchain from 4.5 to 4.6, somehow broke usb on omap3. This morning i tested with linux-linaro-natty: [flag@newluxor linux-linaro-natty]$ git log --oneline -1 f15fd8f LINARO: Linux-linaro-2.6.38-1002.3 and i can reproduce the problem there too. Here is some more info (dmesg, toolchain, lsusb, etcetc): http://pastebin.ubuntu.com/620786/ -- bye, p.

14 years

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[ACTIVITY] June 26-30

by Ira Rosen

Hi, - support of multiple uses of original pattern statements (needed for over-promotion work) - committed upstream - support of widen-mult of unsigned types and constants - merged to gcc-linaro-4.6 - vectorizer peeling heuristic improvement - proposed to merge to gcc-linaro-4.6 Ira

14 years

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Fwd: [Bug gas/12931] ARM: gas fails to set the proper alignment on code sections, causing broken output

by Dave Martin

See the following commit in binutils trunk. If this is causing problems in other places, it could be worth considering for backport into the linaro tools. Cheers ---Dave http://sourceware.org/bugzilla/show_bug.cgi?id=12931 --- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> 2011-06-29 16:29:43 UTC --- CVSROOT: /cvs/src Module name: src Changes by: nickc(a)sourceware.org 2011-06-29 16:29:38 Modified files: gas : ChangeLog gas/config : tc-arm.c Log message: PR gas/12931 * config/tc-arm.c (mapping_state): When changing to ARM or THUMB state set the minimum required alignment of the section. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src… http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-arm.c.diff?cvsro…

14 years

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iDCT implementation in GCC NEON intrinsics, for your perusal

by Michael K. Edwards

Here's an implementation of an 8x8 integer DCT done with NEON intrinsics -- essentially a translation of the assembly version in libjpeg-turbo trunk: https://github.com/mkedwards/crosstool-ng/blob/master/patches/libjpeg-turbo… It is in a compilable (on Linaro 2011.05 GCC 4.5, anyway; a recent Linaro 4.6 snapshot ICEs) but otherwise untested state. Still, it's interesting to compare the assembly that it generates against the hand-written version. I thought I'd give linaro-toolchain a heads-up in case y'all could use a test case that generates plenty of pressure on the VFP/NEON register bank. (I intend to use it to see how much performance difference there really is, on the A8 and A9, between NEON code compiled for 16 vs. 32 registers.) Cheers, - Michael

14 years

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